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FPA Optimized Selective Harmonic Elimination in Symmetric-Asymmetric Reduced Switch Cascaded Multilevel Inverter
FPA Optimized Selective Harmonic Elimination in Symmetric-Asymmetric Reduced Switch Cascaded Multilevel Inverter
3, MAY/JUNE 2020
Abstract—Symmetrical and asymmetrical multilevel inverters MLIs in industries, electric vehicles, and renewable power gen-
(MLIs) have demonstrated its usefulness in a wide range of appli- eration [3]–[7]. MLIs can synthesize staircase sinusoidal-like
cations. This is accomplished due to the ongoing improvement by output depending on the number of dc sources, semiconduc-
reducing the converter size and enhancement in the voltage quality.
In this article, a generalized cascaded MLI structure is developed, tor switches, diodes, and capacitors used in the circuit. Three
which can operate in both symmetric and asymmetric modes. widely used classical MLI structures are diode-clamped MLI
Comparative assessment in terms of the number of components (DMLI), flying capacitor MLI (FMLI), and cascaded H-bridge
and voltage stress warrants the design superiority. A new selective MLI (CMLI) [2], [8]–[10]. Voltage balancing, need of clamping
harmonic elimination (SHE) control using flower pollination algo- diodes/capacitors, liability to module failure due to series con-
rithm (FPA) is investigated for the developed asymmetrical MLI.
The salient features of the FPA such as less burdensome compilation nection of switches are the major concerns in DMLIs and FMLIs.
and ability tos single-stage local and global search ascertain the Compared to these single dc MLIs, multi-dc CMLIs are gaining
elimination of the targeted harmonics through optimum angles a great deal of interest due to the modularity and reliability fea-
computation. Moreover, the competence of the FPA is verified by tures. Further, symmetrical CMLIs have more straightforward
comparing it with well-known SHE algorithms. Simulation analysis control, while asymmetric topologies can significantly enhance
is carried out in MATLAB/Simulink environment, which validates
the workability of the developed system. Experimental tests using the number of levels using the same number of components [11].
fundamental and high switching frequency control techniques are However, a strong limitation of the classical MLIs is the
further conducted under a dynamic environment to demonstrate requirement of more number of semiconductor switches and dc
the efficacy of the proposed methodology. sources. In recent years, continuous research efforts have been
Index Terms—Flower pollination algorithm (FPA), reduced made to optimize the MLI structure in all possible means. MLIs
components, selective harmonic elimination (SHE), switched-diode are researched in three wide varieties such as switched-dc MLI,
multilevel inverter (SMLI), symmetric–asymmetric multilevel switched-capacitor MLI, and switched-diode MLIs (SMLIs)
inverter (MLI). [12]. In [13], a switched-dc symmetrical structure has been
recommended using a reduced number of switches compared
I. INTRODUCTION
to the classical structures. This topology does not require a
ULTILEVEL inverters (MLIs) are dominating over con-
M ventional inverters due to their ability to operate in a vast
range of applications [1]–[5]. Enhanced interference compatibil-
back-end H-bridge for altering the polarity; however, it still
requires isolated sources identical to the CMLI for synthesizing
any voltage level. In the switched-dc category, structures pro-
ity, low voltage stress, improved efficiency, and power quality are posed in [14], [15] are also competitive and cost-effective. These
the key factors behind the tremendous growth and application of reduced switch structures can inherently reverse voltage polarity,
and higher voltage steps can be produced by cascading the basic
Manuscript received October 25, 2019; revised February 9, 2020; accepted units. Using the H-bridge integrated to the basic units, optimal
March 12, 2020. Date of publication March 18, 2020; date of current version structures are disclosed in [16], [17] that can produce 15 levels
April 24, 2020. Paper 2019-IPCC-1365.R1, presented at the 2018 IEEE Interna- using 16 number of switches and 7 isolated dc sources. There
tional Conference on Power Electronics, Drives and Energy Systems, Chennai,
India, Dec. 18–21, and approved for publication in the IEEE TRANSACTIONS is also a possibility of extension to generate any voltage levels
ON INDUSTRY APPLICATIONS by the Industrial Power Converter Committee of utilizing different magnitudes of dc sources and with a reduced
the IEEE Industry Applications Society. This work was supported in part by the voltage stress on the switches. Based on the above concept,
Department of Science and Technology (DST), Government of India Project
under Grant EMR/2017/001880 and in part by the Institution of Engineers (In- symmetrical and asymmetrical MLIs with different pulse width
dia) R&D Grant-in-Aid scheme under Grant RDDR2017017. (Corresponding modulation (PWM) control strategies have also been presented
author: Kaibalya Prasad Panda.) in [18] and [19], respectively. In [20]–[22], switched-dc compact
The authors are with the Department of Electrical Engineering,
National Institute of Technology, Shillong, Meghalaya, India (e-mail: module topologies have been analyzed as a suitable replacement
kaibalyapanda@nitm.ac.in; prabhat.bana@nitm.ac.in; gayadhar.panda@ of the conventional MLIs.
nitm.ac.in). The MLIs, as mentioned earlier, reduce the switch count
Color versions of one or more of the figures in this article are available online
at http://ieeexplore.ieee.org. but do not possess voltage boosting ability. Consequently,
Digital Object Identifier 10.1109/TIA.2020.2981601 switched-capacitor structures are developed, which can enhance
0093-9994 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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PANDA et al.: FPA OPTIMIZED SELECTIVE HARMONIC ELIMINATION IN SYMMETRIC–ASYMMETRIC REDUCED SWITCH CASCADED MLI 2863
Fig. 2. Comparison with prior-art MLI structures (T1 [17], T2 [14], T3 [26], T4 [25], T5 [15], T6 [13], T7 [16], T8 [19], T9 [24], T10 [20], T11 [18], and T12
[27]). (a) Nsw versus Nl . (b) Ndc versus Nl . (c) CLR versus Nl . (d) TSV versus Nl .
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PANDA et al.: FPA OPTIMIZED SELECTIVE HARMONIC ELIMINATION IN SYMMETRIC–ASYMMETRIC REDUCED SWITCH CASCADED MLI 2865
Fig. 4. Programming results for the 13-level SMLI. (a) FF versus Mi. (b) THD versus Mi. (c) CDF versus FF. (d) Harmonics versus Mi. (e) SA versus Mi.
(f) Harmonic spectrum.
TABLE II are implemented along with the proposed FPA. Parameter set-
COMPARISON OF SHE ALGORITHMS FOR 90 POPULATION SIZES, 400
ITERATIONS, AND 20 TRIAL RUNS
tings for all the algorithms are specified in Table II. It should
be noted that the authors have considered several trial runs prior
to the selection of the optimal parameters. The programming is
carried out on a host computer with 8.00-GB installed memory
and an Intel Core, i5, 2.30-GHz processor. Fig. 4(a) shows the
plot between the optimum FF versus Mi. The proposed FPA
is able to minimize the fitness value to below 10−19 for more
than 80% of Mi. The results obtained using CSA are much
closer to the FPA than the other two. Further, the probability of
convergence to the global minima point is evaluated considering
Step-1: Initialize the parameters such as maximum iteration the cumulative distribution function (CDF) [29]. Consequently,
count (iterm ), PS , and the minimum and maximum range Fig. 4(b) illustrates the superior performance of FPA. Moreover,
of the SAs. Randomly initiate the SA population (pollens) for the performance parameter THD [11] is taken into account
FF evaluation. for comparison among the algorithms. Fig. 4(c) implies that
Step-2: To evaluate the stability and quality of the pollens, FF is the THD decreases significantly using the proposed FPA with
evaluated for each αp contingent upon (9). Gbest is initialized the increase in Mi. This also indicates the effectiveness of the
as the optimum FF. For the range of Mi (0:0.01:1), αp is FPA in eliminating low-order harmonics. Out of these algo-
identified and stored in the memory corresponding to the rithms, TLBO and CSA have comparable performance as of
optimum FF. the FPA.
Step-3: All the αp should undergo global pollination (Rule-a) or For the 13-level SMLI, the targeted harmonic orders are
the local pollination (Rule-b). Therefore, a uniform distributed evaluated w.r.t. Mi. Fig. 4(d) depicts that, in the range of 0.9–0.95
random number (rand) is first generated, and then for each Mi, the low-order harmonics are completely eliminated and,
iteration, if PS > rand, pollens follow Rule-a, else Rule-b. at the same time, the fundamental level is maintained which
Step-4: New SAs and corresponding FF are evaluated further to satisfies the elementary SHE principles. The optimum SAs
assess the new Gbest . The optimal SAs in line with the min- obtained using FPA are depicted in Fig. 4(e) that satisfies (9),
imum FF are updated in the memory. This process continues and the continuous solution for the full range of Mi is ensured.
until all the pollens converge to minimum FF for the iterm , The objective of the SHE-PWM control technique is to eliminate
otherwise return to Step-2. the targeted harmonic orders, whereas the SHM-PWM tech-
nique satisfies the power quality standard grid codes. Nonethe-
less, Fig. 4(f) shows that the low-order harmonic that resulted
C. Comparison of FPA With Well-Known SHE Algorithms using the SHE technique also fulfills the grid-code standards EN
With the aim to calculate the optimized SAs for eliminating 50160 and CIGRE WG 36-05 except the 15th order harmonic
the targeted harmonics, three recent-art algorithms such as par- that is not targeted for the 13-level SMLI. This implies that the
ticle swarm optimization (PSO) [29], teaching learning-based use of large-sized filters at the load side can be obviated from
optimization (TLBO) [36], cuckoo search algorithm (CSA) [10] different applications viewpoint.
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PANDA et al.: FPA OPTIMIZED SELECTIVE HARMONIC ELIMINATION IN SYMMETRIC–ASYMMETRIC REDUCED SWITCH CASCADED MLI 2867
Fig. 5. Simulation analysis. (a) Developed 13-level SMLI structure. (b) Standing voltage and power losses in the 13-level SMLI. (c) 13-level output with switching
pulse duration. (d) Terminal voltages in the 13-level SMLI.
Fig. 6. Simulation results: 13-level output voltage with corresponding harmonic spectra under changing Mi condition (a) with SHE-PWM control,
(b) with SPWM control, and (c) output voltage with P1 and P2 algorithms.
V. SIMULATION ANALYSIS verify the optimum THD obtained at 0.93 Mi (as acquired from
the programming results), low (0.25) and medium (0.55) Mi
The SMLI circuit topology with two DSMs shown in Fig. 5(a) values are also considered. The harmonic profile along with Vo
is used to validate the workability in simulation. Ten numbers for a purely resistive load is shown in Fig. 6(a) which confirms
of switches are used in the circuit. Out of these switches, two low overall THD at high Mi, and the results are in agreement
switches (Sa1 and Sa2 ) used to create the levels that block the with the programming findings.
minimum voltage that can be inferred from Fig. 5(b). Power In addition, Vo and the respective harmonic profiles are also
losses of the switches are also pictorially depicted, which is acquired with the SPWM control scheme as shown in Fig. 6(b).
calculated by a detailed simulation of insulated-gate bipolar In light of this, six triangular carriers with a frequency of 5 kHz
transistor (IGBT) switches in the Simulink platform considering are arranged in the same phase with a finite offset value and
Vdc = 200 V and 150 Ω load. As SHE-PWM is considered, the are compared with a reference sinusoidal signal of a nominal
switching losses are almost negligible and conduction losses frequency of 50 Hz to generate the desired switching pulses
are the major contributor to the total power losses. Fig. 5(c) (see Fig. 3). Superior performance of SHE-PWM control is
depicts the kind of 13-level output pattern along with conduction established and the fundamental magnitude declines with change
instances of each switch. The 13-level output (Vo ) and voltages in Mi for the SPWM control. Further, to endorse all the proposed
of each unit (Vr1 , Vr2 , Va1 , and Va2 ) are illustrated in Fig. 5(d). algorithms given in Table I for selection of dc source magnitude,
Further, the competence of the control techniques is demon- results are also shown for P1 and P2 in Fig. 6(c) considering the
strated by applying both SHE-PWM and SPWM control tech- equal output voltage of 1200 V. Considering two DSMs that are
niques. SAs corresponding to the Mi values are evaluated offline cascaded as shown in Fig. 5(a), the SMLI synthesizes 9-level
by the proposed FPA approach and stored in a lookup table. To and 17-level using P1 and P2 , respectively.
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2868 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 56, NO. 3, MAY/JUNE 2020
Fig. 7. Experimental results of output voltage and current waveform, voltages of different units, and standing voltage of some switches with (a) P1 , (b) P2 , and
(c) P3 .
Fig. 8. Experimental verification of the control schemes. (a) Output voltage with changing Mi. (b) Output voltage and current under R-load. (c) Output voltage
and current under changing RL-load. (d) Harmonic analysis of the output voltage under different Mi. (e) Output voltage with dynamic change in frequency. (f)
Output voltage and current under RL-load with SPWM control. (g) Output voltage harmonic profile with SPWM control.
VI. EXPERIMENTAL VERIFICATION and two RGP30D diodes. Control techniques are developed in
a TMS320F28335 control card. The controller transfers pulses
In order to validate the topological advancement and the to the switches through a TLP250 optocoupler driver that en-
control efficiency of FPA, a scaled-down laboratory prototype ables the necessary isolation and pulse amplification. Results
of the SMLI is used which consists of two cascaded DSMs, four are acquired using a ScopeCoder under an RL-load of value
isolated variable dc supplies, ten 12N60A4D IGBT switches, 50 Ω–6.3 mH unless otherwise specified.
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PANDA et al.: FPA OPTIMIZED SELECTIVE HARMONIC ELIMINATION IN SYMMETRIC–ASYMMETRIC REDUCED SWITCH CASCADED MLI 2869
A. Validation of SMLI Operation Using Proposed Algorithms implemented to test the MLI. FPA, as a newly emerging
optimization technique, has been used for the optimal angle
In order to evaluate the operational ability of the SMLI in
relation to the number of levels indicated in Table I, magni- evaluation to eliminate the dominant low-order harmonics from
the output voltage selectively. In comparison with PSO, TLBO,
tudes of the dc sources are selected accordingly. The SMLI can
and CSA, the results reveal fast tracking of FPA towards an
synthesize 9-level, 17-level, and 13-level using P1 , P2 , and P3 ,
respectively, considering two DSMs are cascaded. In the case of optimal solution, less complicated compilation, and high accu-
racy. The selected 3rd to 11th order harmonics are eliminated
P1 , P2 , and P3 , the magnitude of the four dc sources are set as
and satisfy the grid-code standards for the 13-level asymmet-
(30 V, 30 V, 30 V, 30 V), (15 V, 15 V, 45 V, 45 V), and (20 V,
40 V, 40 V, 20 V), respectively. Applying the FPA-SHE control, rical MLI, even accounting single switching per cycle voltage
pattern. Extensive simulation and experimental analysis have
optimum SAs are programmed in the controller for 9-level,
17-level, and 13-level operations. Consequently, Fig. 7(a)–(c) been carried out under different dynamic test cases to justify
shows the successful working of the SMLI. The figure also the proposed method. The developed SMLI works favorably
using different PWM control schemes in both symmetric and
includes the voltage across different units (Vr1 , Vr2 , Va1 , and
Va2 ) and the standing voltage across few switches (Sa1 , Sa2 , Ta1 , asymmetric modes.
and Td2 ). It is worth to mention that the P2 algorithm appreciably
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multilevel selective harmonic elimination PWM: Formulations, solving the B.E. degree in electrical engineering from the
algorithms, implementation and applications,” IEEE Trans. Power Elec- Institute of Engineers, West Bengal, Kolkata, India,
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A. Ruderman, “Simultaneous selective harmonic elimination and THD nology, Shibpur, Howrah, West Bengal, India, and
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Syst., 2018, pp. 1–6. Shillong, India, where he is currently a Professor.
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