CF Industrial Data Sheet en

_______________________________________________________________________________________________
Technical Specification
Industrial Compact Flash Card
Release Date: June 2005

Version: 1.4
_______________________________________________________________________________________
SCM PC-Card GmbH

Sperl-Ring 4
D-85276 Pfaffenhofen
Tel: +49 8441 788 810

Fax: +49 8441 788 900
www.scm-pc-card.de
S-CN CompactFlash Card Industrial Application
Preliminary
S-CN CompactFlash Card

Industrial Application
Product Specification
June 2005
S-CN : Single-Level-Cell-NAND
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Document History
Version Description Date Approved by
1 New issue Apr. 2004 Debby Chang
1. Supported flash kind for block
size.
2.Capacity appearance modify
2 August. 2004 Xeras Xiang
3.Checking Product UDMA
function (announce not supported
multi word DMA)
3 1.Update AC Characteristics December 2004 Ethan Cheng
1. Power Consumptions
2. Environment conditions
3. MTBF
4 June 2005 Verlaine Lin
4. R/W Test
5. Temp Flow Chart
6. PCB No
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Contents
INDUSTRIAL APPLICATION.............................................................................................................................................................................1
1. INTRODUCTION.........................................................................................................................................................................................7
1.1 GENERAL DESCRIPTION ........................................................................................................................................................................7

1.2 FEATURES ...............................................................................................................................................................................................8
2. PRODUCT SPECIFICATION...................................................................................................................................................................9
2.1 OPERATION AND ENVIRONMENT DESCRIPTION ....................................................................................................................................9

2.2 PHYSICAL DESCRIPTION ......................................................................................................................................................................10
3. PRODUCT MODEL ..................................................................................................................................................................................11
3.1 PART NUMBER DEFINITION .................................................................................................................................................................11
4. SUPPORT FLASH MEDIA......................................................................................................................................................................12
4.1 SUPPORTED NAND FLASH TYPE .......................................................................................................................................................12

4.2 LOGICAL FORMAT PARAMETERS (CHS) ............................................................................................................................................12
5. BLOCK DIAGRAM...................................................................................................................................................................................14
5.1 CONTROLLER ARCHIVE.......................................................................................................................................................................14

5.2 FLASH CARD ARCHIVE........................................................................................................................................................................14
6. SPECIFICATION AND FEATURES .....................................................................................................................................................15
6.1 ELECTRICAL SPECIFICATION ...............................................................................................................................................................15

6.1.1 Absolute Maximum Ratings..........................................................................................................................................................15
6.1.2 General DC Characteristic...........................................................................................................................................................15
6.1.3 DC Electrical Characteristics for 5 Volts Operation..................................................................................................................15
6.1.4 DC Electrical Characteristics for 3.3 Volts Operation...............................................................................................................16
6.1.5 Attribute Memory Read Timing Specification .............................................................................................................................16
6.1.6 Configuration Register(Attribute Memory)Write Timing Specification ....................................................................................17
6.1.7 Common Memory Read Timing Specification.............................................................................................................................17
6.1.8 Common Memory Write Timing Specification ............................................................................................................................18
6.1.9 I/O Input (Read) Timing Specification .........................................................................................................................................19
6.1.10 I/O Input (Write) Timing Specification ...................................................................................................................................20
6.1.11 True IDE Mode I/O (Read/Write) Timing Specification........................................................................................................21
6.1.12 True IDE Ultra DMA Mode I/O (Read/Write) Timing Specification ...................................................................................23
6.1.12.1 Ultra DMA Data-In Burst Initiation Timing............................................................................................................................................ 24
6.1.12.2 Sustained Ultra DMA Data-In Burst Timing........................................................................................................................................... 25
6.1.12.3 Ultra DMA Data-In Burst Host Pause Timing ........................................................................................................................................ 25
6.1.12.4 Ultra DMA Data-In Burst Device Termination Timing.......................................................................................................................... 26
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6.1.12.5 Ultra DMA Data-In Burst Host Termination Timing.............................................................................................................................. 26

6.1.12.6 Ultra DMA Data-In Burst Host Termination Timing.............................................................................................................................. 27
6.1.12.7 Sustained Ultra DMA Data-Out Burst Timing........................................................................................................................................ 27
6.1.12.8 Ultra DMA Data-Out Burst Device Pause Timing ................................................................................................................................. 28
6.1.12.9 Ultra DMA Data-Out Burst Device Termination Timing....................................................................................................................... 28
6.1.12.10 Ultra DMA Data-Out Burst Host Termination Timing........................................................................................................................... 29
6.2 POWER MANAGEMENT .......................................................................................................................................................................29
6.2.1 Normal Mode.................................................................................................................................................................................29
6.2.2 Power down Mode ........................................................................................................................................................................29
6.3 PHYSICAL SPECIFICATION ...................................................................................................................................................................30
6.3.1 CompactFlash CF Type I..............................................................................................................................................................30
6.3.2 CompactFlash CF Type II.............................................................................................................................................................30
7. PIN ASSIGNMENT....................................................................................................................................................................................31
7.1 COMPACTFLASH PIN TYPE..................................................................................................................................................................31

7.2 SIGNAL DESCRIPTION ..........................................................................................................................................................................33
8. CIS AND FUNCTIONS CONFIGURATION REGISTERS.............................................................................................................38
8.1 CONFIGURATION OPTION REGISTER (200H) .....................................................................................................................................38

8.2 CARD CONFIGURATION AND STATUS REGISTER (ADDRESS 202H) .................................................................................................39
8.3 PIN REPLACEMENT REGISTER (ADDRESS 204H) ..............................................................................................................................40
8.4 SOCKET AND COPY REGISTER (ADDRESS 206H) ..............................................................................................................................40
8.5 CARD INFORMATION STRUCTURE (CIS) ............................................................................................................................................41
9. ATA SPECIFIC REGISTER DEFINITIONS.......................................................................................................................................55
9.1 MEMORY MAPPED ADDRESSING ........................................................................................................................................................55

9.2 CONTIGUOUS I/O MAPPING ADDRESSING .........................................................................................................................................56
9.3 OVERLAPPING I/O MAPPING ADDRESSING........................................................................................................................................57
9.4 TRUE IDE MODE .................................................................................................................................................................................57
9.5 ATA REGISTERS ...................................................................................................................................................................................58
9.5.1 Data Register .................................................................................................................................................................................58
9.5.2 Error Register ................................................................................................................................................................................58
9.5.3 Feature Register.............................................................................................................................................................................59
9.5.4 Sector Count Register....................................................................................................................................................................59
9.5.5 Sector Number Register ................................................................................................................................................................59
9.5.6 Cylinder Low Register...................................................................................................................................................................60
9.5.7 Cylinder High Register..................................................................................................................................................................60
9.5.8 Drive Head Register......................................................................................................................................................................61
9.5.9 Status Register................................................................................................................................................................................62
9.5.10 Alternate Status Register..........................................................................................................................................................62
9.5.11 Device Control Register...........................................................................................................................................................63
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9.5.12 Drive Address Register ............................................................................................................................................................63
10. ATA COMMANDS................................................................................................................................................................................64
10.1 CHECK POWER MODE - 98H OR E5H ................................................................................................................................................64

10.2 EXECUTE DRIVE DIAGNOSTIC - 90H..................................................................................................................................................65
10.3 ERASE SECTOR(S) - C0H.....................................................................................................................................................................66
10.4 FORMAT TRACK - 50H.........................................................................................................................................................................67
10.5 IDENTIFY DRIVE – ECH ......................................................................................................................................................................68
10.6 IDLE - 97H OR E3H..............................................................................................................................................................................69
10.7 IDLE IMMEDIATE - 95H OR E1H..........................................................................................................................................................70
10.8 INITIALIZE DRIVE PARAMETERS - 91H...............................................................................................................................................71
10.9 READ BUFFER - E4H ...........................................................................................................................................................................72
10.10 READ LONG SECTOR(S) - 22H OR 23H...............................................................................................................................................73
10.11 READ MULTIPLE - C4H .......................................................................................................................................................................74
10.12 READ SECTORS(S) – 20H OR 21H.......................................................................................................................................................75
10.13 READ VERIFY SECTOR(S) – 40H OR 41H...........................................................................................................................................76
10.14 RECALIBRATE - 1XH ...........................................................................................................................................................................77
10.15 REQUEST SENSE - 03H ........................................................................................................................................................................78
10.16 SEEK - 7XH..........................................................................................................................................................................................79
10.17 SET FEATURE - EFH.............................................................................................................................................................................80
10.18 SET MULTIPLE MODE - C6H...............................................................................................................................................................81
10.19 SET SLEEP MODE - 99H OR E6H ........................................................................................................................................................82
10.20 STANDBY - 96H OR E2H......................................................................................................................................................................83
10.21 STANDBY IMMEDIATE 94H OR E0H ...................................................................................................................................................84
10.22 TRANSLATE SECTOR - 87H..................................................................................................................................................................85
10.23 WEAR LEVEL - F5H.............................................................................................................................................................................86
10.24 WRITE BUFFER - E8H..........................................................................................................................................................................87
10.25 WRITE LONG SECTOR(S) 32H OR 33H...............................................................................................................................................88
10.26 WRITE MULTIPLE - C5H .....................................................................................................................................................................92
10.27 WRITE MULTIPLE WITHOUT ERASE – CDH.......................................................................................................................................93
10.28 WRITE SECTOR(S) - 30H OR 31H........................................................................................................................................................94
10.29 WRITE SECTOR(S) WITHOUT ERASE - 38H.........................................................................................................................................95
10.30 WRITE VERITY - 3CH..........................................................................................................................................................................96
11. ERROR POSTING.....................................................................................................................................................................................97
12. IDENTIFY DRIVE INFORMATION...............................................................................................................................................99
13. ATA PROTOCOL OVERVIEW ..................................................................................................................................................... 103
13.1 PIO DATA IN COMMANDS ................................................................................................................................................................ 103

13.2 PIO DATA OUT COMMANDS ............................................................................................................................................................ 103
13.3 NON DATA COMMANDS ................................................................................................................................................................... 103
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14. ULTRA DMA DATA-IN COMMANDS................................................................................................................................................... 104
14.1. INITIATING AN ULTRA DMA DATA-IN BURST.......................................................................................................................................... 104

14.2. THE DATA-IN TRANSFER ........................................................................................................................................................................... 104
14.3. PAUSING AN ULTRA DMA DATA-IN BURST ............................................................................................................................................. 105
14.3.1. Device pausing an Ultra DMA data-in burst ............................................................................................................................... 105
14.3.2. Host pausing an Ultra DMA data-in burst ................................................................................................................................... 105
14.3.3. Terminating an Ultra DMA data-in burst ..................................................................................................................................... 105
14.3.3.1. Device terminating an Ultra DMA data-in burst............................................................................................................................................. 105
14.3.3.2. Host terminating an Ultra DMA data-in burst................................................................................................................................................. 106
14.4. ULTRA DMA DATA-OUT COMMANDS ..................................................................................................................................................... 108
14.4.1. Initiating an Ultra DMA data-out burst........................................................................................................................................ 108
14.4.2. The data-out transfer ...................................................................................................................................................................... 108
14.4.3. Pausing an Ultra DMA data-out burst.......................................................................................................................................... 109
14.4.3.1 Host pausing an Ultra DMA data-out burst...................................................................................................................................................... 109
14.4.4. Terminating an Ultra DMA data-out burst................................................................................................................................... 109
14.4.4.1 Host terminating an Ultra DMA data-out burst................................................................................................................................................ 109
14.4.4.2 Device terminating an Ultra DMA data-out burst............................................................................................................................................ 110
14.5. ULTRA DMA CRC RULES.........................................................................................................................................................................111
15. SECURITY CF ...............................................................................................................................................................................................113
16.SYSTEM ENVIRONMENTAL SPECIFICATIONS............................................................................................................................. 138
16.1 TEMPERATURE TEST FLOW ...................................................................................................................................................................... 138

16.2ALTITUDE TEST .......................................................................................................................................................................................... 139
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1. Introduction
1.1 General Description
The S-CN CompactFlash Card uses NAND-Type flash memory devices, which leads to its
remarkable high performance and comes with capacities from 256 MB to 6GB unformatted.
Compliant with ISA (Industrial Standard Architecture) bus interface standard, the S-CN CompactFlash
Card performs sequential read/write for each sector (512 bytes) count. It also conforms to CompactFlash
Specification and is designed with precision mechanics to enable host devices to read/write from the
CompactFlash interface into Flash Media. It can operate with a 3.3V or 5V single power from the host
side.
The card provides extraordinary memory medium for PC or any other electric equipment and digital
still camera, and, in particular, the S-CN CompactFlash Card has been approved through various
compatibility tests to be used in numerous portable desktop, notebook computers and personal handheld
devices such as handheld audio recorders, PDAs, Palm sized PCs, Handheld PCs and Auto PCs under
industrial environment.
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1.2 Features
PC Card compliant
Conforms to CompactFlash standard
Compatible with PCMCIA ATA specification
Support CIS implemented with attribute memory
Compatible with all PC Card Services and Socket Services
PCMCIA ATA / IDE interface
ATA command set compatible
Support for 8-bit or 16-bit host data transfer
Program and auto-wait-state initiation for compatibility with any IORDY supporting host
Compatibility with host ATA disk I/O BIOS, DOS/Windows file system, utilities, and application
software
Extremely rugged and reliable
Advanced defect block management
Support background erased operation
3.3/5 Volt power supply, very low power consumption
● Zero-power data retention, no batteries required
● Internal self-diagnostic program operates at VCC power on
● Auto sleep mode
High reliability based on internal ECC (Error Correcting Code) function
Zero-power data retention, no batteries required
3 variations of mode access
● Memory card mode
● I/O card mode
● True IDE mode
- PIO Mode 4
- UDMA mode 2
Not supported Multi word DMA formatted.
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2. Product Specification
2.1 Operation and environment description
5V ± 10%
Operating Voltage DC Input Power
3.3V ± 5%
Read Mode: 40mA (Max)
Write Mode: 60mA (Max)
5V
Standby Mode:6.5mA(Approach alues)
Typical Power Read/ Write Peak: 100mA
Consumptions: Read Mode: 20mA (Max)
Write Mode: 35 mA (Max)
3.3V
Standby Mode: 1mA (Approach values)
Read/ Write Peak: 100mA
Extended Temp. -20°C to +85°C
Operating Temperature
Industrial Temp. -40°C to +85°C
Extended Temp. -40°C to +90°C
Storage Temperature
Industrial Temp. -50°C to +90°C
Humidity Operation 5% to 95% (Non-condensing )
Environment conditions
Humidity Non-operation 5% to 95% (Non-condensing )
Shock Operation 3000-G (Max.)
Shock Non-operation 3000-G (Max.)
Vibration Operation 30-G (Peak to peak to maximum)
Vibration Non-operation 30-G (Peak to peak to maximum)
Operation System supported DOS
Compatibility (Microsoft Windows 98 Windows ME
Product) Windows NT Windows 2000 Windows XP
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2.2 Physical description

Weight: 15 g LxWxH
Type I
1.Weight and Measures Pin-Pitch: 1.27 mm 36.4 x 42.8 x 3.3 (mm)
(unit: m) Weight: 23 g LxWxH
Type II
Pin-Pitch: 1.27 mm 36.4 x 42.8 x 5.0 (mm)
2. Storage Capacities Capacity 256MB – 6GB
To/from Flash memory
(burst mode):
Data Transfer Rates up to 20 Mbytes/sec
3. Performance
To/from host (burst mode):
up to 8 Mbytes/sec
Data Access Time 1.2 ms
MTBF 3,000,000 hours
More than 3 bit error correction per
Error Correction
second read
4. Reliability High reliability based on internal
ECC
ECC function
Testdisk:
R/W Test
1,000,000 Read/Write cycles
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3. Product Model & Ordering Information
CFA = Compact Flash Card
CFA-XXXX-13T-00-CP
XXXX: 032M 32Mbyte Type I

064M 64Mbyte Type I
128M 128Mbyte Type I
001G 1GByte Type I
002G 2GByte Type I
003G 3GByte Type I
004G 4GByte Type I
006G 6GByte Type II
008G 8GByte Type II
T: C Commercial Temp. Range 0 / +70° Cel

I Industrial Temp. Range -40 / +85° Cel
CP: Full Metal Housing
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4. Support Flash Media

4.1 Supported NAND Flash Type
4-1-1. Small block size of 16KB
Unit: bits
Flash Capacity 128 Mega 256 Mega 512 Mega
Operation Voltage 2.7V to 3.6V
4-1-2. Large block size of 128KB

Unit: bits
Flash Capacity 1 Giga 2 Giga 4 Giga 8 Giga
Operation Voltage 2.7V to 3.6V
4.2 Logical Format Parameters (CHS)

CF Type I (3.3mm)
Card Capacity*1
Unit: Bytes
Card Density*4 256M 512M
Cylinder 992 1007
Heads 16 16
Sectors/Track*2 32 63
Total
507904 1,015,056
Sectors/Card*3
Capacity*5 260,046,848 519,708,672
Unit: Bytes
*4
Card Density 1GB 2GB 3GB 4GB
Cylinder 2015 4030 6046 8061
Heads 16 16 16 16
Sectors/Track*2 63 63 63 63
Total
2,031,120 4,062,240 6,094,368 8,125,488
Sectors/Card*3
Capacity*5 1,039,933,440 2,079,866,880 3,120,316,416 4,160,249,856
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CF Type II (5.0mm)
Card Density*4 6GB

Cylinder 12092
Heads 16
Sectors/Track*2 63
Total
12,188,736
Sectors/Card*3
Capacity*5 6,240,632,832
Notes:
1. These data are written in Identify table.
2. Total tracks =number of head x number of cylinder.
3. Total sector/Card = sector/track x number of head x number of cylinder
4. Those are general unformatted capacity of all cards.
5. It’s the logical address capacity including the area which is used for file system.
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5. Block Diagram
5.1 Controller Archive
Frequency Provider
Reset
Power Color
x51 Turbo base Micro processor
on Control
CompactFlash NAND
Host Data transfer Flash
Interface Type
Interface Control Memory
Flash
Interface
Data buffer Memory
CIS CCR ECC Logic Control/
Task Status
CIS: Card Information Structure

CCR: Card Configuration Register
ECC: Error Correcting Code
5.2 Flash Card Archive

According Card Capacity From
Power IC Reset IC Range 25MHz ~ 38MHz
Host Interface
Controller
Flash Memory
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6. Specification and Features

6.1 Electrical Specification
6.1.1 Absolute Maximum Ratings

SYMBOL PARAMETER RATING UNITS
VCC Power supply -0.3 to 6 V
VIN Input voltage -0.3 to VCC + 0.3 V
VOUT Output voltage -0.3 to VCC+ 0.3 V
TSTG Storage temperature -50 to 90 ℃
Topr Operating temperature -40 to 85 ℃
6.1.2 General DC Characteristic

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CIN Input capacitance 15 pF
COUT Output capacitance 15 pF
6.1.3 DC Electrical Characteristics for 5 Volts Operation

VIN Input voltage 0 VCC V
VCC Power supply 4.5 5.0 5.5 V
TSTG Storage temperature -50 90 ℃
TOPR Operating temperature -40 85 ℃
VIL Input low voltage CMOS 0.8 V
VIH Input high voltage CMOS 2.4 V
VOL Output low voltage IOL=8mA 0.4 V
VOH Output high voltage IOH=-8mA VCC – 0.8 V
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6.1.4 DC Electrical Characteristics for 3.3 Volts Operation

VIN Input voltage 0 VCC V
VDD Power supply 3.0 3.3 3.6 V
TSTG Storage temperature -50 90 ℃
TOPR Operating temperature -40 85 ℃
VIL Input low voltage CMOS 0.6 V
VIH Input high voltage CMOS 2.4 V
VOL Output low voltage IOL=8mA 0.4 V
VOH Output high voltage IOH=-8mA VDD – 0.8 V
6.1.5 Attribute Memory Read Timing Specification

Attribute Memory Read Timing 300 ns
Item Symbol IEEE Symbol
Read Cycle Time tc(R) tAVAV 300
Address Cycle Time ta(A) tAVQV 300
Card Enable Access Time ta(CE) tELQV 300

Output Enable Access Time ta(OE) tGLQV 150
Output Disable Time from CE tdis(CE) tEHQZ 100
Output Disable Time from OE tdis(OE) tGHQZ 100
Address Setup Time tsu (A) tAVGL 30
Output Enable Time from CE ten(CE) tELQNZ 5
Output Enable Time from OE ten(OE) tGLQNZ 5
Data Valid from Address Change tv(A) tAXQX 0
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6.1.6 Configuration Register(Attribute Memory)Write Timing Specification

Configuration Register(Attribute
250 ns
Memory)Write Timing
Item Symbol IEEE Symbol Min ns Max ns
Write Cycle Time tc(W) tAVAV 250
Write Pulse Width tw(WE) tWLWH 150
Address Setup Time tsu(A) tAVWL 30
Write Recovery Time trec(WE) tWMAX 30
Data Setup Time for WE tsu(D-WEH) tDVWH 80
Data Hold Time th(D) tWMDX 30
6.1.7 Common Memory Read Timing Specification

Output Enable Access Time ta(OE) tGLQV 125
Output Disable Time from OE tdis(OE) tGHQZ 100
Address Setup Time tsu(A) tAVGL 30
Address Hold Time th(A) tGHAX 20
CE Setup before OE tsu(CE) tELGL 0
CE Hold following OE th(CE) tGHEH 20
Wait Delay Falling from OE tv(WT-OE) tGLWTV 35
Data Setup for Wait Release tv(WT) tQVWTH 0
350 (3000 for
Wait Width Time tw(WT) tWTLWTH
CF+)
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6.1.8 Common Memory Write Timing Specification

Data Setup before WE tsu(D-WEH) tDVWH 80
Data Hold following WE th(D) tWMDX 30
WE Pulse Width tw(WE) tWLWH 150
Address Setup Time tsu(A) tAVWL 30
CE Setup before WE tsu(CE) tELWL 0
Write Recovery Time trec(WE) tWMAX 30
Address Hold Time th(A) tGHAX 20
CE Hold following WE th(CE) tGHEH 20
Wait Delay Falling from WE tv(WT-WE) tWLWTV 35
WE High from Wait Release tv(WT) tWTHWH 0
350 (3000 for
Wait Width Time tw (WT) tWTLWTH
CF+)
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6.1.9 I/O Input (Read) Timing Specification

Data Delay after IORD td(IORD) tlGLQV 100
Data Hold following IORD th(IORD) tlGHQX 0
IORD Width Time tw(IORD) tlGLIGH 165
Address Setup before IORD tsuA(IORD) tAVIGL 70
Address Hold following IORD thA(IORD) tlGHAX 20
CE Setup before IORD tsuCE(IORD) tELIGL 5
CE Hold following IORD thCE(IORD) tlGHEH 20
REG Setup before IORD tsuREG(IORD) tRGLIGL 5
REG Hold following IORD thREG(IORD) tlGHRGH 0
INPACK Delay Falling from IORD tdfINPACK(IORD) tlGLIAL 0 45
INPACK Delay Rising from IORD tdrINPACK(IORD) tlGHIAH 45
IOIS16 Delay Falling from Address tdfIOIS16(ADR) tAVISL 35
IOIS16 Delay Rising from Address tdrIOIS16(ADR) tAVISH 35
Wait Delay Falling from IORD tdWT(IORD) tlGLWTL 35
Data Delay from Wait Rising td(WT) tWTHQV 0
Wait Width Time 350 (3000 for
tw(WT) tWTLWTH
CF+)
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6.1.10 I/O Input (Write) Timing Specification

Data Setup before IOWR tsu(IOWR) tDVIWH 60
Data Hold following IOWR th(IOWR) tlWHDX 30
IOWR Width Time tw(IOWR) tlWLIWH 165
Address Setup before IOWR tsuA(IOWR) tAVIWL 70
Address Hold following IOWR thA(IOWR) tlWHAX 20
CE Setup before IOWR tsuCE(IOWR) tELIWL 5
CE Hold following IOWR thCE(IOWR) tlWHEH 20
REG Setup before IOWR tsuREG(IOWR) tRGLIWL 5
REG Hold following IOWR thREG(IOWR) tlWHRGH 0
IOIS16 Delay Falling from Address tdfIOIS16(ADR) tAVISL 35
IOIS16 Delay Rising from Address tdrIOIS16(ADR) tAVISH 35
Wait Delay Falling from IOWR tdWT(IOWR) tlWLWTL 35
IOWR high from Wait high tdrIOWR(WT) tWTJIWH 0
Wait Width Time
tw(WT) tWTLWTH 350
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6.1.11 True IDE Mode I/O (Read/Write) Timing Specification

True IDE Mode I/O
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
(Read/Write Timing item
(ns) (ns) (ns) (ns) (ns)
Specification)
t0 Cycle time (min) 600 383 240 180 120
Address Valid to -IORD/-IOWR
t1 70 50 30 30 25
setup (min)
t2 -IORD/-IOWR (min) 165 125 100 80 70
t2 -IORD/-IOWR (min) Register (8 bit) 290 290 290 80 70
t 2i -IORD/-IOWR recovery time (min) - - - 70 25
t3 -IOWR data setup (min) 60 45 30 30 20
t4 -IOWR data hold (min) 30 20 15 10 10
t5 -IORD data setup (min) 50 35 20 20 20
t6 -IORD data hold (min) 5 5 5 5 5
-IORD data tristate (max)
t6Z 30 30 30 30 30
Address valid to -IOCS16 assertion

t7 90 50 40 n/a n/a
(max)
Address valid to -IOCS16 released
t8 60 45 30 n/a n/a
(max)
t9 -IORD/-IOWR to address valid hold 20 15 10 10 10
Read Data Valid to IORDY active 0
tRD 0 0 0 0
(min), if IORDY initially low after tA
tA tA IORDY Setup time 35 35 35 35 35
tB IORDY Pulse Width (max) 1250 1250 1250 1250 250
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6.1.12 True IDE Ultra DMA Mode I/O (Read/Write) Timing Specification
UDMA UDMA UDMA UDMA UDMA
Name
Mode 0 (ns) Mode 1 (ns) Mode 2 (ns) Mode 3 (ns) Mode 4 (ns)
Min Max Min Max Min Max Min Max Min Max
t2CYCTYP 240 160 120 90 60
CYC 112 73 54 39 25
t2CYC 230 153 115 86 57
tDS 15.0 10.0 7.0 7.0 5.0
tDH 5.0 5.0 5.0 5.0 5.0
tDVS 70.0 48.0 31.0 20.0 6.7
tDVH 6.2 6.2 6.2 6.2 6.2
tCS 15.0 10.0 7.0 7.0 5.0
tCH 5.0 5.0 5.0 5.0 5.0
tCVS 70.0 48.0 31.0 20.0 6.7
tCVH 6.2 6.2 6.2 6.2 6.2
tZFS 0 0 0 0 0
tDZFS 70.0 48.0 31.0 20.0 6.7
tFS 230 200 170 130 120
tLI 0 150 0 150 0 150 0 100 0 100
tMLI 20 20 20 20 20
tUI 0 0 0 0 0
tAZ 10 10 10 10 10
tZAH 20 20 20 20 20
tZAD 0 0 0 0 0
tENV 20 70 20 70 20 70 20 55 20 55
tRFS 75 70 60 60 60
tRP 160 125 100 100 100
tIORDYZ 20 20 20 20 20
tZIORDY 0 0 0 0 0
tACK 20 20 20 20 20
tSS 50 50 50 50 50
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6.1.12.1 Ultra DMA Data-In Burst Initiation Timing
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6.1.12.2 Sustained Ultra DMA Data-In Burst Timing
6.1.12.3 Ultra DMA Data-In Burst Host Pause Timing
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6.1.12.4 Ultra DMA Data-In Burst Device Termination Timing
6.1.12.5 Ultra DMA Data-In Burst Host Termination Timing
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6.1.12.6 Ultra DMA Data-In Burst Host Termination Timing
6.1.12.7 Sustained Ultra DMA Data-Out Burst Timing
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6.1.12.8 Ultra DMA Data-Out Burst Device Pause Timing
6.1.12.9 Ultra DMA Data-Out Burst Device Termination Timing
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6.1.12.10 Ultra DMA Data-Out Burst Host Termination Timing
6.2 Power Management
6.2.1 Normal Mode

The host can reduce the power consumption of the card by changing its status with the following Power
Command.
Sleep mode consumes the lowest power. Response time for the card to change from sleep mode to the active
state is about 30 ms or less.
Standby mode, the response time is about 5ms or less. This is due to the interface of the card that accepts the
command although can't access the media immediately
Idle mode, the card can respond and access the media immediately. The card needs longer time in this mode
than in its active mode in order to active several circuits that were not used in the active mode.
Active mode, the card can respond and access the media immediately, and the commands are processed with
no delay.
6.2.2 Power down Mode

This card can set itself into Power Down mode. To enable this mode, it is needed to use the Information
Change command, which is a vender unique command. The advantage of using this mode is the ability to
move automatically into Sleep mode after command completion.
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6.3 Physical Specification
6.3.1 CompactFlash CF Type I
6.3.2 CompactFlash CF Type II
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7. Pin Assignment
7.1 CompactFlash Pin Type
PC Card Memory Mode PC Card I/O Mode True IDE Mode
No. Pin Name I/O No. Pin Name I/O No. Pin Name I/O
1 GND 1 GND 1 GND
2 D03 I/O 2 D03 I/O 2 D03 I/O
3 D04 I/O 3 D04 I/O 3 D04 I/O
4 D05 I/O 4 D05 I/O 4 D05 I/O
5 D06 I/O 5 D06 I/O 5 D06 I/O
6 D07 I/O 6 D07 I/O 6 D07 I/O
7 CE1# I 7 CE1# I 7 CS0# I
8 A10 I 8 A10 I 8 A10 I
9 OE# I 9 OE# I 9 ATASEL# I
10 A09 I 10 A09 I 10 A09 I
11 A08 I 11 A08 I 11 A08 I
12 A07 I 12 A07 I 12 A07 I
13 VCC 13 VCC 13 VCC
14 A06 I 14 A06 I 14 A06 I
15 A05 I 15 A05 I 15 A05 I
16 A04 I 16 A04 I 16 A04 I
17 A03 I 17 A03 I 17 A03 I
18 A02 I 18 A02 I 18 A02 I
19 A01 I 19 A01 I 19 A01 I
20 A00 I 20 A00 I 20 A00 I
21 D00 I/O 21 D00 I/O 21 D00 I/O
22 D01 I/O 22 D01 I/O 22 D01 I/O
23 D02 I/O 23 D02 I/O 23 D02 I/O
24 WP O 24 IOIS16# O 24 IOCS16# O
25 CD2# O 25 CD2# O 25 CD2# O
26 CD1# O 26 CD1# O 26 CD1# O
27 D11 I/O 27 D11 I/O 27 D11 I/O
28 D12 I/O 28 D12 I/O 28 D12 I/O
29 D13 I/O 29 D13 I/O 29 D13 I/O
30 D14 I/O 30 D14 I/O 30 D14 I/O
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PC Card Memory Mode PC Card I/O Mode True IDE Mode

31 D15 I/O 31 D15 I/O 31 D15 I/O
32 CE2# I 32 CE2# I 32 CS1# I
33 VS1# O 33 VS1# O 33 VS1# O
34 IORD# I 34 IORD# I 34 IORD# I
35 IOWR# I 35 IOWR# I 35 IOWR# I
36 WE# I 36 WE# I 36 WE# I
37 RDY/BSY# O 37 IREQ O 37 INTRQ O
38 VCC 38 VCC 38 VCC
39 CSEL# I 39 CSEL# I 39 CSEL# I
40 VS2# O 40 VS2# O 40 VS2# O
41 RESET I 41 RESET I 41 RESET# I
42 WAIT# O 42 WAIT# O 42 IORDY O
43 INPACK# O 43 INPACK# O 43 RFU*1 O
44 REG# I 44 REG# I 44 RFU*1 I
45 BVD2 I/O 45 SPKR# I/O 45 DASP# I/O
46 BVD1 I/O 46 STSCH#G I/O 46 PDIAG# I/O
47 D08 I/O 47 D08 I/O 47 D08 I/O
48 D09 I/O 48 D09 I/O 48 D09 I/O
49 D10 I/O 49 D10 I/O 49 D10 I/O
50 GND 50 GND 50 GND
Note: 1. RFU is Reserved for Feature Use
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7.2 Signal Description

Signal Name Description I/O Pin
VCC 5V , 3.3V 13,38
(PC Card Memory Mode)
(PC Card I/O Mode)
(True IDE Mode)
GND Ground. 1,50
(PC Card I/O Mode)
(True IDE Mode)
A0-A10 These address lines along with the #REG signal are I 8,10,11,12,
(PC Card Memory Mode) used to select the I/O port address registers within the 14,15,16,17,
card, the memory mapped port address registers 18,19,20
within the Card, a byte in the card's information
structure and its configuration control and status
registers.
A0-A10 This signal is the same as the PC Card Memory Mode
(PC Card I/O Mode) signal.
A0-A10 In True IDE Mode only A0-A2 are used to select the
(True IDE Mode) one of eight registers in the ATA Task File, the other
address lines should be grounded.
D0-D15 These lines carry the Data, Commands and Status I/O 2,3,4,5,6,
(PC Card Memory Mode) between the host and controller. D00 is the LSB of the 21,22,23,27,
(PC Card I/O Mode) even byte of the word. D08 is the LSB of the odd byte 28,29,30,31,
of the word. 47,48,49
D0-D15 In True IDE Mode, all Task File operations occur in
(True IDE Mode) the byte mode on the low order D00-D07 while all
data transfers are 16 bits using D00-D15.
CD1#, CD2# These Card Detect pins are connected to ground on O 25,26
(PC Card Memory Mode) this card and used by the host to determine that the
(PC Card I/O Mode) card is fully inserted into the socket.
(True IDE Mode)
VS1#,VS2# Voltage Sense Signals. O 33,40
(PC Card I/O Mode)
(True IDE Mode)
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CSEL# This signal is not used for this mode. I 39
CSEL# This signal is not used of this mode.
(PC Card I/O Mode)
CSEL# This internally pulled up signal is used to configure
(True IDE Mode) this card as a Master or a Slave. When this pin is
grounded, this card is Master. When this pin is open,
this card is Slave.
CE1#,CE2# These signals are used both to select the card and to I 7,32
(PC Card Memory Mode) indicate to the card whether a byte or a word
(PC Card I/O Mode) operation is being performed. #CE2 always accesses
the odd byte of the word. #CE1 accesses the even
byte or the odd byte of the word depending on A0 and
#CE2.
CS0#, CS1# In the True IDE Mode, #CS0 is the chip select for the
(True IDE Mode) Task File Registers while #CS1 is used to select the
Alternate Status and the Device Control Register.
BVD1 This signal is asserted high as the BVD1 signal since I/O 46
(PC Card Memory Mode) a battery is not used with this card.
STSCHG# This signal is asserted low to alert the host to changes
(PC Card I/O Mode) in the RDY/#BSY and Write Protect states, while the
I/O interface is configured. The Card Configure and
Status Register will control it.
PDIAG# In the True IDE Mode, this I/O is the Pass Diagnostic
(True IDE Mode) signal in the Master/Slave handshake protocol.
BVD2 This signal is always driven to a high state in Memory I/O 45
(PC Card Memory Mode) Mode since a battery is not required for this card.
SPKR# This signal is always driven to a high state in I/O
(PC Card I/O Mode) Mode since this card does not support the audio
function.
DASP# In the True IDE Mode, this I/O is the Disk
(True IDE Mode) Active/Slave Present signal in the Master/Slave
handshake protocol.
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OE# This is an Output Enable Strobe generated I 9
(PC Card Memory Mode) by the host interface. It is used to read
data from the card in Memory Mode and
to read CIS and configuration registers.
OE# In I/O Mode, this signal is used to read the
(PC Card I/O Mode) CIS and configuration registers.
|ATASEL# To enable True IDE Mode, this signal
(True IDE Mode) should be grounded.
RESET When the signal is high, the signal Resets I 41
(PC Card Memory Mode) the card.
RESET When the signal is high, the signal Resets
(PC Card I/O Mode) the card.
RESET# In the True IDE Mode, the signal is the
(True IDE Mode) active low hardware reset from the host.
REG# This signal is used during Memory Cycle I 44
(PC Card Memory Mode) to distinguish between Common Memory
and Attribute Memory accesses. High for
Common Memory and Low for Attribute
Memory.
REG# This signal must be low during I/O Cycles
(PC Card I/O Mode) when the I/O address is on the Bus.
RFU In the True IDE Mode, this signal is not
(True IDE Mode) used and should be connected to VCC by
the host.
WE# This signal is driven by the host and used I 36
(PC Card Memory Mode) for generating memory write cycle to the
registers of the card when the card is
configured in the Memory mode.
WE# In I/O mode, this signal is used for writing
(PC Card I/O Mode) the configuration registers.
WE# In the True IDE Mode, this signal is not
(True IDE Mode) used and should be connected to VCC by
the host.
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WAIT# This signal is driven low by the card to O 42

(PC Card Memory Mode) notify the host to delay completion of the
(PC Card I/O Mode) memory of I/O cycle that is in progress.
IORDY In the True IDE Mode, this signal may be

(True IDE Mode) used as IORDY.
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Signal Name I/O Pin Description

INPACK# O 43 This signal is not used in this mode.
INPACK# The Input Acknowledge signal is asserted when the card is
(PC Card I/O Mode) selected and responds to an I/O read cycle at the address on the
address bus.
RFU In the True IDE mode, this signal is not used.
(True IDE Mode)
IORD# I 34 This signal is not used in this mode.
IORD# This is an I/O Read strobe generated by the host. This signal
(PC Card I/O Mode) gates I/O data onto the bus from the card when the card is
configured to use the I/O interface.
IORD# In the True IDE mode, the signal is the same as the I/O Mode.
(True IDE Mode)
IOWR# I 35 This signal is not used in this mode
IOWR# The I/O Write strobe is used to clock I/O data on the Data bus
(PC Card I/O Mode) into the card controller registers when the card is configured to
use the I/O interface.
IOWR# In the True IDE Mode, this signal is the same as the I/O mode.
(True IDE Mode)
RDY/BSY# O 37 In the Memory Mode, this signal is set high when card is
(PC Card Memory Mode) ready to accept a new data transfer operation and held low
when the card is busy.
IREQ# I/O Operation. After the card has been configured for I/O
(PC Card I/O Mode) Mode, this signal is used as Interrupt Request.
INTRQ In the True IDE Mode, this signal is the active high Interrupt
(True IDE Mode) Request to the host.
WP O 24 Memory Mode, the card doesn't have a write protect switch.
(PC Card Memory Mode) This signal is held low.
IOIS16# I/O Mode, A low signal indicates that a 16 bits or odd byte
(PC Card I/O Mode) only operation can be performed by the addressed port.
IOCS16# In the True IDE Mode, this signal is asserted low when this
(True IDE Mode) device is expecting a word data transfer cycle.
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Card Industrial Application
8. CIS and Functions Configuration Registers

Configuration register specifications
This card supports four Configuration registers for the purpose of the configuration and observation of
this card. These registers can be used in memory and I/O card mode. In True IDE mode, these register
can not be used.
8.1 Configuration Option Register (200H)

This register is used for the configuration of the card and allows issuing software reset through this
register.
<Reset value = 00H>
D7 D6 D5 D4 D3 D2 D1 D0
SRESET LevlREQ INDEX
R/W R/W R/W
Index Those bits are used for selecting an operation mode of the card as follows.
When Power on, Card Hard Reset and Soft Rest, this data is “000000” for the Memory mode
card interface recognition.
LevlREQ This bit sets to “0” when pulse mode interrupt is selected, and sets to “1” when level mode
interrupt is selected.
SRESET Setting this bit to “1”, places the card in the reset state (Card Hard Reset).This operation is
equal to Hard Reset, except this bit is not cleared. Card configuration status is reset and the
card internal initialized operation starts when Card Hard Reset is executed, so next access to
the card should be the same sequence as the power on sequence.
Index Bits Assignment
INDEX bits
Task File register address Mapping mode
5 4 3 2 1 0
0 0 0 0 0 0 OH to FH, 400h to 7FFH Memory mode
0 0 0 0 0 1 xx0H to xxFH Independent I/O mode

1F0H to 1F7H, 3F6H to
0 0 0 0 1 0 Primary I/O mapped
3F7H
170H to 177H, 376H to
0 0 0 0 1 1 Secondary I/O mapped
377H
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8.2 Card Configuration And Status Register (Address 202H)

This register is used for observing the card state.
<Reset value = 00H>
D7 D6 D5 D4 D3 D2 D1 D0
CHGED SIGCHG IOIS8 0 0 PWD INTR 0
R R/W R/W --- --- R/W R ---
INTR INTERRUPT: When set, indicates that the #IREQ pin is low. When clear, indicates that the
#IREQ pin is high. This bit state is available whether I/O card interface has been configured
or not. If interrupts are disabled by the #IEN bit in the Device Control Register, this bit is
zero.
PWD POWER DOWN: When set, the card enters sleep state (Power Down mode). When clear,
the card transfers to idle state (active mode).
IOIS8 I/O IS 8 bit: When set, indicates that the data bus width of the host is 8 bits (D0-D7). When
clear, indicates that the data bus width of the host is 16 bits (D0-D15).
SIGCHG SIGNAL CHGED: This bit is set and reset by the host to enable and disable a state-change
signal from the Status Register, the CHANGED bit control pin 46 and the CHANGED
Status signal. If no state change signal is desired, this bit should be set to zero (0) and pin 46
(#STSCHG) signal will be held high while thie card is configured for I/O.
CHGED Indicated that one or both of the pin Replacement Register (204H) Crdy, or CWProt bits are
set to one (1). When changed bit is set, #STSCHG pin 46 is held low if the SIGCHG bit is a
one (1) and the card is configured for I/O interface.
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8.3 Pin Replacement Register (Address 204H)

This register is used for providing the signal state of #IREQ signal when the card configured I/O card interface.
<Reset value = 0CH>
D7 D6 D5 D4 D3 D2 D1 D0
0 0 CRDY 0 1 1 RRDY RWProt
--- R/W --- R/W 0
RWProt READ WRITE PROTECT: this bit indicates the write protect status. When set, indicates
write protect. When cleared indicates write is enable.
PRDY This bit is used to determine the internal state of the RDY/BSY signal. This bit may be used
to determine the state of the Ready/Busy as this pin has been reallocated for use as interrupt
Request on an I/O card.
CEProt This bit is set to one (1) when RWProt changes state. This bit may be written by the host.
CRDY CARD READY: This bit is set to one (1) when the READY bit changes state. This bit may
be written by the host.
8.4 Socket and Copy Register (Address 206H)

This register is used for identification of the card from other cards. The host can read and write this
register. The host shall set this register before the card’s Configuration Option Register is set.
<Read, Reset value = 00H>

D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 DRV# 0 0 0 0
--- --- --- R/W --- --- --- ---
DRV# DRIVE NUMBER: This bit is set by the host and compared to the DRV bit (D4), in the
ATA Drive/Head Register. In this way, host can perform the card’s master/slave
organization.
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8.5 Card Information Structure (CIS)

The CIS is attribute information of the card and its characteristics, which includes information about the
type of card and the manufacturer. The CIS is allocated in the beginning of the attribute memory, between
addresses 0 and 255. The data is allocated in the even addresses only. The Host uses these registers to
initialize and configure the card.
Address Data 7 6 5 4 3 2 1 0 Description of contents CIS function
000H 01H CISTPL_JEDEC Device info tuple Tuple code
002H 04H TPL_LINK Link length is 4 byte Link to next tuple
004H 02H Device type W Device speed Device type= DH: I/O device Device type, WPS, speed
P WPS=1:No WP
S Device Speed=7: ext speed
006H 79H EXT Speed Speed 400 ns if not wait Extended speed
Mantissa exponent
008H 01H 1x 2k units 2k byte of address space Device size
00AH FFH List end marker End of device End marker
00CH 1CH CISTP_DEVICE_OC Other conditions device info tuple Tuple code
00EH 04H TPL_LINK Link length 4 bytes Link to next tuple
010H 02H EXT Reserved Vcc MWAIT 3V, wait is not used Other conditions info field
012H DBH Device type W Device speed Device type= DH: I/O device Device type, WPS, speed
P WPS=1:No WP
S Device Speed=1:250 ns
014H 01H 1x 2k units 2k byte of address space Device size
016H FFH List end marker End of device END marker
018H 18H CISTPL_JEDEC_C JEDEC ID common memory Tuple code
01AH 02H TPL_LINK Link length is 2 bytes Link to next tuple
PCMCIA’s manufacturer’s
01CH DFH Manufacturer’s ID code JEDEC ID of PC Card ATA
JEDEC ID Code
01EH 01H PCMCIA JEDEC device code 2nd byte of JEDEC ID
020H 20H CISTPL_MANFID Manufacturer’s ID code Tuple code
022H 04H TPL_LINK Link length is 4 bytes Link to next tuple
Low byte of PCMCIA Low byte of manufacturer’s ID
024H 45H manufacturer’s ID
manufacturer’s code code
High byte of PCMCIA Code of 0 because other byte is High byte of manufacturer’s ID
026H 00H
manufacturer’s code JEDEC 1 byte manufacturer’s ID code
028H 01H Low byte of product code Low byte of product code
For PC CARD ATA
02AH 04H High byte of product code High byte of product code
02CH 15H CISTPL_VERS_1 Level 1 version/product info Tuple code
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02EH 1AH T P L _ L I N K Link length is 26 bytes Link to next tuple
030H 04H T P P L V 1 _ M A J O R PCMCIA2.0/JEIDA4.1 Major version
032H 01H T P P L V 1 _ M I N O R PCMCIA2.0/JEIDA4.1 Minor version
034H 43H ‘C’ Info string 1
036H 46H ‘F’
038H 20H ‘’
03AH 43H ‘C’
03CH 61H ‘a’
03EH 72H ‘r’
040H 64H ‘d’
042H 00H Null terminator
044H 43H ‘C’ Info string 2
046H 46H ‘F’
048H 41H ‘A’
04AH 20H ‘’
04CH XXH ‘X’ According for card capacity.
04EH XXH ‘X’
050H XXH ‘X’
052H XXH ‘X’
054H 4DH ‘M’
056H 42H ‘B’
058H 20H ‘‘
05AH 43H ‘C’
05CH 4BH ‘K’
05EH 52H ‘S’
060H 00H Null terminator
062H FFH L i s t e n d m a r k e r End of device END marker
064H 21H C I S T P L _ F U N C I D Function ID tuple Tuple code
066H 02H T P L _ L I N K Link length is 2 bytes Link to next tuple
068H 04H TPLFID_FUNCTION=04H Disk function, may be silicon, may be PC card function code
removable
06AH 01H Reserved R P R=0: No BIOS ROM System initialization byte
P=1: Configure card at power on
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06CH 22H C I S T P L _ F U N C E Function extension tuple Tuple code
06EH 02H T P L _ L I N K Link length 2 bytes Link to next tuple
070H 01H Disk function extension tuple type Disk interface type Extension tuple type for disk
072H 01H D i s k i n t e r f a c e t y p e PC card ATA interface Interface type
074H 22H C I S T P L _ F U N C E Function extension tuple Tuple code
078H 02H Disk function extension tuple type Single drive Extension tuple type for disk
07AH 0CH Reserve D U S V No Vpp< Silicon, single drive Basic ATA option
V=0: No Vpp required Parameter byte 2
S=1: Silicon
U=1: Unique serial#
D=0: Single drive on card
07CH 0FH R I E N P 3 P 2 P 1 P 0 P0: Sleep mode supported Basic ATA option parameter
P1: Standby mode supported byte 2
P2: Idle mode supported
P3: Drive auto power control
N: Some config excludes 3X7
E: Index bit is emulated
I: Twin IOIS 16# datd reg only
R: Reserved
07EH 1AH C I S T P L _ C O N F I G Configuration tuple Tuple code
082H 01H RFS RMS R A S RFS: Reserved Size of fields byte TPCC_SZ
RMS: TPCC_RMSK size-1=0
RAS:TPCC_RADR size-1=1
1 byte register mask
2 b2 byte config base address
084H 03H T P C C _ L A S T Entry with config index of 03H is Last entry of config registers
final entry in table
086H 00H T P C C _ R A D R ( L S B ) Configuration registers are located at Location of config registers
200H in REG space
088H 02H TPCC_RADAR(MSB)
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08AH 0FH Reserved S P C I I: Configuration index Configuration registers present
C: configuration and status mask TPCC_RMSK
P: Pin replacement
S: Socket and copy
08CH 1BH CISTPL_CFTABLE_ENTRY Configuration table entry tuple Tuple code
08EH 08H T P L _ L I N K Link length is 8 bytes Link to next tuple
090H C0H I D Configuration Index Memory mapped I/O configuration Configuration table index byte
I=1: Interface byte follows TPCE_INDX
D=1: Default entry
Configuration index=0
092H 40H W R P B Interface type W=0: Wait not used Interface description field
R=1: Ready active TPCE_IF
P=0: WP not used
B=0: BVD1and BVD2 not used
IF type=0: Memory interface
094H A1H M MS IR IO T P M=1: Misc info present Feature selection
MS=01: Memory space info single TPCE_FS
2-byte length
IR=0: No interrupt info present
IO=0: No I/O port info present
T=0: No toming info present
P=1: Vcc only info
096H 01H R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for Vcc
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
098H 55H X Mantissa E x p o n e n t Nominal voltage=5V Vcc nominal value
TCADO-SCF-000018.4 44/139 0605V4

09AH 08H Length in 256 bytes pages (LSB) Length of memory space is 2 KB Memory space description
structures (TPCE_MS)
09CH 00H Length in 256 bytes pages (MSB)
09EH 20H X R P R O A T X=0: No more misc fields Miscellaneous features field

R: Reserved TPCE_MI
P=1: Power down supported
RO=0: Not read only mode
A=0: Audio not supported
T=0: Single drive
0A0H 1BH CISTPL_CFTABLE_ENTRY Configuration table entry tuple Tuple code
0A2H 06H T P L _ L I N K Link length is 6 bytes Link to next tuple
0A4H 00H I D Configuration Index Memory mapped I/O configuration Configuration table index
I=0: No interface byte TPCE_INDX
D=0: No Default entry
0A6H 01H M MS IR IO T P M=0: No misc info Feature selection byte
MS=00: No memory space inflo TPCE_FS
T=0:No timing info present
P=0: Vcc only info
0A8H 21H R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for Vcc
R: Reserved
0AAH B5H X Mantissa E x p o n e n t Nominal Voltage=3.0V Vcc nominal value
0ACH 1EH X E x t e n s i o n +0.3 V Extension byte
TCADO-SCF-000018.4 45/139 0605V4


0AEH 4DH X Mantissa Exponent Max average current over 10 msec is Max. average current
45 mA
0B0H 1BH CISTPL_CFTABLE_ENTRY Configuration table entry tuple Tuple code
0B2H 0AH TPL_LINK Link length is 10 bytes Link to next tuple
0B4H C1H I D Configuration INDEX Contiguous I/O mapped ATA registers Configuration table index byte
configuration TPCE_INDX
I=1: Interface byte follows
D=1: Default entry
0B6H 41H W R P B Interface type W=0: Wait not used Interface description field
P=0: WP not used
B=0: BVS1 and BVS2 not used
IF type=1: I/O interface
0B8H 99H M MS IR IO T P M=1: Misc info present Feature selection byte
MS=00: No memory space info TPCE_FS
IR=1: Interrupt info present
IO=1: I/O port info present
T=0: No timing info present
P=1:Vcc only info
0BAH 01H R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for Vcc
R: Reserved
0BCH 55H X Mantissa Exponent Nominal Voltage=5V Vcc nominal value
0BEH 64H R S E IO AddrLine S=1: 16-bit hosts supported I/O space description field
E=1: 8-bit hosts supported TPCE_IO
IO AddrLine:4 lines decoded
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0C0H F0H S P L M V B I N S=1: Share logic active Interrupt request description
P=1: Pulse mode IRQ supported structure TPCE_IR
L=1: Level mode IRQ supported
M=1: Bit mask of IRQ present
V=0: No vender unique IRQ
B=0: No bus error IRQ
I=0: No IO check IRQ
N=0: No NMI
0C2H FFH IRQ IR IR IR IR IR OR IRQ0 IRQ level to be routed 0 to 15 Mask extension byte 1
7 Q Q Q Q Q Q recommended TPCE_IR
6 5 4 3 2 1
0C4H FFH IRQ IR IR IR IR IR OR IRQ8 Recommended routing to any Mask extension byte 2
15 Q Q Q Q Q Q “normal, maskable” IRQ TPCE_IR
14 13 12 11 10 9
0C6H 20H X R P R O A T X=0: Nomore misc fields Miscellaneous features field
R: reserved TPCE_MI
A=0: Audi not supported
T=0: Single drive
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0C8H 1BH CISTPL_CFTABLE_ENTRY Configuration table entry tuple Tuple code
0CAH 06H T P L _ L I N K Link length is 6 bytes Link to next tuple
0CCH 01H I D Configuration index Contiguous I/O mapped ATA registers Configuration table index byte
I=0: No Interface byte
0CEH 01H M MS IR IO T P M=0: No Misc info present Feature selection byte
IR=0: No Interrupt info present
P=1:Vcc only info
0D0H 21H R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for Vcc
R: Reserved
0D2H B5H X M a n t i s s a E x p o n e n t Nominal voltage =3.0V Vcc nominal value
0D4H 1EH X E x t e n s i o n +0.3V Extension byte
0D6H 4DH X M a n t i s s a E x p o n e n t Max average current over 10 msec is Max. average current
45mA
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0D8H 1BH CISTPL_CFTABLE_ENTRY Configuration table entry tuple Tuple code
0DAH 0FH T P L _ L I N K Link length is 15 bytes Link to next tuple
0DCH C2H I D Configuration index Contiguous I/O mapped ATA registers Configuration table index byte
I=1: Interface byte follows
D=1: Default entry follows
0E0H 41H W R P B Interface type W=0: Wait not used Interface description field
P=0: WP not used
0E2H 99H M MS IR IO T P M=1: Misc info present Feature selection byte
P=1:Vcc only info
0E4H 01H R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for Vcc
R: Reserved
0E6H 55H X Mantissa E x p o n e n t Nominal Voltage=5V Vcc nominal value
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0E8H EAH R S E I O A d d r L i n e R=1: Range follows I/O space description field
S=1:16-bit hosts supported E=1: 8-bit TPCE_IO
hosts supported
IO AddrLines: 10 lines decoded
0EAH 61H
0ECH FOH 1st I/O base address(LSB) 1st I/O range address
0EEH 01H 1st I/O base address(MSB)
0F0H 07H 1st I/O length-1 1st I/O range length
0F2H F6H 2nd I/O base address(LSB) 2nd I/O range address
0F4H 03H 2nd I/O base address(MSB)
0F6H 01H 2nd I/O length-1 2nd I/O range length
0F8H EEH S P L M I R Q l e v e l S=1: Share logic active Interrupt request description
IRQ level is ORQ 14
0FAH 20H X R P R O A T X=0: Nomore misc fields Miscellaneous features field
R: reserved TPCE_MI
T=0: Single drive
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0FEH 1BH CISTPL_CFTABLE_ENTRY Configuration table entry tuple Tuple code
0FCH 06H T P L _ L I N K Link length is 15 bytes Link to next tuple
100H 02H I D Configuration index ATA primary I/O mapped Configuration table index byte
102H 01H M MS IR IO T P M=0: No Misc info Feature selection byte
P=1: Vcc only info
R: Reserved
106H B5H X M a n t i s s a E x p o n e n t Nominal voltage =3.0V Vcc nominal value
108H 1EH X E x t e n s i o n +0.3V Extension byte
10AH 4DH X M a n t i s s a E x p o n e n t Max average current over 10 msec is Max. average current
45mA
10CH 1BH CISTPL_CFTABLE_ENTRY Configuration table entry tuple Tuple code
10EH 0FH T P L _ L I N K Link length is 15 bytes Link to next tuple
110H C3H I D Configuration index ATA secondary I/O mapped Configuration table index byte
I=1: Interface byte follow
D=1: Default entry
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114H 41H W R P B Interface type W=0: Wait not used Interface description field
P=0: WP not used
112H 99H M MS IR IO T P M=1: Misc info present Feature selection byte
P=1:Vcc only info
R: Reserved
118H 55H X Mantissa E x p o n e n t Nominal Voltage=5V Vcc nominal value
11AH EAH R S E I O A d d r L i n e R=1: Range follows I/O space description field
S=1:16-bit hosts supported E=1: 8-bit TPCE_IO
hosts supported
IO AddrLines: 10 lines decoded
11CH 61H LS AS N r a n g e LS=1: Size of lengths is 1 byte I/O range format description
AS=2: Size of address is 2 bytes
N Range=1: Address range-1
11EH 70H 1st I/O base address(LSB) 1st I/O range address
120H 01H 1st I/O base address(MSB)
122H 07H 1st I/O length-1 1st I/O range length
124H 76H 2nd I/O base address(LSB) 2nd I/O range address
126H 03H 2nd I/O base address(MSB)
128H 01H 2nd I/O length-1 2nd I/O range length
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12CH EEH S P L M I R Q l e v e l S=1: Share logic active Interrupt request description
IRQ level is ORQ 14
12AH 20H X R P R O A T X=0: Nomore misc fields Miscellaneous features field
R: reserved TPCE_MI
T=0: Single drive
12EH 1BH CISTPL_CFTABLE_ENTRY Configuration table entry tuple Tuple code
132H 03H I D Configuration index ATA secondary I/O mapped Configuration table index byte
134H 01H M MS IR IO T P M=0: No Misc info Feature selection byte
P=1: Vcc only info
R: Reserved
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140H B5H X M a n t i s s a E x p o n e n t Nominal voltage =3.0V Vcc nominal value
138H 1EH X Extension +0.3V Extension byte
142H 4DH X M a n t i s s a E x p o n e n t Max average current over 10 msec is Max. average current
45mA
144H 14H CISTPL_NO_LINK No link control tuple Tuple code
146H 00H Link is 0 bytes Link to next tuple
148H FFH CISTPL_END End of tuple Tuple code
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9. ATA Specific Register Definitions

As we described the adapter provides several kinds of addressing modes, Memory mode, I/O mode, and
True IDE. Below are described the procedures access for accessing each mode the Task File registers.
9.1 Memory Mapped Addressing

Memory Mapped Addressing
#REG Offset A10 A4 – A9 A3 A2 A1 A0 #OE = “0” #WE = “0”

1 0H 0 X 0 0 0 0 Even read data Even write data
1 1H 0 X 0 0 0 1 Error Feature
1 2H 0 X 0 0 1 0 Sector Count Sector Count
1 3H 0 X 0 0 1 1 Sector Number Sector Number
1 4H 0 X 0 1 0 0 Cylinder Low Cylinder Low
1 5H 0 X 0 1 0 1 Cylinder High Cylinder High
1 6H 0 X 0 1 1 0 Drive/Head Drive/Head
1 7H 0 X 0 1 1 1 Status Command
1 8H 0 X 1 0 0 0 Duplicate Even Duplicate Even
Read Data Write Data
1 9H 0 X 1 0 0 1 Duplicate Odd Duplicate Odd
1 DH 0 X 1 1 0 1 Duplicate Error Duplicate
Feature
1 EH 0 X 1 1 1 0 Alternate Status Device Control
1 FH 0 X 1 1 1 1 Drive Address Reserved
1 8H 1 X X X X 0 Even Read Data Even Write Data
1 9H 1 X X X X 1 Odd Read Data Odd Write Data
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9.2 Contiguous I/O Mapping Addressing

Contiguous I/O Mapping Addressing
#REG Offset A10 A4 – A9 A3 A2 A1 A0 #IORD = “0” #IOWR = “0”
0 0H 0 X 0 0 0 0 Even read data Even write data
0 1H 0 X 0 0 0 1 Error Feature
0 2H 0 X 0 0 1 0 Sector Count Sector Count
0 3H 0 X 0 0 1 1 Sector Sector Number
Number
0 4H 0 X 0 1 0 0 Cylinder Low Cylinder Low
0 5H 0 X 0 1 0 1 Cylinder High Cylinder High
0 6H 0 X 0 1 1 0 Drive/Head Drive/Head
0 7H 0 X 0 1 1 1 Status Command
0 8H 0 X 1 0 0 0 Duplicate Duplicate Even
Even Read Write Data
Data
0 9H 0 X 1 0 0 1 Duplicate Odd Duplicate Odd
0 DH 0 X 1 1 0 1 Duplicate Duplicate
Error Feature
0 EH 0 X 1 1 1 0 Alternate Device Control
Status
0 FH 0 X 1 1 1 1 Drive Address Reserved
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9.3 Overlapping I/O Mapping Addressing

Overlapping I/O Mapping (Primary, Secondary) Addressing
A4 – A9
#REG A10 A3 A2 A1 A0 #IORD= “0” #IOWR =“0”
Primary Secondary
Even read data Even write
0 X 1FH 17H 0 0 0 0
data
0 X 1FH 17H 0 0 0 1 Error Feature
0 X 1FH 17H 0 0 1 0 Sector Count Sector Count
Sector Sector
0 X 1FH 17H 0 0 1 1
Number Number
0 X 1FH 17H 0 1 0 0 Cylinder Low Cylinder Low
0 X 1FH 17H 0 1 0 1 Cylinder High Cylinder High
0 X 1FH 17H 0 1 1 0 Drive/Head Drive/Head
0 X 1FH 17H 0 1 1 1 Status Command
Alternate Device
0 X 3FH 37H 1 1 1 0
Status Control
0 X 3FH 37H 1 1 1 1 Drive Address Reserved
9.4 True IDE Mode

True IDE Mode
#CS0 #CS1 DA2 DA1 DA0 #IORD = “0” #IOWR = “0”

1 1 X X X Hi-Z Not Used
1 0 0 X X Hi-Z Not Used
1 0 1 0 X Hi-Z Not Used
0 0 X X X Invalid Invalid
1 0 1 1 0 Alternate Status Device Control
1 0 1 1 1 Device Address Not Used
0 1 0 0 0 Data Data
0 1 0 0 1 Error Feature
0 1 0 1 0 Sector Count Sector Count
0 1 0 1 1 Sector Number Sector Number
0 1 1 0 0 Cylinder Low Cylinder Low
0 1 1 0 1 Cylinder High Cylinder High
0 1 1 1 0 Drive/Head Drive/Head
0 1 1 1 1 Status Command
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9.5 ATA Registers
9.5.1 Data Register

The Data register is a 16-bit register used to transfer data blocks between the ATA data buffer and the host.
In addition, the Format Track command uses this register to transfer the sector-information. Setting this
mode requires calling the Set Features command.
bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0

D7 D6 D5 D4 D3 D2 D1 D0

D15 D14 D13 D12 D11 D10 D9 D8
9.5.2 Error Register

The Error Register contains additional information about the source of an error. The information in the
register is only valid when an error is indicated in ERR-bit (bit-0 = 1) of the Status Register. This register is
valid when the BSY bit in Status register and Alternate status register are set to “0”(Ready).

BBK UNC MC[0] IDNF MCR[0] ABRT T0NF[0] AMNF
BBK Bad Block mark detected in the requested sector ID field - Not
supported
UNC Non-Correctable data error encountered
MC[0] Removable media access ability has changed - not supported (is 0)
IDNF Requested sector ID-field Not Found
MCR[0] Media Change Request indicates that the removable-media drive's
latch has changed, indicating that the user wishes to remove the
media - not supported (is 0)
ABRT Drive status error or Aborted invalid command
T0NF[0] Track 0 Not Found during a Recalibrate command - Not
supported
AMNF Address Mark Not Found after finding the correct ID field - Not
supported
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9.5.3 Feature Register

This register enables drive-specific features. See the Set Features or Get/Set Features command
descriptions.

Feature byte
9.5.4 Sector Count Register

The Sector Count Register contains the number of data sectors requested to be transferred during a read or
write operation between the host and the adapter. A zero register value specifies 256 sectors. The
command was successful if this register is zero at command completion. If the request is not completed,
the register contains the number of sectors left to be transferred.
This register’s initial values is “01H”
Some commands (e.g. Initialize Drive Parameters or Format Track) may redefine the register’s contents.)

Sector count byte
9.5.5 Sector Number Register

In the CHS (Cylinder, Head, Sector) mode, the Sector Number register contains the subsequent command's
starting sector number, which can be from 1 to the maximum number of sectors per track. In LBA (logical
block address) mode, this register contains LBA bits 0-7, which are updated at command completion. See
the command descriptions for register contents at command completion (whether successful or
unsuccessful).

SN7 SN6 SN5 SN4 SN3 SN2 SN1 SN0
LBA7 LBA6 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0
SN0 – SN7 Sector number byte (8-bits)
LBA0 – LBA7 LBA bits 0 to 7
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9.5.6 Cylinder Low Register

In the CHS mode, the Cylinder Low Register contains the cylinder number low-8 bits and reflects their
status at command completion. In LBA mode, this register contains LBA bits 8-15 and reflects their status
at command completion.

CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0
CL0 – CL7 Cylinder Low byte (8-bits)
9.5.7 Cylinder High Register

In the CHS mode, the Cylinder High Register contains the cylinder numbers high-8 bits and reflects their
status at command completion. In LBA mode, this register contains LBA bits 16-23 and reflects their status
at command completion.

CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
CH0 – CH7 Cylinder High byte (8-bits)
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9.5.8 Drive Head Register

The Drive/Head Register is used to select the drive and head (heads minus 1, when executing Initialize
Drive Parameters command). It is also used to select the LBA addressing instead of the CHS addressing.

1 LBA 1 DRV HS3 HS2 HS1 HS0
HS0-HS3/ Head number.
DRV Drive select number. When DRV=0, the master drive is selected.
When DRV=1, the Slave drive is selected.
LBA24-LBA27 MSB of the LBA addressing.
LBA Address mode select.
0 = CHS (Cylinder, Head, Sector) mode.
1 = LBA (Logical Block Address) mode.
Logical Block address interrupted as follows:
LBA07-LBA00 :Sector Number Register D7-D0
LBA15-LBA08:Cylinder Low Register D7-D0
LBA23-LBA16:Cylinder High Register D7-D0
LBA27-LBA24:Drive/Head Register HS3-HS0
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9.5.9 Status Register

This register contains the adapter status. The contents of this register are updated to reflect the current
state of the adapter and the progress of any command being executed by the adapter. When the BSY bit is
equal to zero, the other bits in this register are valid. When the BSY bit is equal to one, the other bits in this
register are not valid. When the register is read, the interrupt (#IREQ pin) is cleared.

BSY DRDY DWF DSC DRQ CORR 0 ERR
ERR When set, indicates that an error has occurred during the previous
command execution. The bits in the Error Register indicate the
cause.
IDX Index is not used – always set to Zero.
CORR Indicates that a data error was corrected; transfer is not
terminated.
DRQ Data Request. When set, indicates that the adapter is ready to
transfer a word or byte of data between the host and the adapter.
DSC Drive Seek Complete. When set, indicates that the requested
sector was found.
DWF Drive Write Fault status. When set, indicates that an error has
occurred during write.
DRDY Indicates whether the adapter is capable of performing drive
operations (commands). This bit is cleared at power up and
remains cleared until the drive is ready to accept a command. On
error, DRDY changes only after the host reads the Status register.
BSY This signal is set during the time the adapter accesses the
command buffer or the registers. During this time the host is
locked out from accessing the command register and buffer. As
long as this bit is set no bits in the register are valid.
9.5.10 Alternate Status Register

The Alternate Status Register contains command block status information (see Status register). Unlike the
Status register, reading this register does not acknowledge or clear an interrupt.

BSY DRDY DWF DSC DRQ CORR 0 ERR
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9.5.11 Device Control Register

The Device Control Register is used to control the drive interrupt request and issue an ATA soft reset to the
drive.

--- --- --- --- 1 SRST #IEN 0
#IEN INTERRUPT ENABLE: When set (0), it enables interrupts to
the host (using the #IREQ tri-state pin). When inactive (1) or
drive is not selected, it disables all pending interrupts (#IREQ in
high-Z). This bit is ignored in Memory mode.
SRST SOFT RESET: When set, forces the ATA to perform an AT disk
control soft reset operation.
9.5.12 Drive Address Register

This register reflects the drive and its heads. This register is provides for compatibility with the AT disk
interface. It’s recommended that this register is not mapped into this host’s I/O space because of potential
conflicts on bit7.

High-Z #WTG #HS3 #HS2 #HS1 #HS0 #DS1 #DS0
#DS0 When set (0), it indicates that drive 0 is active and selected.
#DS1 When set (0), it indicates that drive 1 is active and selected.
#HS0 - #HS3 Negation of the head number in the Drive/Head Register.
#WTG When set (0), it indicates that a write operation is in progress,
otherwise it is inactive (1) - not supported.
Note: Addressing Mode Descriptions - The adapter, on a command by command basis, can operate in
either CHS or LBA addressing modes. Identify Drive Information tells the host whether the drive supports
LBA mode. The host selects LBA mode via the Drive/Head Register. Sector number, Cylinder Low,
Cylinder High, and Drive/Head Register bits HS3=0 contain the zero-based LBA. The drive's sectors are
linearly mapped with: LBA = 0 => Cylinder 0, head 0, sector 1. Regardless of the translation mode, a sector
LBA address does not change. LBA = (Cylinder * no of heads + heads) * (sectors/track) + (Sector - 1).
TCADO-SCF-000018.4 63/139 0605V4

10. ATA Commands

10.1 Check Power Mode - 98H or E5H
This command checks the current power mode of the adapter. When this command is issued and the
adapter is in standby mode, or is being set to standby mode, or during a recovery from standby mode is
attempted, adapter sets the BSY bit in the Status register and sets the Sector Count Register to “00H”. Then
the BSY bit in the Status register is cleared. When the adapter is in the Idle mode, it sets the BSY bit in the
Status register and sets “FFH” in the Sector Count Register. Then the BSY bit in the Status register is
cleared. An interrupt is issued after the BSY bit is cleared.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count N/A
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Command 98H or E5H
OUTPUTS
Register 7 6 5 4 3 2 1 0
BSY DRDY DWF DSC DRQ CORR IDX ERR
Status
V V V V V V
Sector Count Power Mode Code.(00H or 80H or FFH)
BBK UNC MC IDNF MCR ABRT TK0NF AMNF
Error
V
TCADO-SCF-000018.4 64/139 0605V4

10.2 Execute Drive Diagnostic - 90H

This command performs self-diagnostics on various internal components of the adapter. Results of the test
are reported in the Error Register. Note that the bit definitions for the Error Register do not apply with this
command. Instead, the value in the Error Register is a diagnostic code, defined in the table below.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count N/A
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV
Command 90H
OUTPUTS: The diagnostic code written into the Error Register is an 8-bit code as shown in the table
below.
Register 7 6 5 4 3 2 1 0
Status
V V V V
Error Diagnostic code, see table below
Code Description
01H No error detected
02H Format Media error
03H Sector buffer error
04H ECC logic error
05H Controlling microprocessor error
TCADO-SCF-000018.4 65/139 0605V4

10.3 Erase Sector(s) - C0H

This command is processed as a NOP command.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count [LBA mode only] The number of sectors to be formatted on the track, must be
set to FFH
Sector Number [LBA mode only] LBA[7:0] of the first sector/LBA to transfer
Cylinder Low Cylinder[7:0] or LBA[15:8] of the first sector/LBA to transfer
Cylinder High Cylinder[15:8] or LBA[23:16] of the first sector/LBA to transfer
Device/Head LBA DEV H[3:0] or LBA[27:24] of the starting
sector/LBA
Command C0H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V
Error
V V V V
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10.4 Format Track - 50H

This command is processed as a NOP command.
INPUTS
Register 7 6 5 4 3 2 1 0
Features
Sector Count [LBA mode only] The number of sectors to be formatted on the track. Must be
set to FFH
Sector Number [LBA mode only] LBA[7:0] of the first sector/LBA to transfer
sector/LBA
Command 50H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V
Error
V V V
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10.5 Identify Drive – ECH

The Identify Drive command enables the host to receive parameter information from the adapter. When the
command is issued, the adapter sets the BSY bit, prepares to transfer the 256 words of adapter identification
data to the host, sets the DRQ bit, clears the BSY bit, and generates an interrupt. The host can then
transfer the data by reading the Data register. All reserved bits or words are all zero. See following table
for the identify drive information for this adapter
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count N/A
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV
Command ECH
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status V V V V V V
Error V
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10.6 Idle - 97H or E3H

Although this command is supported for backward compatibility, it has no actual function. The adapter will
always return a ‘good’ status at the completion of this command.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count Time-out Parameter. This parameter is ignored by the adapter
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV
Command 97H or E3H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V
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10.7 Idle Immediate - 95H or E1H

Although this command is supported for backward compatibility, it has no actual function. The adapter will
always return a ‘good’ status at the completion of this command.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count N/A
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV
Command 95H or E1H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V
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10.8 Initialize Drive Parameters - 91H

Initialize Drive Parameters allows the host to alter the number of sectors per track and the number of heads
per cylinder. This command does not check the validity of counts of sectors and heads. If an invalid value is
set, an error will be reported when another command attempts an invalid access.
The Sector Count Register specifies the number of logical sectors per logical track, and the Device/Head
register specifies the maximum head number.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count Number of sectors
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV Max Head (no. of head = 1)
Command 91H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V
Error
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10.9 Read Buffer - E4H

The Read Buffer command enables the host to read the current contents of the adapter’s sector buffer. This
command has the same protocol as the Read Sector(s) command.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count N/A
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head LBA DEV
Command E4H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V
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10.10 Read Long Sector(s) - 22H or 23H

Read Long (w/ and w/o retry) is similar to the Read Sectors command, except that the content of the Sector
Count Register is ignored and only one sector is read. The 512 data bytes and 4 ECC bytes are read into the
buffer (with no ECC correction) and then transferred to the host.
The Cylinder Low, Cylinder High, Device/Head and Sector Number specify the starting sector address to
be read. The Sector Count Register shouldn’t specify a value other than 1.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count The number of sectors/logical blocks to transfer. This should be set to 01 for
compatibility
Sector Number Sector[7:0] or LBA[7:0] of the sector/LBA to transfer
Cylinder Low Cylinder[7:0] or LBA[15:8] of the sector/LBA to transfer
Cylinder High Cylinder[15:8] or LBA[23:16] of the sector/LBA to transfer
Device/Head LBA DEV H[3:0] or LBA[27:24] of the
sector/LBA to transfer
Command 22H (retries enabled) or 23H (retries disabled)
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Sector Count 00 if the command proceed without error, else the number of untransfered
sectors.
Sector Number Sector[7:0] or LBA[7:0] of the last sector read
Cylinder Low Cylinder[7:0] or LBA[15:8] of the last sector read
Cylinder High Cylinder[15:8] or LBA[23:16] of the last sector read
Error
V V V V
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10.11 Read Multiple - C4H

This command functions like the Read Sector(s) command, but instead of issuing interrupts for each sector,
interrupts are issued when a block containing the counts of sectors, defined by the Set Multiple command
is, transferred. Also, the DRQ required for the transfer only has to be set at the start of the data block and
does not affect other sectors. When the Read Multiple command is issued, the requested sectors (not the
block counts or the sector counts in a block) are written into the Sector Count Register. Errors occurring
during command execution are reported at the start of a block transfer or at the start of transfer of part of a
block. However, the transfer continues even if DRQ is set and the data is corrupted. After the data transfer,
the content of the task file with the block data containing the sectors where the error occurred is not defined.
To obtain valid error information the host has to request a re-transmission. The next block or part of a block
is transferred only if the error is correctable. For all other errors the command is aborted after transferring a
block containing an error. The Read Multiple command is supported for backward compatibility. If R/W
Multiple commands have been enabled by a previous valid Set Multiple command, the Read Multiple
command is identical to the Read Sectors operation except that several sectors are transferred as a block to
the Host without the intervening Host handshaking. The block count stands for the number of sectors to be
transferred as a block. It is established using the Set Multiple command. Although the Set Multiple, and
R/W Multiple commands are supported, the only valid block count is one.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count The number of sectors/logical blocks to transfer
Device/Head LBA DEV Head number or LBA
Command C4H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V V
Sector Count The first sector where the first unrecoverable error occurred
Sector Number Sector[7:0] or LBA[7:0] of the last good sector transferred
Cylinder Low Cylinder[7:0] or LBA[15:8] of the last good sector transferred
Cylinder High Cylinder[15:8] or LBA[23:16] of the last good sector transferred
Device/Head LBA DEV H[3:0] or LBA[27:24] last good sector transferred
Error
V V V V V V V V
TCADO-SCF-000018.4 74/139 0605V4

10.12 Read Sectors(s) – 20H or 21H

The Cylinder Low, Cylinder High, Device/Head and Sector Number or LBA registers specify the starting
sector address to be read. The Sector Count Register specifies the number of sectors to be transferred.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count The number of sectors/logical blocks to transfer
Command 20H (retry enabled) or 21H (retries disabled)
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V V
Device/Head LBA DEV H[3:0] or LBA[27:24] last good sector
transferred
Error
V V V V V V V
TCADO-SCF-000018.4 75/139 0605V4

10.13 Read Verify Sector(s) – 40H or 41H

The Read Verify Sectors command verifies one or more sectors on the card by transferring data from the
Flash media to the data buffer in the card and verifying that the ECC is correct. It is performed identically to
the Read Sectors command, except that DRQ is not asserted, and no data is transferred to the host. If an
uncorrectable error occurs, the Read Verify command will be terminated at the failing sector. The task file
registers contain the CHS, or LBA of the sector in which the error occurred.
The Cylinder Low, Cylinder High, Device/Head and Sector Number specify the starting sector address to
be verified. The Sector Count Register specifies the number of sectors to be verified.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count The number of sectors/logical blocks to verify
Sector Number Sector[7:0] or LBA[7:0] of the first sector/LBA to verify
Cylinder Low Cylinder[7:0] or LBA[15:8] of the sector/LBA to verify
Cylinder High Cylinder[15:8] or LBA[23:16] of the first sector/LBA to verify
sector/LBA to verify
Command 40H (retries enabled) or 41H (retries disabled)
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V V
Error
V V V V V V V
TCADO-SCF-000018.4 76/139 0605V4

10.14 Recalibrate - 1XH

The adapter performs only the interface timing and register operations. When this command is issued, the
adapter sets BSY and waits for an appropriate length of time after which it clears BSY and issues an
interrupt. When this command ends normally, the adapter is initialized.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count N/A
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV
Command 1XH
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V
Error
V
TCADO-SCF-000018.4 77/139 0605V4

10.15 Request Sense - 03H

This command requests extended error information for the previous command. The table below defines the
valid extended error codes. Those codes are placed in the Error Register.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count N/A
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV
Command 03H
OUTPUTS
The diagnostic code written into the Error Register is an 8-bit code as shown in the table below.
Register 7 6 5 4 3 2 1 0
Status
V V V V
Error Sense code, see table below
Code Description
00H No error detected
01H Self test OK (No error)
03H Write/Erase failed
09H Miscellaneous Error - N/A
20H Invalid Command
21H Invalid Address (requested Head or Sector invalid)
2FH Address Overflow (address too large)
35H, 36H Supply or generate Voltage Out of Tolerance
11H Uncorrectable ECC Error
18H Corrected ECC Error - N/A
05H, 30H-34H, 37H, 3EH Self Test Diagnostic Failed
10H, 14H ID Not Found - N/A
3AH Spare Sectors Exhausted
1FH Data Transfer Error / Aborted Command
0CH, 38H, 3BH, 3CH, 3FH Corrupted Media Format - N/A
TCADO-SCF-000018.4 78/139 0605V4

10.16 Seek - 7XH

This command seeks and picks up the head to track specified in the Task File registers. Actually the adapter
performs only an interface timing and register information.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count N/A
Sector Number (Valid in LBA mode only) LBA[7:0] of the track
Cylinder Low Cylinder[7:0] or LBA[15:8] of the track
Cylinder High Cylinder[15:8] or LBA[23:16] of the track
Device/Head LBA DEV H[3:0] or LBA[27:24] of the track
Command 7XH
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V V V V
TCADO-SCF-000018.4 79/139 0605V4

10.17 Set Feature - EFH

This command is used by the host to establish or select from the specific features listed below.(after a power
up or a hardware reset) An ATA software reset does not set the features to default. The feature code is
set to 81H, this mode is the default mode.
INPUTS
Register 7 6 5 4 3 2 1 0
Features Feature number according to the table below
Sector Count Configuration required
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV
Command EFH
Feature Codes
Code Description
01H Enable 8-bit data transfers
55H Disable Read Look Ahead
66H Disable reverting to power on defaults
81H Disable 8-bit data transfers
BBH 4 bytes of ECC apply on read long/write long commands
CCH Enable reverting to power on defaults
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V
TCADO-SCF-000018.4 80/139 0605V4

10.18 Set Multiple Mode - C6H

The Set Multiple command allows the adapter to perform Read Multiple and Write Multiple operations. It
also sets the block count (counts of sectors making up a block) for these commands. The sector count per
block is placed is the Sector Count Register. The adapter supports only blocks with one sector.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count Sector Count per Block( = 1)
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV
Command C6H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V
TCADO-SCF-000018.4 81/139 0605V4

10.19 Set Sleep Mode - 99H or E6H

This is the only command that allows the host to set the adapter into Sleep mode. When the adapter is set to
sleep mode, the adapter clears the BSY line and issues an interrupt. The adapter enters sleep mode and the
only method to make the adapter active again (back to normal operation) is by performing a hardware reset
or software reset.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count N/A
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV
Command 99H/E6H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V
TCADO-SCF-000018.4 82/139 0605V4

10.20 Standby - 96H or E2H

This command is sets the adapter in Standby mode. If the Sector Count Register is a value other than 0H,
an Auto Power Down is enabled and when the adapter returns to the idle mode, the timer starts a
countdown. The time is set in the Sector Count Register.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count Time period value
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV
Command 96H or E2H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V
TCADO-SCF-000018.4 83/139 0605V4

10.21 Standby Immediate 94H or E0H

This command sets the adapter into standby mode.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count N/A
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV
Command 94H or E0H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V
TCADO-SCF-000018.4 84/139 0605V4

10.22 Translate Sector - 87H

This command allows the host a method of determining the exact number of times a sector was used
(erased). The controller responds with the 512-byte buffer of information that includes the Hot Count, if
available, for the sector. This command is not supported in this adapter and will always return the Hot
Count as “00”.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count Sector Count
Sector Number Sector[7:0] or LBA[7:0] of the first sector/LBA to transfer
sector/LBA
Command 87H
OUTPUTS
The diagnostic code written into the Error Register is an 8-bit code as shown in the table below.
Register 7 6 5 4 3 2 1 0
Status
V V V V V
Error
V V V
Address Information
00H - 01H Cylinder MSB (00H), Cylinder LSB (01H)
02H Head
03H Sector
04H - 06H LBA MSB (04H) - LSB (06H)
07H - 12H Reserved
13H Erased Flag (FFH) = Erased; (00H) = Not Erased
14H - 17H Reserved
18H - 1AH Hot Count MSB (18H) - LSB (1AH)
1BH - 1FFH Reserved
TCADO-SCF-000018.4 85/139 0605V4

10.23 Wear Level - F5H

This command is effectively a NOP command and only implemented for backward compatibility. The
Sector Count Register will always return the value “00H”, indicating that wear leveling is not needed.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count N/A
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV
Command F5H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Sector Count Always “00H”
Error
V V V V V V V
TCADO-SCF-000018.4 86/139 0605V4

10.24 Write Buffer - E8H

This command enables the host to rewrite the contents of the adapter data buffer in the adapter with the
desired data sting. This data buffer can be accessed by and read by the Read Buffer Command.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count N/A
Sector Number N/A
Cylinder Low N/A
Cylinder High N/A
Device/Head DEV
Command E8H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V
TCADO-SCF-000018.4 87/139 0605V4

10.25 Write Long Sector(s) 32H or 33H

This command operates in the same way as the Write Sector command except that it writes data and ECC
bytes for long commands directly from the sector buffer. ECC bytes for long commands are byte writes that
consist of a 4-byte fixed length data. This command can write only one sector at a time.
INPUT
Register 7 6 5 4 3 2 1 0
Features N/A
Sector Count “01h”
sector/LBA
Command 32H or 33H
OUTPUTS
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TCADO-SCF-000018.4 89/139 0605V4

TCADO-SCF-000018.4 90/139 0605V4


Status
V V V V V V
Sector Count Bit-0 if the command proceeded successfully, other – untransferred sectors
count
Error
V V V
TCADO-SCF-000018.4 91/139 0605V4

10.26 Write Multiple - C5H

This command functions in the same way as the Write Sector command. When this command is issued, the
adapter sets the BSY within 400nsec. Interrupts are not issued for every sector but after one block
consisting of the counts of sectors defined by the Set Multiple command is transferred. The DRQ required
for the transfer only has to be set at the beginning of the block and does not affect other sectors.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Device/Head LBA DEV H[3:0] or LB[27:24] of the starting
sector/LBA
Command C5H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Sector Count Bit-0 if the command proceeded successfully, other – untransferred sectors count
Error
V V V V V V
TCADO-SCF-000018.4 92/139 0605V4

10.27 Write Multiple without Erase – CDH

This command is similar to the Write Multiple command with the exception that an implied erase before
using this command. Please note that before using this command it is required to erase the respective
sectors using the Erase Sector command.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
Device/Head LBA DEV H[3:0] or LB[27:24] of the starting
sector/LBA
Command CDH
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V V V V V V
TCADO-SCF-000018.4 93/139 0605V4

10.28 Write Sector(s) - 30H or 31H

This command allows the host to write the specified number (1 to 256) of sectors in the Sector Count
Register. A sector count of 0 indicates a write request of 256 sectors. The write operation starts from the
sector specified in the Sector Number register. The command ends execution by placing the cylinder, head
and sector number of the last written sector in the Task File registers.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
sector/LBA
Command 30H or 31H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V V V V V V
TCADO-SCF-000018.4 94/139 0605V4

10.29 Write Sector(s) without Erase - 38H

This command is similar to the Write Sector command with the exception that an implied erase before
using this command. Please note that before using this command it is required to erase the respective
sectors using the Erase Sector command.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
sector/LBA
Command 38H
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V V V V
TCADO-SCF-000018.4 95/139 0605V4

10.30 Write Verity - 3CH

This command is similar to the Write Sector command with the exception that each sector is verified
immediately after writing.
INPUTS
Register 7 6 5 4 3 2 1 0
Features N/A
sector/LBA
Command 3CH
OUTPUTS
Register 7 6 5 4 3 2 1 0
Status
V V V V V V
Error
V V V V
TCADO-SCF-000018.4 96/139 0605V4

11. Error Posting

Command Error Register Status Register
BBK UNC IDNF ABRT AMNF DRDY DWF DSC CORR ERR
Check Power Mode 9 9 9 9 9
Execute Drive Diagnostic 9 9 9
Erase Sector(s) 9 9 9 9 9 9 9 9
Format Track 9 9 9 9 9 9 9
Identify Drive 9 9 9 9 9
Idle 9 9 9 9 9
Idle immediate 9 9 9 9 9
Initialize Drive Parameter 9 9 9
Read Buffer 9 9 9 9 9
Read Multiple 9 9 9 9 9 9 9 9 9 9
Read Long Sector 9 9 9 9 9 9 9 9
Read Sector(s) 9 9 9 9 9 9 9 9 9 9
Read Verify Sectors 9 9 9 9 9 9 9 9 9 9
Recalibrate 9 9 9 9 9
Request Sense 9 9 9 9
Security Disable Password 9 9 9 9 9
Security Erase Prepare 9 9 9 9 9
Security Erase Unit 9 9 9 9 9
Security Freeze Lock 9 9 9 9 9
Security Set Password 9 9 9 9 9
Security Unlock 9 9 9 9 9
Seek 9 9 9 9 9 9
Set Features 9 9 9 9 9
Set Multiple Mode 9 9 9 9 9
Set Sleep Mode 9 9 9 9 9
Stand By 9 9 9 9 9
Stand By Immediate 9 9 9 9 9
Translate Sector 9 9 9 9 9 9 9 9
Wear Level 9 9 9 9 9 9 9 9 9
Write Buffer 9 9 9 9 9
Write Long Sector 9 9 9 9 9 9 9 9
Write Multiple 9 9 9 9 9 9 9 9
Write Multiple w/o Erase 9 9 9 9 9 9 9 9
TCADO-SCF-000018.4 97/139 0605V4
Write Sector(s) 9 9 9 9 9 9 9 9
Write Sector w/o Erase 9 9 9 9 9 9 9 9
Write Verify 9 9 9 9 9 9 9 9
Invalid command Code 9 9 9 9 9
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12. Identify Drive Information

Word Data Description
0 848AH General configuration bit-significant information
1 Note 1 Number of Cylinders
2 0000h Reserved
3 Note 1 Number of Heads
4 0000H Obsolete
5 XXXXH Obsolete
6 Note 1 Number of sectors per track
7-8 XXXXH Number of sectors per card (Word 7= MSW, Word 8= LSW )
9 XXXXH Obsolete
10-19 XXXXH 20 ASCII char serial number.
20 0002H Obsolete
21 0002H Obsolete
22 0004H ECC bytes passed on Read/Write Long Commands
23-26 XXXXH Firmware revision in ASCII chars.
27-46 XXXXH Model Number (Vendor Unique)
47 0001H Maximum Block Count=1 for Read/Write Multiple command
48 0000H Reserved
49 2F00H Capabilities: LBA supported (bit 9).
Capabilities: LBA supported (bit 9).
15 0= interleave DMA not supported
14 0=command queuing not supported
13 1=overlap operation supported
12 0=ATA software reset required (Obsolete)
11 0=IORDY not supported
10 0=IORDY maybe enable
9 0=LBA not supported
8 0=DMA not Supported
7-0 Vendor specification
50 0000H Reserved
51 0200H PIO data transfer cycle timing mode
52 0000H Obsolete
53 0003H Translation Parameters Vaild (bit0:Word54 to 58 are valid,
bit1:Word 64 to 70 are valid)
15-3 Reserved
TCADO-SCF-000018.4 99/139 0605V4


2 1= the field reported in word 88 are valid
0= the field reported in word 88 are not valid
1 1= the field reported in word 64-70 are valid
0= the field reported in word 64-70 are not valid
0 1= the field reported in word 54-58 are valid
0= the field reported in word 54-58 are not valid
54 Note 1 Number of Current Cylinders
55 Note1 Number of Current Heads
56 Note 1 Number of Current Sectors Per Track
57 Note 1 LSW of the Current Capacity in Sectors
58 Note1 MSW of the Current Capacity in Sectors
59 0100H Multiple sector setting
If bit 8 is set to one, bits 7-0 reflect the number of sector currently
set to transfer on a READ/WRITE MULTIPLE command.
This filed may default to the preferred value for the device.
Command Code: C6h
60 Note 1 LSW of the total number of user addressable LBA’s
61 Note 1 MSW of the total number of user addressable LBA’s
62 0000H Reserved
63 0001H 15-11 Reserved
10 1=Multiword DMA mode 2 is selected
0=Multiword DMA mode 2 is not selected
9 1= Multiword DMA mode 1 is selected
8 1= Multiword DMA mode 0 is selected
7-3 Reserved
2 0= Multiword DMA mode 2 and below are not supported
1 0= Multiword DMA mode 1 and below are not supported
0 1= Multiword DMA mode 0 is supported Multiword
DMA mode selected.
64 0003H Advanced PIO Modes supported (bit0: PIO-3,
bit1:PIO4,supported)
15-8 Reserved
7-0 Supported
Bits 7 through 0 of word 64 of the Identify Device parameter
information is defined as the PIO data and register transfer
supported field. If this field is supported, bit 1 of word 53 shall
TCADO-SCF-000018.4 100/139 0605V4

be set to one.
Of these bits, bits 7 through 2 are Revered for future PIO
modes. Bit 0, if set to one, indicated that the device supports
PIO mode 3. All device except CFA and PCMCIA device shall
support PIO mode 3 and shall set bit 0 to one. Bit 1, if set to
one, indicated that the device support PIO mode 4.
65 01E0H (DMA Minimum Multiword DMA transfer cycle time per word
2) 15-0 Cycle time in nanoseconds
0000H (PIO 4) If this field is supported, bit 1 of word 53 shall be set to one.
Any device that supports Multiword DMA mode 1 or above
shall support this field, and the value in word 65 shall not be
less than the minimum cycle time for the fastest DMA mode
supported by the device.
If bit 1 of word 53 is set to one because a device supports a
field in words 64-70 other than this filed and the device does
not support this filed, the device shall return a value of zero in
this field.
Manufacturer’s recommended Multiword DMA transfer cycle
time
15-0 Cycle time in nanoseconds
01E0H
66 If this field is supported, bit 1 of word 53 shall be set to one,
0000H (PIO 4)
Any device that supports Multiword DMA mode 1 or above
shall support this field, and the value in word 66 shall not be
less than the value in word 65.
Minimum PIO transfer cycle time without flow control
67 0078H
Minimum PIO transfer cycle time with IORDY flow control
68 0078H
69-79 0000H Reserved (for feature command overlap and queuing)
80-81 0000H ... Reserved for CFA
82 0000H Features/Command sets supported
83 0000H Feature/Command sets supported
86 0000H Feature/Command sets supported
88 0700H 15-14 Reserved
13 1= Ultra DMA mode 5 is selected
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0=Ultra DMA mode 5 is not selected
7-6 Reserved
5 0= Ultra DMA mode 5 and below are not supported
4 1= Ultra DMA mode 4 and below are supported
0 1= Ultra DMA mode 0 is supported
89 0000H Time required for Security erase unit completion
90 0000H Time required for Enhanced security erase unit completion
91 XXXXH Current Advanced power management value
92 - 127 0000H Reserved
128 0000H Security status
129 - 159 0000H Vendor unique bytes
160 0000H Power requirement description
161 0000H Reserved
162 0000H Key management schemes supported
163 - 255 0000H Total 166 Bytes Reserved
Note1: Variable by capacity
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13. ATA Protocol Overview

Command classes are grouped according to protocols described for command execution. For all commands,
the host must first check for BYS=0 before proceeding further. For most commands, the host should not
proceed until DRDY=1.
13.1 PIO Data In Commands

Execution includes one more 512 bytes data-sector drive-to-host transfer. If the drive presents error status, it
prepares to transfer data at the host's discretion. The host writes parameters to the Feature, Sector Count,
Sector Number, Cylinder, and Drive/Head register. The host writes the Command Register's command
code. The drive sets BSY and prepares for data transfer when a data sector is available; the drive sets
DRQ, clears BSY, and asserts interrupt. At interrupt, the host reads the Status register, the drive negates
interrupt, and the host reads one data-sector from Data Register. The drive clears DRQ. If another sector
is required, the drive sets BSY and repeats the data transfer from 4.
13.2 PIO Data Out Commands

Execution includes one or more 512 bytes host-to-drive data-sector transfers. The host writes parameters to
the Features, Sector Count, Sector Number, Cylinder, and Drive/Head Registers. The host writes the
Command register's command code. The drive sets DRQ when it can accept the first sector of data
The host writes one sector of data to the Data register. The Drive clears DRQ and sets BSY. At sector
processing complete, the drive clears BSY and asserts interrupt. If another sector transfer is required, the
drive also sets DRQ. The host reads the Status register after detecting interrupt. The drive negates the
interrupt if another sector transfer is required, the sequence repeats from 4.
13.3 Non Data Commands

Command execution involves no data transfer. The host writes parameters to the Features, Sector Count,
Sector Number, Cylinder, and Drive/Head registers. The host writes the Command register's command
code. The Drive sets BSY. When the drive completes sector processing, it clears BSY and asserts
interrupt. The host reads the Status register after detecting interrupts the drive negates the interrupt.
TCADO-SCF-000018.4 103/139 0605V4

14. Ultra DMA data-in commands
14.1. Initiating an Ultra DMA data-in burst

The following steps shall occur in the order they are listed unless otherwise specified.
a) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.
b) The device shall assert DMARQ to initiate an Ultra DMA burst when DMACK- is negated.
Afterassertion of DMARQ the device shall not negate DMARQ until after the first negation of
DSTROBE.
c) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
d) The host shall negate HDMARDY-.
e) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-, DA2, DA1,
and DA0 negated until after negating DMACK- at the end of the burst.
f) Steps (c), (d), and (e) shall have occurred at least tACK before the host asserts DMACK-. The host shall keep
DMACK- asserted until the end of an Ultra DMA burst.
g) The host shall release DD(15:0) within tAZ after asserting DMACK-.
h) The device may assert DSTROBE tZIORDY after the host has asserted DMACK-. Once the device has
driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the
end of an Ultra DMA burst.
i) The host shall negate STOP and assert HDMARDY- within tENV after asserting DMACK-. After
negating STOP and asserting HDMARDY-, the host shall not change the state of either signal until after
receiving the first negation of DSTROBE from the device (i.e., after the first data word has been received).
j) The device shall drive DD(15:0) no sooner than tZAD after the host has asserted DMACK-, negated STOP,
and asserted HDMARDY-.
k) The device shall drive the first word of the data transfer onto DD(15:0). This step may occur when the
device first drives DD(15:0) in step (j).
l) To transfer the first word of data the device shall negate DSTROBE within tFS after the host has negated
STOP and asserted HDMARDY-. The device shall negate DSTROBE no sooner than tDVS after driving
the first word of data onto DD(15:0).
14.2. The data-in transfer

a) The device shall drive a data word onto DD(15:0).
b) The device shall generate a DSTROBE edge to latch the new word no sooner than tDVS after changing the
TCADO-SCF-000018.4 104/139 0605V4
state of DD(15:0). The device shall generate a DSTROBE edge no more frequently than tCYC for the
selected Ultra DMA mode. The device shall not generate two rising or two falling DSTROBE edges more
frequently than t2cyc for the selected Ultra DMA mode.
c) The device shall not change the state of DD(15:0) until at least tDVH after generating a DSTROBE edge to
latch the data.
d) The device shall repeat steps (a), (b), and (c) until the Ultra DMA burst is paused or terminated by the
device or host.
14.3. Pausing an Ultra DMA data-in burst

14.3.1. Device pausing an Ultra DMA data-in burst

a) The device shall not paused an Ultra DMA burst until at least one data word of an Ultra DMA burst has
been transferred.
b) The device shall pause an Ultra DMA burst by not generating additional DSTROBE edges. If the host is
ready to terminate the Ultra DMA burst.
c) The device shall resume an Ultra DMA burst by generating a DSTROBE edge.
14.3.2. Host pausing an Ultra DMA data-in burst

a) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been
transferred.
b) The host shall pause an Ultra DMA burst by negating HDMARDY-.
c) The device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY-.
d) When operating in Ultra DMA modes 2, 1, or 0: If the host negates HDMARDY- within tSR after the
device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data
words; or, if the host negates HDMARDY- greater than tSR after the device has generated a DSTROBE edge,
then the host shall be prepared to receive zero, one or two additional data words. While operating in Ultra
DMA modes 4 or 3 the host shall be prepared to receive zero, one, two or three additional data words after
negating HDMARDY-. The additional data words are a result of cable round trip delay and tRFS timing for the
device.
e) The host shall resume an Ultra DMA burst by asserting HDMARDY-.
14.3.3. Terminating an Ultra DMA data-in burst
14.3.3.1. Device terminating an Ultra DMA data-in burst

Burst termination is completed when the termination protocol has been executed and DMACK- negated. The
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device shall terminate an Ultra DMA burst before command completion.

z The device shall initiate termination of an Ultra DMA burst by not generating additional DSTROBE edges.
z The device shall negate DMARQ no sooner than tSS after generating the last DSTROBE edge. The device
shall not assert DMARQ again until after DMACK- has been negated.
z The device shall release DD(15:0) no later than tAZ after negating DMARQ.
z The host shall assert STOP within tLI after the device has negated DMARQ. The host shall not negate STOP
again until after the Ultra DMA burst is terminated.
z The host shall negate HDMARDY- within tLI after the device has negated DMARQ. The host shall continue
to negate HDMARDY- until the Ultra DMA burst is terminated. Steps (d) and (e) may occur at the same time.
z The host shall drive DD(15:0) no sooner than tZAH after the device has negated DMARQ. For this step, the host
may first drive DD(15:0) with the result of the host CRC calculation (see 9.15);
z If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. No data
shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall
remain asserted until the Ultra DMA burst is terminated.
z If the host has not placed the result of the host CRC calculation on DD(15:0) since first driving DD(15:0)
during (f), the host shall place the result of the host CRC calculation on DD(15:0) (see 9.15).
z The host shall negate DMACK- no sooner than tMLI after the device has asserted DSTROBE and negated
DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than tDVS after the host places
the result of the host CRC calculation on DD(15:0).
z The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-.
z The device shall compare the CRC data received from the host with the results of the device CRC calculation.
If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the
command the device shall report the first error that occurred (see 9.15).
z The device shall release DSTROBE within tIORDYZ after the host negates DMACK-.
z The host shall not negate STOP nor assert HDMARDY- until at least tACK after negating DMACK-.
z The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating DMACK.
14.3.3.2. Host terminating an Ultra DMA data-in burst

a) The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst
has been transferred.
b) b) The host shall initiate Ultra DMA burst termination by negating HDMARDY-. The host shall
continue to negate HDMARDY- until the Ultra DMA burst is terminated.
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c) The device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY-.
d) When operating in Ultra DMA modes 2, 1, or 0: If the host negates HDMARDY- within tSR after the
device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional
data words; or, if the host negates HDMARDY- greater than tSR after the device has generated a
DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words.
While operating in Ultra DMA modes 4 or 3 the host shall be prepared to receive zero, one, two or three
additional data words after negating HDMARDY-. The additional data words are a result of cable round
trip delay and tRFS timing for the device.
e) The host shall assert STOP no sooner than tRP after negating HDMARDY-. The host shall not negate
STOP again until after the Ultra DMA burst is terminated.
f) The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not assert
DMARQ again until after the Ultra DMA burst is terminated.
g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. No
data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE.
DSTROBE shall remain asserted until the Ultra DMA burst is terminated.
h) The device shall release DD(15:0) no later than tAZ after negating DMARQ.
i) The host shall drive DD(15:0) no sooner than tZAH after the device has negated DMARQ. For this step, the
host may first drive DD(15:0) with the result of the host CRC calculation .
j) If the host has not placed the result of the host CRC calculation on DD(15:0) since first driving DD(15:0)
during (9), the host shall place the result of the host CRC calculation on DD(15:0).
k) The host shall negate DMACK- no sooner than tMLI after the device has asserted DSTROBE and negated
DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than tDVS after the
host places the result of the host CRC calculation on DD(15:0).
l) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-.
m) The device shall compare the CRC data received from the host with the results of the device CRC
calculation. If a miscompare error occurs during one or more Ultra DMA burst for any one command, at
the end of the command, the device shall report the first error that occurred.
n) The device shall release DSTROBE within tIORDYZ after the host negates DMACK-.
o) The host shall neither negate STOP nor assert HDMARDY- until at least tACK after the host has negated
DMACK-.
p) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating
DMACK.
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14.4. Ultra DMA data-out commands
14.4.1. Initiating an Ultra DMA data-out burst

a) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.
b) The device shall assert DMARQ to initiate an Ultra DMA burst when DMACK- is negated.
c) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
d) The host shall assert HSTROBE.
e) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-, DA2, DA1,
and DA0 negated until after negating DMACK- at the end of the burst.
f) Steps (c), (d), and (e) shall have occurred at least tACK before the host asserts DMACK-. The host shall
keep DMACK- asserted until the end of an Ultra DMA burst.
g) The device may negate DDMARDY- tZIORDY after the host has asserted DMACK-. Once the device
has negated DDMARDY-, the device shall not release DDMARDY- until after the host has negated
DMACK- at the end of an Ultra DMA burst.
h) The host shall negate STOP within tENV after asserting DMACK-. The host shall not assert STOP until
after the first negation of HSTROBE.
i) The device shall assert DDMARDY- within tLI after the host has negated STOP. After asserting DMARQ
and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by
the host.
j) The host shall drive the first word of the data transfer onto DD(15:0). This step may occur any time
during Ultra DMA burst initiation.
k) To transfer the first word of data: the host shall negate HSTROBE no sooner than tUI after the device
has asserted DDMARDY-. The host shall negate HSTROBE no sooner than tDVS after the driving the
first word of data onto DD(15:0).
14.4.2. The data-out transfer

a) The host shall drive a data word onto DD(15:0).
b) The host shall generate an HSTROBE edge to latch the new word no sooner than tDVS after changing the
state of DD(15:0). The host shall generate an HSTROBE edge no more frequently than tCYC for the
selected Ultra DMA mode. The host shall not generate two rising or falling HSTROBE edges more
frequently than t2cyc for the selected Ultra DMA mode.
c) The host shall not change the state of DD(15:0) until at least tDVH after generating an HSTROBE edge to
latch the data.
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d) The host shall repeat steps (a), (b), and (c) until the Ultra DMA burst is paused or terminated by the device
or host.
14.4.3. Pausing an Ultra DMA data-out burst

14.4.3.1 Host pausing an Ultra DMA data-out burst

a) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been
transferred.
b) The host shall pause an Ultra DMA burst by not generating an HSTROBE edge. If the host is ready to
terminate the Ultra DMA burst.
c) The host shall resume an Ultra DMA burst by generating an HSTROBE edge .
12.4.3.2. Device pausing an Ultra DMA data-out burst
a) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has
been transferred.
b) The device shall pause an Ultra DMA burst by negating DDMARDY-.
c) The host shall stop generating HSTROBE edges within tRFS of the device negating DDMARDY-.
d) When operating in Ultra DMA modes 2, 1, or 0: If the device negates DDMARDY- within tSR after
the host has generated an HSTROBE edge, then the device shall be prepared to receive zero or one
additional data words; or, if the device negates DDMARDY- greater than tSR after the host has generated an
HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words.
While operating in Ultra DMA modes 4 or 3 the device shall be prepared to receive zero, one, two or three
additional data words after negating DDMARDY-. The additional data words are a result of cable round
trip delay and tRFS timing for the host.
e) The device shall resume an Ultra DMA burst by asserting DDMARDY-.
14.4.4. Terminating an Ultra DMA data-out burst
14.4.4.1 Host terminating an Ultra DMA data-out burst

a) The host shall initiate termination of an Ultra DMA burst by not generating additional HSTROBE edges.
b) The host shall assert STOP no sooner than tSS after the last generated an HSTROBE edge. The host
shall not negate STOP again until after the Ultra DMA burst is terminated.
c) The device shall negate DMARQ within tLI after the host asserts STOP. The device shall not assert
DMARQ again until after the Ultra DMA burst is terminated.
d) The device shall negate DDMARDY- within tLI after the host has negated STOP. The device shall not
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assert DDMARDY- again until after the Ultra DMA burst termination is complete.
e) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated
DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA burst is terminated.
f) The host shall place the result of the host CRC calculation on DD(15:0)
g) The host shall negate DMACK- no sooner than tMLI after the host has asserted HSTROBE and STOP
and the device has negated DMARQ and DDMARDY-, and no sooner than tDVS after placing the result
of the host CRC calculation on DD(15:0).
h) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-.
i) The device shall compare the CRC data received from the host with the results of the device CRC
calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command,
at the end of the command, the device shall report the first error that occurred.
j) The device shall release DDMARDY- within tIORDYZ after the host has negated DMACK-.
k) The host shall neither negate STOP nor negate HSTROBE until at least tACK after negating DMACK-.
l) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating
DMACK.
14.4.4.2 Device terminating an Ultra DMA data-out burst

Burst termination is completed when the termination protocol has been executed and DMACK- negated. The
device shall terminate an Ultra DMA burst before command completion. The following steps shall occur in the
order they are listed unless otherwise specified.
a) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA
burst has been transferred.
b) The device shall initiate Ultra DMA burst termination by negating DDMARDY-.
c) The host shall stop generating an HSTROBE edges within tRFS of the device negating DDMARDY-.
d) When operating in Ultra DMA modes 2, 1, or 0: If the device negates DDMARDY- within tSR after the
host has generated an HSTROBE edge, then the device shall be prepared to receive zero or one
additional data words; or, if the device negates DDMARDY- greater than tSR after the host has generated
an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words.
While operating in Ultra DMA modes 4 or 3 the device shall be prepared to receive zero, one, two or
three additional data words after negating DDMARDY-. The additional data words are a result of cable
round trip delay and tRFS timing for the host.
e) The device shall negate DMARQ no sooner than tRP after negating DDMARDY-. The device shall not
assert DMARQ again until after DMACK- is negated.
f) The host shall assert STOP within tLI after the device has negated DMARQ. The host shall not negate
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STOP again until after the Ultra DMA burst is terminated.

g) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated
DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA burst is terminated.
h) The host shall place the result of the host CRC calculation on DD(15:0).
i) The host shall negate DMACK- no sooner than tMLI after the host has asserted HSTROBE and STOP
and the device has negated DMARQ and DDMARDY-, and no sooner than t DVS after placing the
result of the host CRC calculation on DD(15:0).
j) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-.
k) The device shall compare the CRC data received from the host with the results of the device CRC
calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command,
at the end of the command, the device shall report the first error that occurred.
l) The device shall release DDMARDY- within tIORDYZ after the host has negated DMACK-.
m) The host shall neither negate STOP nor HSTROBE until at least tACK after negating DMACK-.
n) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating
DMACK.
14.5. Ultra DMA CRC rules

The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra
DMA burst, and reporting any error that occurs at the end of a command.
1) Both the host and the device shall have a 16-bit CRC calculation function.
2) Both the host and the device shall calculate a CRC value for each Ultra DMA burst.
3) The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of
an Ultra DMA burst before any data is transferred.
4) For each STROBE transition used for data transfer, both the host and the device shall calculate a new
CRC value by applying the CRC polynomial to the current value of their individual CRC functions and
the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after
the Ultra DMA burst termination request has been acknowledged.
5) At the end of any Ultra DMA burst the host shall send the results of the host CRC calculation function to
the device on DD(15:0) with the negation of DMACK-.
6) The device shall then compare the CRC data from the host with the calculated value in its own CRC
calculation function. If the two values do not match, the device shall save the error. A subsequent Ultra
DMA burst for the same command that does not have a CRC error shall not clear an error saved from a
previous Ultra DMA burst in the same command. If a miscompare error occurs during one or more
Ultra DMA bursts for any one command, the device shall report the first error that occurred. If the
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device detects that a CRC error has occurred before data transfer for the command is complete, the device
may complete the transfer and report the error or abort the command and report the error.
7) For READ DMA, WRITE DMA, READ DMA QUEUED, or WRITE DMA QUEUED commands:
When a CRC error is detected, the error shall be reported by setting both ICRC and ABRT (bit 7 and bit 2
in the Error register) to one. ICRC is defined as the “Interface CRC Error” bit. The host shall respond to
this error by re-issuing the command.
8) For a REQUEST SENSE packet command (see SPC T10/955D for definition of the REQUEST SENSE
command): When a CRC error is detected during transmission of sense data the device shall complete
the command and set CHK to one. The device shall report a Sense key of 0Bh (ABORTED
COMMAND). The device shall preserve the original sense data that was being returned when the CRC
error occurred. The device shall not report any additional sense data specific to the CRC error. The host
device driver may retry the REQUEST SENSE command or may consider this an unrecoverable error
and retry the command that caused the Check Condition.
9) For any packet command except a REQUEST SENSE command: If a CRC error is detected, the device
shall complete the command with CHK set to one. The device shall report a Sense key of 04h
(HARDWARE ERROR). The sense data supplied via a subsequent REQUEST SENSE command shall
report an ASC/ASCQ value of 08h/03h (LOGICAL UNIT COMMUNICATION CRC ERROR). Host
drivers should retry the command that resulted in a HARDWARE ERROR.
10) A host may send extra data words on the last Ultra DMA burst of a data-out command. If a device
determines that all data has been transferred for a command, the device shall terminate the burst. A device
may have already received more data words than were required for the command. These extra words are
used by both the host and the device to calculate the CRC, but, on an Ultra DMA data-out burst, the extra
words shall be discarded by the device.
11) The CRC generator polynomial is: G(X) = X16 + X12 + X5 + 1. Table 46 describes the equations for
16- bit parallel generation of the resulting polynomial (based on a word boundary).
NOTE Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock
derived from the bus strobe. The combinational logic is then equivalent to shifting sixteen bits serially through
the generator polynomial where DD0 is shifted in first and DD15 is shifted in last.
NOTE If excessive CRC errors are encountered while operating in an Ultra mode, the host should select a slower
Ultra mode. Caution: CRC errors are detected and reported only while operating in an Ultra mode.
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15. Security CF
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16.System Environmental Specifications

16.1 Temperature Test Flow
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16.2Altitude Test
Altitude Product
Altitude(relative to sea level) Operating 80,000 feet maximum

&Non- Operating
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_______________________________________________________________________________________________

Release Date: June 2005

SCM PC-Card GmbH

Tel: +49 8441 788 810

S-CN CompactFlash Card

TCADO-SCF-000018.4 1/139 0605V4

3 1.Update AC Characteristics December 2004 Ethan Cheng

TCADO-SCF-000018.4 2/139 0605V4

1.1 GENERAL DESCRIPTION ........................................................................................................................................................................7

2.1 OPERATION AND ENVIRONMENT DESCRIPTION ....................................................................................................................................9

3. PRODUCT MODEL ..................................................................................................................................................................................11

3.1 PART NUMBER DEFINITION .................................................................................................................................................................11

4. SUPPORT FLASH MEDIA......................................................................................................................................................................12

4.1 SUPPORTED NAND FLASH TYPE .......................................................................................................................................................12

5.1 CONTROLLER ARCHIVE.......................................................................................................................................................................14

6. SPECIFICATION AND FEATURES .....................................................................................................................................................15

6.1 ELECTRICAL SPECIFICATION ...............................................................................................................................................................15

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6.1.12.5 Ultra DMA Data-In Burst Host Termination Timing.............................................................................................................................. 26

7.1 COMPACTFLASH PIN TYPE..................................................................................................................................................................31

8. CIS AND FUNCTIONS CONFIGURATION REGISTERS.............................................................................................................38

8.1 CONFIGURATION OPTION REGISTER (200H) .....................................................................................................................................38

9. ATA SPECIFIC REGISTER DEFINITIONS.......................................................................................................................................55

9.1 MEMORY MAPPED ADDRESSING ........................................................................................................................................................55

9.5.12 Drive Address Register ............................................................................................................................................................63

10. ATA COMMANDS................................................................................................................................................................................64

10.1 CHECK POWER MODE - 98H OR E5H ................................................................................................................................................64

11. ERROR POSTING.....................................................................................................................................................................................97

12. IDENTIFY DRIVE INFORMATION...............................................................................................................................................99

13. ATA PROTOCOL OVERVIEW ..................................................................................................................................................... 103

13.1 PIO DATA IN COMMANDS ................................................................................................................................................................ 103

14. ULTRA DMA DATA-IN COMMANDS................................................................................................................................................... 104

14.1. INITIATING AN ULTRA DMA DATA-IN BURST.......................................................................................................................................... 104

15. SECURITY CF ...............................................................................................................................................................................................113

16.SYSTEM ENVIRONMENTAL SPECIFICATIONS............................................................................................................................. 138

16.1 TEMPERATURE TEST FLOW ...................................................................................................................................................................... 138

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2.2 Physical description

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3. Product Model & Ordering Information

CFA = Compact Flash Card

XXXX: 032M 32Mbyte Type I

T: C Commercial Temp. Range 0 / +70° Cel

CP: Full Metal Housing

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4. Support Flash Media

Operation Voltage 2.7V to 3.6V

4-1-2. Large block size of 128KB

Operation Voltage 2.7V to 3.6V

4.2 Logical Format Parameters (CHS)

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Card Density*4 6GB

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CIS: Card Information Structure

5.2 Flash Card Archive