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    Inverters 4th Chapter

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    Uday Kumar

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    © All Rights Reserved
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    5.1. INTRODUCTION W3\ : sion: Inversion is a process of egnvertin jverter: Inverter 1S @ device which converts D.C power to A.C power at a certain output voltage and frequency or at a certain current level and frequency. Inve? Industrial applications of inverter inverters are used in various industrial applications such as 1. Variable speed A.C motor drives 1. Induction heating 3. Uninterruptible power supplies 4. Stand by aircraft power supplies 5. HVDC transmission lines ete. 5.2 CLAassiFIcATION OF INVERTERS 1. Line commutated Inverters 2. Forced commutated Inverters 3. Load commutated Inverters 4. Voltage source Inverters 5. Current source Inverters. Line commutated inverters Line commutated Inverters are those devices where the phase controlled converters operates in an inversion mode ie., (from 90° < & < 180°). In the cas of A.C circuits, A.C line voltage is available across the device. Wheneve, the current through the thyristor passes the natural zero value. itg cts Erne process of commutation is known as ine commutation or sane es Oe This uutation. Line commutated inverters are € those device commutation process. €s which undergo this line ~ oN a! 5.2 Power Electronics Forced commutated inverters In the case of D.C eirenits, as the supply voltage is constant it natural zero value. Hence, m order to commutate the thyristor th the thyristor is forcibly made to pass zero value by inserti components m the main circuits. Generally, the commutating cory are inductor and capacitor. This process of commutation is doesn, © curren, NZ com, wig OMENS eee kn OWN as fy commutation rene Foreed commutated Inverters are those devices which undergo, this f commutation process. ‘Otcey Load commutated inverters Load commutated Inverters are those devices in which the commu of an SCR takes place by the load present in the circuit, This type o process became popular with the synchronous motor drives, as th motors when over excited have machine voltages which ca commutation of the inverter. tation proces, commutatig synchroni Nn be useg for Voltage source inverters Voltage source Inverters are those devices converting D.C input Voltage to 4c ouput voltage more or less constant because of the presence of low internal impedance which does not depend upon load. The terminal voltage is determine, by the inverter whereas the load current waveform is determined by load, Thex voltage source inverters are characterised if the internal impedance of the soure is low. The voltage source inverter circuit diagram is as shown in Fig. 5.1(, Current source inverters Current source inverters are those devices where the supply current cannot change in a quick manner. By using a large inductance value in series with de supply the constant current property is achieved. By changing the magnitude of the D.C supply voltage which feeds a large inductance, the magnitude of the load current may be changed. Current source inverter circuit is represented as shown in Fig. 5.1(b) These devices are used to charge the commutating capacitors. L TS TOON + te! Figure 5.1 (a) Voltage source inverter Figure 5.1(b) Current source Inver! A Inverters are also classified as follows depending upon the connection commutating components with the main circuit. a, Series Inverters b. Parallel Inverters c. Bridge Inverters Inverters 5.3 ores of Inverters are deseribed in the following sections as follows qs a are those inverters in which the commutating elements Land C sine in series with the load, This constitute a series R L-c resonance snare type of thyristorised inverter produces an approximate sinusoidal eet at high output frequency whose range is given as 200 Hz — 100k Hz, jas monly used in relatively fixed output applications such as ulttasonse nese induction heating, sonar transmitter, flouroscent tubes etc ‘The size pea nis gets reduced due to high switching frequency of SCRs omponen = : INVERTERS rg base series Inverter eicuit is as shown in figure 5.2), ¢ Figure 5.2a Basic series inverter Cireuit description Leonsists of two thyristors which are used to produce the positive and negative half cycles respectively in the output. The commutating elements L and C are omnected in series with the load as shown in Fig. 5.2(a). Here, the values of L and Care so selected that they form an under damped circuit in order to produce ‘herequired oscillations, . 4L Whenever R2<-— the above condition gets fullfilled, where the values of L ae are selected by satisfying the above relation. Its operating principle may be lained in different modes Mode ; ti 1: Connect D.C supply to the inverter circuit, When the thyristor T, is cane YY Biving a gate signal toi, thyristor, starts conducting. Itresults in ba Voltape through R-L-C series circuit. Now, capacitor ‘C” gets charged up Be Ew a .§.2(a), Load current flows Sought peg the Polarity as shown in Fig. $.2(a). Loa -C-L-R-Eyo Ea de 5.4 Power Electronics The load current produced is of alternating in nature wh: \ ich is due underdamped circuit formed by the commutating elements. 0 the When the load current reaches its peak value, the voltage acy is given as Ey. Afier this instant, the current starts decreasi s “te 7 E d 7 NE Whey capacitor voltage rises to a value of (Ey. + Ec) and remains eon ie e stant thoug, fe load current reaches a zero value, Here, Eq is the initial voltage capacitor when the SCR T, is triggered. When the load current Teaches 3 re, value, SCR T, gets turned off. Mode 2: During this mode, the load current remains consta Period of time before SCR T, is triggered. It is necessary to maintain load constant in order to prevent dead short circuit of supply which may be cay, when both the SCRs ate inthe conducting mode. Duting this mode, bog a T, are in off state. Here, the capacitor voltage remains constant, Det Nt for a sy CUrrany Mode 3: From fig 5.2(a), we observe that positive polarity of capacitor «cr at the anode terminal of the thyristor T3 and hence SCR T, biased. When SCR T, is triggered, it starts conducting and the discharged through it. Here, the load current direction is opp: load current direction of the mode (1). The load current flow: Ct-T,-R-L-c appears becomes forwar Capacitor ‘c gets Osite to that of the S through the path | | | 5S the ca | | | | | Teversed to some value. After some time, a; gain thyristor T, is triggered and the above process is repeated. Hence, altern: ‘ating output which is of sinusoidal in nature is obtained. | The current has been drawn from supply for positive alternation of A.C output whereas it is drawn from capacitor, for negative alternation of A.C output. Hence, the supply from D.C source is said to be of intermittent in nature Note: Time delay maintained SCR T; must be more th some minimum time t between turnoff of SCR T, and conduction of | an the turn off time of SCR. After the instant A, '4min Must elapse for T, to regain its forward blocking | eae, 7 . ue : Capability. This minimum time is given by ta min = i(t-z). T The output frequency is given as Inverters 5.5 eC eri ci give atts the Time period of oscillations given by Tl; 2 Y 2 JC a) zoulp" at frequency in rad/sec, 0 vit ringing frequency in rad/sec, zcite . ont rval between the instant T, is turned off an ted by Tygr= AB, where Tyr > t secs, spe time inte id the instant T, is jon is indicat ‘qmin wnt ng Tost Value, frequency can be varied without changing the y chang! of jements. stating ¢! at a A Ex Voltage across} capacitor E, +E, {226 voltage: Waveform Ey 2 ies Inverter i 5.2(b) Associated waveforms of ser Figure 5. 5.6 Power Electronics Drawbacks : 1. Power flow from the de supply is discontinuous. 3 The de supply will have a high peak current and hence contains harmon, 3. fproper time delay is not ensured between the turn off process of th a T, and turn on process of thyristor T), short circuit of supply Voltag place. 4. Asthe current drawn from de source is discontinuous, more ripples are Dresen Yistoy takes init. 5. Load circuit parameters determine the peak amplitude and duration Of load current which results the poor output regulation of an inverter. 6. The ratings of the commutating elements must be high because these components carry load current continuously and the capacitor supplies the load current in every alternate half cycle. Analysis of circuit (fig 5.2()) Mode 1: The equation describing mode (1) is represented as follows; Le _ Bae = Gfidt Both Gy tik () where E, is initial voltage across the capacitor. Here, voltage drops across T, and T, are neglected. By applying initial conditions ie., t= 0. a. Initial current becomes i(o) =0 b. Initial voltage on capacitor is given as Ec (t= 0)=-E, | Since the circuit is an underdamped one, the solution of the equation (1) is given as ane it) =Ae 2L sina,t @ Here, @, is known as resonant frequency and is given by G 3) &= \Vie7ap ( By applying initial conditions, constant A can be determined from equation (1) di fg - Bac tPc @ Eat Inverters 5.7 di equation 2) GH Ut=0=4 ©, (5) from ir « 4 ca)and (5), We get fen Byte Ae ol - 6 | § substituting equation (6) in equation (2), we get | ays | | EgetEo Rt it) = ol ¢ sino ) | The time Tax When current i(t) becomes maximum may be obtained from | secondition | di | dt —RTmax Tmax o,e 2b 998 Tra SE e 2L sin ©,T pax = 0 —BTmax RT, o o,e 2b R pean an ©, Tmax SiN, Tyaag 2 C080, Tray o = tan ©; Trax ae Trax = o, ‘an (8) The current i(t) becomes zero at t= ~™& - SCR T, gets turned off, capacitor ‘C’ gets charged to voltage V,. Mode: During this mode, se. from the instant A to B, SCRST, and T, are in off State, ‘5 ()=0 and V,=E.+ By Mode 3: When thyristor T gets turned on, reverse resonant current flows through q 2 the load, 5.8 Power Electronics This mode of operation is described by 1 di fot +L a +R v at (9) with the initial condition i(t) = 0. positive and negative load current waveforms must be equal under s, ea state conditions. dy The necessary condition for steady state is V, = Ege + Ee c (10) The capacitor voltage, at the end of each half cycle is given as 14 & fist -B 0 substituting equation (10) in equation (11) we get yy 17 Ah fist -E, é (uy y 1 Ee "¢ fiat - 2B, 0 E,.+Ec -Rt dC ¢ 2L sinw,t dt | - 2E, @,L i The solution to above equation is given as Ey. +E, ft Ege = 7S x4 f+ Port _ 2B (12) a 242 C(R? + 40? L?) from equation (12), E, may be given as Re 4L Fork E,.41-| ————— | I te 7°" - C(R? +40? Lv) (13) he 4L tee 2k |_2 R? +40? 2) ‘Inverters 5.9 jnuting value of @, from (3), we get subst 8) = @ 20yL E, = Ege | ——- “lol (14) Loe 2ob ee 8 f,1, (AF) (16) 2. Design of capacitance (c) . 1 R From the express a ri Pression Tr 1 R? o2—- 2 r LC 4? 1 1 or c= L ot +R? es (17) In order to maintain the circuit in the under damped condition, maximum value of R must be used if the load is a variable one. Voltage rating of capacitor must be greater than (Eq + Eg.) for reliable Operation of the circuit. il, The voltage Ey, obtained by equation (14) must be of sufficient magnitude to commutate the thyristors with in turn off time (T, oft): Here, minimum value of ‘R’ is used. 5.10 Power Electronics 3. a. b. 5.4 MoprFiep SERIES In order to overcome some 0} series inverter is intro mutually coupled indu same value of inductance an‘ Selection of SCR The forward blocking vo! value (Ee + Bac) Peak load current riage rating of the thyristor must be greater h ‘AN the value is given as Re efor ce ect E peak o,L The load current rating of SCR must be greater than the peak load currg In this case R value is minimum. ent, The ringing frequency @, value must be approximately equal tothe desir output frequency (@,) such that the off time of thyristors is greater than i. turn off time of the SCRs. 1 Here, Tor = (er secs. INverTER the drawbacks of basic series Inverter, modified e normal inductance is replaced by a duced in which th 5.3(a). Inductors Ly and Ly have tance as shown in fig d are closely coupled. L,=L2 Figure 5.3 (b) Figure 5.3 (a) DP,’ | Oo Inverters 5.44 this mutually coupled inductor, even if SCR gone ven off process of SCR T, there will ne 1s turned ona little I ¢ tl ot be pele ss de source. © any possibi foe Feit ofthe de source. It may be explained as follows, ao concept OF Dead zone: assume that SCR T, is triggered a lit wet “When the SCR T) is triggered at i iret num of Process of capacitor 1S slightly less than (Eg + E4,) value and the load ae across the current values are nearly equal to zero. A voltage equal to th a He load petween the voltage across capacitor and load voltage ap oe ifference AsL; is closely coupled to L, this voltage appears across L - peross Ly, the cathode potential of the thyristor when compared to re a ea = Associated Voltage and current igure. 5-3(¢) waveforms of Fig 5.3 (b) 5.12 Power Electronics ~~, As a result, the thyristor T, gets turned off by reverse volta, e across it. Hence, even if thyristor T, is turned on before the tur : Pei a Off o¢ thyristor, the short-circuit of D.C source doesnot take place, - y Inthe same manner, even if SCR T, is triggered a little before the con process of SCR T, short circuit of de source doesnot take place limit of output frequency may be increased above the resonant fre, the RLC resonant circuit. 2. The draw back of high pulsed current from de source is overcome 5 two capacitors connected across source. The circuit diagram is as g fig 5.3 (b). Circuit description It consists of two capacitors C, and C, such that C, = C) and two inductors | and Ly where Ly = Lp. Power can be drawn from the de source during both i) half cycles of output voltage. Here, one half of the load current is supplied by de source and the other half by using capacitor C or C2. TAMUtat ign Thus, WMency of Y Usin, how ig Its operation may be explained as follows Initially, capacitor C2 is assumed to be charged to a voltage ‘E,.’ with polarity as shown in fig 5.3(b). As the capacitors C, and C, are connected across the supply they have to share the source voltage such that the voltage across capacitor C now becomes (Eq, + Ec) with upper plate positive and lower plate negative When thyristor T, is triggered at the instant t = 0, two currents flow through T, and R, where current ‘i,’ flows through the path as follows. Eq. —T, - Ly - load - Cy - Ey Now, the capacitor C, gets charged with the upper plate positive and lower plate negative. The another current which flows through load is the capacitor discharging current i, whose path is given as C\*-T, -L, - load — C,~ as shown in figure 5.3(b) As the driving voltage (Eg + Eg,), capacitors C,, Cp and initial conditions are same for both these paths, i, is always equal to iy. Therefore, 50% of the load current is drawn from source voltage and 50% is drawn from capacitors. At the instant A, the load voltage and load current becomes zero and hence the thyristor T, gets turned off and the voltage across the capacitors gets reversed At this instant capacitor Cy gets charged to (Ec + Ey,) in opposite direction where as capacitor C, charges to a voltage of Ec. When the SCR T) is triggered at the instant ‘B’, same operation takes plac? and hence the cycle repeats. Here also, 50% of the load current is obtained from the de input source and the remaining 50% from the capacitor discharge current ; ve, the Thus, the input de supply doesnot remain intermittent in nature and hence, th ripples are minimized. 5.5 PARALLEL INVERTER syallel inverters are those inverters where the commutating elements L and C ae connected across the load. Its circuit diagram is as shown in fig 5.4 (a). N A 8B Transformer et FOCOHOOONS \ cegegee 4-H $ [I tc Figure 5.4 (a) 5.20 Power Electronics Circuit description ' . r he primar’ It consists of two thyristors Ty and T, connected to the primary of the transformer Here, the capacitor is connected across load via the transformer and hence, itis Here ne paralicl inverter. The function of L sto make the source current const at Tp and in order to prevent the instant discharge of capacitor *C” wheneyey occurs. Parallel inverter ts generally used to produce a Square ayn ihe D.C souree. By alternately switching the WO SCRS D.C sour 1 temative manner to the each half of the transformer prinan, lta across secondary of the transformer is obtained, source is connected to mid point of the primary, Its ined in different modes as follows: thyristor switching is connected in and there by square wave V Positive terminal of D.C operation principle may be expl , is turned on. The current starts flowing through Mode 1: At the instant t= 0, T and its direction is given by the leftside of the primary winding, Ego - L-K-C-1, -B& ‘As a result, supply voltage Ege appears across the left half of the transformer primary. Because of the closely coupled coil and same number of turns the voltage across the DK is also Ey,. By the dot convention, the voltage across kC=+E,., voltage across DK = Eqc. On the secondary side of the transformer 2E4, is induced. Hence the capacitor gets charged to a voltage of 2E4, with the polarity as shown in fig 5.4 (a). Mode 2: At the instant t = Tp, thyristor T, is triggered. When thyristor T, is in the conduction state, commutating capacitor ‘C’ applies a voltage 2E4, across the thyristor T,. Due to the reverse voltage drop across the thyristor T, for a sufficient amount of time, it gets turned off. When T) is on, the current starts flowing through the right side of the primary winding and its direction is given by Eg,t - L-K-D-T)- Eg voltage across KD = Ey,, voltage across CK = Eye. During this mode, a voltage of 2Eg, appears across transformer secondary and the commutating capacitor has reverse polarity. As a result, negative cycle of the output voltage is obtained as shown in fig 5.4(b). Mode 3: At the instant, t= 2To, thyristor T, is triggered and hence the thyristor Ty gets tumed off by following the above process. Hence, in this way if triggering pulses are given at regular intervals of time to the alternate thyristors, approximately rectangular voltage waveform may be obtained as shown in fig 5.4 (b)- Advantage The circuit is so simple, small in ploys complementary voltage commutation, ze and less expensive as it em 2 eae en nN NGIAECAS GA dei A i a ii asia baie Inverters 5.24 A Supply voltage I i | i | it It Figure 5.4 (b) Voltage and current waveforms for parallel inverter CO TT NT NET — — — ——— ee 5.22 Powor Electronics Disadvantage Whenever the cireuit is operated at low frequencies, transformer's gg, saturated which isan undesirable restlt, This is because, at low frequen”! turates the transformers Pina! thyristor conducts for higher duration which s re. Analysis of circuit 5.4(a) Incase of purely resistive load, the circu circuit as shown in fig $.4(c). t 5.4(a) must be reduced to 1S eqquivay len N, 000000000000000000000 [7 000000009000000000000 4 = SS N to DDI p PB —— a L Ih : Figure 5.4 (c) The following assumptions are made before analyzing the circuit. 1, The transformer used is assumed perfect so that it has ampere turn balance between windings at all times, 2. Magnetizing current is neglected. Practically, the de source voltage Ey, across the winding can be maintained by a changing flux which demands a magnetising current. When thyristor T, conducts, the switch has the position shown in fig 5.4 (¢) and the instantaneous conditions can be expressed as di ede () where Ep, is the voltage drop across Ty. For a purely resistive load, from fig 5.4(c), we get =I, and oN = RNY F seconds) where N, is the number of primary turns and Ny is the number of second re turns. eee ‘Inverters 5.23 = Ny gan fb SACD igNy = (i, - ic) Ty =i 2 N = (iy ~ 2ig) ee 6) eh (4) equation (3) and (4), we get jor ea - dE. \N, Np = | ip -2C —C JO 'oN2 (. dt } 2 (5) from (5) and (2) dE.) R(N,Y =|i)-2c—£) S|) Av Ec (1 Cc | = (2) (6) Ifthe value of ‘L’ is so selected that i 148 substantially constant at a value I, ‘hen equation (6) gives first order equatio: nie., deo | 2 1 dt * ro Ec= 2c ae (7) N 2 ne 'N, 2nd K is constant that may be determined as follows: he capacitor volta qT ie at the beginning of the second half period has the “me magnitude as at th '¢ beginning of a period, but with opposite sign. Hence, 2 IR (Gn To!2Y/ -IR cial CR =—>_K an? tKe re o's the periodic time. From equation (8), (8) “here we get (9) 5.24 Power Electronics from equations (9) and (7), we get nt IR yee Fem 2n? (01,2) (10) at | But, if Ny is replaced by one half of the tot 21R [5] Ni’ ¢ half of the primary winding and I is the current in this load when dE ($2) =0 2IR el By substituting above equation (10), we get In equation (10), 1 = a IR ws primary turns Nj’, then > 7 becomes = . This is the load resistance reflected across ont Ec=2E /2/, (ul) ine 16) AR From equation (11), it becomes clear that the capacitor voltage Ec increases (0°) CR exponentially towards a limiting voltage 2E. The practical value of generally such that any (2 e CR <<] and hence, nif 5 He MCR 7) Snuetters 5.95 sg when Be © O, equation (12) becomes, tel yo Days / mr 0 -wli-% AK mug 2-4 e CK Mtoe o 6 Ras 2h = log.2 = 0.6931 0.6931xCR tone = aa (3) The value of C, load resistance R and n? must be chosen such that tory is. eater than the turn off time of the SCRs. 5.6 Parattet INVERTER WITH Fee Back Diopves Greuit description ‘Thecircuit diagram for the parallel inverter with feed back diodes is shown in the figure 5.5(a) D, and D3 are known as feed back diodes. The diode D; is used to alow the trapped energy in the inductance (L) to discharge. A small value of msistance is connected in series with the diode (D3) to speed up the discharge of ‘he inductive energy. Inactive with Inactive toad i Parallel Inverter relia Come and feed back diodes 5.26 Power Electronics Operation is explained in different modes: Mode 1: Give the gate signal for the S.C.R (1). Now the current start through the upper half of the primary winding. ‘The current path ae Mowing ~O-M-T,-L~-Eac.- Fection i 1c ‘The voltage Ege is present in the upper hajp oy ing Because ofthe closely coupled inductor, same amount te pending upon the dot convention. The capac Ese th lower plate positive and upper plate siter-C 5 Bative ‘ E gee primary wt induced in the lower half de charged to voltage of 2E ye Wi shown in fig.5.5(a) Trigger T, E “f sroger 7. —+ A. \ haf | | i. i i ot + I i 1 1 i t i i i i i KY +t Tylon 4 i | i 1 a i i 1 i i 1 i t 1) L 1 i i i Toy ot a we of tt ! i I 1 | 1 ! | 1 i | T —t ret | i i i <= oot SF et T i 1 Figure 5.5(b) As (b) Associated wave forms of parallel inverter with feedback si0%#* Inverters 5.27 peScR (7) is fired, the voltage across the capacitor which is 7 We es the main $.C.R (T)). The SCR T, gets turned off, yA oe bias ¥ et pias actoss S.C.R (T)) gradually decreases from 2Ey, as the thee charged in the opposite polarity (C, - N- O ~ M -C_). During Fase ion, $.C.R (T) must be completely turned off. The voltage Py Oe or becomes oscillatory during the charging condition, The ce begins to conduct and it will take the ssa of the load current because the load voltage has changed the polarity, current continues to flow in the same direction due to the presence a pnuctance ofthe load. When the Diode (D,) is conducting the energy is fed uth te source (feed back diodes). When the Diode (D,) starts conducting Mmrappes energy in the inductor dissipates through the Diode (D3) and pesistance(R). ‘When the load current is reversed and the capacitor voltage reaches tp Eye the Diode (D3) stops conducting. Now, the 8.C.R(T) takes the load curent This period will continue upto the instant S.C.R (T}) gets triggered. Diodes pyand Dy will conduct till the load current reverses again, The draw back of the circuit is, during commutation a large current flows through the S.C.R and the inductance (L) is almost independent of the load current. Atthe end of the commutation the rate of rise of current is high and small value ofthe inductance is connected in series to bring the high value of di/dt in S.C.Rs toreasonable limit. Design aspects Based upon the following assumptions, the commutating components L and C of parallel inverter with feed back diodes are designed. 1. The load current (I,) waveform should be of rectangular shape. 2. The circuit turnoff time must be greater than that of the turnoff time (t,) of an SCR. 3. The peak current rating of the thyristor must be twice that of the normal load current value, When the thyristor T, is triggered, the discharge current is represented by the equation i())= A sin ot + B cos at re)) where, 5.28 Power Electronics Land € are commutating components A and Bare constants wwhech may be determined OM the in conditions: Such as io) = 105 i AP 4c tho L from (1) and (2), we Bet att 0 Bel, By differentiating equation (1) with respect to *U, we get di(t) it Aw cos ot - Bo sin ot di and qi}. = A® atho a (5) we get By substituting equation (3) in or from equations (1), (4), (6), we get F iC i(t) = 2a fS sin at + [,' cos ot | “+ peak discharge current from the capacitor should be twice the refle? | load current or f fal’ transformer wes! | | ae when Inverters 5.99 nal load current = reflected load current gor sion (8) becomes atid 7 Cc : fc ary SVL je D, conducts until the discharging current reaches the Peak value, the Div gemains in reverse biased condition ao ° s the diode D, conducts ne period must be at least equal to the turnoff time 7 ofanSCRT He ve considerations, ty may be given as I pg aove (9) = 12 4R,C (12) Voltage rating of the capacitor is given as Eq >> 2B ye Current rating of the inductor is I, >> 21, Peak current rating of thyristor is greater than twice the reflected load current ‘alte and forward blocking voltage of thyristor is also greater than twice the Supply voltage. 5.7 Sincte-PHase Brroce INVERTERS Single-phase Bridge Inverters are of two types. They are 1 . Single-phase half-bridge inverters Single-phase full-bridge inverters. 5.7.1.4, Single-phase half ~bridge inverter: (Resistive load) 's circuit diagram is as shown in figure 5.7(a). Cir It on arasce and resistive load. The two thyristors T, and T. sts of two SCRS > which ate in series are connected across the source. fy { 5.30 Power Electronics Operation Its operation is explained as a follows when thyristor T is —1- = turned on for a time period of E/2 a Tp/2, the instantaneous voltage L paneer ny y across the load ep is Eg/2. Atthis ee | | instant (= Tp/2, thyristor T, gets commutated and T) is turned on. ¢ 73 When T) conducts for a period of T,/2, the instantaneous voltage across the load is given as ~Es/ 2. Hence, the voltage across load is an alternating one whose amplitude as Eg/2 witha frequency 1/Tg Hz. By controlling the time period *T, fra ty of the inverter output voltage may be varied. Here, conduction Period ar SCR is equal to the gate pulse period. As soon as the gate pulse is ee thyristor gets commutated. he Its voltage and current waveforms are as shown in Fig. 5.7(b). (a) Single phase halt bridge i, © inven ' E fg | | | I f ! 1_,t it 1/2 TT, BT /2 le i | I | i i —+t Tt T, i i | | j j E/2 aa - 1, 1 E ot 0 Tet, [te -EJ2 |- i \ i . i i \ = EJR A i i j 1 ot Figure 5.7(b) ictal Invortors 5.34 “e load ; itv si voltage is given as age ONT ne Ky forO Fundamental current at ot Load current waveform with large value of load inductance Figure 5.8(d) ee 'nvorters 5.44 gg the interval 0. This process repeats for T, and diode D, and so on. For RLC and RLC overdamped load case Inthe RLC load overdamped case, and RL load, T, gets turned off by forced commutation circuitry at To/2 eventhough it carries current due to the presence of load inductance. As a result, voltage across the L component of the load gets reversed and hence diode D, is forward biased and conducts the freewheeling current. When the circuit current reverses it’s direction, diode D, switches off and the current flows through T, which has been already triggered at t= To/2. R . c Figure 5.8(e) RLC Series.circuit 5.42 Power Electronics RLC under damped ioag RLC over damped load Figure 5.8(f) Associated waveforms of series RLC circuits 5.8 MC Murray Hate Brioce Inverter MC Murray half bridge inverter circuit diagram is as shown in figure 5.9(2)- +o Figure 5.9(a) it description enter eappeT de supply 'S connected to this circuit Since, the auxiliary SCR St gation process occurs in this Sircuit, this is also known as auxiliary SCR- inverter. I consists of two main thyristors Ty and T). Its commutating auxiliary thyristors T,,, T,5 aporation may be explained as follows: Oe ere eens 5 set from the previous mode, thyristor T, 's carrying the load current whereas Vator Cis charged to a voltage more th han 2E 4. with the pol: : i olarity as shown in 2), All other devices are in off state, pee pmtate i vs are common LC network and the In order to commutate thyristor Ty, auxiliary thyristor T,, is triggered. irerever thyristor Ta) is triggered, the capacitor C begins to discharge. It’s qgnmay be given as C-L-T-T-c- Whenever the above discharge current (Ic) exceeds load current (1,), the urent flow through thyristor T, gets decreased to zero and the excess current jows through diode Dy. Due to the forward threshold voltage of Dj, thyristor T, stumed off, Here.the capacitor continues to discharge through the diode D, aid hence, delivers the load current After some time, the discharging of capacitor ‘C* inthe reverse polarity takes pl inductance *L’, and again recharging of it face in an oscillatory manner due to the presence of The capacitor current (Ic) assumes a peak value whenever the v. ‘gets reduced to zero and it decays subsequently. Whenever, Ic becomes equal to I, after the peak value attainment thyristor Ty should be \iggered. In order to control the capacitor voltage delay of triggering the thyristor T with response to T,) is maintained. As soon as, thyristor Ty gets sed on the discharge current flows through it instead of flowing through Diode >i. Here, the load current (1,.\¥is maintained by load inductance and charging of “apacitor ‘Cr, oltage across When the charging of capagitor C, is completed. With right hand plate positive and left hand plate negative, the net current through the thyristor T, reduces to a 210 value and the excess current (Ig - I.) flows through diode D5. Due to the “Ward threshold voltage of D, thyristor T, gets turned off. Here, the load inductance ‘L’ feeds the energy back to lower half of the Source, Due to the presence, of inductance, current in diode D) cannot increase Mtantaneously from zero to a full load current value. It gradually takes up the ero resulting the turnoff process of deurrent 1, during which Iya Feduces to zero r 8 Pp ‘tistor T, |: Diode D, continues to conduct till the load current ‘I," becomes zero, and sent and reverse current flows. "tistor T may conduct if it’s gate signal is present an s. et 5.44 Power Electronics auxiliary thyristor Taps thyristor T, is turned offand Fig. 5.9(b) C¥Cle rep, ts, Ry tiggcrng forms are ed wave! as shown in Tis assoc 4 g triggered 7) '$ trigger 7, istriggered > s triga ‘ed T, IS trigger Y is triggered ered 5. 1 i Lt ' rot T 1 ' i t I ‘ \ jit | jt i 1 + Tand In i ' ' ! ‘ 1, Lt mT | — ' 7 ; ly a> ian { 1 a hy ory ns ! ' t ) 1 i [+ [ 1 od “ ' yobs 1 itt + La ! tt 1 f rr tot r tlt t Figure 5.9(b) V (b) Voltage and current waveforms in McMurray Inverter Inverters oreo MC Murray Hair B opal bridge inverter is a current o naiagram i8 as Shown in fig 5.19(q) 5.45 RIDGE InvertER ; ommutated volt * yr age source inverter, sc \, Main TOUT ate Figure 5.10(a) circuit description consists of main thyristors T, T and the main diodes D, TynTap auxiliary diodes D,,D | and D>. Auxiliary thyristors ‘a2 damping resistor Ry, inductor ‘L’ and capacitor Here, three wire de supply is required and the ac load sconnected between the terminals P and Q as shown in fig 5.10 (a). Here the capacitor provides the energy required to commutajé (he main thyristors where asinductance limits di/dt value to. a safer value in thain and auxiliary thyristors. Asthis circuit includes the components, auxiliatydigdes and damping resistor ‘fa’ when compared to the original circuit, itis known as modified MC Murray halibridge inverter. The operation of circuit will be described for a lagging power factor load (RL load) with the following assumptions. |. During the commutation interval, load current remains constant, 2. Thyristors and diodes are ideal switches. 3. Inductor L and capacitor C are ideal so that they have no resistance. The operation of this circuit may be explained in different modes. Mode 1: Thyristor T, is in the conducting state which conducts a constant load current ic., Ip) = Ig. Because of the commutation of previously conducting thyristor Ty, capacitor ‘C’ is charged to a voltage of about Eg, with the polarity 38 shown in fig 5.10(b). When T, conducts, the commutation cireuit is sad to be fig 5.10(b). inpassive mode. T peered a = f the main ’ . liary thyristor Tis triggered at t= 0 to turn off th a les aay eurrent Ic builds up through resonant circuit whos¢ path is Eetistor Ty, capac Tar ~ C= L The voltage drop across the thyristor T, ven as Lt — Ty — nics Power Electro 5.46 reverse biases Dj, hence. the thyristor T, only carries the current I. ang reverse bia . 5 ¥ ecrease a nd ny diode Dy. An inerease 1 Je value decreases the value of Iy,, 25 1, is ¢, (21, tlonk J. At ty. ic rises 10 Ig and hence Ip, = 9. Asa resui, ts turned off at ty thyristor Ty £¢' hee {<1} Figure 5.10(b) Mode I, for € < 0 whenever discharg ent flows throug Figure 5.10(c) Mode Il, for 0 < 1 ing current Ic exceeds the load ¢ h diode Dy. This diode D, is knows The forward threshold voltage of Dy reverse biases te rwvard blocking mode. The capacitor current Ic r voltage Vc reduces to zero. Ai sult the cap Mode 3: After ys (Ig). this excessive curr ‘ey recovery diode. to bring it to fo a peak value Icp. Whenever the capacito! attainment of Iep value, Ic begins to decrease and as are: begins to charge in the reverse direction. Mode 4: At tg, stops conducting and t current I, flows through the path ener: thyristor T, falls to Ig value. Now, the di the capacitor current Ic ucts if the gate signal is present. C the thyristor T, cond! Ee Ege Bal typ Cob = toad “3 when the auxiliary thyrist ly with reverse polarity and at tr, or Ta, is triggered. Load current charges lot, Figure 5.10(e) Mode IV: for e~ Wh

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