ITPM-ER01-IT8212F V0.4.

2
Date:10/23/2006

Errata V0.1 for IT8212F V0.4.2

Note: The corrections have been highlighted in red in the corresponding pages attached.
Errata Version Section Correction Page
0.1 5 • In table 5-4 Pin Descriptions of Flash/ROM Interface*, added “5V 10
tolerant” to Flash/ROM Interface.

1 IT8212F V0.4.2 Errata 0.1 Released on 10/23/2006

IT8212F
Table 5-3. Pin Descriptions of IDE Secondary Channel Interface
Signal Pin(s) No. Attribute Description
IDE Secondary Channel Interface (3.3V CMOS I/F, 5V tolerant)
SDD15-0 90, 95, 97, IOP IDE Secondary Channel Data Bus
101, 103,
105, 107,
112, 111,
106, 104,
102, 100,
96, 94, 89
SA2-0 82, 85, 84 OP IDE Secondary Channel Device Address
SCS1-0# 81, 83 OP IDE Secondary Channel Chip Select
SIOW# 98 OP IDE Secondary Channel IO Write Strobe
SIOR# 93 OP IDE Secondary Channel IO Read Strobe
SDRQ 88 I IDE Secondary Channel DMA Request
SDACK# 87 OP IDE Secondary Channel DMA Acknowledge
SIORDY 91 I IDE Secondary Channel IO Channel Ready
SINT 86 I IDE Secondary Channel Interrupt
SCBLID# 114 I IDE Secondary Channel Cable Assembly Type Identifier
SRST# 115 OP IDE Secondary Channel Reset

Table 5-4. Pin Descriptions of Flash/ROM Interface*

Signal Pin(s) No. Attribute Description
Flash/ROM Interface (3.3V CMOS I/F, 5V tolerant)
FWE# 83 OP Flash/ROM Memory Write Enable
This signal is multiplex with SCS0#.
FOE# 81 OP Flash/ROM Memory Output Enable
This signal is multiplex with SCS1#.
FCS# 109 O8 Flash/ROM Memory Chip Select
This signal is multiplex with PCK66ME.
FA16-0 84, 85, 90, OP Flash/ROM Memory Address
51, 53, 82, These signals are multiplex with the following signals (from MSB to
52, 55, 54, LSB): SA0, SA1, SDD15, PCS1#, PCS0#, SA2, PA2, PA1, PA0,
59, 61, 63, PDD15-8.
66, 71, 73,
75, 79
FD7-0 80, 78, 74, IOP Flash/ROM Memory Output Enable
72, 70, 65, These signals are multiplex with PDD7-0.
62, 60
*: The above pins are multiplex function pins.

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