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The Bipolar Opearation Amplifier Ua741: 1 Bias Generator
The Bipolar Opearation Amplifier Ua741: 1 Bias Generator
The 741 is a 3 stage bipolar opamp. The dierential input signal is rst amplied and converted to a single ended output by a pnp dierential amplier. The single ended output is further amplied by a common emitter amplier and then given to the nal push-pull output stage which includes short circuit protection. A bias generator provides bias currents to all stages of the opamp.
V+ Q9 Q12 Q13 13A Q19 Q18 40K Q16 Q7 Q11 5K Q10
R4 R10
Q8
13B Q1
R5
Q2 Q4
30pF
39K
Q3
R7
Q17 Q6
R3
Q23 Q24
R11
Q5
R1
R9
100
R8
1K
50K
50K
This circuit looks quite complicated. It is much easier to understand if we look at various functional blocks of this circuit individually.
Bias Generator
The purpose of the this circuit is to provide a reference current for various current mirrors used by the amplier stages. The circuit is based on a Widlar current mirror circuit.
V+ Q9 Q12 Q8
Idiff
Q13 13A
Iref
13B .75
.25
Drive for Class AB Output
R5
39K
Middle Stage
Q11
Q10
R4
5K V-
R5 sets up a reference current Iref which ows through the diode connected transistor Q11. V+ V 2VBE R5 With a nominal supply voltage of 15V, VBE = 0.65V and R5=39K, this gives a value of 736A for Iref . This is mirrored by Q10 which is connected in Widlar conguration with a resistor R4 in its emitter. Equating voltages at the base of Q10 and Q11, Iref = VT ln Iref Is = VT ln IWidlar Is + R4 IWidlar
where Is is the reverse saturation current of identical transistors Q10 and Q11, and VT is the thermal voltage KT /q. Iref VT IWidlar = ln R4 IWidlar This can be solved iteratively to get IWidlar . This gives Suppose we start with a guess value of 500 A for IWidlar , The next few values which are calculated are: (in A) 2, 30.6, 16.5,19.7, 18.7, 19, 18.9 etc. Thus, IWidlar is nearly 19 uA. This current source is connected to another pnp current source, which mirrors the total current of the dierential stage. Suppose the current through each arm of the dierential stage is I. Then a current 2I ows through the reference transistor Q8. This means that Q9 sources a current which is 2I minus the base current of two pnp transistors. The base currents of the pnp transistors in the dierential stage are added to this. The base voltage of the dierential transistors now adjusts till the current through Q9 plus the base current of two pnps equals the current through Q10. Since the base current of pnp transistors is cancelled out, each arm of the diential amplier will get half the current through Q10. Thus, each arm of the dierentila amplier gets 9.5A in our example.
The dierential stage is the rst gain stage seen by the inputs. Since a high input impedence is required, each arm of the diential amplier uses an npn emitter follower, which feeds a pnp common base amplier.
V+ Q9 Q12
2I 2/(1+2/ p)
Q8
Q1
I R5
Q2
I
39K
Q3
2/ p
Q4
Q7 Q11
R4
Q10
Q5
R1 R3
Q6
R2
5K
1K
50K
1K V-
A common base pnp stage allows us to take out the base current of the two pnp transistors for compensating the mismatch in the current mirror Q8-Q9. The dierential stage is loaded by a current mirror which also does dierential to single ended conversion. The npn current mirror load Q5-Q6 uses the transistor Q7 to supply the base current of Q5,Q6.
V+ Q9 Q12
2I 2/(1+2/ p)
Q8
Q1
I R5
Q2
I
39K
Q3
2/ p
Q4
Q7 Q11
R4
Q10
Q5
R1 R3
Q6
R2
5K
1K
50K
1K V-
V+
Bias Ref
Q13
13B 30pF
Input
50K
R9
100 VV+
R8
Bias
Q13
Q14 27 27
R6
13B 30pF
R7
Q23
V-
V+
R7
Q22 Q24
R11
50K VV+ Q9 Q12 Q13 13A Q19 Q18 40K Q16 Q7 Q11 5K Q10
R4 R10
Q8
13B Q1
R5
Q2 Q4
30pF
39K
Q3
R7
Q17 Q6
R3
Q23 Q24
R11
Q5
R1
R9
100
R8
1K
50K
50K