3/29/2023

ĐẠI HỌC
CÔNG NGHỆ VIETNAM NATIONAL UNIVERSITY HANOI (VNU) ĐẠI HỌC
CÔNG NGHỆ
Outline
ĐẠI HỌC
CÔNG NGHỆ VNU UNIVERSITY OF ENGINEERING AND TECHNOLOGY
• Introduction
• Design methodology
• Half Adder (HA)

INS3179: Digital Design • Full Adder (FA)

Combinational Logic Design Principles • Half Subtractor (HS)

• Full Subtractor (FS)
• N-bit Adder-Subtractor
Xuan-Tu Tran, PhD
VNU Laboratory for Smart Integrated Systems (SISLAB) • Comparator
• Multiplexer/De-multiplexer
• Encoder/Decoder

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ĐẠI HỌC
CÔNG NGHỆ Introduction ĐẠI HỌC
CÔNG NGHỆ
Analysis of Mixed-Logic Circuits

• History
– The earliest hardware for carrying out digital
communication was a simple adding machine A
built by Blaise Pascal (1640) called the B
Pascaline.
C
– In 1822 Charles Babbage designed a
mechanical calculator called a difference D
engine (a famous calculating engine), which
was capable of holding and manipulating
seven numbers of 31 decimal digits each.
E
The London Science Museum's working
difference engine, built from Charles
– Both of this calculators were constructed using Babbage's design (1991).
gears, cams, levers, and the like.

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ĐẠI HỌC
CÔNG NGHỆ
Analysis of Mixed-Logic Circuits ĐẠI HỌC
CÔNG NGHỆ
Analysis of Mixed-Logic Circuits

A A+ B A A+ B
B B ( A + B )C
C C

D D
A+ B + D

E E

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ĐẠI HỌC
CÔNG NGHỆ
Analysis of Mixed-Logic Circuits ĐẠI HỌC
CÔNG NGHỆ
Analysis of Mixed-Logic Circuits

A A+ B A A+ B
B ( A + B )C B ( A + B )C
C (( A + B)C )(A + B + D ) C (( A + B)C )(A + B + D )
D D F
A+ B + D A+ B + D

E E
DE DE

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ĐẠI HỌC
CÔNG NGHỆ
Design methodology ĐẠI HỌC
CÔNG NGHỆ Design methodology

• Designing a switching circuit • Example

A B C

– Construct the Truth table – Design a comparator for two inputs (A & 0 0 1
B) with 0 1 0
– Build the switching function
• C = 1 when A = B
– Optimize this switching function 1 0 0
• C = 0 when A  B
– From the switching function, design the switching circuit by using basic 1 1 1

logic elements

C
A
C = A B + AB
B
Karnaugh map can be used !
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ĐẠI HỌC
CÔNG NGHỆ Half Adder (HA) ĐẠI HỌC
CÔNG NGHỆ Half Adder (HA)

• Description • Schematic S = A B
– HA has two inputs, generally labelled A and B, A B S C
and two outputs, the sum S and carry C. 0 0 0 0 XOR C = A.B
0 1 1 0
– S is the two-bit XOR of A and B, and 1 0 1 0 A
– C is the AND of A and B. 1 1 0 1 S
B
S = A B
C = A.B A S C

B HA C
– Essentially the output of a half adder is the sum of
two one-bit numbers, with C being the most
significant of these two outputs

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ĐẠI HỌC
CÔNG NGHỆ Full Adder (FA) ĐẠI HỌC
CÔNG NGHỆ
Full Adder (FA)

• Description
A B Ci S CO S = A  B  Ci
0 0 0 0 0
– 3 inputs: A, B, and carry in Ci Co = AB + Ci ( A  B) = AB + Ci A + Ci B
0 1 0 1 0
– 2 outputs: the sum S and carry out CO 1 0 0 1 0
Ci
1 1 0 0 1
A S 0 0 1 1 0 S
B 0 1 1 0 1 A
FA CO
Ci 1 0 1 0 1
1 1 1 1 1 B

CO
S = Ci ( AB + A B) + Ci ( A B + AB) CO = Ci AB + Ci ( AB + A B + AB)
= Ci ( AB + A B ) + Ci ( AB + A B ) ( )
= Ci + Ci AB + Ci ( AB + A B)
= A  B  Ci = AB + Ci ( A  B)
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ĐẠI HỌC
CÔNG NGHỆ
Full Adder (FA) ĐẠI HỌC
CÔNG NGHỆ
4-bit adder

S = A  B  Ci
A3 B3 Cin3 A2 B2 Cin2 A1 B1 Cin1 A0 B0 Cin0
Co = AB + Ci ( A  B) = AB + Ci A + Ci B

Ci FA FA FA FA

S
A
HA
HA Cout3 S3 Cout2 S2 Cout1 S1 Cout0 S0
B

• Use four FA units in parallel

CO • The carry out of the previous FA is connected to the carry in of the
next FA

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ĐẠI HỌC
CÔNG NGHỆ
4-bit adder circuits ĐẠI HỌC
CÔNG NGHỆ Half Subtractor

• Description
A B D Br
– Subtraction
5 A1 S1 4 10 A1 S1 9
– Inputs: A and B 0 0 0 0
3 A2 S2 1 8 A2 S2 6
– Outputs: D (Difference) and Br (Borrow)
14 13 3 2 0 1 1 1
A3 S3 A3 S3
12 10 1 15
A4 S4 A4 S4 1 0 1 0
6 B1 6 B1
D = A B 1 1 0 0
2 7
B2 B2 Br = A.B
15 4
B3 B3
11 16
B4 B4
7 C0 C4 9 7 C0 C4 14 A D D
A

74LS283 74LS83 B HS Br
Br
B

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ĐẠI HỌC
CÔNG NGHỆ Full Subtractor ĐẠI HỌC
CÔNG NGHỆ
Full Subtractor

• Description A B Bri D BrO D = A  B  Bri

– Subtraction
– Inputs: A, B, and borrow in Bri 0 0 0 0 0 Bro = A.B + A.Bri + B.Bri
– Outputs: D (Difference) and BrO (Borrow
out) 0 1 0 1 1
Bri D
1 0 0 1 0
Bri HS
1 1 0 0 0
A D
A
FS 0 0 1 1 1
HS
B BrO
0 1 1 0 1 Bro
B
1 0 1 0 0
D = A  B  Bri
1 1 1 1 1
Bro = A.B + A.Bri + B.Bri

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ĐẠI HỌC
CÔNG NGHỆ Full Adder vs. Full Subtractor ĐẠI HỌC
CÔNG NGHỆ
Full Adder vs. Full Subtractor

• May we use FA to construct FS?

• Constructing FS from FA
D = A  B  Bri

D = A  B  Bri FS
Bro = A.B + A.Bri + B.Bri Bro = A.B + A.Bri + B.Bri
A Bri
S D
Ci S
= A.B. A.Bri .B.Bri B A
FA CO FA BrO
( )( )
A
= ( A + B ) A + Bri B + Bri Ci CO
B
B

= ( A + B )(Br + A.B )
i

= A.Bri + B .Bri + A.B

= A.B + A.Bri + B .Bri
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ĐẠI HỌC
CÔNG NGHỆ
4-bit parallel Adder/Subtractor ĐẠI HỌC
CÔNG NGHỆ 4-bit parallel Adder/Subtractor

• Operation principle
• Architecture B3 B2 B1 B0
SUB / ADD
B3 B2 B1 B0
– Addition operation
SUB / ADD A3 Cin3 A2 Cin2 A1 Cin1 A0
SUB / ADD = 0
A3 Cin3 A2 Cin2 A1 Cin1 A0 FA
FA FA
FA FA
FA FA
FA

– Subtraction operation
SUB / ADD = 1 Cout3 S3 Cout2 S2 Cout1 S1 Cout0 S0
FA FA FA FA

Cout3 S3 Cout2 S2 Cout1 S1 Cout0 S0

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ĐẠI HỌC
CÔNG NGHỆ Equal comparator ĐẠI HỌC
CÔNG NGHỆ Equal comparator (cont’d)

• Functionality • NXOR function

A B C

– If A = B then C = 1 0 0 1 NXOR symbol

– If A  B then C = 0 1 0 0
A C = A B + AB
0 1 0
From the Truth table, we have
1 1 1 B
C = A B + AB
Using De Morgan’s theorem, we have

C = A + B + A + B = ( A + B )(A + B ) = AB + A B A
C = A B + AB
➔ NXOR function B

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ĐẠI HỌC
CÔNG NGHỆ
Equal comparator (cont’d) ĐẠI HỌC
CÔNG NGHỆ 4-bit equal comparator

• Construct an 1-bit equal comparator (NXOR function) from NOT and NOR gates?
• Comparison for two 4-bit number
– A = A3 A2 A1 A0
– B = B3 B2 B1 B0 A0
B0
– Q = 1 when A = B
A1
– Q = 0 when A  B
B1
Q
A2
B2
A3
B3

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ĐẠI HỌC
CÔNG NGHỆ 1-bit comparator ĐẠI HỌC
CÔNG NGHỆ
1-bit comparator (cont’d)

• Functionality
– When A > B then Y2 = 1, Y1 = Y = 0 Y2 = AB ; Y1 = A B Y = AB + AB = A B + AB
– When A < B then Y1 = 1, Y2 = Y = 0
– When A = B then Y = 1, Y1 = Y2 = 0
Y1 (A < B)
A
A B Y2 Y1 Y
Y (A = B)
0 0 0 0 1 A= B B
Y2 (A > B)
0 1 0 1 0 A< B

1 0 1 0 0 A> B

1 1 0 0 1 A= B

Y2 = AB ; Y1 = A B Y = A.B + AB = A B + AB
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ĐẠI HỌC
CÔNG NGHỆ
1-bit comparator (cont’d) ĐẠI HỌC
CÔNG NGHỆ
N-bit comparator

• Construct an 1-bit comparator from 2-input NOR gates (IC 7402).
• Algorithm for building N-bit comparator
– A & B are two given binary N-bit numbers.
– Begin the comparison by looking at the high-order bits
– If the high-order bit of B is a 1 and that of A is 0, then A less than B
– If they are the same, either both 0 or both 1, we must look at the bits of the next higher
order.
– Continuing bit-by-bit comparison from left to right → we will eventually determine the
ordering of the two numbers (A & B).

– Using the algorithm to design 1-bit comparator and then, by cascading n of these,
produce an n-bit comparator.

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ĐẠI HỌC
CÔNG NGHỆ N-bit comparator (cont’d) ĐẠI HỌC
CÔNG NGHỆ N-bit comparator (cont’d)

• 1-bit comparator Ein Gin Ai Bi Eout Gout Eout = Ein Ai Bi + Ein Ai Bi Gout = Gin + Ein Ai Bi
– 4 inputs: Ai, Bi, Ein, and Gin
– 2 outputs: Eout, Gout
0 0 - - 0 0 = Ein ( Ai Bi + Ai Bi )
0 1 - - 0 1
Note: when Eout = Gout = 0 → Ai < Bi 1 0 0 0 1 0 = Ein ( Ai  Bi )
Ai, Bi Ai 1 0 0 1 0 0 Ai Bi
Ein, Gin 00 01 11 10 1 0 1 0 0 1
00 00 00 00 00 1 0 1 1 1 0

01 01 01 01 01
Eout = Ein Ai Bi + Ein Ai Bi Ei (L)
Eout (L)

Gin = Ein ( Ai Bi + Ai Bi )
11 - - - -
Ein = Ein ( Ai  Bi ) Gi (L)
Gout (L)

10 10 00 10 01
Eout, Gout Gout = Gin + Ein Ai Bi
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ĐẠI HỌC
CÔNG NGHỆ N-bit comparator (cont’d) ĐẠI HỌC
CÔNG NGHỆ
Multiplexer (MUX)

• Why
– A single line is required to carry two or more different signals
An-1 Bn-1 A1 B1 A0 B0
• Only one signal at a time can be placed on the one line.

Ein Eout Ein Eout Ein Eout E(L)

(A=B) • Definition
– MUX: a device allows us to select, at different instants, the signal we wish to place on
Gin Gout Gin Gout Gin Gout G(L) this common line.
(A>B)
– As known as: Data selector

Iterative array of 1-bit comparators forming an N-bit comparator

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ĐẠI HỌC
CÔNG NGHỆ Multiplexer (cont’d) ĐẠI HỌC
CÔNG NGHỆ Multiplexer (cont’d)

I3 Y = I 0 S1S0 + I1S1S0 + I 2 S1S 0 + I 3 S1S 0

S1 S0 I3 I2 I1 I0 Y
• Example
– Assume that there are four lines, I0, I1, 0 0 - - - 0 0
I2, and I3, which are to be multiplexed I2
0 0 - - - 1 1
on a single line Y
0 1 - - 0 - 0
Y
– ➔ we need two additional inputs to I1
0 1 - - 1 - 1
select which of the I inputs is to appear
at the output 1 0 - 0 - - 0
I0 I3
1 0 - 1 - - 1
1 1 0 - - - 0 I2
Y
1 1 1 - - - 1
I1

Y = I 0 S1S0 + I1S1S0 + I 2 S1S 0 + I 3 S1S 0 I0

S1 S0 S1 S0
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ĐẠI HỌC
CÔNG NGHỆ De-multiplexer (DEMUX) ĐẠI HỌC
CÔNG NGHỆ
DEMUX (cont’d)

S1 S0 Y3 Y2 Y1 Y0 Y0 = I S 1 S 0
• Perform the reserve task of the
0 0 0 0 0 I Y1 = IS1S 0
MUX
– One data input line
0 1 0 0 I 0 Y2 = IS1 S 0
– Four data output lines
1 0 0 I 0 0 Y3 = IS1S 0
1 1 I 0 0 0
– Two control lines are needed to
select which output will be
Y0 = I S 1 S 0
connected to the input.
Y1 = IS1S 0
Y2 = IS1 S 0
Y3 = IS1S 0

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ĐẠI HỌC
CÔNG NGHỆ
DEMUX (cont’d) ĐẠI HỌC
CÔNG NGHỆ
DEMUX (cont’d)

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ĐẠI HỌC
CÔNG NGHỆ Analog MUX/DEMUX ĐẠI HỌC
CÔNG NGHỆ
Analog MUX/DEMUX (cont’d)

• Has the same functionalities except: VDD

– Accept analog signals in multiplexing and de-multiplexing
– MUX and DEMUX have the same structure
T1
D0 C
T4
D1 Y T2

A B A B
D2

D3
C A
T3
C
S0 B = A when VC = H
Channel address decoder T3 T4
S1
B
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ĐẠI HỌC
CÔNG NGHỆ
CMOS tri-state buffer ĐẠI HỌC
CÔNG NGHỆ
Analog MUX/DEMUX (cont’d)

• Application
EN = High ➔ Y = X VDD
– MUX, DEMUX (digital and analog signals)
– Modulators, demodulators
T1
– A/D, D/A converters
– Frequency, phase, resistance control units
T1 – …

X Y
• Some MUX/DEMUX circuits
T2
– CD4051 (8-input MUX), CD4052 (2 x 4-input MUX), CD4053 (3 x 2-input MUX)
EN
T2
X Y

EN

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ĐẠI HỌC
CÔNG NGHỆ
Encoding and Decoding ĐẠI HỌC
CÔNG NGHỆ Encoding: Binary-to-complement

• Why need encoding and decoding processes?

• Binary-to-complement binary encoding
– 2’s complement used to represent the negative Binary code
• Encoding
number.
– Binary-to-complement binary encoding
– Subtraction can be done by the addition with a 2’s
– Binary-to-Gray encoding
– Decimal-to-BCD encoding complement number. 1’s complement code

1110
• Decoding
original number 1011
– BCD-to-Decimal decoding inversion
2’s complement code
– BCD-to-7 segment code decoding
1’s complement 0100
– Johnson code-to-Decimal decoding
+1
2’s complement 0101
-1110
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ĐẠI HỌC
CÔNG NGHỆ Encoding: Binary-to-complement ĐẠI HỌC
CÔNG NGHỆ Encoding: Binary-to-complement

• Binary-to-complement binary Decimal Binary 2’s complement

• Binary-to-complement binary encoding
encoding A3 A2 A1 A0 B3 B2 B1 B0 B0 = A0
0 0 0 0 0 0 0 0 0
B1 = A0  A1
1 0 0 0 1 1 1 1 1
B0 = A0 2 0 0 1 0 1 1 1 0
A0 B0 B2 = ( A0 + A1 )  A2
B1 = A0  A1 3 0 0 1 1 1 1 0 1
A1 B1 B3 = ( A0 + A1 + A2 )  A3
4 0 1 0 0 1 1 0 0
B2 = ( A0 + A1 )  A2 5 0 1 0 1 1 0 1 1

B3 = ( A0 + A1 + A2 )  A3 6 0 1 1 0 1 0 1 0 B2
7 0 1 1 1 1 0 0 1 A2
8 1 0 0 0 1 0 0 0
9 1 0 0 1 0 1 1 1 B3
10 1 0 1 0 0 1 1 0 A3
11 1 0 1 1 0 1 0 1
12 1 1 0 0 0 1 0 0 Binary-to-Complement encoder
13 1 1 0 1 0 0 1 1
14 1 1 1 0 0 0 1 0
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ĐẠI HỌC
CÔNG NGHỆ Encoding: Binary-to-Gray ĐẠI HỌC
CÔNG NGHỆ
Encoding: Binary-to-Gray

Decimal Binary Gray code

• Binary-to-Gray encoding
A3 A2 A1 A0 G3 G2 G1 G0 G0 = A0  A1
– Gray code: only one change in 0 0 0 0 0 0 0 0 0
bit between two successive 1 0 0 0 1 0 0 0 1 G1 = A1  A2 A0
G0
numbers 2 0 0 1 0 0 0 1 1 G2 = A2  A3
– Why Gray code? 3 0 0 1 1 0 0 1 0 A1
4 0 1 0 0 0 1 1 0 G3 = A3 G1
G0 = A0  A1 5 0 1 0 1 0 1 1 1
A2
G1 = A1  A2 6 0 1 1 0 0 1 0 1 G2
7 0 1 1 1 0 1 0 0
G2 = A2  A3 8 1 0 0 0 1 1 0 0 A3 G3
G3 = A3 9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
Binary-to-Gray encoder
Hint: Go from left to right, if meet 12 1 1 0 0 1 0 1 0
‘1’ then the following bit will be 13 1 1 0 1 1 0 1 1
inversed. 14 1 1 1 0 1 0 0 1

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1 1 1 1 0 0 0
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ĐẠI HỌC
CÔNG NGHỆ
Encoding: Decimal-to-BCD ĐẠI HỌC
CÔNG NGHỆ
Encoding: Decimal-to-BCD

Truth table
A = L1 + L3 + L5 + L7 + L9
N L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 D C B A
B = L2 + L3 + L6 + L7
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 C = L4 + L5 + L6 + L7 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9

2 0 0 0 0 0 0 0 1 0 0 0 0 1 0 D = L8 + L9
3 0 0 0 0 0 0 1 0 0 0 0 0 1 1 D
4 0 0 0 0 0 1 0 0 0 0 0 1 0 0
5 0 0 0 0 1 0 0 0 0 0 0 1 0 1 Note: 4-input OR gates are normally C
6 0 0 0 1 0 0 0 0 0 0 0 1 1 0 constructed from 2-input NOR and 2-
input NAND gates (use De Morgan B
7 0 0 1 0 0 0 0 0 0 0 0 1 1 1
theorem to get the logic schematic).
8 0 1 0 0 0 0 0 0 0 0 1 0 0 0
9 1 0 0 0 0 0 0 0 0 0 1 0 0 1 A

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ĐẠI HỌC
CÔNG NGHỆ Decoding: BCD-to-Decimal ĐẠI HỌC
CÔNG NGHỆ
Decoding: BCD-to-Binary

Truth table

D
0
C
0
B
0
A
0
L9
0
L8
0
L7
0
L6
0
L5
0
L4
0
L3
0
L2
0
L1
0
L0
1
L0 = A B C D L5 = AB CD
0 0 0 1 0 0 0 0 0 0 0 0 1 0
L1 = AB C D L6 = A BCD
0 0 1 0 0 0 0 0 0 0 0 1 0 0
0 0 1 1 0 0 0 0 0 0 1 0 0 0 L2 = A BC D L7 = ABCD
0 1 0 0 0 0 0 0 0 1 0 0 0 0
0 1 0 1 0 0 0 0 1 0 0 0 0 0 L3 = ABC D L8 = A B C D
L4 = A B CD
0 1 1 0 0 0 0 1 0 0 0 0 0 0
0 1 1 1 0 0 1 0 0 0 0 0 0 0 L9 = AB C D
1 0 0 0 0 1 0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0 0 0 0 0 0 0

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L0 = A B C D L5 = AB CD
L1 = AB C D
ĐẠI HỌC
CÔNG NGHỆ
Decoding:
L = A BCD
6
BCD-to-Decimal ĐẠI HỌC
CÔNG NGHỆ
Decoding: BCD-to-Decimal
L2 = A BC D L7 = ABCD
L3 = ABC D L8 = A B C D • Circuit 74LS42, 74LS45, 74145
L4 = A B CD L9 = AB C D
L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 – 4 inputs: A, B, C, and D
– 10 outputs: L0, L1, L2,… L9
D C B A – Logic schematic as bellow

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ĐẠI HỌC
CÔNG NGHỆ
Decoding: BCD-to-7 segment code ĐẠI HỌC
CÔNG NGHỆ
Decoding: BCD-to-7 segment code

• Structure of 7-segment LED and LCD

a a a
a b c d e f g
f b b b b f b
a g g g
f b e c c e c c
g
e c d d d

d Common K
a a a a a
7-segmen LED
f f b f b f b
g g g g
c e c c e c c

d d d d
a b c d e f g
Common A
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ĐẠI HỌC
CÔNG NGHỆ
Decoding: BCD-to-7 segment code ĐẠI HỌC
CÔNG NGHỆ
Decoding: BCD-to-7 segment code

Truth table • Write the switching function for the decoder

D C B A a b c d e f g
• Build the logic schematic for the decoder
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 0 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 0 0 1 1

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ĐẠI HỌC
CÔNG NGHỆ
Decoding: BCD-to-7 segment code ĐẠI HỌC
CÔNG NGHỆ Decoding: Johnson-to-BCD

• Decoding circuits 7447, 74247 +5V Truth table

– (Common Anode)
N J4 J3 J2 J1 J0 D C B A
0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 1
A a 2 1 1 0 0 0 0 0 1 0
B b 3 1 1 1 0 0 0 0 1 1
C c 4 1 1 1 1 0 0 1 0 0
D d
5 1 1 1 1 1 0 1 0 1
EI e
LI f 6 0 1 1 1 1 0 1 1 0
RBI g 7 0 0 1 1 1 0 1 1 1
8 0 0 0 1 1 1 0 0 0
9 0 0 0 0 1 1 0 0 1
10 0 0 0 0 0 0 0 0 0

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ĐẠI HỌC
CÔNG NGHỆ
Decoding: Johnson-to-BCD ĐẠI HỌC
CÔNG NGHỆ Priority encoder

• Write the switching function for the decoder

• Computer systems
• Build the logic schematic for the decoder – Many I/O devices are connected to
the central processor for
communicating/exchanging data.
• For example: keyboard, disks…

– ➔ need different priority levels

Y1 = P3 + P2
Y0 = P3 + P2 P1
R = P3 + P2 + P1 + P0

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