THE PROCESSOR

▪ Compiler and instruction set architecture determine the instruction count required for a given program
▪ Determined by ISA and compiler
▪ Processor implementation determines both the clock cycle time and the number of clock cycles per instruction
▪ Determined by CPU hardware
▪ We will examine two MIPS implementations
▪ A simplified version
▪ A more realistic pipelined version
▪ Subset of core MIPS instruction set
▪ Integer arithmetic-logical instructions
▪ (ADD, SUB, AND,OR, and SLT (Set Less Than))
▪ Memory-reference instructions
▪ (load word (lw) and store word (sw))
▪ Branch instructions BEQ, and J (jump)
▪ The first two steps are identical:
▪ 1. Fetch the instruction
▪ 2. Read one or two registers
▪ For the load word instruction, we need to read only one register
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 An Overview of the Implementation
• MIPS instructions, include
– Integer
– Arithmetic-logical instructions,
– The memory-reference instructions,
– Branch instructions
• The first two steps are identical:
– Theprogram counter (PC) to the memory that contains the code and
fetch the instruction from that memory
– Read one or two registers, using fields of the instruction to select the registers to read
– Load word instruction, need to read only one register, but
most other instructions require that read two registers
• After these two steps, the actions required to complete the instruction depend on the instruction class
– The three instruction classes (memory-reference, arithmetic-logical, and branches)
– The actions are largely the same independent of exact instruction

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 An Overview of the Implementation
▪ By making the execution of many of the instruction classes similar
▪ Except jump, all instruction classes, use ALU after reading the registers
▪ The memory-reference instructions for an address calculation
▪ The arithmetic-logical instructions for the operation execution
▪ Branches for comparison
▪ After using the ALU, the actions required to complete various instruction classes differ
▪ A memory-reference instruction will need to access the memory either to read data for a load or write
data for a store
▪ An arithmetic-logical or load instruction must write the data from the ALU or memory back into a register

▪ A branch instruction, may need to change the next instruction address based on the comparison

▪ Otherwise, the PC should be incremented by 4 to get the address of the next instruction

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High-level view of a MIPS implementation
▪ Showing the major functional units and their inter connections
▪ Shows most of the flow of data through the processor
▪ Omits two important aspects of instruction execution
▪ Multiplexer & control unit
▪ All instructions start by using the program counter
▪ PC supply the instruction address to the instruction memory
▪ The register operands specified by the fields of that instruction are fetched
▪ Register operands operated on to compute
▪ a memory address (for a load or store),
▪ an arithmetic result (for an integer arithmetic-logical instruction),
▪ or a compare (for a branch)
• The result from the ALU must be written to a register (AL instruction)
• For load or store, the ALU result is used as an address to either store a value from the registers or load a value from memory into
the registers
• The result from the ALU or memory is written back into the register file
• Branches require the use of the ALU output to determine the next instruction address
• The thick lines interconnecting the functional units represent buses (consisting of multiple signals)
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Multiplexers

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MIPS Subset Implementation
including Multiplexors and Control Unit
▪A control unit has the instruction as an input Determine control
lines for the functional units and multiplexors
▪ The top multiplexor (“Mux”) controls what value replaces the
PC (PC + 4 or the branch destination address) Controlled by
AND gate with input as Zero output of the ALU and a control
signal indicating the instruction is a branch
▪ The middle multiplexor, to the register file, steer the output of
the ALU (in the case of an AL instruction) or the output of the
data memory (in case of a load) for writing into the register file
▪ Bottommost multiplexor determine whether the second ALU
input is from the registers (for an AL instruction OR a branch) or
from the offset field of the instruction (for a load or store)
▪The added control lines are straightforward and determine
▪ The operation performed at the ALU,
▪ Whether the data memory should read or write,
▪whether the registers should perform a write operation

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