SIF2020: ELECTRONICS 2

1
Continuation of Lecture 3….
DC Analysis of FET amplifiers- Graphical approach
Important note:

𝐼𝐺 ≅ 0 𝐴
𝐼𝐷 = 𝐼𝑆

For JFET & depletion-MOSFET, Shockley equation

applies:

𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝑉𝑝

For enhancement-MOSFET and MESFET:

𝐼𝐷 = 𝑘(𝑉𝐺𝑆 − 𝑉𝑇 )2
2
 Fixed-bias configuration

𝐼𝐺 = 0 𝐴
𝑉𝑅𝐺 = 𝐼𝐺 𝑅𝐺 = 0𝑉
Applying Kirchhoff Law:
𝑉𝐺𝑆 = −𝑉𝐺𝐺

Since VGG is a fixed dc supply, VGS is fixed in magnitude;

Network for dc analysis
ID is controlled by Shockley’s Eq:
𝑉𝐺𝑆 2
Recall: 𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝑉𝑝
The coupling capacitor C1 & C2 are
Open circuit – DC analysis
Short circuit – AC analysis
RG is present to ensure Vi appears at the input to the FET amplifier for ac analysis
3
Fixed-bias configuration- graphical analysis

• Recall that choosing VGS = VP/ 2 will result in

a drain current of IDSS/4.
• The fixed level of V GS superimposed as a
vertical line at VGS = -VGG.
• The point where the two curves intersect is
the quiescent or operating point, Q -point.

Plotting Shockley’s equation Finding the solution for the fixed-bias

configuration

4
Example: 1

5
6
JFET Self-bias configuration

• Capacitors replaced by “open circuits”

• Resistor RG replaced by a short-circuit equivalent; IG = 0 A.

DC analysis

• Self-bias configuration eliminates the need for two dc supplies

• The controlling gate to-source voltage is determined by the voltage across a resistor RS

7
The current through RS is the source current IS, BUT IS= ID

𝑉𝑅𝑠 = 𝐼𝐷 𝑅𝑆
Step A
From the closed loop:

(1)

NOTE: V GS is a function of output current I D and not fixed in magnitude

Steps to solve via graphical approach:
A. Establish the device transfer characteristic using Shockley’s equation
B. Since, Eq. 1 is linear equation, identify 2 points on the graph and draw the straight
line between the two points
1st point
ID =0 A; VGS =-IDRS = 0V
2nd point:

8
By applying Kirchhoff Law & using Eq. (1):

9
Example 2: Determine the following for the network below:

10
 For Shockley’s equation, choosing VGS = VP/2 = -3 V,
ID = IDSS/4 = 8 mA / 4 = 2 mA

Choosing ID = 8 mA; VGS = - 8 V

11
Next superimpose the network and device characteristic of the JFET

The resulting operating point results in a quiescent

value of gate-to-source voltage of VGSQ = 2.6 V

12
Voltage-divider biasing

• All capacitors – open circuit equivalent

• VDD separated into 2 equivalent circuit

Network redrawn for

DC analysis

✓ Since, IG = 0A, Kirchhoff’s current law requires, IR1 = IR2

✓ Fig. (a) is used to find VG using voltage-divider rule:

𝑅2 𝑉𝐷𝐷 ✓ Applying Kirchhoff’s voltage law in clockwise

𝑉𝐺 =
𝑅1 + 𝑅2
13
 (2)

Is the straight line equation! 2. When VGS = 0 V, ID is as follows:

We need 2 points to plot this:
1. When ID = 0 mA, VGS is as follows

14
❖ Intersection on the vertical axis is determined by RS
❖ If RS is higher ID reduces and vice versa; thus the Q-point varies accordingly
❖ For example (refer to Fig below):
❖ Once the Q-point is determined; the remaining network
analysis is performed as usual:

15
Example: 3 Determine the following for the network below:

16
1. First step: Plot the transfer characteristic:
𝐼𝐷𝑆𝑆 8𝑚𝐴 𝑉𝑃 4𝑉
𝐼𝐷 = = = 2 𝑚𝐴; then 𝑉𝐺𝑆 = =− = −2𝑉
4 4 2 2
2. The network equation is

17
Continuation….

18
Common-gate configuration

19
1.Applying Kirchhoff’s voltage law 2. Applying Kirchhoff’s voltage law around the loop

20
Example: 4

21
Since VSS = 0 V

Choosing ID = 6 mA and solving VGS

22
23
24