Sequential Logic Circuits

Sequential Logic Circuits
Dr. Radhakrishnan A N
Assistant Professor of Physics
TM J M Govt. College, Manimalakunnu
BSc. Physics Semester 5 : Digital Electronics and Programming (Module 2)

Logical Circuits
1. Combinational Logic Circuits: Basic building blocks are logic gates
Examples: Adder, subtractor, encoder, decoder, multiplexer and demultiplexer
2. Sequential Logic Circuits: Basic building blocks are flip-flops
Examples: flip-flops, registers, counters
• Sequential Logic Circuits involve timing and memory devices
• Two types of Sequential Logic Circuits
a) Synchronous (use pulsed or level inputs and a clock input to drive the circuit)
b) Asynchronous (do not use a clock signal)

Latches
• Latches are digital circuits that store a single bit of information and hold its value until it is
updated by new input signals.
• They are used in digital systems as temporary storage elements to store binary information.
• Latches are sequential circuit with two stable states (bistable circuits).
• Latches can reside in either of the two states (LOW and HIGH) by using a feedback
arrangement
• Latches are level sensitive circuits
• A latch’s output depends on its current and previous inputs
• Latches can be implemented using various digital logic gates, such as AND, OR, NOT, NAND,
and NOR gates.

RS Latches (RESET – SET Latches)
• RS latches are the simplest
form of latches and are
implemented using two
inputs: S (Set) and R (Reset).
• RS latches are formed by
using two cross coupled
NAND gates or NOR gates
ഥ are two
• Here Q and 𝑸
outputs

Flip-flops
• A flip flop in digital electronics is a circuit with two stable states that can be used to store
binary data.
• The stored data can be changed by applying varying inputs.
• Flip-flops and latches are fundamental building blocks of digital electronics systems used in
computers, communications, and many other types of systems.
• Both are used as data storage elements.
• The primary difference between a latch and a flip-flop is a gating or clocking mechanism.
• Flip Flops are edge-triggered and a latch is level-triggered.

SR Flip-flop (SET – RESET Flip-flops)
• The four modes of operation of SR flip-flop is similar to that of latches

SR Flip-flop (SET – RESET Flip-flops)

Clocked SR Flip-flop
• Flip-flops are synchronous bistable devices means the output changes its state only
at a specified point on a triggering input called ‘clock (CLK)’

Clocked SR Flip-flop
• When clock is HIGH, the latch performs

the normal mode of operation
• Inputs S and R can never be HIGH when
CLK goes HIGH
• CLK pulse has no effect on output
when S and R are at LOW level
• If the flip-flop is made in wait condition
until the CLK at LOW before output can
change is called ‘NEGATIVE CLOCKING’.

D (Delay) Flip-flop
• D flip-flop is basically an SR flip-flop with an inverter in the R input
• For the operation of SR flip-flop two input signal are required.
a) For storing 1, S= HIGH and R = Low
b) For storing 0, S = LOW and R = HIGH
• To overcome this difficulty, a D flip-flop is used which has only one input
• The binary input at D is delayed by one clock pulse from getting to output Q
• When the clock signal is LOW, the flip flop holds its current state and ignores the D input.
• When the clock signal is high, the flip flop samples and stores D input.

D (Delay) Flip-flop

J K Flip-flop
• J K flip-flop is considered as universal flip-flop since it has the features of all other flip-
flops
• The prohibited state, when R=S=1, of SR flip-flop is refined in JK flip-flop
• When CLK input is HIGH
a) J= K = 0, flip-flop remain in hold state
b) J =0, K =1, Q set to 0
c) J=1, K=0, Q set to 1
d) J=K=1, flip-flop changes its output as the compliment of previous state. This is
called TOGGLING operation. The repeated clock pulses cause the output to turn-off-
on-off-on… and son on. This is called RACING CONDITION.

J K Flip-flop

MASTER -SLAVE J K Flip-flop
• MASTER-SLAVE JK (MSJK) flip-flop is used to overcome RACING CONDITION in JK flip
• MSJK flip-flop contains two clocked flip-flops – MASTER and SLAVE
• When CLK is HIGH master is active and slave is inactive so that output remains in the
previous state.
• When CLK is LOW master is inactive and slave is active.
• Final output of MSJK flip-flop is the output of the slave flip-flop
• Final output of MSJK flip-flop is available at the end of the clock pulse

MSJ K Flip-flop

MSJ K Flip-flop
• Basic operation of MSJK flip-flop is same that of JK flip-flop except the RACING CONDITION
• The information present at the J and K inputs is transmitted to the master flip-flop on the
positive edge of the clock pulse and is held there until the next negative edge of the clock
pulse after which it is allowed to pass through the slave flip-flop.

MSJ K Flip-flop

T (TOGGLE) Flip-flop
• T (TOGGLE) Flip-flop is the single input version of JK flip-flop
• T flip-flop is obtained by connecting together both inputs of the JK flip-flop
• T flip-flop has the ability of toggle or change the output state
• When T=1 , the state of the flip flop is complimented and when T = 0, the state remains
the same

T (TOGGLE) Flip-flop

D and T flip flops using JK flip-flop
• JK flip-flop is a universal flip-flop and hence it is very easy to convert it into D and T flip-flops

Summary of Flip-flops

Summary of Flip-flops

Registers
• An array of flip-flops used to store binary information is known as registers
• To store an n-bit data n-bit register which contains n flip-flops are needed
• The number of flip-flops need equal to number bits in the binary word
• Two fundamental characteristics of registers:
1. Registers are used for the temporary storage of binary information in digital systems
2. Data shifting capability of registers permits the movement of data from stage to stage
or into or out of the registers upon application of clock pulses

Storing Data in a D flip-flop
• A D flip-flop can store one bit of data
• 1 is applied to the D input and a clock
pulse is applied, the output of the D flip-
flop is set to 1
• When the input 1 is removed, the flip-flop
remains in the SET state
• The same procedure is applied to store 0

Buffer Register
• The simplest type of register is a buffer register that stores a binary word
• It is composed of several D flip-flops, number of which depends on number of bits present
in binary word.

Buffer Register
• Figure shows a 4-bit buffer register which contains 4 D flip-flops to store a 4-bit binary
word
• When clock pulse arrives, all the X bits are loaded into D inputs of all the flip-flops
• Then the stored binary data becomes as 𝑸 = 𝑸𝟑 𝑸𝟐 𝑸𝟏 𝑸𝟎 = 𝑿𝟑 𝑿𝟐 𝑿𝟏 𝑿𝟎
• For example to store 4 bit binary 1101 in buffer register,
Input: 𝑿𝟑 = 𝟏; 𝑿𝟐 = 𝟏; 𝑿𝟏 = 𝟎; 𝑿𝟎 = 𝟏;
Output: Q =1101
• The operation is very simple and easy to use, but there is no control over X-bits

Controlled Buffer Register
• Controlled buffer register consists of a group of flip-flops and gates
• Flip-flops store binary information and gates control when and how new information is
transferred into the register
• Whenever the ‘CLEAR’ signal is HIGH, all the flip-flops are in RESET condition and circuit is
ready for operation
• If LOAD signal is LOW, X-bits cannot reach the flip-flops
• When LOAD signal is HIGH, X-bits are transmitted to the data inputs and the flip-flops are
ready for loading
• When the clock pulse is active, the X-bits are loaded into the flip-flops as 𝑿𝟑 𝑿𝟐 𝑿𝟏 𝑿𝟎

Controlled Buffer Register

Data Movement in Registers
• Data can be entered into registers in two ways:
1. Serial method – one bit at a time
2. Parallel method – all bits at the same time
• Based on data storage and data reading methods, registers can be classified into four modes
of operation
1) Serial in – Serial out : Registers accept data serially – one bit at a time on a single line
It produces the stored information on its output in serial form

2) Serial in – Parallel out: Data bits are entered serially, but all stored bits are available
simultaneously at the output line
2) Parallel in – Serial out: All data bits can be entered at the same time using parallel input
lines. The output is available in serial form

4) Parallel in – Parallel out: Register employs both input and output in parallel method.
Data can be entered simultaneously and all bits appear on parallel output lines

Serial In – Serial Out (SISO) Register
• A 4-bit SISO shift register implemented using D flip-flops is shown in the figure
• This shift register moves the stored bits towards left side and is also known as shift-left
register

Serial In – Serial Out (SISO) Register
• The Q output of each flip-flop is connected to the D input of the flip-flop at its left side
• Each clock pulse shifts the content of the register one bit position to the left
• Steps to store a binary word: 1101
1. Register should be CLEAR initially and output is 0000
2. First clock pulse: 𝑸𝑨 is set to 1 and data stored is now 0001
3. Second clock pulse: 𝑸𝑨 is set to 1, 𝑸𝑨 is shifted left to 𝑸𝑩 and data stored is now 0011
4. Third clock pulse: 𝑸𝑨 is set to 0, 𝑸𝑩 is shifted left to 𝑸𝑪 , 𝑸𝑨 is shifted left to 𝑸𝑩 and now the
stored data is 0110
5. Fourth clock pulse: 𝑸𝑨 is set to 1, 𝑸𝒄 is shifted left to 𝑸𝑫 , 𝑸𝑩 is shifted left to 𝑸𝑪 , 𝑸𝑨 is shifted
left to 𝑸𝑩 and now the stored data is 1101

Serial In – Parallel Out (SISO) Register
• A 4-bit SIPO shift register implemented using D flip-flops is shown in the figure
• This shift register moves the stored bits towards right side and is also known as shift-right
register

Serial In – Parallel Out (SIPO) Register
• The Q output of each flip-flop is connected to the D input of the flip-flop at its right side
• Each clock pulse shifts the content of the register one bit position to the right
• Steps to store a binary word: 1101
1. Register should be CLEAR initially and output is 0000
2. First clock pulse: 𝑸𝑨 is set to 1 and data stored is now 1000
3. Second clock pulse: 𝑸𝑨 is set to 0, 𝑸𝑨 is shifted left to 𝑸𝑩 and data stored is now 0100
4. Third clock pulse: 𝑸𝑨 is set to 1, 𝑸𝑩 is shifted left to 𝑸𝑪 , 𝑸𝑨 is shifted left to 𝑸𝑩 and now the
stored data is 1010
5. Fourth clock pulse: 𝑸𝑨 is set to 1, 𝑸𝒄 is shifted left to 𝑸𝑫 , 𝑸𝑩 is shifted left to 𝑸𝑪 , 𝑸𝑨 is shifted
left to 𝑸𝑩 and now the stored data is 1101

Counters
• Counter is a sequential circuit which is used for a counting pulses is known counter.
• Counter is a group of flip-flop with clocked signal applied to perform counting operation
• The modulus of a counter is the number of states in its count sequence.
• The maximum possible modulus is determined by the number of flip-flops.
• If a counter consists of n flip-flops, its modulus is 2n
• According to the way they are clocked, counters are classified into two categories:
1. Synchronous Counters
2. Asynchronous Counters

Asynchronous Counters
• In Asynchronous counters, the first flip-flop is clocked by an external pulse and then each
ഥ output of the previous flip-flop.

successive flip-flop is clocked by the 𝑸 𝒐𝒓 𝑸
• In an Asynchronous counter, the flip-flops are not clocked simultaneously
• Asynchronous counters are serial counters and are also called ripple counters
Synchronous Counters
• In an Synchronous counter, the flip-flops are clocked simultaneously
• Synchronous counters are faster than asynchronous counters due to simultaneous clocking
• Synchronous counters are parallel counters

Mod-8 Ripple Counter
• Mod-8 ripple counter is 3-bit asynchronous counter, consists of eight states due to three
number of flip-flops
• Figure shows a mod-8 counter with three JK flip-flops

• CLK input is connected to the first flip-flop only
• The second flip-flop is triggered by 𝑸𝑨 output of the first flip-flop
• The third flip-flop is triggered by 𝑸𝑩 output of the second flip-flop
• The three flip-flops are never simultaneously triggered resulting in asynchronous operation
• The three flip-flops are connected for TOGGLE operation(J=K=1)
• Initially all the flip-flops are RESET, output of the counter is 𝑸𝑪 𝑸𝑩 𝑸𝑨 = 𝟎𝟎𝟎
• When first CLK is HIGH:𝑸𝑨 becomes HIGH and since 𝑸𝑨 is LOW, it has no effect on second and
third flip-flops. Output is now 𝑸𝑪 𝑸𝑩 𝑸𝑨 = 𝟎𝟎1

• When second CLK is HIGH:𝑸𝑨 toggles to LOW and since 𝑸𝑨 is HIGH, the second flip-flop toggles -
𝑸𝑩 becomes HIGH. Since 𝑸𝑩 is LOW, it has no effect on the third flip-flop. Output is now 𝑸𝑪 𝑸𝑩 𝑸𝑨 =
𝟎𝟏0
• When third CLK is HIGH:𝑸𝑨 toggles to HIGH and since 𝑸𝑨 is LOW, the second flip-flop is inactive. Since
𝑸𝑩 is also LOW, it has no effect on the third flip-flop. Output is now 𝑸𝑪 𝑸𝑩 𝑸𝑨 = 𝟎𝟏1
• When fourth CLK is HIGH:𝑸𝑨 toggles to LOW and since 𝑸𝑨 is HIGH, the second flip-flop toggles -
𝑸𝑩 becomes LOW. Since 𝑸𝑩 is HIGH, the third flip-flop is active and 𝑸𝑨 becomes HIGH. Output is now
𝑸𝑪 𝑸𝑩 𝑸𝑨 = 𝟏𝟎0

• When fifth CLK is HIGH:𝑸𝑨 toggles to HIGH and since 𝑸𝑨 is LOW, it has no effect on second and third
flip-flop. Output is now 𝑸𝑪 𝑸𝑩 𝑸𝑨 = 𝟏𝟎1
• When sixth CLK is HIGH:𝑸𝑨 toggles to LOW and since 𝑸𝑨 is HIGH, the second flip-flop toggles-
𝑸𝑩 𝐛𝐞𝐜𝐨𝐦𝐞𝐬 𝐇𝐈𝐆𝐇. Since 𝑸𝑩 is also LOW, it has no effect on the third flip-flop. Output is now 𝑸𝑪
𝑸𝑩 𝑸𝑨 = 𝟏𝟏0
• When seventh CLK is HIGH:𝑸𝑨 toggles to HIGH and since 𝑸𝑨 is LOW, it has no effect on second and
third flip-flop. Output is now 𝑸𝑪 𝑸𝑩 𝑸𝑨 = 𝟏𝟏1
• When eighth CLK is HIGH:𝑸𝑨 toggles to LOW and since 𝑸𝑨 is HIGH, the second flip-flop toggles-
𝑸𝑩 𝐛𝐞𝐜𝐨𝐦𝐞𝐬 𝐋𝐎𝐖. Since 𝑸𝑩 is also HIGH, the third flip-flop toggles -𝑸𝑪 becomes LOW. Output is now
𝑸𝑪 𝑸𝑩 𝑸𝑨 = 𝟎𝟎𝟎
• When eighth CLK is HIGH:𝑸𝑨 toggles to LOW and since 𝑸𝑨 is HIGH, the second flip-flop toggles-
𝑸𝑩 𝐛𝐞𝐜𝐨𝐦𝐞𝐬 𝐋𝐎𝐖. Since 𝑸𝑩 is also HIGH, the third flip-flop toggles -𝑸𝑪 becomes LOW. Output is now
𝑸𝑪 𝑸𝑩 𝑸𝑨 = 𝟎𝟎𝟎

• Timing diagram of one cycle of Mod-8 ripple counter is shown below

Digital to Analog Converter (DAC)
• The process of converting a digital signal into an analog signal is called digital to analog conversion
(D/A conversion) and the system used for D/A conversion is called Digital to Analog Converter (DAC).

Principle of D/A Conversion
• The input digital data is applied to a number of voltage switches
• The switches are connected to a reference voltage source (VRef)
• At the time digital data is applied to voltage switches, the switches provide one of the
possible outputs : 0 V (LOW) or VRef (HIGH).
• The switches feed a resistive summing network that converts each bit into its weighted
current value sums them for a total current.
• It is then fed to an amplifier which gives the proper analog voltage value for the equivalent
digital data

R-2R Ladder Type Digital to Analog Converter (DAC)
• A 4-bit DAC that uses R-2R ladder type resistive network is shown in figure. The ladder type network
has two values of resistors, one two times the resistance of other and hence the name R-2R Ladder
type.


OPERATION :
• Let us assume that the digital input is 0001 : 𝑺𝟎 = 𝟏; 𝑺𝟏 = 𝟎; 𝑺𝟐 = 𝟎; 𝑺𝟑 = 𝟎;
• By the application of Thevenin’s theorem, the resistive summing network can be simplified
as in Fig. (a).
• At AA’, the equivalent resistance is R since 2R is parallel to 2R and Thevenin’s equivalent
𝑽𝑹
voltage is .
𝟐
• Similarly, at BB’ , CC’, and DD’, we have circuits as shown in Fig (c), (d) and (e) respectively
𝑽𝑹
• The equivalent voltage corresponding to LSB = 1 is
𝟐𝟒
• Similarly for the digital inputs 0010, 0100 and 1000, the equivalent voltages are
𝑽𝑹 𝑽𝑹 𝑽𝑹
, and
𝟐𝟑 𝟐𝟐 𝟐𝟏

• The equivalent resistance in each case is 3R and equivalent circuit is shown in figure.

𝑹𝒇 𝑽𝑹 𝑹𝒇 𝑽𝑹 𝑹𝒇 𝑽𝑹 𝑹𝒇 𝑽𝑹
𝑽𝒐 = − 𝟒
𝑺𝟎 + 𝟑
𝑺𝟏 + 𝟐
𝑺𝟐 + 𝟏
𝑺𝟑
𝟑𝑹 𝟐 𝟑𝑹 𝟐 𝟑𝑹 𝟐 𝟑𝑹 𝟐
𝑹𝒇 𝑽𝑹 𝟑
𝑽𝒐 = − 𝟒
𝟐 𝑺𝟑 + 𝟐𝟐 𝑺𝟐 + 𝟐𝟏 𝑺𝟏 + 𝟐𝟎 𝑺𝟎
𝟑𝑹 𝟐
Using the above expression, the analog output voltage is determined for various switch
positions of the digital input

Analog to Digital Converter (ADC)
• The process of converting a analog signal into a digital signal is called analog to digital conversion
(A/D conversion) and the system used for A/D conversion is called Analog to Digital Converter (ADC)
Counter Type Analog to Digital Converter (ADC)
• A counter type A/D converter consists of a voltage comparator. An AND gate, a BCD counter
and a D/A converter
• The analog voltage is applied at the analog input of the circuit shown in figure.
• The voltage comparator compares the voltage coming from the D/A converter and analog
input voltage


OPERATION
• First the counter begins with RESET and output of the D/A converter is zero.
• If the analog input voltage applied at A is greater than the voltage at B of the comparator, then
output of the comparator switches to a HIGH state enabling AND gate.
• Clock pulse is allowed to increase or advance the count of the BCD counter through its states
• The counter continues to advance from one binary state to the next higher state and count will be
displayed at the output as 𝑫𝟑 𝑫𝟐 𝑫𝟏 𝑫𝟎 .
• D/A converter converts binary output of BCD counter to analog voltage and this voltage is applied at
input B of the comparator.

OPERATION
• The count on the counter increases until the feedback voltage from D/A converter the analog input
voltage
• Whenever the voltage at B is greater than A, the comparator output will go LOW and disables the
AND gate.
• As a result, the Clock pulses to the counter is cut off and counter stops.
• The output of the counter at this state is the binary equivalent of analog input
• Later the counter resets and is ready to begin the counting to sample input analog voltage

Sequential Logic Circuits - Module 3 - Sem 5

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BSc. Physics Semester 5 : Digital Electronics and Programming (Module 2)

1. Combinational Logic Circuits: Basic building blocks are logic gates

Examples: Adder, subtractor, encoder, decoder, multiplexer and demultiplexer

2. Sequential Logic Circuits: Basic building blocks are flip-flops

Examples: flip-flops, registers, counters