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Microcomp Theory Tec-1
Microcomp Theory Tec-1
eoNnAirJ5 THE
PROGRAM .
ADDRESS 6U5
1<\(6ortfkD
INNIS HEX 09-1F). PNAM is
emPoRAK`f
01234 MEmORY. 1'f
5 67 Is 9 LOSES j-r
A c_o E 2 80 EPKoM KAM coigTENJTs
F+ W fiENI PowER/
Is REMOVED .
CLOCK Drat-e
ti
A CiU I —FIE OUTPUT i.MTcH
HOLDS ORMITTiOW
SOT-HAT WE CAN/ SEE
11-m CLOCK' T OW -n+E OI SPLAYS
cRERIES
-THE 'SpEED' IN PUT OUT-POT
of THE LATCH LATCH
compuTER,
ELECTRONICS NOTEBOOK 3 35
WHAT A COMPUTER/ WILL DO.
INPUT Mick()
OUTPUT
CIRculT SYSTEM DEVICE
DES1Grs1 THE
INPUT CIKCUIT
MUST 0 CONNECT THE
pRoOUCE 5v OUTPUT OEViCE
ON TN IS. LINE. o SPEAKER,, RELAY;
ec
TO Activii-re PRODUCE THE Cw LoSE )
-rHE ‘micasoi PROGRAM
IOU WILL GAN 11 LOT $y rtEAO(NCt THE AR-ficLE on/ THE 1-141.1411,4-
ELEc-TkONLcS Ur-Wu-TER, `TES- - I A /iv TE MAGAZINE 1$suEs
10 micaocomP PROJECT IN ISSUES /3 —.. I.
VE.t•J MORE WILL I&1INEJD Z-v eviLOINCr ONE OR, 1301-11 MODELS
ISS `Al.0 pug, 015cu%stolv WILL f'E. CENTRED 'ARour-3() THEM.
36 ELECTRONICS NOTEBOOK 3
MuLT!V!SRFITOR, CAcurr bUCTEPv TR.RN ISTOR,
PRoDuctNG. A NEAR- PERFECT SpvAR,ES-UP MuLT‘VeR.ATOR,
SQUARE -WAVE wAvEfORM --to PRODUCE A PER,VECT
FREQUENCY WAVEFORM.
ANVS-TMENT
'MHz. -351CHz.
PRE - pROGR,AMMED
CHIP
GOTING-
-TRIINJ51S-TOR,
Fop,
LATCH SEE
NEXT pRGES
+5.
TN CP
,
MAIO OUTPUT
All
Ctiip 11 LATCH
24 An
16
11 32
Ax
25 33
34
7--SECTMEniT
L11
35
36
An
Ar
DISPLAYS
38
A. A DECIMAL
39
lmfd Z 00 4°
PoINT
BC 557
x BC 547
GA-Tin/G. I-RAN/VS-(0R/
VOR, INPUT PoR,-T PULL -DOWN( DRIVER, TRANSIS-ToR,S
SEE fqvcc PAGE INPUT CLESIs-roR,5 CONNECTS cA -rlioDE
SWITCHES ON 0A-TA BUS OF DISPLAY TO —vE
DIODES PRE VENT ONE own (SEE NEXT PAGE)
LINE INTERXER,INC-c WI -rpt
(ANOTHER. WHEN DIP
swrrotEs PR,E 04.
ELECTRONICS NOTEBOOK 3 37
SHE iNpUT CATIN1C4 —RANSIS-foR,
TE IN - ou-c REQ .)EST LINE IORQ --1HE Z-$ 3o is r soc-rwARE
oRysiew 00-cPuT Pin). MEANS IT is Ac.-CivATEC) (GOES LoW
As A R.EsuLT OF S-VAIEmENT IN A PRoc:Rnm) SUCH As IN A(O')
WI (00A OR, (02.) (0 it.) (0%') ETC] .
38 ELECTRONICS NOTEBOOK 3
THE OO-cPUT GATINCT IWOSis-nA,
THE 01541ECT OV THE cifkcorr is -11) GATE (comZuvE) AI & IOPoR To
CIC..-rwATE THE oUTPuT LATCH.
iF
tOk,
Dqnc) 15 LATCHED
CLACK. PULSE: ori RISING EDGE.
cp Tif IS LiNE 15
ACTWE LOW.
OuT PUT 6ECAUSE of THIS, You
L.43TcH WILL HAVE 1-0 READ
I-1oW THE CiRcurr
oPERATES.
CP IS RtsING EOCTE
ict
To TUr A- 19c.cvtAvo910R, •
02, =n0ORESS LINE NI
10 A,
THIS iS-71-1E SEQUENCE To LA-cc) 091- 9 INTO THE Ot1WUT
T-HE 2-g0 RECEIVES AN ou-tpuT STATEMENT OUT ce z 24A
N THIS CAUSES "THE 0191.19 W AccuMULATaR/
GUS RC isiDDikESs LINE A i qog...,HIG,H.
P AFL ON 1 i OfriR
ELECTRONICS NOTEBOOK 3 39
—THE Z -SO CPO HoW IT WORKS
LE Ds TuRN ON/OFF .
- SIMILAR, TO
AV
A GINGR,y coutki-rgik,
l c I.ocK,
C.LOCK,
40 ELECTRONICS NOTEBOOK 3
WHAT s /NSIOE
ALL iHE \AJoRK.5 ARE.
Z-SQ? CONCENTRATED IN A
CHIP IN THE
CENTRE OF THE IC ,
-rHe SIZE of THE
IC IS OicTriTED e.Y
-77-1E NuM6ER, OF PINS
& NOT The comPLEiciTy
pF THE ELECTRONICS .
SINCE yot.) CAN'T SEE
-51E, top.ipotvENTs in/ il+E Z-20
You v1 /4 /11..i. Hnve AccEpT
\A/RI-I
-TEN ExpLiWATioniS
CSASILALLY THE Z -%o Conisis-rS sc) IA COMPUTER_ INSIOE A UHF) I-r HAS
IS OWN PROGRAMMED MEM017s.y ZuS L.INirS & SET OF commANDS
ODOODOCIO
EACH CELL ACCEPTS R ZINHAY VALUE WHICH CAN ONLY 6 0 wt.
e's• 111-6- ED El ET
wHEN1 A cu./.. con/Tows A I I IT is SET. WH.t‘l IT CONTAINS A %
IT IS RESET
THC VALVE OF A CELL. IS CALLED A 8 T AND THESE ARE NumeER.E0
s oLLovs15:
DEIDEILICIDD
61T 0
7
•
ELECTRONICS NOTEBOOK 3 41
-174E Z-80 HA5 16 ADDRESS LINES g< $ OgTA LINES
AP.E cALLE0 THE AOC•RESS eus & ofwe 6u5.
--INFORMATION ENT ERS z-so VIA THE ocr A ev$ gcEmERGeS
VrATHis riAS —1-r is 19 -TWO- WAY. eus.
THE ADDRESS SOS IS A ONE-WAY 6v5. THE 7-7,0 %ENos OUT
f;00RESSES \/119 -T'H IS VAS To MEMORY
- MEMORY eAN I3E EITHER, RAM ock ROM.
RAM ts -rEmPocOr SToRgicTE MEMORY
9,01-I IS PERMANENT Si-oRAGE MEMORY.
— ALL INFoRmiciTION IS FORM OV HIGHS 8‹. LOWS.
42 ELECTRONICS NOTEBOOK 3
THE CPO REGISTER, SET : FOR THE Z —
MOST of THE OPERATIONS ARE CARRIEO °kir (n/ -7-HE A CcomootrroFki 7TRis
IS escAosE, THE AccuMuLA-roR, HAS A Lo-r of VEAToRES WHICH THE
0111E.g. REcatSIERS 00 NOT HAVE..
THE. HIGH GYTE & C.. 1$ THE LOW BYTE . ALSO D IS 'DIE
NIGH BYTE 8. E is THE Lovi ZYTE
ELECTRONICS NOTEBOOK 3 43
-7—HE PCCOMOLATOR,
1,10s1 OV THE OPERATIONS INA Mic.g.OPROcESSoR, ARE CFIRRIE0 otiT I IV THE.
Accu v AT 0 "TR 15 COOS )51" S OF A SET of 8 FLIP-FLOPS WITH A Lai oc
suypok -c c.Acormy, so-Ti-iFry THE L_Lo\A/ING. CAN SE PERSOR,MED:
OTHER, REGISTERS CAN 00 SOME oc THE FOLLOWING , W0-I ALL
li-HfFoKi\4$ THE 6Asts0 ALL PkOGKAMS & WE WILL %HovJ How EACH
sErJ-TEmc, IS coNvER-rE0 TO H MACHINE CODE INSTRUCTI0T/
iHE PfkocEsSoRi Ofq0ER/STANDS
44 ELECTRONICS NOTEBOOK 3
THE Z-q0 HOw iT Wo&K,S
CONNEcTiNict *Me Z-530 TO RN EPROM.
MRER
30 Ao
A.
31 kt
i A
32 A5 As
33
34. THIS IS THE
IIJT AS A5 ADDRESS
Ib 35
36 Ac. A4 2 e05
NMI 17 37 Ai A7 ' 2716 dea_ 1-HESE Two CHIPS WILL
3tc At
605Kg Z5 At Aq "I-Audio EActi OTHER,
Ato At° EPROM & RAW IR mricilitvE CODE
PROG R.9 . CLCX.K,
LINE GETS THEM G0INCT.
;3:11F---77
t5 Oi Pi 10
RESET Oz DZ 11 ITIS 15 THE
2.6 12 93
P3 13 -4* DATA BUS
7 Ds. 74.
0s Os 15 12,
2? 06 16
/3 0 07 17
6
OM,
ELECTRONICS NOTEBOOK 3 45
THE 2716 EPROM
THE DIAGRAM okl. THE PREviouS PAGE CAN 6E SIMPLIFIED 6Y
DRAWN CI THE. ROSES A5 1=1 PATH WRY' :
THE CPROm MUST (SE TURNED ON ONLY OUR1NQ- THE TIME WHEN IT
15 REQuAEo. THIS IS BECAUSE THE. DATA 8< ADDRESS 6OSE5 eR,E
R,..quifkED BY OTHER, CHIPS in/ THE SYSTEM.
CE OE
2716 2716
,READ TH15 I:4 S EPROM
EPROM
OH -EEE, AND
MENTALLY ao-re
iNCLOSION oF THE BM (2)
-1-AgiNicr OE HIGH cAu5E.5 THE QUTPOT LINES OF THEEPROM TO Q-0 INTO
A HIGH 12GOOrVCE STATE . OUTPUT OA1 15 SUPPLIED VERy QUICKLY
ACTER, OE 15 -TAKEN e.
-1-FiKiNct CE sW2) CAUSES THE OUTPUT LINES To GO INTO A HIGH
imPED9WcE STATE AND 141-90 'PoWER---powri f 5TR-re . GUT WHEN
CE GOES LOW,THE EPROM TAKES CONSIDERABLY LoNGER, -ro PROVIDE
DATA ON ME 00-reof PiNs.
A HIGH 11"-TEDFINCE STATE 15 10ENTICAL To SAYING- "nti-s- iTE.
SO 71-IAT THEY PUT NO LOAD ON THE BuSES,
46 ELECTRONICS NOTEBOOK 3
THE Z-W AlOW iT WORAS
LET U5 LOOK, AT THE EXECUTION OF A SINGLE 6\fTE- INSTRUCT104.—
cALLED NO OPER-PrrIonl.
ELECTRONICS NOTEBOOK 3 47
_131TS, NIBBLES & BYTES
rs1 RN S-B1T MICROPROCESSOR, SYSTEM SuCH as 2--g0 LINES
OF INFoRmlaTiopi 15 PRESENTED TO THE PROLE SoR, 19T THE SAME TIME.
MICRO - I
-4-11S IS THE 111QHEST VALUE
4INES LIME. 1T /5 CALLED n
CAN 10' PROCESS°
ONLY SE
HIGH
oft [Z-(30.1
Lovi
16 16-81T
48 ELECTRONICS NOTEBOOK 3
LAI-T-11.)Q A PRoGkori
I,JI NI toRITINI A tiqctiin)E CODE PROGRAM I-HERE nizE 3 POINTS
`(OV mk.)s-c- RE MEM GER, t
OEN(.14 SCEP MUST ISE VERY SMALL 7ThE MicKo is C.APAISLE O
PERFORMING ONLY A VER'( SIMPLE TASK AT ANY ONE -rime.
EACH STEP MUSS %S. ABLE -co . GE CONVERTED TO A MACHINE -WOE
itJSTRoc•IION •
)1"..11E PROCESSOR, WILL r&E RUNNINCIALL THE TINE & THus PROGRAMS
t-WS'T GE EITHER, n LOOP OR, INcLuctz DELAYS TO %Lou/ DOWN
TvIEAR. ExEculloN RATE TO Sorr HuNAPJ INVoLvst-in)-1".
to,Ni,ras Tz
C
TR, 1$ FA
Tilts is Tiis
AccutivLATert%
4-
(
/n.IPUT St4i-t-cklES
(") ffooI
-111Ey ARE ‘L.00KE.0 Ri I DURING- THE `IN' inISRuctIoni. WHEN Tiff 1OUT
11\1%-c10c-cioN IS EXECUTED THE VALUE IN EACH f LIP cLoP WILL 13E PASSED
sEGMV\ITS pF THE OISPLAy.
ELECTRONICS NOTEBOOK 3 49
TO 6LINK, DISPLAY
WE CAN Com6iNE 00R, KNOWLEDGE OF OUT & DJNZ la A PROGRAM
WHICH DUNKS THE DISPLAY.
LO 6,00 06 oo
LD A" 06 3E 06
(NT 02.) A OS oz
DONZ.
DJNZ, io0 FE
0 jt42 FE lo FE
1-0 A 1 0 0 3€ oo
OUT (02.)A 03 02
Dona FE
DoN2 FE 10 FE
FE
0JrsIz. FE to FE
EA Is EA
IS WHERE COMPUTER, IS SPENDING TimE DOING
NO-THING (' cE.c..EPT REGISTER, 6l WHILE DISPLAY
RE.MAINS I Lut-IINWTZ0 (oR 6LANK SO TROT RE HUMAN EYE COW
0c1ELT THE \ GLiNKINIc.1 EFFECT.
-174E CLINK RATE- WILL DEPEND ON T-HE VIZEQUENCY OF I.HE CLOCK,
AND You CAN A00 MORE 031\1Z.1 5 IF REQUIRED.
OWN ONE. 1-0 r3,00 15 REQUIRED AND IT IS 1T --CHE VI-ART OF `RE
PckockMil.„ q-c ComPLETIoN oc A OJN2.. oPER.ATIoNI REcAtSTER.
IS LEFT IN A ZEKO STATE AND I5 ReAw< ?OR THE NEXT DONIZ..
THE NccomuLkteoR, 15 LOADED WI-V H 06 IN -1-HE Pi2owZAm eoT C,RN BE
LoADED ANI VALUE 'FROM. 01 -ro FF.
THE VALUE YOU CHOOSE WILL DEPENO UPON HOW THE 015PLAY IS
WO-EC) 'Rr W1-1191- YoU wAn/T TO APPEAR', THE MiCROComc (SEE
ITJSI0E OVER OF THIS IssuE)H195 THE FoLt.ovsliN1 4 SEGMENT VALvES;
YOU WILL N117ric-E THE VALUES inicReASE.
CACC.0fLOING. LE T -tERINC OF Ti+E SEGMENTS
2 AR.t. EASY -TO rzr.lz.1-1(6ER--..
PRoOucE Le-v -r- zkS OR Num6ERS olv THE
DISPLAY THE HEx. VALUES ARE ADDED
06 56 4F 66 60 7 07 7F 67 3F
50 ELECTRONICS NOTEBOOK 3
To irickEmErvi THE DISPLAY
HERO ARE TWO WAYS OF IrsicREMENTiNq HE DISPLAY. ONE IS
BINARY INCREmENT, ---IHE OTHER, 15 NUMERICAL INcKEMENIT.
XOR f1 IRF
LOCA 4F
IN A, 01 06 01 114E PROGRAM LOOPS 14c.RE IF THE
6 1 77 A cis 7f 13u-v-cohl is NoT PRESSED. w 4St`i
JR, Z 28 FA %3UT-row is PRESSED PRomtalm ROvANcES
INC C DC
LDAs 79
oui(09A 03 oz.
IN A (0) DB of PROctRAM LOOPS HERE WHILE 6UTTolv
gri 7,A cg 7F 15 PRESSeD AND ADVANCES WHEN/
Oft, NZ. 20 FA 13'-1- TON RELEASED.
SR, )8 EE
ELECTRONICS NOTEBOOK 3 51
0 et Cou►JTEf, PRocitzAM
r 00$0'
COA QE. OA
LO DE 00130 1 oo 08 SF = 0
Ak0i) D 01
E 61-r 7,A
3R, Z
INc. DE.
c6 7F
ZS FA
13
06 = I
56 = 2,
4F = 3
66 =4
LO A (OE IA 6D 7- 5
DVT (023A 0302,. 7O =6
-7-1(4 A Col) 06 01 07 = 7
617 71 A C6 7F 7F --
1 SRNZ 20 cA 67 =
DSC C. 00
Eg
19 E5
52 ELECTRONICS NOTEBOOK 3
O couNTER,
P9.000cING C-HARfiCviZS SocH AS 0, 12,1 ETc. Ot\J R olspLAN
REQUIRES 1-(461E . SHE MICRO STEP5'1-HROuGt4 -1-
HiS 113BLE AND
E 1115 COUNTING-.
00$0 '3F
r4T pogo ) THE VALUE 3 IS Vour.)0.
= 3O 0 *02+01+ +08
lot
30toF =3F
ELECTRONICS NOTEBOOK 3 53
is A sPEciAL TWO 13Y -TE AWS-IROc-noi.) US)Nc: THE t3 REGISTER,.
11- IS MAINLY USED To PROOuc.E. A SHORT DELAY & OPERAT E S ir4 THE
Fot,LoWiN1c:
LD 6,C? 06 CF
LD NOS 3E o8
()v.v. 0/ A D3 02
03r4Z. ro. 10 FE
031\17- 10 FE
03N2... 10 FE
N2_ 10 FE
54 ELECTRONICS NOTEBOOK 3
lc 6 is LOPPED wIl'14 (60, A StIORIER, DELAY WILL
Clt.s s -1-1-kus
LO (3 SO 06 SO
03N2 FE Feb- to FE
if" MORE 1-11iNN ONE D3NZ_ Is uSED ONLY THE CIRST DON2.. WILL gE
St4ocz.-r AS REGIS-MR, S WILL GE ZERO Al' THE BEGINNING of 'MG
° & 5" 03NZ.
2(.4
LO 1300 o6 00
LUcI o8 SE o2
0U-I (02. D3 OZ,
r•I7- 10 f A -1
•(00 3vmP RACK, THOS
LO 1?) 00 oG oo
LO OS SE oil
otY o2.) A 03 02
oaw F2 ID vg
N.S-1'0 LoOP
A1\1%mr)
n LOOP ccw 1,E CREA-CE0 kh-tH THE 0,WrZ. INSIROC-rioN
14ZR fi, C215- Z19.,1 PIS FOLLOWS :
46c AN01
C LO IS 00
LO C. 2.0
D3r4 Z FEE
Oc.c C
39.NZ.
-THE- FtRST TWO ihisiftomoNs ARE cALLED *SE-T UP" & II- IS imPoRIANIT
t•101 TO JUMP PaAcK -Co -CHEsE CaliEwISE THE LOOP(S) WILL NEveR. QE
0EcRE1-/tEni-r0 io Z.. -1z.O.
1
-C-1. PROGRAM W1LL FoRfotkivl 256 Lop-PS OF OEct?..ErIC-NrriNcf 6 -ntEt.i
svoviiNc 'CO 'N OC-c C. I C 15 No-T ZERO 11-IE. pg.oc.Itzqm WILL .UMP
GALIc -Co ()mi. 1 -tioS 11 WILL PERCORm 20H I-00PS of DTZ.
E 20rt Loo9S 7---. 32. L00951 :1-415 PROGRAM IS 1 LOOP Willi/NJ 0 LOOP
012, NES-CEO LOOP & tS VERY HANDY FoR pRoouc. irvc.T LONG TIME
of:LANs.
ELECTRONICS NOTEBOOK 3 55
,o. zs
0 Machine Codes
SHEET
11
This table contains over 700 BIT 5,A CB 6F JP P,ADDR F2 XX XX LD HL.,(ADDR) 2A XX XX RES 5,B CB AB SET 1 (IY+dis) ED CB XX CE
Machine Code instructions BIT 5.B CB 68 JP PE.ADDR EA XX XX LD HL, dddd 21 dd dd RES 5,C CB A9 SET 1,A CB CF
for the Z80. BIT 5.0 CB 69 JP PO.ADDR E2 XX XX LD I,A ED 47 RES 5,D CB AA SET 1.6 CB C8
It has been compiled from BIT 5.D CB 6A JP Z.ADDR CA XX XX LD IX,(ADDR) DD 2A XX XX RES 5,E CB AB SET 1,C CB C9
Zilog Data sheets. SGS Data BIT 5,E CB 6B JR C.dis 38 XX LD IX,dddd DD 21 dd dd RES 5.H CB AC SET 1,D CB CA •
books, Z80 Programming by BIT 5.H CB 6C JR dis 18 XX LD IY,(ADDR) FD 2A XX XX RES 5,L CB AD SET 1,E CB CB
P. Levison (now out of print)BIT 5,L CB 6D JR NC.dis 30 XX LD IY,dddd FD 21 dd dd RES 6,(HL) CB B6 SET 1,H CB CC
and Micro-Professor Pro- BIT 6,(HL) CB 76 JR NZ,dis 20 XX LD 1.,(HL) 6E - RES 6,(IX+dis) DD CB XX B6 SET 1 L CB CD
gramming Handbooks. BIT 6.(IX+dis) DD CB XX 76 JR Z.dis 28 XX LD L,(IX+dis) DD 6E XX RES 6,(IY+dis) FD CB XX B6 SET 2,(HL) CB D6
Two books to help with the BIT 6.(IX+dis) FD CB XX 76 ID (ADDREA 32 XX XX LD L,(IY+dis) FD 6E XX RES 6,A CB B7 SET 2,(IX+dis) DD CB XX D6
interpretation of this table BIT 6,A CB 77 I D (ADDREBC ID 43 XX XX LD LA 6F RES 6,B CB BO SET 2,(IY+dis) FD CB XX D6
are: Z80 ASSEMBLY BIT 6,8 CB 70 LD (ADDR),DE ED 53 XX XX LD L,B 68 RES 6.0 CB B1 SET 2,A CB D7
LANGUAGE by Lance A. BIT 6,C CB 71 LD (ADDR),HL ED 63 XX XX LD L,C 69 RES 6,D CB B2 SET 2,B CB DO
Leventhal.CMc Grew Hill), BIT 6,D CB 72 LD (ADDREHL 22 XX XX LD L,D 6A RES 6,E CB B3 SET 2.0 CB DI
and PROGRAMMING Um ZISO BIT 6.E CB 73 LD (ADDREIX DD 22 XX XX LD L,dd 2E dd RES 6,H CB B4 SET 2,D CB D2
by Rodney Zaks. (Sybex). BIT 6.H CB 74 LD (ADDR),IV FD 22 XX XX LD L,E 68 RES 6,L CB B5 SET 2,E CB D3
BIT 6.L CB 75 LD (ADDR).SP ED 73 XX XX LD LH 6C RES 7, HL) CB BE SET 2,H CB D4
• ADC A,(HL) 8E BIT 7.11-IL) CB 7E LD (BC) A 02 LD L,L 6D RES 7, 1X+dis) DD CB XX BE SET 2,L CB 05
ADC A,(1X+dis) DD 8E XX BIT 7.(1X+dis) DO CB XX 7E LD (DE).A 12 LD R,A ED 4F RES 7, IY+dis) FD CB XX BE SET 3.(H1) C13 DE
ADC A,IIY+dis) FD 8E XX BIT 7.(IY-Fdis) FD CB XX 7E LD (HLEA 77 LD SP,(ADDR) ED 7B XX XX RES 7,A CB BF SET 3,(IX+dis) DD CB XX DE
ADC A,A 8F BIT 7.A CB 7F LD (HLEB 70 LD SP,dddd 31 dd dd RES 7,6 CB 88 SET 3,(IY+dis) FD CB XX DE
ADC A.B 88 BIT 7.B CB 78 LD (HL).0 71 LD SP,HL F9 RES 7,C CB B9 SET 3,A CB DF
ADC A,C 89 BIT 7,C CB 79 LD (HL),D 72 LD SP,IX DD F9 RES 7,D CB BA SET 3.6 CB 138
ADC A,D 8A BIT 7.0 CB 7A LD (HL),dd 36 dd LD SP,1Y FD F9 RES 7,E CB BB SET 3,C CB D9
ADC A,dd CE dd BIT 7.F CB 76 ID (HL).E 73 LDD ED A9 RES 7,H CB BC SET 3,D CB DA
ADC A,E 8B BIT 7.14 CB 7C LD (HL),H 74 LDDR ED B8 RES 7,L CB BD SET 3,E CB DB
ADC A,H 8C BIT 7,L CB 70 LD (HLEL 75 LW ED AO RET C9 SET 3,H CB DC
ADC A,L 8D CALL ADDH CD XX XX LD (IX+dis),A DD 77 XX LDIR ED BO RET C D8 SET 3.L CB DD
ADC HL.BC ED 4A CALL C.ADDR DC XX XX ID (1X+dis).E1 DD 70 XX NEG ED 44 RET M F8 crI
rnSET . E6
ADC HIDE FD 5A CALL M.ADDR FC XX XX LD (IX+dts),C OD 71 XX NOP 00 RET NC DO -I SET 411X+dis) DD CB XX E6
ADC 1-11.HL ED 6A CALL NC,ADDR D4 XX XX LD (1X+disED DD 72 XX OR HL) B6 RET NZ CO ASET 4, IY+dis) FD CB XX E6
ADC HL.SP ED 7A CALL NZ.ADDR C4 XX XX ID (1X+dis).48 DD 36 XX dd OR IX+dis) 130 136 XX RET P FO i- ,
ADD A,(HL) 86 CALL P.ADDR F4 XX XX LD X+dis 5 DO 73 XX OR IY+dis) FD 86 XX RET PE E8 SET 4,B CB E0
ADD A.(IX+dis) DD 86 XX CALL PE.ADDR-EC XX XX LD X+dis ,H DD 74 XX OR A B7 RET PO E0 SET 4,C CB El
ADD A.(1Y+dis) ED 86 XX CALL PO,ADDR E4 XX XX LD X+dis ,L DD 75 XX OR B BO RET Z C13
n
is SET 4,D CB E2
ADD A,A 87 CALL Z.ADDR CC XX XX ID Y+dis A FD 77 XX OR C B1 RETI ED 4D ,,,, SET 4,E CB E3
ADD A,8 80 CCF 3F LD Y+dis ,B FD 70 XX OR D B2 RETN ED 45 or SET 4,H CB E4
ADD A.0 81 CP (HI) BE LD V+dis ,C FD 71 XX OR dd F13 dd RL HL) CB 18 SET 5, HL) CB EE
ADD A,0 CP (IX+dis) DD BE XX LD Y+dis 13 FD 72 XX OR E 83 RI IX+dis) DD CB XX 16 SET 5, IX+dis DD CB XX EE
ADD A,dd C6 dd CP (I`E-Fdis) FD BE XX LD Y+dis ,dd FD 38 XX dd OR H 84 RL IY+dis) FD CB XX 16 SET 5, IY+dis FD CB XX EE
ADD A.E 83 CPA BF LD Y+dis ,E FD 73 XX OR L 55 RL A CB 17 SET 5,A EF
ADD A,H 84 CP B B8 LD Y+dis ,H FD 74 XX OTDR ED BB RL B CB 10 SET 5,8 CB E8
ADD A.L 85 CP C B9' LD Y+dis 1 FD 75 XX OTIR ED B3 RL C CB 11 SET 5,C CB E9
ADD HL,BC 09 CP 0 BA LD A,IADDR) 3A XX XX OUT IC .A ED 79 RL D CB 12 SET 5,D CB EA
ADD HL,DE 19 CP dd FE dd LD A, BC OA OUT C ,8 ED 41 RL E CB 13 SET 5,E CB EB
ADD HL,HL 29 CP E BB LD A. DE 1A OUT C ,C ED 49 RL H CB 14 SET 5,H CB EC
ADD HL,SP 39 CP H BC ID A, HL 7E OUT C X/ ' ED 51 RL L CB 16 SET 5,1 CB ED
ADD IX,BC DD 09 CP L BD LD A, IX dis) DD 7E XX OUT C ,E ED 59 RLA 17 SET 6 HL) CB F6
ADD IX.DE DD 19 CPD ED A9 LD A. IY+dis) FD 7E XX OUT C ,H ED 61 RLC 11-1L) CB 06 SET 6, IX+dis) DD CB XX F6
ADD IX,IX DD 29 CPDR ED B9 LD A,A 7F OUT C .I. ED 69 RIC IX+dis) DD CB XX 06 SET 6, IY+dis) FD CB XX F6
ADD IX,SP DD 39. CPI ED Al LD A.B 78 OUT port,A D3 port RIC IY+dis) FD CB XX 06 SET 6,A CB F7
ADD IY.BC FD 09 CPIR ED B1 LD A,C 79 OUTD ED AB RLC A CB 07 SET 6,B CB FO
ADD IY.DE FD 19 CPL 2F LD A,D 7A OUTI ED A3 RLC B CB 00 SET 6,C CB Fl
ADD IY.IV FD 29 DAA 27 LD A,dd 3E dd POP AF Fl RIC C CB 01 SET 6,D CB F2
ADD IY,SP FD 39 DEC (HL) 35 LD A,E 7B POP BC CI RLC D CB 02 SET 6,E CBF3
AND (HL) A6 DEC (IX+dis) DD 35 XX LD A,H 7C POPDE D1 RLC E CB 03 SET 6,H CB F4
AND (IX+dis) DO A6 XX DEC (PC-Fdis) FD 35 XX LD A.1 ED 57 POPHL El RLC H CB 04 SET 6,1 CB F5
AND (IY+dis) FD A6 XX DEC A 3D ID A.L 7D POPIX DD El RLC L CB 05 SET 7,r) CB FE
AND A A7 DEC B 05 LD A,R ED 5F POPIY FD El RLCA 07 SET 7, IX+dis) DD CB XX FE
AND B AO DEC BC OB LD 131HL) 46 PUSH AF F5 RLD ED 6F SET 7, IY+dis) FD CB XX FE
AND C Al DEC C OD LD B, IX+dis) DD 46 XX PUSH BC C5 RR 1HL) CB 1E SET 7,A CB FF .
AND D A2 DEC D 15 LD B. IY+dis) FD 46 XX PUSH DE D5 RR IX+dis) DD CB XX 1E SET 7,B CB F8
AND dd E6 dd DEC DE 1B LD B,A 47 PUSH HL E5 RR IY+dis) FD CB XX 1E SET 7,C CB F9
AND E A3 DEC F 10 LD 13,8 40 PUSH IX DO E5 RR A CB IF SET 7,D CB FA
AND H A4 DEC H 25 LD B.0 41 PUSH IY FD E5 RR B CB 18 SET 7,E CB FB
AND L A5 DEC HL 2B LD B,D 42 RES 0, HL) CB 86 RR C CB 19 SET 7,H CB FC
BIT 0.)HL) CB 46 DEC IX DD 2B LD B.dd 06 dd RES 0.(IX+dis) DD CB XX 86 RR D CB 1A SET 7,L CB FD
BIT 0,(IX+dis) DD CB XX 46 DEC IV FD 2B LD B.E 43 RES 0,(IY+dis) FD CB XX 86 RR E CB 18 CB 26
SLA HL
BIT 0.(IY+dis) FD CB XX 46 DEC L 2D ID B.H 44 RES 0.A CB 87 RR H CB 1C SLA IX+dis) DD CB XX 26
BIT 0.A CB 47 DEC SP 3B LD 5.1 45 RES 0.13 CB 80 RR L CB 10 SLA IY+dis) FD CB XX 26
BIT 0.13 CB 40 DI F3 LD. BC,(ADDR) ED 48 XX XX RES 0,C CB 81 RRA 1F CB 27
SLA A
BIT 0,C CB 41 DJNZ (Its 10 XX LD BC,dd 01 dd dd RES 0.D CB 82 RRC HL) CB OE CB 20
SLA 13
BIT 0,0 CB 42 El FR LD C, HL) 4E RES 0.E CB 83 RRC IX+dis) DD CB XX OE SLA C CB 21
BIT 0.E CB 43 EX (SPEHL 53 LD C. IX+dis) DD 4E XX RES 0,H CB 84 RRC IY+dis) FD CB XX OE SLA D CB 22
BIT 0.H CB 44 EX (SPEIX DD E3 LD C, IY+dis) FD 4E XX RES 0.1 CB 85 RRC A CB OF SLA E CB 23
BIT 0,1 CB 45 EX (SP),IY FD E3 LD C,A 4F RES 1,(HL) CB 8E RRC 13 CB 08 SLA H CB 24
BIT 1,(HL) CB 4E EX AF.AF 08 LD C,B 48 RES 1.(IX+dis) DD CB XX 8E RRC C CB 09 SLA L CB 25
BIT 1,(IX+dis) DD CB XX 4E EX DE.HL EB LD C,C 49 RES 1 (IY+dis) FD CB XX BE RRC D CB OA SRA HI) CB 2E
BIT 1.(IY+dis) FD CB XX 4E EXX D9 LD C,D 4A RES 1,A CB 8F RRC E CB OB SRA IX+dis) DD CB XX 2E
BIT 1,A CB 4F HALT 76 LD C,dd OE dd RES 1,B CB 88 RRC H CB OC SRA IY+dis) FD CB XX 2E
BIT 1.13 CB 48 M0 ED 46 LD C,E 4B RES 1,C CB 89 RAC L CB OD SRA A CB 2F
BIT 1.0 CB 49 M 1 ED 56 LD C,H 4C RES 1,D CB 8A RRCA OF SRA B CB 28
BIT 1,0 CB 4A M 2 ED 5E LD C,L 4D RES 1,E CB 88 RRD ED 67 SRA C CB 29
BIT 1,E CB 4B N A.(C) ED 78 LD D, HL) 56 RES 1,H CB 8C RST 00 Cl SRA D CB 2A
BIT 1.H CB 4C N &port DB XX LD D. IX+dis) DD 56 XX RES 1 L CB 8D RST 08 CF SRA E CB 26
BIT 1,L CB 4D N B.(C) ED 40 LD D, IY+dis) FD 56 XX RES 2,(HL) CB 96 RST 10 D7 SRA. H CB 2C
BIT 2,(HL) CB 56 N C.(C, ED 48 LD D,A 57 RES 2,(IX+dis) DD CB XX 98 RST 18 OF SRA L CB 2D
BIT 2.(IX+dis) DD CB XX 56 N DEC) ED 50 LD D,B 50 RES 2,(IY+dis) FD CB XX 96 RST 20 E7 SRL n) 3E
BIT 2,(IY+dis) FD CB XX 56 N E IC) ED 58 LD D.0 51 RES 2,A CB 97 RST 28 EF SRL IX+dil DD C CB XX 3E
BIT 2,A CB 57 N H.,CI ED 60 LD D.13 52 RES 2,8 CB 90 RST 30 F7' SRL IY+dis FD CB XX 3E
BIT 2,8 CB 50 N 1.(C) ED 68 LD D,dd 16 dd RES 2,C CB 91 RST 38 FF SRL A CB 3F
BIT 2,C CB 51 NC (HL) 34 1_13.D,E 53 RES 2,D CB 92 SSC A, HL) 9E SRL B CB 38
BIT 2,D CB 52 NC (1X+dis) DD 34 XX LD D.H 54 RES 2,E CB 93 SBC AI X+dis) DD 9E XX SRL C CB 39
BIT 2,E CB 53 BC (IY-Fdis) ED 34 XX LD D.L 55 RES 2,H CB 94 SBC A, IY+dis) FD 9E XX SRL D CB 3A
BIT 2,H CB 54 NC A 3C LD DE,(ADDR) ED 5B XX XX RES 2,L ' CB 95 SBC A,A 9F SRL E CB 3B
BIT 2,L CB 55 NC B 04 LD DE,dddd 11 dd dd RES 3,(FIL) CB 9E SBC A,B 98 SRL H CB 3C
BIT 3,(HL) CB 5E NC BC 03 LD E,(HL) 5E RES 3,(IX+dis) DD CB XX 9E SBC A,C 99 SRL L CB 3D
BIT 3,(IX+dis) DD CB XX 5E NC C OC LD E,(IX+dis) 013 5E XX RES 3,(IY+dis) FD CB XX 9E SBC A,D 9A 96
BIT 3,(IY+dis) FD CB XX 55 NC D 14 LD E.(/Y+dis) FD 5E XX 3,A SBC A,dd DE dd SUB IX+dis) DD 96 XX
BIT 3,A CB 5F NC DE 13 LD EA 5F RES 3,8 CB 98 SBC A,E 96 IY+dis) FD 96 XX
SUB (IY+dis(
SUB
BIT 3,B CB 58 NC E 1C LD E.B 58 RES 3,C CB 99 SBC AM 9C SUB A 97
BIT 3,C CB 59 NC H 24 LID E.0 59 RES 3,D CB 9A SBC A.1 9D SUB B 90
BIT 3.D CB 5A NC HL 23 LD E,D 5A RES 3,E CB 9B SBC HL,BC ED 42 SUB C 91
BIT 3,E CB 5B NC IX DD 23 LD E,dd 15 dd RES 3,H CEI 9C SBC HL,DE ED52 SUB D 92
BIT 3,H CB 5C NC DI FD 23 LD E,E 58 RES 3.L C8 9D SBC HL,HL ED 62 SUB dd D6 dd
BIT 3.1 CB 5D NC L 2C LD E,H 5C RES 4,)HL) CB A6 SBC HL,SP ED 72 SUB E 93
BIT 4.(HL) CB 66 NC SP 33 LD E.L 5D RES 4,(1X+dis) DD CB XX A6 SCF 37 SUB H 94
BIT 4.(IX+dis) DD CB XX 66 ND ED AA LD NHL) 66 RES 4,(IY+dis) FD CB XX A6 SET 0,(HL) CB C6 SUB 1 95
BIT 4,(IY+dis) FD CR XX 66 NOR ED BA LD H,(IX+dis) DD 66 XX RES 4,A CB A7 SET 0,(IX+dis) DD CB XX C6 XOR(HL) AE
BIT 4.A CB 67 NI ED A2 LD H,(IY+dis) FD 66 XX RES 4,8 CB AO SET 0,(IY+dis) ED CB XX C6 XOR (IX+dis) DD AE XX
BIT 4.B CB 60 NIR ED B2 LD H.P. 67 RES 4,C CB Al SET 0.A CB C7 XOR (IY+dis) FD AE XX
BIT 4.0 CB 61 JP (HE) E9 LD H,B 60 RES 4,D CB A2 SET 0,B CB CO XOR A AF
BIT 4,D CB 62 JP (IX) DD E9 LD H,C 61 RES 4,E CB A3 SET 0,C CB Cl XOR B A8
BIT 4.E CB 63 • JP (IV) FD E9 LD HAD 62 RES 4,H CB A4 SET 0,D CB C2 XOR C A9
BIT 4,H CB 64 JP ADDR C3 XX XX LD H,dd 26 dd RES 4.L CB A5 SET 0,E CB C3 XOR D AA
BIT 4.1 CB 65 JP C.ADDR DA XX XX LD H,E 63 RES 5.(H1) CB AE SET 0.H CB C4 XOR dd EE dd
BIT 5.(HL) CB 6E JP M,ADDR FA XX XX LD H.H 64 RES 5,)IX+dis) DD CB XX AE SET 0,L CB C5 XOR E AB
BIT 5.(IX+dis) DD CB XX 6E JP NC.ADDR D2 XX XX LD H.L 65 RES 5,(IY+dis) FD CEI XX AE SET 1,(HL) CB CE XOR H AC
BIT 5,(IY+dis) FD CB XX 6E JP NZ.ADDR C2 XX XX ED HLIADDRI ED 6B XX XX RES 5,A CB AF SET 1,(IX+dis) DD CB XX CE XOR L AD
_ - -
corrected 16 - 6 - 1985
62 ELECTRONICS NOTEBOOK 3
Machine Codes SHEET
Z80 FOR DISASSEMBLY 12
' °
o nononoonnnoonnno onno normon000nnononnnoonn nonnoonnonnononon nnonnnonnoononno non000 nnm ,mmmmmm,,,mmm,-mm mmmm mmmmm mmmm mm00 0pou
LD. I,A
OT3 >
„
D,Imo nco>
=
,i,i,,i,,
As
SET 2,H
.mm.,,,,,D .
,
-- M T: r7P 0
ED 47
00 0 00(Ju ouououououri
mmm mcommmm mm mm mmmmm m mmm a3m mmmm mmmmmmmmmm mm alm m com m000 0000 00 000000comm comm incomm commalmcommcom mmoo m anomm on com co mmco m m co mmm oo mco m m com m in comm co mm co mcom
co uln wu.o•-Nma ul toNcomamonw L..o,-Nm.e.to,mm<morD w u.o,-Nmq m w,mmgm oou,.0-Nm,,.,mmam oow L,,,-Nmqmtor-comam oow LL 0,
CB D4
2 *('-i-
LD H,D
.
62 IN C,(C)
.
.
CB D5 SET 2,L ED 48
a ›
This is a Z-80 MACHINE 63
W) .
M
LO H,E SET 2,(HL) OUT (C),C
_,s,,,,T,,,,,,,,,
CB D6 ED 49
CODE disassembly 64 LD H,H SET 2,A ADC HL,BC
a
CB D7 ED 4A
table. Use it in 65 LD H,L SET 3.B LD FIC,(ADDR)
In
CB D8 ED 48
conjunction with the Z- 66 LD H.(HL)
==
SET 3,C RETI
m o141w.-,
CB D9 ED 4D
67 LD H,A SET 3.D LD R.A
,i,i4„,:44,i,riLi6L6 6- 6L6,6
80 Machine Codes C B DA ED 4F
68 LD L. SET 3,E
,,
presented previously CB DB ED 50 IN DAC)
' 69 LD L,C
..„
.,,
›,.
CB DC SET 3,H ED 51 OUT (C),D
...,0,ww.wo .ww,,N,,,NN,,N,,N,Nmmcomm m w .
T '8e- M -P C
,
for the creation of your 6A LD L,D
.
CB DD SET 3,L ED 52 SBC HL,DE
,10-
own programs. 68 LD L,E SET 3,(1-1L) ED 53 LD (ADDR),DE
CB DE
6C LD L,H
%r “ 0 .
SET 3.A IM 1
a
CB DF ED 56
These lists make pro- 6D LD L,L
-om mo om n.m,
CB EO SET 4.6 ED 57 LD A.I
,.,,,,,
6E LD L,(HL)
===
assembly easy. Fit them CB E2 ED 59 OUT (C),E
Er
70 LD (HL),B CB E3 SET 4,E ED 5A ADC HL,DE
;
into a.plastic sleeve and
g.
0
71 LD (HL),C
,
›Q
SET 4,H LD DE,(ADDR)
T;
CB E4 ED 56
keep them handy. 72 LD (HL),D CB E5 SET 4,L ED 5E IM 2
73 LD (HL),E SET 4,(HL)
ouououououucw 0000 000 00 00 0 00ueuo uououo uuouou ououououuououou ououououou:)uououo uouo uououououo uououuouououou
CB E6 ED 5F LD A,R
,,, t'X W, a,
,E, u,
74 LD (HL),H SET 4,A
a
CB E7 ED 60 IN 1-1,(C)
75 CB E8 SET 5,6 ED 61 OUT (C),H
'
76 LO
HALT
L
LT ) CB E9 SET 5,C ED 62 SBC HL,HL
77 LD (HL),A CB EA SET 5,D ED 63 LD (ADDR),HL
00 NOP 78 LD A,B
.
CB EB SET 5,E ED 67 RRD
01 LD BC,dddd 79 LD A,C
-n r. D
.=
SET 5,H
,,,
CB EC ED 68 IN L(C)
E
02 LD (BC),A 7A LD A.D
) * (-> T % 6 g'4 -2g 2
CB ED SET 5.L ED 69 OUT (C),L
5 ,,i,,,,:
03 INC BC 7B LD A,E CB EE SET 5,(HL) ED 6A ADC HL,HL
04 INC B 7C LD A,H
,= ,,,-1-lw
SET 5,A
=
4gt, T
CB EF LD HL(ADDR)
a
ED 613
05 DEC 8 7D LD A,L °1
'a
CB FO SET 6.6 ED 6F RLD
06 LD B,dd 7E LD A,(HL) SET 6,C
m ,„"i
CB Fl ED 72 SBC HL,SP
07 RLCA 7F LD A,A
g,
CB F2 SET 6.D ED 73 LD (ADDR),SP
.
08 EX AF,A'F' 80 ADD A,B
.
SET 6,E
mmm mm com mx=xmcc mccm ccx mccx= xxm ccx= xx mx=x mccm m mxx m ccxx xxxm x= mmx m mx= m ccx = mccm ccm=mm o ow www wwoowm tn w moww om
CB F3 ED 78 IN A.IC)
09 ADD HL,BC 81 ADD A,C
.m
CB F4 SET 6,H ED 79 OUT (C),A
OA LD A,(13C) 82 ADD A,D E SET 6,L
,...
CB F5 ED 7A ADC HL,SP
m0 00
SET 6.(HL)
g
CB F6 ED 7B LD SP,(ADDR)
ta 1
a
CB F7 ED AO LDI
.
OD DEC C 85
1 W-ro
ADD A,L
m commco mmmm mmmonom wm mmmm mmcomm mmcom mmco m mmcom mmwm commm comcom mcommco mmmm mmmm mmmmmmmw mmcom mmmm mmmm ,
CB F8 SET 7,13 ED Al
.;664:5 66666,
OE LD C,dd 86 ADD A,(HL)
,,,,nononnon-
- M M O OM
a
CB FF ED BO LDIR
15 DEC D 80 ADC A,L
1i - X MO OM >a
ED 62 INIR
17 RIA RE ADC A,A DD 21 LD IX.dddd ED B3 OTIR
18 JR dis 90 SUB B DD 22 LD (ADDR),IX ED B8 LDDR
'11
FD 19 ADD IY,DE
1E LD E.dd 96 SUB (HL) DD 35 DEC,(IX + dis) FD 21 LD IY,ddrld
,inir4c4 r4 ri
1F RRA
4N -o
97 SUB A
m>a ,.„,
_7
DD 66 FD 35 DEC,(IY + dis)
zmun wm
FD 39
28 JR Z,dis AND B
- M Iil„„i„mpl
2D DEC L
M ,
FD 6E
2E LD L,dd A6 AND (HL) DO 7E LD A,(IX + dis) LD (IV + dos),B
FD 70
=,
FD 74 LD (IV + dos),H
33 INC SP AB XOR E DD A6 AND (IX + As) FD 75 LD (IV + dos),L
34 INC (HL) AC XOR H DD AE XOR (IX + dis) FD 77 LD (IV + dos).A
a
FD B6
3D DEC'A B5
E
OR L
tI tt=orTI
40 LD 13,13 88 CP B
Nma.w ,
FD CB XX 2E
44 LD B,H BC CP H DD CB XX 76 BIT 6,(IX + dis) SRL (IV + dos)
FD CB XX 3E
a
45 LD 8,L BD CP L
C
49
:r
fif
:
48 LD C.E C3 JP ADDR
O tgg tit tttt t
FD CB XX 96
==
'_,=
5E LD E,(HL) D6 SUB dd
0,-
mc.,0 0
ED 43 LD (ADDR),BC FD E3 EX (SP),IY
51 LD E,A D7 RST 10 ED 44 NEG FD E5 PUSH IV
60 LD H,8 08 RET C
Nm
ED 45 RETN E9 JP (IV)
61 LD H,C A
,;i
D9 EXX ED 46 IM 0 F
ED F9 LD SP. IY
..
ELECTRONICS NOTEBOOK 3 63
Machine Codes SHEET 13
Z80 EXPLAINED Part 1
A BRIEF description for each Z-80 instruction:
EX (SP)HL . The contents of the location addressed by the Stack
ADC A,( ) . The value of the byte pointed to by the address in ( ) Pointer are exchanged with the contents of the CPU
plus the value of the carry flag, is added to the register L. The contents of the H register are
accumulator. exchanged with the contents of the stack pointer plus
ADC A,B . . The value of the B register plus the value of the carry one.
flag is added to the accumulator. EX AF,AF' . . The contents of the accumulator and status register
ADC HL,BC . The value of the register pair BC plus the value of the are exchanged with the contents of the alternate
carry flag . is added to the HL register pair. accumulator and status register.
ADD A,( ) . The byte at the address ( ) is added to the accumulator. EX DE,HL . . Exchange the contents of DE and HL registers.
ADD A,B . . The value of the B register is added to the accumulator. EXX . . . . Exchange the contents of the general purpose
ADD HL,BC . The value of the BC register pair is added to the HL registers with corresponding alternate registers.
register pair. HALT . . . . CPU suspends operation and executes NOP's. It
ADD IX,BC . The value of the BC register pair is added to the index maintains memory refresh logic.
register. IM 0 . . . . Sets interrupt mode 0.
AND ( .. The value of the byte pointed to by the address in ( ) is IM 1 . . . . Program RESTARTS at 0038H when interrupted.
logically ANDed with the accumulator. IM 2 . . . Sets interrupt mode 2.
AND A . . . The accumulator is ANOed with itself. IN A,(C) . . Data (from the input port specified by the contents of
AND B . . . The B register is ANDed with the accumulator. register C) is loaded into register A.
BIT 0,( .• Bit 0 of the byte pointed to by the address in ( ) is INC (HL) . . The contents of a memory location are incremented by
tested and if found to be '0', the ZERO FLAG is set to '1'. one.
BIT 0,A . . . Bit 0 of the A register is tested and if it is '1' the zero INC A . HL Increment register A (Or a register Pair e.g. BC DE etc.)
flag is set to '0'. IND . . . . Input from a port specified by the contents of register
CALL Addr . . The program is diverted to a sub-routine. C. One byte of data is transferred to the memory
CALL C The CALL will only be performed if the carry flag in the location addressed by the contents of the HL register
Address F register is '1'. pair. The value in register B and HL will be
CALL M The CALL will only be performed if the S flag (sign flag) decremented at the end of this instruction.
Address is negative. INDR . . . . Same as IND except the instruction continues until
CALL NC The CALL will only be performed if the NON-CARRY register B reaches zero.
Address condition is present. i.e. carry flag '0'. INI Same as IND except the contents of HL register pair
CALL NZ The CALL will only be performed if a NON-ZERO are decremented at the conclusion of the instruction.
AddreSs condition is satisfied. i.e. the zero flag is '0'. INIR . . . . Same as INI except the instruction repeats until
CALL P The CALL will only be performed if the sign flag in the F register B reaches zero.
Address register is positive. i.e S = 1. JP (HL) . . Jump to the address contained in register pair HL.
CALL PE The CALL instruction will only be executed if the JP ADDR . . See CALL instructions.
Address PARITY is EVEN. This means the P/V flag is SET (1). JP C,ADDR . A conditional relative addressing jump. See CALL for
CALL PO The CALL directive will only be executed if the PARITY JP M,ADOR meaning of C, NC, NZ Et, Z.
Address is ODD. This means the P/V flag is reset (0). LD (ADDR),A The contents of the accumulator are loaded into the
CALL Z The CALL will only be executed if the zero flag is SET address contained within the ( ).
Address (1). LD (ADDR)BC The contents of C are loaded into the immediate
CCF Complements the CARRY FLAG - reverses the address and B into the address plus one.
condition of the carry flag. LD (BC),A . The contents of the accumulator are loaded into the
CP ( Compare the value of the byte pointed to by the location pointed to by the contents of BC.
address in ( ) with the accumulator. LD ( ),A . . The contents of A are loaded into the memory location
CP A The accumulator is compared with itself. (IX + dis) obtained by adding a displacement value to the
CP B The value of the B register is compared with the contents of the IX register.
accumulator. LD A,(ADDR) Load the accumulator with the contents of the
CPD . . The contents of the memory location pointed to by the immediately specified memory address.
HL register pair is subtracted from the accumulator LD A,A . . . Load the data from one CPU register into another.
and the result discarded. Both HL and BC are LD A,dd . . Load one byte of data into the CPU register specified.
decremented. LD BC,dd dd Load 2 bytes of data into the CPU register pair
CPDR . As above but instruction will terminate when BC = 0 or specified. e.g. The first byte loads into C and the
A = (HL). second byte into B.
CPI The contents of the memory location pointed to by the LD A,I . . . Load the accumulator with the contents of the
HL register pair are compared with the contents of the Interrupt Vector register.
accumulator. HL is then incremented and BC LO A,R . . . Load the accumulator with the contents of the
decremented. Memory Refresh register.
CPIR . Compare the contents of the address pointed to by the LD I,A . . . Load the Interrupt vector register, from the
HL register pair with the accumulator. HL is then accumulator.
incremented and BC decremented until BC = LD R,A Load the Memory Refresh register with the contents of
0. or if A = (HL). the accumulator.
CPL Complement the accumulator. i.e. all 1's are changed LOD . . The contents of a memory location pointed to by the
to O's etc. contents of the HL register pair are transferred to the
DAA Decimal Adjust the Accumulator. Produces one digit location pointed to by the contents of the DE register
for the 4 least significant bits and one for the 4 most pair. After the data has been transferred both HL and
significant bits. The carry flag is set to '1' if an overflow DE are decremented by one. Also the 'counter-
Occurs. register' pair BC is decreased by one.
DEC ( ) . Decrement the contents of a memory location by one. LDDR Same as LDD except if contents of BC do not go to
DEC A . Decrement the contents of a CPU register by one. zero, the Program Counter will be decreased by a value
DI Disable a maskable interrupt signal. of two and the instruction will be re-executed. The
DJNZ . . . A conditional relative addressing jump. The contents instruction will continue until the value in the register
of register B is firstly decremented. If the result is NOT pair BC goes to zero.
ZERO, a jump, determined by the value of the LDI Same as LDD except register pairs HL and DE are
displacement byte, will take place. If the result is zero, increased by a count of one.
the next instruction will be executed. LDIR Same as LDDR except register pairs HL and DE are
El This one-byte instruction ENABLES the maskable incremented by one after the data has been
interrupt function by setting the interrupt flip flops. transferred.
64 ELECTRONICS NOTEBOOK 3
Z80 Machine Codes
EXPLAINED Part11
NEG Each bit in the accumulator is reversed sign. One's go RLD . . . The 4 low-order bits of a memory location (pointed to
to zero and zero's go to one. Then one is added to the by the contents of register pair in brackets) are
result. transferred to the 4 high-order bits of the same
NOP The NO OPERATION instruction. Only the Program memory location. The 4 high-order bits are transferred
Counter advances. into the 4 low-order bits of the accumulator. The
OR ( ) . The logic OR operation is performed between the previous 4 low-order bits of the accumulator are
accumulator and the contents of the memory location transferred to the 4 low-order bits of the memory
pointed to by the address in ( ). location specified above.
OR A,B,C etc A logic OR operation is performed between the RR ( j . Rotate the contents of a memory location pointed to by
accumulator and a specified register. the contents of the register in ( ) to the right, through
OTDR . . . Data from the memory location specified by the the carry bit.
contents of the HL register is outputted to a port as RR A,B,C etc Rotate the indicated register to the right through the
specified by the contents of register C. The HL pointer carry bit.
has its value decremented after each transfer RRA . . . . Rotate the accumulator right, through the carry bit.
operation. The value of register B is decremented and RRC ( ) . . Rotate the contents of a memory location pointed to by
if the result is zero, the Program Counter register is set the contents of the register in ( ) to the right but not
back 2 units so that the instruction is re-executed. through the carry bit. The C flag is set to the status of
OTIR . . . . Same OTDR except that the HL pointer is incremented the register's least significant bit.
after each execution. RRC A,B,etc Rotate register to the right but not through the carry
OUT (C),A etc The contents of A, B, C, D, etc are outputted to the port bit.
specified by the contents of register C. RRCA . . . . A one-byte instruction for RRC A.
OUT port,A . . The contents of the accumulator is outputted to the RRD . . . . The 4 high-order bits of a memory location (pointed to
port specified. by the contents of register pair HL) are transferred to
OUTD Data is outputted from memory location specified by the 4 low-order bits of the same location. The 4 low-
the contents of the HL register pair to the port order bits are transferred to the 4 low-order bits of the
specified by the contents of register C. (contents of accumulator. The previous 4 low-order bits of the
register B will be decremented but no repeat operation accumulator are transferred to the 4 high-order bits of
will be performed.) HL register pair has its contents the memory location specified above. A special one-
decremented after the conclusion of the operation. RST 00 . . . A special one-byte subroutine call directive called
OUTI Same as OUTD except HL has its contents RESTART.
incremented at the conclusion of the operation. RST 00 will restart at page zero, location 00. i.e. 00 00
POP AF . . . Two bytes are removed from the stack. The first byte is RST 08 will restart at location 08. i.e. 00 08 etc.
loaded into F and the second into A. SBC A,( ) . Subtract the contents of memory pointed to by the
PUSH HL . . . Two bytes are placed onto the stack. The contents of contents of the register pair in ( ) and the carry flag
the HIGH ORDER register are stored in the stack at from the accumulator. Store the result in the
the address of the stack pointer less one. The content accumulator.
of the LOW ORDER register are stored at the address SBC A,B . . The contents of the B register and the carry flag (the C
of the stack pointer less two. flag in the F register) are subtracted from the contents
RES 0,() . . RESET BIT 0, 1, 2, 3, 4, 5, 6, 7 to the logic ZERO of the accumulator. The result is stored in the
conditon of the specified register. accumulator.
RET The unconditional RETURN instruction SCF . . . The carry flag (the C flag in the F register) is set to 1.
RET C . . . Return from the sub-routine if the carry flag in the F SET 0,( ) . Bit 0, etc at the memory location pointed to by the
register is true (1). contents of the register in ( ) is set to 1.
RET M . . . . The instruction will only be performed if the S flag (sign SET 0,B . . The indicated bit in the selected register is set to 1.
flag) is negative. SLA ( j . . SHIFT LEFT ARITHMETIC. Shift the contents of the
RET NC . . The instruction will only be performed if the NON- memory location pointed to by the contents of the
CARRY condition is present. i.e. the CARRY FLAG is register in ( ) one bit to the left, resettng the least
'0'. significant bit to 0.
RET NZ . . The instruction will only be performed if a NON-ZERO SLA A,B,etc Shift the contents of the specified register left one bit,
condition is satisfied. i.e. the ZERO FLAG is '0'. resetting the least significant bit to 0.
RET P . . . . The instruction will only be performed if the sign flag in SRA ( ) . . SHIFT RIGHT ARITHMETIC. Shift the contents of a
the F register is positive. i.e. S = 1. memory location pointed to by the contents of the
RET PE . . . The instruction will only be performed if the PARITY is register in ( ) to the right. The high-order bit is not
EVEN. This means the P/V flag is SET (1). altered. Bit 0 is shifted into the carry bit.
RET PO . . . The instruction will only performed if the PARITY is SRA A,B,etc Shift the contents of a register one bit to the right.
ODD. This means the P/V flag is reset (0). High-order bit is unchanged. Bit 0 is shifted into the
RET Z . . . . The instruction will only be performed if the ZERO flag carry bit.
is SET (1). SRL ( ) . . SHIFT RIGHT LOGICAL. The contents of the memory
RETI Return from INTERRUPT. location pointed to by the contents of the register in ( )
RETN . . . . Return from non-maskable INTERRUPT. are shifted to the right. Bit 7 is reset to 0. Bit 0 is
RI. ( ) . . . The content of the memory location contained in ( ) is shifted into the carry bit.
rotated to the left, through the carry bit. SRL A,B,etc The contents of the indicated register is shifted one bit
RI. A,B,C,etc . The contents of the register is rotated one bit position position to the right. Bit 7 is reset to 0. Bit 0 is shifted
to the left, through the carry bit. into the carry bit.
RLA This is a one-byte instruction of RI. A and rotates the SUB ( . . Subtract the contents of the memory location pointed
contents of the accumulator one bit position to the left, to by the contents of the register in ( ) from the
through the carry bit. accumulator.
RLC ( . . . The contents of a memory location pointed to by the SUB A,B,etc Subtract the contents of the specified register from the
contents of the location in ( ) is shifted one bit to the accumulator.
left but not through the carry. The C flag is set to the SUB dd . . Subtract immediate data from the accumulator.
original status of the register's least significant bit. XOR ( ) . Perform the Exclusive-OR operation on data pointed to
RLC A,B,etc . The contents of the indicated register is shifted one bit by the contents of the register in ( ) with the
position to the left. It does not shift through the carry accumulator.
bit but does set the C flag to the original status of the XOR A,B,etc Exclusive-OR the contents of the specified register
register's most significant bit. with the accumulator.
RLCA . . . . This is a one byte instruction of RLC A and operates as XOR dd . . Exclusive-OR the immediate data with the
above. accumulator.
ELECTRONICS NOTEBOOK 3 65