N-channel MOSFET I-V Characteristics

Electronic Devices Lab : Experiment 8

Department of Electrical Engineering

Indian Institute of Technology, Bombay

EE236 : Experiment 8 Dept. of EE, IIT-Bombay 1/13 1 / 13

Aim of the experiment

In this experiment, the following tasks need to be performed:

Obtain output and transfer characteristics of an N-channel enhancement type

MOSFET (also called NMOS).

Measure of trans-conductance and output resistance from the obtained

characteristics.

Investigate the effect of body bias on the characteristics of the NMOS.

EE236 : Experiment 8 Dept. of EE, IIT-Bombay 2/13 2 / 13

Background Information

The MOSFET is the commonly used transistor in both digital and analog
circuits.
It has four terminals- Gate (G), Drain (D), Source (S) and Body (B).
The device working principle is that the voltage applied between its gate and
source terminal controls the current through the source and drain terminals.
The body terminal of an PMOS is connected to the highest voltage in the
circuit i.e, VDD while that of an NMOS is connected to ground.

EE236 : Experiment 8 Dept. of EE, IIT-Bombay 3/13 3 / 13

Background Information

For an NMOS to be ”ON”, the applied gate-source voltage must be greater

than the threshold voltage i.e. VGS > VT . Otherwise it is said to be ”OFF”
(or in cut-off region).

Conditions for different operating regions of an NMOS that is turned on-

Linear Region : VDS < VGS − VT

Saturation Region : VDS ≥ VGS − VT

EE236 : Experiment 8 Dept. of EE, IIT-Bombay 4/13 4 / 13

Background Information
The NMOS current equation (in different regions):

ID ≈ 0 Cut-off region
 
W VDS
ID = µn Cox VDS VGS − VT − Linear region
L 2
1 W
ID ≈ µn Cox (VGS − VT )2 (1 + λVDS ) Saturation region
2 L

µn - mobility of charge carriers (electrons in NMOS)

Cox - per unit area capacitance between the gate and body
W , L - width and length of the channel respectively
λ - channel length modulation factor

The trans-conductance and the output resistance are respectively given by-

∂ID ∂VDS
gm = ro =
∂VGS const VDS ∂ID const VGS

EE236 : Experiment 8 Dept. of EE, IIT-Bombay 5/13 5 / 13

Components Necessary

ALD1106 NMOS IC
1k Potentiometer ×2
Breadboard and connecting wire
DC power supply

EE236 : Experiment 8 Dept. of EE, IIT-Bombay 6/13 6 / 13

ALD1106 NMOS

Figure: ALD1106 Pinout

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Part I : Transfer Characteristics (Linear)

Estimate the value of threshold voltage and trans-conductance in linear region:

Bias the transistor in linear region by keeping VDS = 200 mV .
Plot ID vs VGS characteristics by varying VGS from 0 to 3V .
From this characteristic, obtain VT and gm .

EE236 : Experiment 8 Dept. of EE, IIT-Bombay 8/13 8 / 13

Part I : Transfer Characteristics (Saturation)

Estimate the value of threshold voltage and trans-conductance in saturation

region:
Bias the transistor in saturation region by keeping VDS = 3V .
Plot ID vs VGS characteristics by varying VGS from 0 to 3V .
From this characteristic, obtain VT and gm .

EE236 : Experiment 8 Dept. of EE, IIT-Bombay 9/13 9 / 13

Part II : Drain Characteristics

For the drain characteristics, ID vs VDS must be plotted for multiple (3 different)
VGS values.
Measure ID vs VDS by varying VDS from 0 to 5V , while keeping VGS
constant at 1.5V .
Repeat the same for VGS = 2.5V and 3.5V .
Plot all the 3 characteristics in a single plot to observe the drain
characteristics.
Find the output resistance ro using the slope of the plot for VGS = 3.5V , in
saturation region.

EE236 : Experiment 8 Dept. of EE, IIT-Bombay 10/1310 / 13

Circuit for Part I and Part II

Figure: NMOS I-V circuit

EE236 : Experiment 8 Dept. of EE, IIT-Bombay 11/1311 / 13

Part III : Body Effect

Bias the transistor in linear region by keeping VDS = 200mV .

Repeat the step from Part I (linear) to get 3 more sets of ID vs VGS
characteristics for VSB = 1V , 2V and 3V .
Show all five ID vs VGS characteristics on the same plot.
Obtain the value of threshold voltage from each plot.
Plot VT vs VSB and obtain body effect coefficient (γ) using below equation.
p p

VT = VT 0 + γ ϕs + VSB − ϕs

Here, ϕs is Surface Potential = 0.9V and VT 0 is the threshold voltage when

VSB = 0V .

EE236 : Experiment 8 Dept. of EE, IIT-Bombay 12/1312 / 13

Circuit for Part III

Figure: NMOS Body effect circuit

EE236 : Experiment 8 Dept. of EE, IIT-Bombay 13/1313 / 13