Logic and Computer Design

Fundamentals 5th Edition Mano

Solutions Manual
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 Problem Solutions – Chapter 7

CHAPTER 7
© 2016 Pearson Education, Inc.

7-1.*
a) A  16, D  8 b) A  19, D  32 c) A  26, D  64 d) A  31, D  1

7-2.
a) (835)10  (11 0100 0011)2 , (15, 103)10  (00111010 1111 1111)2
b) (513)10 = (10 0000 0001)2, (44,252)10 = (1010 1100 1101 1100)2

7-3.*
Number of bits in array =  216  24  220  210  210
Row Decoder size = 210
a) Row Decoder = 10 to 1024, AND gates  210  1024 (assumes 1 level of gates with 10 inputs/gate)
Column Decoder = 6 to 64, AND gates = 26 = 64 (assumes 1 level of gates with 6 inputs/gate)

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Total AND gates required = 1024 + 64 =1088

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b) (32000)10  (0111110100 000000)2 , Row  500, Column  0
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a) Number of RAM cell arrays  8 (2G  231 ) / (214  214  228 )  (23  8)
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a) Number of RAM cell array s = 8(2G = 231)/(214 x 214 = 228) = (23 = 8)

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Each line is connected to the respective array decoder enable

7-5.
15 row pins + 14 column pins  229  512 M addresses

7-6.
With 4-bit data, the RAM cell array contains 232/22 = 230 words.
The number of address pins is 30/2 = 15.

7-7.
Interval between refreshes = 64ms/8192 = 7.8125 μs
Using the 60 ns refresh time from the text example, total time for refresh = 8192 × 60 ns = 0.49 ms
Minimum number of pins = 13

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently
exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Problem Solutions – Chapter 7

7-8.*
a) 2 MB/128 K × 16 = 2MB/ 256 KB = 8 b) With 2 byte/word, 2MB/2 B  220 , Add Bits = 20
128K addresses per chip implies 17 address bits. c) 3 address lines to decoder, decoder is 3-to-8-line

7-9.

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7-10.
An SDRAM simultaneously reads the desired row and stores all of the information in the I/O
logic. Next the desired column is read from the I/O logic and the data appears on the output.
During burst transfers, the subsequent data words are read from the I/O logic and placed on the
output. This occurs for the predetermined number of words known as the burst length. For burst
transfers, this is faster since the row has already been pre-read.

7-11.
A DDR SDRAM uses both the positive and negative edges of the clock to transfer data. This
allows the DRAM to transfer twice as much data while keeping the same clock frequency.

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently
exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.