EC3091D - Electronic Circuits Lab II

7
Experiment-6:Class AB Push Pull Power Amplifier

Aim:
1. To design and set up a Class AB Push Pull Power Amplifier to deliver a maximum ac power of 1W
to a load of 10Ω
2. To test the performance of the amplifier by appropriate measurements.
Circuit Diagram

Procedure
1. Design and set up the circuit in the figure 1 without diodes to get class B circuit (short the bases of
two transistors).
2. Apply a 2V peak sinusoidal signal of frequency 5kHz and observe the cross over distortion in the
output signal.
3. Find the signal amplitude at which the output gets clipped.
4. Design and set up the circuit in the figure 1(the class AB circuit).
5. Apply a 2V peak sinusoidal signal of frequency 5kHz and observe the output signal.
6. Measure the maximum ac output power.
7. Calculate the conversion efficiency η.
8. Connect a variable load and plot output power Vs RL .
9. Now connect a resistance of 2kΩ(RS ) series with signal source and measure the output power delivered
to 10Ω load resistor.(Amplitude of signal voltage same as in step 6).
10. Design and set up the circuit in the figure 2.Adjust CE for the required voltage gain.
11. Do the power output measurement as in step 9 (without output clipping).
12. Connect a 8Ω speaker to the signal source directly and hear the audio output.
13. Now remove RL and connect the 8Ω speaker as the load of amplifier and hear the audio output and
feel the effect of power amplifier.
Design:
Circuit in fig.1
1. Check the data sheet of the power transistor ICs (available in lab) to find its large signal parameters
and other electrical characteristics.
2
VCC
2. Design the value of VCC from the relationship PL(max) = 8RL

3. Take the current I through the biasing network to be 2mA. (This order of current will ensure the
diodes are on and drop across each of them is approximately 0.7V .
4. Calculate R using the relationship VCC = 2IR + 2VBE (Assume the two transistors are just at cut in
so that IC ≈ 0)
5. Take CC1 and CC2 such that at the operating frequency , the magnitude of impedance due to CC1
and CC2 are negligible.
Circuit in fig.2
1. Take Q3 as BC547B.

1
 2
VCC
2. Design the value of VCC from the relationship PL(max) = 8RL
3. Take the current IC3 to be 2mA.
4. Design the driver stage with Q3 as an inverting amplifier of gain 5, with maximum output swing.
5. Take CC1 ,CC2 and CE such that at the operating frequency , the magnitude of impedance due to
these capacitors are negligible.