A Fast Scrubbing Method Based on Triple Modular Redundancy for
SRAM-Based FPGAs
Rong-Sheng Zhang, Li-Yi Xiao*, Xue-Bing Cao, Jie Li, Jia-Qiang Li, and Lin-Zhe Li
Microelectronics Center, Harbin Institute of Technology, Harbin 150001, China
* Email: xiaoly@hit.edu.cn
Abstract
In recent years, SRAM-based FPGAs (Field
Programmable Gate Arrays) have been popular in space
applications because of their high speed and
reconfigurability. The specific structure cell SRAM
(Static Random Access Memory) not only speed up the
user design but also speed up the configuration and
reconfiguration. However, SRAM is very sensitive to the
space particles that can change the value stored in
SRAM. For improving the reliability of user design in
SRAM-based FPGA, this paper proposes a scrubbing
method based on TMR (Triple Modular Redundancy) for
SRAM-based FPGAs. This method improves the
reliability of TMR design by reducing the possibility of
SEUs accumulation. We test the proposed scrubbing
method through fault injection and the experimental
results indicate the proposed scrubbing method can
improve the reliability of TMR design in SRAM-based
FPGAs.
Keywords: SRAM-based FPGAs, reliability, scrubbing,
fault injection.
1. Introduction
FPGAs become more and more popular because they can
be configured flexibly. Especially for SRAM-based
FPGAs, they can be configured many times in a very
short time. However, there is a problem if SRAM-based
FPGAs are used in space applications. That is the
memory cells in SRAM-based FPGAs are very sensitive
to SEU (Single Event Upset) which restricts the
application of SRAM-based FPGAs [1, 2].
The SEU effects in SRAM-based FPGAs are different
from ASIC (Application Specific Integrated Circuit) [3].
Configuration memory is an important part in
SRAM-based FPGAs that controls the function of
FPGAs. If SEU occurs in configuration memory, the
function of user design may change permanently, unless
the FPGA is reconfigured. Therefore, it is important to
design some fault tolerant techniques to improve the
reliability of SRAM-based FPGAs in space applications.
Redundancy technique is the most common fault tolerant
technique that contains hardware redundancy and time
redundancy. One representative redundancy technique is
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TMR technique. The user design is designed into three
identical circuits and a majority voter as shown in figure
1. TMR is suitable for SRAM-based FPGAs too. If SEU
occurs in FPGA, one incorrect redundancy circuit cannot
change the final correct output. TMR technique belongs
to the SEU mitigation technique.
Module 1
INPUT OUTPUT
Module 2 Voter
Module 3
Figure 1. The TMR scheme
Obviously, TMR technique has some disadvantages. The
three identical circuits must lead to the increase of area
and power consumption [4]. The majority voter is the
key of TMR technique. If SEU occurs in the majority
voter, the function of majority voter may change. The
incorrect majority voter will lead to incorrect output of
TMR.
For SRAM-based FPGAs, TMR technique has a
non-negligible problem. That is the accumulation of
SEUs in FPGA. Usually, the configuration memory will
not change after the configuring of SRAM-based FPGA.
If SEU occurs, it will remain in the FPGA. When two or
three redundancy circuits of TMR are wrong, the
majority voter will give the incorrect output. Therefore,
it is necessary to repair the SEUs in configuration
memory at intervals to ensure the correct running of
TMR design.
Scrubbing is a very effective method to resolve the
accumulation of SEUs in configuration memory.
Scrubbing belongs to the SEU recovery technique.
Scrubbing can be divided into two types, blind scrubbing
and detecting scrubbing [5]. Blind Scrubbing is a simple
method to repair the SEUs in configuration memory by
reload the original correct frames into the configuration
memory at set intervals. The scrubbing rate of blind
scrubbing is the key problem because it is restricted by
the configuration clock frequency and the size of
configuration memory. Detecting scrubbing repairs the
SEUs in configuration memory by readback of the
bitstream, detecting an upset and reloading the original
correct frames.
The combination of detecting scrubbing and ECC (Error
Correction Code) is an effective scrubbing method. The
advantage of this method is decreasing the area
consumption because it omits the large storage space to
store the original correct frames [6, 7].
For SRAM-based FPGAs, only TMR technique or
scrubbing method is not enough to ensure the reliability
of user design. It is a good choice that combining the
TMR technique and scrubbing method. In order to
combine the TMR technique and scrubbing method more
effectively, this paper proposes a scrubbing method
based on TMR which can fast repair the SEUs in TMR
design.
voter identifies an error module, the scrubbing address
controller turn into the error mode that the scrubbing
frame addresses transform into the region of the error
module. When completing the scrubbing of the error
module region, the scrubbing address controller turn into
the normal mode. The three identical modules are routed
in advance. The proposed scrubbing execution is
performed through the scrubbing algorithm illustrated in
figure 3.
FPGA
Scrubber
FSM
Decoder of
FRAME_ECC

2. The proposed scrubbing method

Scrubbing
According to the type of configuration port, scrubbing address Majority voter
can be divided into two types, external scrubbing and controller
internal scrubbing. External scrubbing reload the correct
frames by using external configuration port, such as
SelectMAP. Internal scrubbing reload the correct frames
by using internal configuration port ICAP (Internal Module 1 Module 2 Module 3
Configuration Access Port). This paper adopts the
internal scrubbing method because the speed of internal User design
scrubbing is faster than the speed of external scrubbing
and all designs can be designed in one FPGA. Figure 2. The scheme of scrubbing platform
This paper adopts the method that combining the
detecting scrubbing and ECC. FRAME_ECC is the /* Initialization */
internal Xilinx logic that can detect single or double scrub_initialization();
/* Normal mode scrubbing */
SEUs in configuration memory. The FRAME_ECC logic while(1)
can calculate the syndrome value according to the bits in {
scrub_current_frame(frame_address);
one frame including the ECC bits. When read the frames if(majority voter error)
from the configuration memory, we can confirm whether {
goto scrub_error_mode();
an SEU occurs according to the syndrome value. This }
method do not need any additional storage space because else
{
we do not need to store the original correct frames. frame_address = next_normal_mode_frame_address;
}
The entire scrubbing platform composes of scrubber and }
user design, as shown in figure 2. The FSM (Finite State /* Error mode scrubbing */
scrub_error_mode()
Machine) is the core of scrubber that controls the {
readback and rewrite of the scrubbing. The function of frame_address = fisrt_error_module_frame_address;
while(1)
decoder of FRAME_ECC is to decode the {
FRAME_ECC logic. The scrubbing address controller scrub_current_frame(frame_address);
if(error repaired or frame_address == last_error_module_frame_address)
controls the scrubbing frames address according to the {
output of majority voter. frame_address = next_normal_mode_frame_address;
goto scrub_current_frame(frame_address);
Usually, scrubber and user design do not need any }
else
interconnection. But in this paper, we put the majority {
voter and the scrubber together. The majority voter is frame_address = next_error_module_frame_address;
}
optimized that not only can filter the output of error }
module but also can identify which module is wrong. }

When FPGA starts, the scrubber is running. The

scrubbing address controller has two modes, normal Figure 3. The scrubbing algorithm
mode and error mode. In normal mode, the scrubbing
frame addresses are ergodic in sequence. If majority 3. Test for proposed scrubbing method

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This paper adopts the fault injection technique to verify
the proposed scrubbing method. This is because fault
injection is a fast and effective evaluation method [8].
Our fault injection tool uses ICAP too. When fault
injection runs, the scrubbing will pause. Until the SEU is
injected, the scrubbing continues to run.
There is an important factor that may influence the
experimental results. That is the interval between each
injected SEU. Firstly, it is necessary to make the interval
random. Secondly, the length of the interval cannot be
too long or too short. The long interval will bring the
large time consumption and the short interval cannot
show the randomness that will influence the
experimental results. We consider that 1-5 times length
of entire frames is appropriate.
Another important factor is the injected frame address. It
is necessary to make the injected frame addresses
uniform random. Therefore, we design a fault injection
address generator that can generate the effective uniform
random addresses in real time [9]. Real-time effective
addresses can speed up the fault injection flow because it
can save the time of waiting for the effective addresses.
The fault injection tool not only can inject an SEU, but
also can repair the current injected SEU. If the injected
SEU changes the function of one or more modules, the
SEU is a critical SEU. If not, it is not a critical SEU. If
the injected SEU is not a critical SEU, it will be repaired
by the fault injection tool, because the repairing time
does not influence the experimental result.
4. Experimental results
We test the proposed scrubbing method in
XC6VLX240T Virtex-6 FPGA of ML605 evaluation
board. Two of ISCAS85 benchmark circuits are chose
for the user designs, c7552 and c6288. The input vectors
are generated by an ATPG (Automatic Test Pattern
Generation) tool named atalanta to meet the high fault
coverage rate.
If an SEU is a critical SEU, the SEU is regarded as an
error. In this paper, we test the average scrubbing frames
of repairing an error. We implement experiment a large
number of times to improve the accuracy of
experimental results. The experimental data is illustrated
in table 1.
Table 1. The experimental data
user average scrubbing frames of repairing an error
design normal scrubbing proposed scrubbing
c7552 10772 2445
c6288 10834 1179
This paper tests two scrubbing methods, normal
scrubbing and the proposed scrubbing. The frames of
normal scrubbing method are ergodic. From table 1, the
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proposed scrubbing method has a higher speed to repair
the accumulation of SEUs in TMR design. Because the
existential time of SEU in TMR design decreases, the
reliability of TMR design in SRAM-base FPGAs is
improved.
5. Conclusion
Because SRAM-based FPGAs are sensitive to SEU, it is
necessary to design some tolerant techniques if the
FPGAs are used in space application. The combination
of TMR technique and scrubbing is a good choice. This
paper proposes a scrubbing method that can faster repair
the SEUs in TMR design. That is, the proposed
scrubbing method can improve the reliability of TMR
design in SRAM-based FPGAs.
Acknowledgments
This work was supported by the Fundamental Research
Funds for the Central Universities (Grant
No.HIT.KISTP.201404), Harbin science and innovation
research special fund (2015RAXXJ003), and Special
fund for development of Shenzhen strategic emerging
industries (JCYJ20150625142543456).
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