Journal of Electronic Testing

https://doi.org/10.1007/s10836-018-5717-x

Handling Unknown with Blend of Scan and Scan Compression

Pralhadrao V. Shantagiri 1 & Rohit Kapur 2

Received: 15 November 2017 / Accepted: 7 March 2018

# Springer Science+Business Media, LLC, part of Springer Nature 2018

Abstract
In scan compression, all scannable Flip-Flops are part of internal scan channels connected between Decompressor and
Compressor. The capture-X (unknown values in the test response) in the Flip-Flops after capture cycle of scan
synthesis, results in loss of coverage and/or pattern inflation when masking is used to block the Xs irrespective of
the X-masking techniques used in scan compression. In this paper, we exploited this potential and propose a hybrid
DFT (Design For Testability) architecture to achieve better compression and reduce patterns count. This is a mixture of
an external scan chain and scan compression. A methodology has been put in place based on the potential of a
capture-X value of occurring in Flip-Flips, to find out which Flip-Flops (scan cells) should be part of the internal
scan channels (chains) between Decompressor and Compressor, and which Flip-Flops should be put outside the codec
(Compressor-Decompressor) as an external scan chain. The results show the benefits of the hybrid architecture which
is shown to bring significant improvement in pattern count.

Keywords ATPG . DFT . Hybrid scan . Scan compression . X-chain . X-masking

1 Introduction contentions or tri-state buffers, generating patterns pulsing multi-

Scan Compression has alleviated the problems of the test
application time and test data volume issues seen in scan
testing. By inserting decompression logic between the
scan-ins and the scan chains few inputs are used to sup-
ply test data to a large number of scan chains.
Compression logic between the scan chains and the
scan-outputs allows for all the values in the Flip-Flops
to be observed on the test equipment. The biggest chal-
lenge in scan compression, is the ability to handle un-
knowns (Xs) in the test response without having to in-
crease the number of patterns for equivalent fault cover-
age or to prevent a loss of fault coverage.
X’s come from many sources: un-initialized RAMs are a com-
mon source of X’s. These embedded memories are typically
bounded by wrapper scan chains which capture the unknown
values. False Path, Multi-cycle paths, Tri-state buses or bus
Responsible Editor: N. A. Touba
* Pralhadrao V. Shantagiri
gpralhadrao@gmail.com
1
Department of Computer Science, Jain University, Bengaluru, India
2
Research Guide, Jain University, Bengaluru, India
ple clocks of interacting clock domains to detect maximum faults
per pattern, unmodeled blocks such as analog or mixed signal,
multi-domain interactions, black boxed modules, limitation in ac-
curacy of simulation are sources of unknowns in a design under
test [1–5, 7–9, 11–13, 17–30, 33, 34, 36–38, 40, 42, 44–50]. The
X effect is further exacerbated in high compression
implementations where the value in a Flip-Flop combines with
many other values in the compressor.
Scan compression techniques employ different ways to han-
dle capture-X values present in the scan cell. These capture-X
values affect the observability by corrupting the final test re-
sponse as it is brought together by the compressor [6, 28, 48].
Different EDA (Electronic Design Automation) vendor tools use
different techniques to handle the X-profile in the scan chain.
There are three types of compactors: space compactors,
time compactors and hybrid space-time compactors. The
different X-handling techniques used in these different
scan compression technologies have been described below:
1.1 X-Bounding or X-Blocking
In this technique, capture-Xs are blocked from reaching the
scan cell of the scan channel. Proposed in [40, 41], X-
bounding or X-blocking was to eliminate the sources of
capture-X values by modifying the Design Under Test

(DUT). This prevents propagation of capture-Xs to scan
cells by adding DFT logic and avoids creation of capture-
X value by forcing capture-X sources to 0 or 1 using a
control point [40–43]. The addition of DFT logic, adds
up to increased design area and may result in functional
timing issues. The X-block method in [43] falls under this
category, requiring simpler test logic and less control data.
The LFSR (Linear-Feedback Shift Register) re-seeding
technique of [42] also blocks capture-Xs from reaching
the scan cell. The method in [22], masks capture-X value
reaching scan cell by reseeding of the LFSR while ensuring
faults’ effects to propagate. The unknowns can also be
blocked by inserting test points [17]. But these techniques,
using scan compaction neither blocks nor removes all un-
knowns reaching scan cell completely during testing.
1.2 X-Masking
X-Masking is the popular technique used in all scan com-
pression schemes provided by EDA. This method allows to
mask capture-Xs at the input to response compactor with-
out modifying the DUT. The masking of the whole internal
scan channel or slice of an internal scan channels or chain
output at specified clock cycles are addressed in this meth-
od. The X-Masking is done by adding DFT logic to the
output response compactor between internal scan channel
and compactor. These mask bits are controlled through
control bits [8]. These control bits are run from tester chan-
nels to decide when to mask scan chain or slice or scan cell
at specified clock cycle. During the X-Masking process,
good values (0 or 1) also get masked, impacting pattern
inflation, coverage and observability loss [6, 28, 48].
Masking of selected unload capture-Xs by adding DFT
circuitry is shown in OPMISR [1, 2] and making sure not
reaching compactor. The combinational compactor with
small MISR (Multiple-Input Signature Register) is used
in between internal scan channel output and compactor
inputs with improved test time is shown in [44]. Static
X-chain partitioning within codec, with better compres-
sion and reduced test application time and cost is shown
in [5]. The limited Xs with aggressive multiple clocking
exhibited more observability than pulsing single clock at
time in the ATPG (Automatic Test Pattern Generator) [3].
The interval-based mask analysis presented in [4] shows
high X-tolerance achieved. The formation of separate in-
ternal X-chains from a set of internal scan channels pres-
ent between codec to improve observability and reduce
pattern inflation is shown in [47] is the motivation for this
work.
Many techniques have been published for designing X-
Masking DFT Logic and reduced mask data requirement in
scan compression [7, 21, 23–26, 30, 33, 34, 37, 45, 46, 48].
J Electron Test
1.3 Tolerant / X-Canceling
X-Canceling MISR is useful when there is a low density
of unknowns present in the scan chains, requiring less
number of control bits compared to X-Masking tech-
niques. The X-tolerant hybrid compaction methods of
both time and space are shown in [12, 27, 28]. These
compactors consider value, shifting out of internal scan
channels (I) in a finite number of shift-out cycles (C) into
observable compacted test response at (O) outputs, where
I > O. Much higher compaction ratio can be achieved in
convolution compaction schemes. The convolutional com-
pactors are best suited for X-tolerance [27].
Handling of simultaneous errors and Xs coming from a
set of internal scan channels in XOR (Exclusive-OR) trees
response compactor is shown in X-compact [18, 19].
MISR based compactors are worse than XOR based com-
pactors in handling of capture-Xs. Hence, addition of
DFT logic is required to handle them [20]. The masking
logic inserted between internal scan channels output and
response compactor inputs, is shown in Fig. 1. Couple of
hybrid unload compactors use Steiner Triple System [9],
which support 2 unknowns per shift without affecting the
observability of any other internal scan channel in the
codec.
Several methods of X-Tolerant compactions have been de-
signed and shown in [11, 13, 16, 29, 36, 38, 49, 50].
1.4 X-Impact
X-Impact technique handles capture-Xs on space compactors
algorithmically using ATPG and without adding any extra
DFT logic [39].
1.5 X-Filtering
The X-Filtering scheme proposed in [32], cancel out
capture-Xs from response compactor by means of error
correcting codes (ECC), while retaining correction and
detection capabilities. The X-filtering logic needs inputs
from ATE (Automated Test Equipment), every clock cycle
[32]. Another X-Filtering scheme is toggle-masking,
which is used to mask consecutive bits of capture-Xs at
the output of all scan chains [31].
1.6 Hybrid Methods (Combination of X-Masking
and X-Canceling)
X-Masking method stops the capture-X’s from reaching
response compactor and X-canceling cancels the capture-
X’s using selective XORing at response compactor. The
hybrid method of X-Masking and X-canceling need more
J Electron Test
Fig. 1 Compression architecture
showing masking with MISR
re-usable control bits to remove X’s from signature with-
out loosing fault coverage and improved test time [14].
Our research is about the trade-off between scan and
scan compression having X-chains partitions within codec
or part of an external scan chain. Every Flip-Flop (FF)
need not be part of scan compression architecture. We pro-
pose the hybrid DFT architecture which is a blend of scan
and scan compression. While the concepts we discuss are
independent of the compression scheme, we use the
DFTMAX Ultra technology for our experiments. The FFs
having capture-X are put into an external chain and other
FFs into the internal scan channels between Compressor
and Decompressor (codec). This external scan chain is re-
ferred as external X-Chain or scan X-Chain. While the X-
chains are no longer between the Decompressor and
Compressor the compression scheme still needs masking
as not all the X’s are removed from the internal scan
chains. The proposed hybrid DFT architecture trades-off
I/O bandwidth to the scan compression scheme with the
usage of masking to block Xs within the codec.
Furthermore, removing scan chains from within a codec
is beneficial from a congestion perspective. The trade-off
of our implementation is best seen in Fig. 2, some of the
scan inputs and outputs (Si_16, So_16) are used to supply
scan data to external scan X-chain, while others (Si_1–15,
So_1–15) are used to supply and observe compressed data
of a compression architecture.
In Section 2, we explain the X-Chain partitioning in
adaptive scan compression which we used in our experi-
ment as base. It includes architecture of X-Chains parti-
tion within codec with high x-tolerant support [5]. In
Section 3, we discuss the proposed research, analytics to
form an external X-chain and scan compression.
Specifically in Section 3.1, we have shown the formula
to find length of an external X-Chain. In Section 3.2, we
have shown the probability of capture-X Flip-Flop occur-
rence in unload pattern and probability calculation for
each scan cell. The details about unload patterns analysis
with respect to capture-X is done in Section 3.3. Section 4
explains the algorithm which is used to determine Flip-
Flops to be part of an external X-chain or codec. Finally,
we present the results, and conclusion of our work.
2 X-Chain Partitioning in Scalable Adaptive
Scan
Motivation for the proposed hybrid DFT architecture is a
blend of scan and scan compression which is based on
Scalable Adaptive Scan architecture presented in [5, 6].
The Scalable Adaptive scan with X-chain partitioning is
described below:
It is observed that, scan cells capturing X do not
capture stuck-at, transition or any other faults. So it is
better to avoid observing such cells at the output [5],
otherwise they increase pattern inflation and test time
and lead to increased test cost. Figure 3 shows the
capture-X distribution in the industrial design and these
capture-Xs are distributed randomly in the internal scan
channels. Masking and observation of such cells were
done accordingly. This distribution of capture-Xs ran-
domly, leads to reduced observability of faults, as
known values (0 and 1) observation also got impacted
and resulted into fault coverage loss [5]. When X-cells
are grouped separately, there will be an impact on
routing, but the impact is small and can be ignored.
 J Electron Test

Fig. 2 Blend of Scan and Scan

compression architecture having
multiple Scan input and output
ports of DFTMax-Ultra. External
chain with X-Cells

The capture-X values are created from a different X-
Profile, as depicted in Section 1.
In X-tolerant adaptive scan compression architecture in-
ternal scan channels are partitioned based on the capture-X
value and non-unknown values. To find out capture-X
cells, the design rule checking method is used in [5]. The
structures producing Xs and scan cells to which it is being
propagated, have been identified by analyzing the test pat-
terns and structural tracing.
All X-cells were grouped together to form X-chains
within the codec of Scalable Adaptive Scan [6] without
mixing them with non-X scan cells chains. As scalable adap-
tive scan doesn’t support chains having only scan-in, separate
scan out for these chains was considered to avoid loss of

Fig. 3 Distribution of static Xs in

an industrial circuits [5]
J Electron Test
observability. The masking control bits are fed to masking
block accordingly. The X-chains in scalable adaptive scan
have been shown in the Fig. 4.
The disadvantage of this method is: as X-chains are
partitioned within the codec, it still needs masking and
separate output to observe. The additional X-chains with-
in the codec leads to more fan-out from external port to
internal scan channels at decompressor and leads to more
congestion and routing. Adaptive scan compression feeds
the same value to multiple internal scan channels for bet-
ter compression, leading to more patterns generation com-
pared to scan. Separate scan-out for X-chains also adds to
pattern inflation to some extent.
Hence, to avoid these problems, we propose hybrid DFT
architecture which is blend of scan and scan compression to
handle capture-Xs in the design. We pick up scan cells,
capturing X value, based on probability calculation of oc-
currence of capture-X in unload pattern is sown in
Section 3.2. The highest probability of capturing X’s cells
will be picked (based on patterns/ design rule checking
/assume scan) and put into an external chain. But these scan
cells also might capture other value with less probability.
3 Architectural Considerations with FF
Compressability
The existing adaptive scan compression techniques re-
quire high test cost, test time and pattern inflation
Fig. 4 Partitioning the chains into
static X capturing and non-static
X capturing chains. A masking
scheme implemented to match the
x-chains [5]
(a)
because of higher compression ratio demand. This hap-
pens because of a low number of interface input ports
being connected to multiple internal scan channels in
the scan compression. The adaptive scan compression
feeds the same value to multiple internal scan channels
connected between decompressor and compressor. This
leads to more pattern inflation to detect faults. Hence,
more capture-X values in scan cells lead to loss of
coverage and pattern inflation. The internal scan chan-
nels having capture-X FFs have negative impact on the
observability of good responses that come together in
the compressor [15]. The internal scan channel(s) hav-
ing capture-Xs need(s) masking and separate output to
observe. When outputs of the many internal scan chan-
nels are brought together through logic to fewer observ-
able outputs the capture-Xs in the response compactor
kill the fault detection ability in scan cells that are part
of X-chains between Decompressor and Compressor [4].
The X-chains between Decompressor and Compressor
leads to more fan-out from external port to internal scan
channels at Decompressor and leads to more congestion
and routing [6].
To overcome these disadvantages, we propose hybrid
DFT architecture which includes an algorithm to reduce
patterns inflation by pulling Flip-Flops with capture-Xs
having higher probability of occurrence in unload pattern
is shown in Table 1. More details about probability of
capture-X cells is described in Section 3.2. The proposed
hybrid DFT architecture is shown in Fig. 2. The external
(b) (c)
 J Electron Test

Table 1 Showing probability

calculations for each scan cell in FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 FF9 FF10
the scan chain based on unload
patterns P1 H H H H H H H M L M
P2 M L M H L M L M M M
P3 L M L H L H M M H L
P4 H H L L L H M M M M
P5 H L H H M L L M L M
P6 L M M H M M H M M M
P7 H L H L H M M M M M
P8 H H M L H L M M H M
P9 H L H H H L H M M M
OESC 1 2 3 0 2 3 4 9 5 8
Prob_X-Cell 0.11 0.22 0.33 0 0.22 0.33 0.44 1 0.56 0.89

The 'M' represents capture-X

X-chain is created by embedding these Flip-Flops into an steps:, DFT Configuration, Scan Synthesis and Generate
external chain. This helps to avoid masking for these Protocol File and Scan inserted design can be replaced
Flip-Flops and killing fault detection ability in X-chain. by Assume scan or design rule checking to get the list
The proposed hybrid DFT architecture also helps to re- of Flip-Flops having static capture-X. The ATPG pat-
duce pattern count and improves coverage as no masking terns generated for scan chains are then analyzed to
is required for an external scan chain. It also reduces determine if the FF is to be part of the scan (external
congestion and routing. The proposed hybrid DFT archi- chain) or scan compression in our hybrid DFT architec-
tecture doesn’t add extra overhead in the DUT. The FFs ture. Each bit of the pattern represent Flip-Flip of a
that are to be scanned remain scanned. The trade-off is in scan chain.
the use of the scan terminals (ports) for compression and The proposed hybrid DFT architecture is a blend of
scan. Since the total scan-ins and scan-outs remain the scan and scan compression architecture, which is
same and there is no additional overhead to a scan com- depicted in this section and proposed algorithm to select
pression scheme where all the chains are embedded with- Flip-Flips to be embedded into an external X-chain is
in the codec. depicted in Section 4. The length of an external X-
The total scan-ins (input ports) and scan-outs (output
ports) budget of adaptive scan compression is reduced by
one, as we need to allocate just one scan input and out-
put port to an external X-chain. Hence, scan-ins and
scan-outs port budget for scan architecture remains the
same before and after applying proposed hybrid DFT
architecture.
Many hybrid unload compactors use Steiner Triple
System [9], which supports 2 capture-Xs per shift with-
out affecting the observability of any other internal scan
channel in the codec. In our proposed hybrid DFT ar-
chitecture, we put these capture Xs into separate exter-
nal chain and hence there is no need of masking and
helps to overcome the limitation of Steiner Triple sys-
tem in the external X-chain.
The proposed algorithm analyzes a sample or all pat-
terns created in a way where the values are determined
in the Flip-Flops without having to worry about the
usability of the patterns. This can be achieved by run-
ning ATPG in a assumed scan approach or design rule
checking, or by actually inserting scan and creating the
test patterns. The flow of execution of the proposed Fig. 5 Showing flow of DFT Synthesis and pattern generation for pre and
approach is depicted in Fig. 5. In Fig. 5, the first three post external chain insertion
J Electron Test
chain calculation has been shown in Section 3.1. The
formation of external chain process will take into ac-
count the length of the chain as shown in Section 3.1.
The Flip-Flops embed into an external X-chain and are
excluded from adaptive scan compression technique.
The two phase method is used to implement proposed
method. The scan synthesis of design based on DFT
configuration to insert test logic is carried out and then
test patterns are generated. In the next phase, unload
patterns are analyzed for captured-X values as per the
algorithm provided in Section 4. Then formation of an
external X-chain happens based on Table 1. The calcula-
tion of a length of an external chain, probability of FF
having capture-X occurrence calculation and pattern
analysis are done in the following sub-sections. Once
the external chain is formed, again scan synthesis of
SerLength ¼ size of the load serializer register in Decompressor of codec
IntChainMaxLen ¼ size of longest internal scan channel embedded between Decompressor and Compressor
ExtChainLen ¼ SerLength þ IntChainMaxLen
The value of SerLength can be found in StreamingStructure
block of protocol file. The length of each internal scan channel
is also available in the ScanStructure block of protocol file. The
longest internal scan channel BIntChainMaxLen^ between
Decompressor and Compressor is obtained from protocol file
generated for the compression mode by DFTMax-Ultra tool of
Synopsys Inc. after scan synthesis.
3.2 Probability of Capture-X Flip-Flop Occurrence
Calculation in Unload Pattern
The test patterns for the scan architecture are generated
using the ATPG tool named Tetramax [10]. Each and
every unload pattern is mapped to scan chain. Each bit
of unload pattern is mapped to scan cell in the corre-
sponding scan chain. The proposed hybrid DFT archi-
tecture is based on the probability analysis of capture-X
cells present in the design. The analysis of probability
of occurrence of each capture-X scan cells in the scan
chain is determined based on the unload patterns gener-
ated. The occurrence of capture-X cell in the unload
patterns is represented as BOESC^. The total number
of patterns generated is represented as BTotPat^.
OESC ¼ occurrence of a capture‐X for a scan cell in the design
TotPat ¼ total number of patterns generated
Prob: X‐Cell ¼ OESC=TotPat
Probability occurrence of each X-cell is calculated and
arranged in descending order based on the probability
design is carried out. This mixture of external scan chain
and scan compression is called hybrid DFT architecture
which is proposed in this research. The patterns are gen-
erated for hybrid DFT architecture using ATPG tool.
3.1 Deciding Length of an External X-Chain
The length of an external scan chain is based on two
parameters: length of load serializer register and length
of longest internal scan channel (chain) in the codec.
Let us consider BSerLength^ as length of the load
serializer and BIntChainMaxLen^ as length of longest
internal scan channel between Decompressor and
Compressor. The summation of BSerLength^ and
BIntChainMaxLen^ gives the size of external X-chain.
value. The probability value ranges from 0 to 1. Same
has been illustrated in Section 3.3.
3.3 Patterns Analysis
This algorithm is based on captured-X value of Flip-
Flops. There are two types of capture-X’s: static-Xs
[3, 5] and Dynamic-Xs [3, 5]. If captured value in scan
cell is always ‘X’ through functional logic, then it is
static-X. If the captured value is boolean (0 or 1) and
some times capture-X, then it is dynamic-X. In [3, 5]
capture ‘X’ cells are put within codec as part of internal
scan channel at the beginning and have special masking
to avoid coverage loss. This is shown in Fig. 6. In the
proposed hybrid DFT method, we pull the scan flip-
flops that meet the criteria out of the codec and put
them into an external X-chain, simultaneously we re-
duce one scan-in and scan-out port from the scan-ins
and scan-outs port budget of scan compression architec-
ture. This scan-in and scan-out port is assigned to an
external X-chain. This ensures that the total allocated
scan-ins and scan-outs port budget remains the same.
In this method, we analyze capture-X scan cells (FFs)
in the scan chain using the test patterns generated in the
scan mode. Each and every FF in the scan chain, has
capture-X occurrence probability value range from 0 to
1 in the unload patterns. The probability of occurrence
of capture-X (Prob_X-cell in Section 3.2) for each Flip-
Flop is calculated as shown in the representative
Table 1. The value ‘L’, ‘H’ and ‘M’ represents ‘0’, ‘1’
 J Electron Test

Fig. 6 Scan compression

architecture DFTMax-Ultra with
X-chains inside the codec

and ‘X’ respectively. The FF1 to F10 represent repre-
sentative scan cell in the scan chain. The P1 to P9
represent representative patterns.
The representative Table 1 shows the probability of
capture-X for each scan flip-flop in the scan chain. These
FFs are arranged in descending order based on the proba-
bility value of capture-X of each FF. The ordered FFs of
scan chain are shown in representative Table 2.
Suppose BExtChainLen^ is 6, then we pick 6 FFs from
the representative Table 2. These cells can be F8, FF10,
FF9, FF7, FF3 and FF6. The algorithm to choose scan cells
for an external X-chain has been described in Section 4.
4 Algorithms to Determine
the Compressability of a FF
The external chain can be formed based on the scan
cells having captured-X value present in the unload pat-
terns. This decision is made based on the occurrence of
capture-Xs for a scan cell in the unload patterns. The
probability of occurrence of a scan cell having capture-
X in unload patterns is calculated as per the data shown
in representative Table 1 and method described in
Section 3. The algorithm for the same has been depicted
in this section.
4.1 External X-Chain Based on Highest Occurrence
of Weighted Random Patterns of Capture X’s
in the Unload Patterns
In this algorithm, an external X-chain is formed based
on the FFs having highest probability of captured-X’s in
the output/unload patterns. The number of FFs being
embedded into an external X-chain is equal to the
BExtChainLen^.
The capture-X FFs can be obtained from patterns
generated by ATPG or from ‘Assume scan’ or from
Pre-DRC (Design Rule Check) of X-cells analysis. But
in our proposed method, we obtain capture-X cells from
ATPG patterns generated. Every Flip-Flop in the design
can be analyzed based on output/unload test pattern.
The unload pattern can have ‘L’, ‘H’ and ‘M’ in scan
cell as a bit value. The ‘M’ represents capture-X, ‘L’
and ‘H’ represents 0 and 1 respectively. Each bit of the
pattern is mapped back to scan cell in the scan chain.

Table 2 Showing ordered scan

cells based on probability of Scan cell FF8 FF10 FF9 FF7 FF3 FF6 FF2 FF5 FF1 FF4
occurrence of capture-X for each
cell in the scan chain Prob-X-Cell 1 0.89 0.56 0.44 0.33 0.33 0.22 0.22 0.11 0
J Electron Test

Following is an algorithm to form an external X-chain in

this method:

Algorithm: creating X-chain

Assumption:
1. Patterns for the scan mode have been generated.
2. The generated patterns are available in “unload_patterns_list”.
3. The length of an external chain (ExtChainLen) has been calculated.
Inputs:
1. unload_patterns_list - set having unload patterns
2. ExtChainLen.
3. “X_list” to hold occurrence of capture-X for each scan cell.
Output:
1. X_list: A set of scan cells having capture-X in unload pattern to form an external X-chain.
Steps:
1. Initialize X_list elements to zero
2. No_of_patterns = sizeof(unload_patterns_list)
3. Initialize Count to 0
4. Initialize Flag to 0
5. foreach pattern in unload_patterns_list
6. Length= length(pattern).
7. Initialize Pos to 0
8. Increment Count by 1
9. If (Count == No_of_patterns)
10. Flag = 1
11. Endif
12. While (Pos != Length ) do
13. If (pattern[Pos] equal to “M”) // i.e “X”
14. ‘X_list[0][Pos] = X_list[0][Pos] + 1’
15. EndIf
16. If (Flag == 1) // Probability calculation
17. X_list[1][Pos] = X_list[1][Pos] / No_of_patterns
18. EndIf
19. Increment Pos by 1.
20. EndWhile
21. EndForeach
22. Sort X_list in descending order based on probability of occurrence, stored in X_list[1]
23. Select first “ExtChainLen” Scan cells (FFs) and form an external X-chain.
24. End
 J Electron Test

5 Experimental Results channels connected between codec. The ‘#Patterns’ and

The proposed hybrid DFT architecture applied to 7 indus-
trial designs. These designs have FF count from 6703 to
530,352, having different capture-X densities. All these
designs have genuine capture Xs and were not introduced
for research purpose. The results captured here are gener-
ated for all faults including stuck-at, transition etc… Used
DFTMax Ultra [10] for inserting the scan chains, com-
pressor and decompressor. ATPG tool TetraMax [35] used
to generate test patterns.
The results are shown in Table 3, with internal X-Chain
partition within adaptive scan codec as ‘Before’ and with
our proposed method as BProposed hybrid DFT^. We com-
pared the patterns count of ‘Before’ with ‘Proposed hybrid
DFT’ at same test coverage. To evaluate patterns count im-
provement of hybrid DFT architecture, TetraMax ATPG was
run on the scan synthesized design with and without our pro-
posed hybrid DFT architecture.
In Table 3, column ‘Design Name’ shows the name of the
circuit. Total number of Flip-Flops present in the circuit have
been shown in column ‘#FFs’. Column ‘I/O Ports count’ rep-
resents number of external scan-in and scan-out ports used.
Column ‘#Chains’ represents number of internal scan
‘%Coverage’ in ‘Before’ column represent number of ATPG
patterns generated and percentage of coverage obtained re-
spectively. Column ‘#Patterns’ and’%Coverage’ in
‘Proposed hybrid DFT’ column represent the number of pat-
terns generated and coverage achieved using proposed hybrid
DFT architecture. Column ‘%Patterns count improvement’
shows the percentage of patterns count improvement achieved
using hybrid DFT architecture at same test coverage of both
‘Before’ and ‘Proposed hybrid DFT’.
The Table 3 shows the result before (scan compression)
and after using hybrid DFT architecture which is depicted
in Section 3.
The results show the benefits of the hybrid DFT architecture
which is shown to bring significant improvement in pattern
count.
6 Conclusion
In this paper, we proposed a hybrid DFT architecture which is a
mixture of an external scan chain and adaptive scan compres-
sion. It takes advantage of scan as well as adaptive scan com-
pression techniques. The proposed method reduces volume of

Table 3 Results showing for both scan compression and hybrid DFT architecture proposed

Design name #FFs I/O Ports count #Chains Before Proposed hybrid DFT % Patterns count improvement

#Patterns %Coverage #Patterns %Coverage

D1 147,283 8 800 6889 94.42% 2972 94.42% 56.80%

10 500 5745 95.31% 4936 95.31% 14.00%
16 800 6128 95.05% 4980 94.05% 18.80%
16 1000 5383 94.51% 2312 94.51% 57.00%
16 2000 7550 92.28% 6655 92.28% 11.85%
D2 232,453 8 2000 30,105 99.74% 21,009 99.74% 30.21%
12 2000 14,774 84.66% 11,453 84.66% 22.48%
16 400 11,678 99.75% 9715 99.75% 16.80%
D3 11,497 16 2000 5839 97.47% 5303 95.55% 9.18%
D4 6703 8 400 2120 94.08% 1999 93.88% 5.70%
D5 330,174 8 800 8371 95.93% 7783 95.94% 7.00%
12 2000 9770 95.89% 9079 95.89% 7.00%
16 2000 9708 93.88% 8095 95.89% 16.61%
D6 530,352 8 400 9255 92.86% 7947 92.86% 14.32%
8 2000 13,428 92.95% 11,944 92.95% 11.00%
10 1000 8869 92.90% 7619 92.88% 13.50%
16 2000 7550 92.28% 6291 92.28% 16.88%
16 3000 13,727 93.05% 11,223 92.98% 18.24%
D7 28,480 4 200 2774 74.97% 1457 74.97% 47.48%
6 300 2798 75.42% 590 75.42% 78.90%
8 100 1988 74.27% 1095 74.27% 44.92%
8 400 2765 75.61% 602 76.09% 78.22%
J Electron Test
test patterns which is significant. There is no overhead of hy-
brid DFT architecture. The FFs that are to be scanned remain
scanned. The trade-off is in the use of the scan terminals (ports)
for compression and scan. Since the total scan-ins and scan-
outs remain the same there is no additional overhead to a scan
compression scheme where all the chains are embedded within
the codec. All other X handling techniques would also work
with our method to get a complete benefit. For example, X-
Masking of codecs would still be used to handle the X’s left
embedded in the codec. Since fewer X’s would exist masking
is used infrequently. The existing results were added to an
environment that has most of the prior X handling methods.
So the results improvement is showing how in the existing
solution ecosystem the results can be improved further. Our
proposed solution is developed on adaptive scan compression
technology using DFTMax Ultra [10] tool from Synopsys Inc.
ATPG patterns are generated using Tetra-max [35].
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Pralhadrao V. Shantagiri received the MIT in Information Technology
and MS in VLSI-CAD from Manipal University, Manipal, Karnataka,
India in 2003 and 2010, respectively, and M.Phil in Computer Science
from Christ University, Bengaluru, Karnataka, India. He is pursuing PhD
in Computer Science at Jain University, Bengaluru, Karnataka, India. His
current research interests include design automation and IC Test methods
and their use in design flows.
Rohit Kapur is an IEEE Fellow and a Research guide at Jain University,
Bengaluru, Karnataka, India. His research interests include IC Test
methods and their use in design flows. He has a BS in electronics engi-
neering from Birla Institute of Technology, Mesra, India, and MS and
PhD in Computer Engineering from the University of Texas at Austin.