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2.4/5.2 GHz Concurrent Band LNA with Noise Cancellation
Yu-Chen Cheng, Chih-Feng Yang and Hsiao-Chin Chen, Member, IEEE,
 technique is proposed in [5]. The LNA achieves the 3-dB
Abstract— A2.4/5.2 GHz concurrent band low noise amplifier
is designed and implemented for Wi-Fi 6 applications. The
primary stage of the LNA is based on the inverter stage with
splitting-load inductive peaking, while the noise canceling stage of
the LNA is used to reduce the noise contributed by the primary
stage. The LNA is fabricated using TSMC 90nm CMOS
technology. Consuming the power of 19.8 mW from the 1.1-V
supply, the LNA achieves the S21 of 14.04/11.3 dB, NF of 1.51/2.09
dB and IIP3 of -5.9/-5.8 dBm at 2.4/5.2 GHz.
Index Terms—Low noise amplifier (LNA), noise canceling,
noise figure (NF), concurrent band.
I. INTRODUCTION
I N order to support the higher data rate, the technology of
wireless local area networks(WLANs) evolves into the new
generation every few years. The latest WLAN standard,
IEEE 802.11ax, also named Wi-Fi 6, is proposed in 2019. As
the successor to 802.11ac, 802.11ax operates in both the 2.4
GHz and 5 GHz frequency bands and supports the speed up to
10Gbps. It allows multiple users to access one network
simultaneously while improving the average throughput per
user by a factor of at least four as compared to 802.11ac Wave
1. To optimize the RF systems for Wi-Fi 6 applications, 2.4/5
GHz concurrent-band RF building blocks are necessary.
Many concurrent-band LNAs have been presented in
literature [1-4]. The concurrent dual band LNA that
simultaneously operates at 2.45 GHz and 5.25 GHz is presented
in [1], where out-of-band interference is reduced and the noise
figure of 2.3dB/4.5dB at 2.45/5.25 GHz is achieved. However,
it requires off-chip capacitors and inductors, which increases
the cost. A 0.9/1.8 GHz concurrent-band LNA is designed by
using two parallel separate input matching networks and
resonant loads [2]. The LNA exhibits the noise figure less than
2.5 dB. Despite improving the lagging for LNA, the parallel
passive network architecture increases the cost, area and power
consumption. A 0.9/1.8 GHz dual-band receiver is presented in
[3], where the dual band function is achieved by using a switch.
The receiver operates in one band at a time and the noise
introduced by the switch degrades the sensitivity of the dual-
band receiver. The dual-band LNA achieves the NF below 3 dB.
A 2.4/5.2 GHz concurrent-band LNA is implemented by using
a double-peak single-notch network that produces one series
and two parallel resonances [4]. The measured noise figures are
3.89 dB and 3.73 dB at 2.4 GHz and 5.2 GHz. Moreover, the
double-peak single-notch network contains two large inductors
and occupies large chip area.
A wideband amplifier using cascade multistage resistive-
feedback inverters with splitting-load inductive peaking
Hsiao-Chin Chen is with the department of electrical engineering, National
Taiwan University of Science and Technology, Taipei 106, Taiwan, R.O.C.( e-
mail: hcchen@mail.ntust.edu.tw)
1
frequency up to 12 GHz and the NF of 5 to 5.6 dB at 1-11 GHz.
This work also proves that the splitting-load inductive peaking
technique is superior than the conventional inductive peaking
technique in the effect of bandwidth extension.
Most the LNAs mentioned above suffer from high power
consumption and large chip area. Moreover, their noise figures
can be improved by using noise cancellation. In previous works,
the noise canceling technique has been applied to LNAs to
improve the noise figures in the bands of interest [6-7]. In these
works, noise canceling is achieved by introducing a noise
canceling stage to create an extra signal path in addition to the
primary one so that along the two signal paths the signals are in
phase and the noises are out of phase by 180. Moreover, the
frequency response of the required gain of the noise canceling
stage is investigated to optimize the noise cancellation at high
frequencies in the previous work [7].
In this work, a concurrent-band LNA operating in both the
2.4 GHz and 5 GHz frequency bands is designed and
implemented using noise cancellation, where the splitting-load
inductive peaking technique in [5] is adopted in the primary
stage. The transfer functions of the inverter-based amplifiers
adopting conventional/splitting-load inductive peaking
techniques are analyzed and compared. Moreover, the required
gains of the noise canceling stage are analyzed for noise
cancellation LNAs adopting conventional/splitting-load
inductive peaking techniques in the inverter-based primary
stage. The rest of the paper are arranged as follows. In Section
II, the theoretical results including the gain-bandwidth
relationship of the primary and required gain of noise canceling
stage are provided. The circuit design is then described. The
measurement results are reported and compared with simulation
results in Section III. Finally, this work is summarized in
Section IV.
II. CIRCUIT DESIGN
A. The Primary Stage for Noise-canceling LNA
The noise canceling amplifier in [6] is suitable for
applications with frequency of operation below 1 GHz. To
extend the frequency of operation, the inductive peaking
technique can be adopted in the primary stage. In this section,
two topologies with different inductive peaking techniques are
investigated and compared. The primary stage adopting the
conventional inductive peaking technique is shown in Fig.1 (a).
The inductor is placed in series with the transistors to cancel the
input capacitance associated with 𝐶𝑔𝑠𝑝 and 𝐶𝑔𝑠𝑛 by forming a
series resonance.
Alternatively, the splitting load inductive peaking technique
can be adopted by placing the inductor between the input node
Yu-Chen Cheng is with the department of electrical engineering, National
Taiwan University of Science and Technology, Taipei 106, Taiwan, R.O.C.
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VDD VDD

Mp Mp
Lg Rf Rf
Y Y
Vout Vin Vout
r

X
Lg
r

Mn Mn
G
(a)
Cgd
Fig. 1 Inverters (a) using inductive peaking technique (b) splitting-load
inductive peaking technique. [5]
Rf

and gate of the NMOS, as shown in Fig. 1(b). Vn,x Vn,Y

The frequency responses of the circuits in Fig. 1(a) and Fig. r

1(b), namely the inverters using conventional inductive peaking Rs

Lg
Cgsp ro
technique and splitting load inductive peaking technique, can Cin
I²nd

be compared by considering their transfer functions. The

transfer function of the inverter using conventional inductive
peaking technique can be expressed as:
(b)
𝐴𝑣1 (𝑠)
1 Fig. 2 Noise model of the inverters (a) using inductive peaking technique (b)
= splitting-load inductive peaking technique
1 + 𝑠 2 𝐿𝑔 (𝐶𝑔𝑠𝑛 + 𝐶𝑔𝑠𝑝 ) (1)
1 − 𝑅𝑓 (𝑔𝑚𝑛 + 𝑔𝑚𝑝 )
× Let 𝑉𝑛,𝐺 and 𝑉𝑛,𝑌 represent the noise voltages at nodes G and
1 + 𝑅𝑓 (𝑠𝐶𝑑𝑠𝑛 + 𝑠𝐶𝑑𝑠𝑝 + 𝑟𝑜𝑛 −1 + 𝑟𝑜𝑝 −1 )
Y of the primary stages in Fig. 1(b), respectively. When the
where 𝑟𝑜𝑛 /𝑟𝑜𝑝 , 𝑔𝑚𝑛 /𝑔𝑚𝑝 , 𝐶𝑔𝑠𝑛 /𝐶𝑔𝑠𝑝 and 𝐶𝑑𝑠𝑛 /𝐶𝑑𝑠𝑝 represent inverter using splitting-load inductive peaking technique is
the output resistance, transconductance, gate-to-source adopted as the primary stage of the LNA using noise
capacitance and drain-to-source capacitance of the cancellation, with the noise model in Fig. 2(b), the required gain
NMOS/PMOS, respectively [5]. The transfer function of the of the noise canceling stage 𝐴𝑣,𝑁𝐶2 can be derived as:
inverter using splitting-load inductive peaking technique can be 𝑉𝑛,𝑌
expressed as: 𝐴𝑣,𝑁𝐶2 (𝑠) = =1+
𝑉𝑛,𝐺
𝐴𝑣2 (𝑠) (4)
𝑠𝑅𝑠 𝑅𝑓 [𝐶𝑔𝑠𝑝 + 𝐶𝑔𝑠 ′ − 𝜔2 𝐿𝑔 𝐶𝑔𝑠 ′ (𝐶𝑔𝑑 ′ + 𝐶𝑔𝑠𝑝 )] + 𝑅𝑓 − 𝜔2 𝐿𝑔 𝐶𝑔𝑠 ′ (𝑅𝑠 +𝑅𝑓 )
1 1 − 𝑅𝑓 (𝑔𝑚𝑛 + 𝑔𝑚𝑝 ) + (1 − 𝑔𝑚𝑝 𝑅𝑓 )𝑠2 𝐿𝑔 𝐶𝑔𝑠𝑛 (2) 𝑅𝑠 (1 + 𝑠𝐶𝑔𝑑 ′ 𝑅𝑓 )
= ×
1 + 𝑠2 𝐿𝑔 𝐶𝑔𝑠𝑛 1 + 𝑅𝑓 (𝑠𝐶𝑑𝑠𝑛 + 𝑠𝐶𝑑𝑠𝑝 + 𝑟𝑜𝑛 −1 + 𝑟𝑜𝑝 −1 ) where 𝐶𝑖𝑛 is equal to the summation of 𝐶𝑔𝑠𝑛 and the input
capacitance of the noise cancelling stage and 𝐶𝑔𝑑 ′ = 𝐶𝑔𝑑𝑛 +
1
Notably, the pole in the former transfer function 𝐶𝑔𝑑𝑝 .
√𝐿𝑔 (𝐶𝑔𝑠𝑛 +𝐶𝑔𝑠𝑝 )
1 The gain requirements of the noise cancelling stage are
is moved upwards to in the latter. Moreover, a zero is compared over the frequency range from 0.1 GHz to 6 GHz by
√𝐿𝑔 𝐶𝑔𝑠𝑛
introduced into the latter transfer function so that the bandwidth substituting corresponding parameter values into the equations,
of the circuit can be extended while using identical device as shown in Fig. 3. It is found that the required gain of the noise
dimensions. As the candidates for the primary stage of the LNA canceling stage is lower at high frequencies if the inverter using
using noise cancellation, the two circuits can be compared by the splitting-load inductive peaking technique is adopted as the
considering the gain requirements of the corresponding noise primary stage of the LNA using noise cancellation. Namely, the
canceling stages. gain requirement of the noise canceling stage is relaxed when
Let 𝑉𝑛,𝑋 and 𝑉𝑛,𝑌 represent the noise voltages at nodes the inverter using the splitting-load inductive peaking technique
and Y of the primary stage in Fig. 1(a), respectively. When the is adopted as the primary stage of the LNA using noise
inverter using conventional inductive peaking technique is cancellation. Therefore, the inverter using the splitting-load
adopted as the primary stage of the LNA using noise inductive peaking technique is adopted as the primary stage of
cancellation, with the noise model in Fig. 2(a), the required gain the LNA with noise cancellation in this work. As presented in
of the noise canceling stage 𝐴𝑣,𝑁𝐶1 can be derived as [7], the output signal of the primary stage would pass a source
𝑉𝑛,𝑌 𝑠𝐶𝑖𝑛 𝑅𝑓 𝑅𝑠 +(𝑅𝑓 −𝜔2 𝑅𝑓 𝐿𝑔 𝐶𝑖𝑛) follower to be combined with the output signal of the noise
𝐴𝑣,𝑁𝐶1 (𝑠) = =1+ (3) canceling stage, as shown in the simplified schematic in Fig. 4.
𝑉𝑛,𝑋 𝑠(𝐶𝑔𝑑 ′𝑅𝑓 𝑅𝑠 +𝐿𝑔 )+(𝑅𝑠 −𝜔2 𝑅𝑓 𝐿𝑔 𝐶𝑔𝑑 ′)
where 𝐶𝑖𝑛 is equal to the summation of 𝐶𝑔𝑠𝑛 and the input The loading effects associated with the input and output of the
source follower should be considered during the derivation of
capacitance of the noise cancelling stage and 𝐶𝑔𝑑 ′ = 𝐶𝑔𝑑𝑛 +
the require gain of the noise canceling stage. The required gain
𝐶𝑔𝑑𝑝 .
𝐴𝑣,𝑁𝐶2,𝑆𝐹 (𝑠) can be modified as
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𝑅 𝑅𝐿
𝐴𝑣,𝑁𝐶2,𝑆𝐹 (𝑠) = 𝐴𝑣,𝑁𝐶2 (𝑠) × × (5)
𝑅 + 𝑅𝑜𝑢𝑡,𝑃 𝑅𝐿 + 𝑅𝑜𝑢𝑡,𝑆𝐹
Fig. 3. Gain requirements of noise canceling stages for three
primary stage topologies.
VDD
M2
R
Vin C1
C2
Y Rf
M3
Rf C3 Vout
Lg
G
M1
r
Cgsc
Fig. 4 Simplified schematic of the LNA for considering the loading effect
of source follower during the derivation of the gain requirement of the
noise canceling stage.
𝑅𝑜𝑢𝑡,𝑃 and 𝑅𝑜𝑢𝑡,𝑆𝐹 represent the output impedance of the
primary stage and the source follower, respectively, while 𝑅𝐿
represents the load impedance. As mentioned in [7], R is
usually much larger than 𝑅𝑜𝑢𝑡,𝑃 and the output impedance of
the source follower matches the load impedance of 50 ohm for
the case of a heterodyne receiver. Therefore, the required gain
1 noise canceling stage are 1.14 and 1.4 at 2.4 GHz and 5.2 GHz,
of the noise canceling stage is reduced to 𝐴𝑣,𝑁𝐶2 (𝑠) × for the
2 respectively, during the simulation. In other words, the gain
LNA that adopts noise cancellation and consists of the primary
stage and source follower shown in Fig. 4.
B. The Concurrent-Band Noise-Canceling LNA
The schematic of the concurrent-band LNA using noise-
cancellation is shown in Fig. 5. Based on the inverter using the
splitting-load inductive peaking technique in Fig. 1(b), the
primary stage is composed of 𝑀1 , 𝑀2 , 𝑅𝑓 and inductors
𝐿𝑔 ,𝐿𝑠1−𝑠2 . As mentioned previously, the inductor 𝐿𝑔 is used to
extend the bandwidth of the primary stage and the gain
requirement of the noise canceling stage can be relaxed by using
the splitting-load inductive peaking technique in the primary
stage. Moreover, the source degeneration inductors, 𝐿𝑠1 and
𝐿𝑠2 , are used to move the optimal source impedance and the
3
complex conjugate of the input impedance toward each other to
achieve noise and power match simultaneously. Meanwhile, the
input matching network is simplified by proper device selection
so that the loss and noise degradation contributed by passive
elements are minimized.
A cascode amplifier is adopted as the noise canceling stage
because it achieves good reverse isolation and stability. An
inductor (L2) is inserted between transistors 𝑀3 and 𝑀4 to
reduce parasitic capacitance and improve the power transferred
to the common-gate stage. As the noise current of the transistors
𝑀1,2 flow through the feedback resistor 𝑅𝑓 and the source
resistor 𝑅𝑠 to generate two in-phase noise voltages at the input
and output nodes of the primary stage. The noise voltage at the
output node of the primary stage is delivered to the output
through the source follower. The noise voltage at the input node
of the primary stage is converted to an out-of-phase noise
voltage through the noise canceling stage and combined with
the noise voltage that passes the source follower. As the two
noise voltages are out-of-phase, they would be cancelled by
each other at the output of the LNA.
The gain requirement of the noise canceling stage is newly
VDD
r
Ls2
R
M2 C2
Vin
c
C1 M5
C3 L3 Vout
r
VB
r
Lg
M4 C4 L4
M1
r
r
Ls1
L2
M3
Fig. 5 Schematic of the concurrent-band LNA using noise cancellation
derived for the primary stage that is based on the inverter using
the splitting-load inductive peaking technique and inductive
source degeneration. The theoretical gain requirement and gain
simulation results of the noise canceling stage are shown in Fig.
6. The gain requirements of the noise canceling stage are 5.5
and 9.13 at 2.4 GHz and 5.2 GHz, respectively. The gains of the
requirements of the noise canceling stage are met by 20.7 % and
15.3 % at 2.4 GHz and 5.2 GHz, respectively. It can be expected
that the noise of the primary stage would be reduced by the
same percentages. According to the noise summary of the
simulation, the output noises of transistors 𝑀1−2 are reduced by
26.6 % and 16.1 % after the noise canceling stage is introduced,
which agrees well with the theoretical estimation. In the band
of interest, the noise figure of the LNA is reduced from 2.31-
2.47 to 1.73-1.72 dB after the noise canceling stage is included.
Also, the input referred noise is reduced from 0.35 to 0.3
aV2 /Hz.
In a direct-conversion receiver, the LNA is directly
connected to the subsequent circuit (mixer) so the output
matching would be unnecessary. However, in a heterodyne
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receiver, the LNA is normally followed by the image reject

filter so the output matching is critical in that situation. For the
measurement purpose, the output impedance matching is
considered for the stand-alone LNA in this work. The output
matching network consists of four passive devices and the
output impedance can be approximated to (1/𝑔𝑚5 + 1/𝑠𝐶3 +
𝑠𝐿3 )||(1/(𝑠𝐶4 )||s𝐿4 ). To achieve the concurrent-band output
matching, the 1/𝑔𝑚5 of 12.5 ohm is firstly achieved. Then, the
series LC network (𝐿3 , 𝐶3 ) with the resonant frequency of 3.8
GHz, around the middle of the two bands of interest, is included
to obtain the impedance 𝑍𝑂𝑢𝑡,𝑆 = (1/𝑔𝑚5 + 1/𝑠𝐶3 + 𝑠𝐿3 )
which lies on the constant resistance circle of 12.5 ohm, as
shown in Fig. 7. From Fig. 8, the impedance 𝑍𝑂𝑢𝑡,𝑆 is 14.9-
j24.9 and 18.35+ j27.35 at 2.4 GHz and 5.2 GHz, respectively.
Note that the impedance 𝑍𝑂𝑢𝑡,𝑆 is capacitive for frequency
below 3.8 GHz and inductive for frequency above 3.8 GHz.
Particularly, the corresponding admittance 𝑌𝑂𝑢𝑡,𝑆 is 0.019+ Fig. 7 𝑍𝑂𝑢𝑡,𝑆 on constant resistance circle
j0.03 (siemens) and 0.019- j0.022 (siemens) at 2.4 GHz and 5.2
GHz, respectively. The real part of the admittance 𝑌𝑂𝑢𝑡,𝑆 is
0.019 (siemens) (close to 0.02 siemens) at both 2.4 GHz and
5.2 GHz. Therefore, the parallel LC network (𝐿4 , 𝐶4 ) can be
designed as follows. The parallel LC network ( 𝐿4 , 𝐶4 ) is
included to obtained the admittance 𝑌𝑂𝑢𝑡,𝑃 , where the
susceptance of the admittance 𝑌𝑂𝑢𝑡,𝑆 is diminished. In other
words, the admittance 𝑌𝑂𝑢𝑡,𝑆 is moved to 𝑌𝑂𝑢𝑡,𝑃 along a
constant transconductance circle. From the admittance 𝑌𝑂𝑢𝑡,𝑆
observed in Fig. 9, the parallel LC network (𝐿4 , 𝐶4 ) needs to
provide the susceptance of -0.03 and 0.022 (siemens) at 2.4
GHz and 5.2 GHz, respectively. Then the values of L4 and C4
can be determined by solving the simultaneous equations (6-7)
From (6-7), the required inductance of 1.3 nH and capacitance
of 1.4 pF can be obtained.
1
𝑗𝜔𝐶4 + = −0.03j (6)
j𝜔L4 Fig. 8 𝑍𝑂𝑢𝑡,𝑆 at 2.4 GHz and 5.2 GHz on the impedance Smith Chart.
1
𝑗𝜔𝐶4 + = 0.022j (7)
j𝜔L4

Fig. 6 Theoretical gain requirement and simulated voltage gain of the noise Fig. 9 𝑌𝑂𝑢𝑡,𝑆 at 2.4 GHz and 5.2 GHz on the admittance Smith Chart.
canceling stage
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Fig. 7 The die photograph of 2.4/5.2 GHz concurrent band LNA .

Fig. 10 Chip microphotography of the LNA.

Fig. 11 S11 measurement and simulation results.

III. SIMULATION AND MEASUREMENT RESULTS
The concurrent-band noise canceling LNA is implemented
using 90 nm CMOS technology. The overall chip size is 1.09 x
0.925 𝑚𝑚2 (The active area is 0.44 x 0.55 𝑚𝑚2 .) and chip
micrograph is shown in Fig. 10. The power consumption is 19.4
mW at a 1.1-V supply voltage. The S-parameters are measured
using the network analyzer (Keysight 5222A). The noise figure
analyzer (Agilent N4955A) is used to perform the measurement
of the noise figure. The signal generator (Agilent E4245C) and
spectrum analyzer (Agilent E4440A) are used to measure the
P1dB and IIP3 of the LNA. The simulation and measurement
results of the S-parameters are shown in Fig. 11, Fig. 12 and Fig.
13. As shown in Fig. 11, the simulated input return loss is below
-10 dB from 2 to 6 GHz and measured is below -5 dB from 2 to
Fig. 12 S22 measurement and simulation results
6 GHz. The simulated output return loss is below -15 dB from
2.4 to 2.5 GHz and 5.1 to 5.9 GHz, while the measured output
return loss is below -10 dB from 2.4 to 2.5 GHz and -5 dB from
5.1 to 5.9 GHz, as shown in Fig. 12. The measured power gain
is 14.04 at 2.4 GHz and simulated is 15.05 dB at 2.5 GHz, as
shown in Fig. 13. The simulated noise figure is below 2.1 dB
from 2 to 5.9 GHz and the measured noise figure is 1.51 dB at
2.4GHz and 2.09 at 5.2GHz, as shown in Fig. 14. The
simulation results of the IIP3 are shown in Fig. 15, where the
IIP3 is -4.01/-0.95 dBm at 2.4/5.2 GHz. The measurement
results of the IIP3 are shown in Fig. 16, where the IIP3 is -5.9/-
5.4 dBm at 2.4/5.2 GHz. During the simulation and
measurement for the band of 2.4 GHz and 5.2 GHz, the two-
tone signals at 2.4/2.41 GHz and 5.2/5.21 GHz are applied,
respectively. The simulated P1dB of low noise amplifier is -
Fig. 13 S21 measurement and simulation results.
15.26/-12.56 dBm at 2.4/5.2 GHz, as shown in Fig.15. The
measured P1dB is -16/-16 dBm at 2.4/5.2 GHz, as shown in Fig.
14.
Table I and Table II summarize the performance of the LNA
and other previous reported LNAs for comparison. The figure
of merit (FoM) for LNA is given as follows [9]:
𝐺𝑎𝑖𝑛[𝑎𝑏𝑠] ∙ 𝐼𝐼𝑃3 [𝑚𝑊] ∙ 𝑓𝑜 [𝐺𝐻𝑧]
𝐹𝑜𝑀 = 20 ∙ 𝑙𝑜𝑔10 ( )
(𝑁𝐹[𝑎𝑏𝑠] − 1) ∙ 𝑃𝐷𝐶 [𝑚𝑊]

Fig. 14 NF measurement and simulation results.

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(a) (b) Fig. 17 Simulated P1dB at (a) 2.4 GHz and (b) 5.2 GHz
Fig. 15 Simulated IIP3 at (a) 2.4 GHz and (b) 5.2 GHz

Fig. 14 Measured P1dB at (a) 2.4 GHz and (b) 5.2 GHz.

(a) (b)
Fig. 16 Measured IIP3 at (a) 2.4 GHz and (b) 5.2 GHz.

TABLE I
COMPARISON TABLE OF 2.4 GHz LNA

This work [12] [13] [15] [16]

Technology(nm CMOS) 90 180 180 180 130
Frequency(GHz) 2.4 2.4 2.4 2.4 2.4
S21 (dB) 14.01 14.1 10.8 16.5 19.3
NF (dB) 1.51 8.7 3.25 3 3.2
IIP3 (dBm) -5.9 -5 4.5 -16 -20.1
Chip area(𝑚𝑚2 ) 0.63 1.44 1.03 1.2 -
Power consumption 19.8 2 11.7 0.6 2.4
FOM -8.45 -10.46 5.1 -2.72 -21.64

TABLE II
COMPARISON TABLE OF 5.2 GHz LNA

This work [13] [14] [16]

Technology(nm CMOS) 90 180 60 130
Frequency(GHz) 5.2 5 5.5 5.2
S21 (dB) 11.41 8 16.7 17.5
NF (dB) 2.09 4.1 1.32 3.3
IIP3 (dBm) -5.8 3 -7.4 -18.1
Chip area(𝑚𝑚2 ) 0.63 1.03 0.8 -
Power consumption 19.8 11.7 6 2.4
FOM -3.98 2.7 10.14 -13.11

are expected to be reduced by 20.7 % and 15.3 % at 2.4 GHz

IV. CONCLUSIONS
A concurrent-band low noise amplifier simultaneously
operating at 2.4 GHz and 5.2 GHz is presented in this work. The
noise canceling technique is adopted to improve the NF of the
LNA, where the required gain of noise canceling amplifier is
formulated. By estimation, the output noises of input transistors
and 5.2GHz, respectively, which agrees with the simulation
results obtained from the noise summary. The concurrent-band
LNA achieves the NF of 1.9/1.98 dB and S21 of 14.56/12.3 dB
at 2.4/5GHz.
> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 7

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