Microelectronics Reliability 52 (2012) 1247–1252

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Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Variability aware low leakage reliable SRAM cell design technique

A. Islam a,⇑, Mohd. Hasan b
a
Dept. of ECE, Birla Institute of Technology (Deemed University), Mesra, Ranchi, Jharkhand, India
b
Electronics Engineering Department, Aligarh Muslim University, Aligarh, Uttar Pradesh, India

a r t i c l e i n f o a b s t r a c t

Article history: This paper presents a technique for designing a low power SRAM cell. The cell achieves low power dis-
Received 9 October 2011 sipation due to its series connected drivers driven by bitlines and read buffers which offer stack effect.
Received in revised form 2 January 2012 The paper investigates the impact of process, voltage, and temperature (PVT) variations on standby leak-
Accepted 10 January 2012
age and finds appreciable improvement in power dissipation. It also estimates read/write delay, read sta-
Available online 31 January 2012
bility, write-ability, and compares the results with that of standard 6T SRAM cell. The comparative study
based on Monte Carlo simulation exhibits appreciable improvement in leakage power dissipation and
other design metrics at the expense of 84% area overhead.
Ó 2012 Elsevier Ltd. All rights reserved.

1. Introduction compared in Section 3. Finally, the concluding remarks are pro-

Recently evolved multi-core architectures need large SRAM
cache memories to support high bandwidth and capacity require-
ments. This has resulted in SRAM caches to take up to a 90% of
the total chip area (Montecito processor) [1]. Since the total leak-
age power is proportional to the number of transistors, a reduction
of the SRAM cache leakage is therefore inevitable for low power
design. The cache memory remains in idle state for long period
when not accessed, especially L2 cache. In those circumstances
the leakage power dissipation in SRAM caches can exceed the dy-
namic power as seen in the 8 KB instruction cache of the M32R
processor at 45 nm technology [2].
For modern VLSI devices, Isub (subthreshold leakage current),
IBTBT (band-to-band tunneling current) or IJN (junction leakage cur-
rent) and Ig (gate leakage current) are becoming important leakage
component, for applications such as embedded cache and battery-
operated systems where leakage currents must be kept extremely
low. Therefore, leakage is a serious issue in scaled technology.
This paper proposes a low power 11-transistor SRAM cell (here-
after called 11T) and compares its read/write delay, read stability,
write-ability, dynamic power dissipation, leakage power dissipa-
tion and variability with those of standard 6T cell, which is no
more reliable for nanoscale cache design.
To verify the proposed technique, extensive simulations on
HSPICE using 22 nm Predictive Technology Model (PTM) [3] are
performed.
The rest of the paper is organized as follows. Section 2 presents
the proposed design. Simulation results are discussed and
vided in Section 4.
2. Proposed 11T SRAM cell
This paper proposes a low power fully differential 11T SRAM
bitcell, the width over length (W/L) ratios (in nm scale) of its tran-
sistors are shown in Fig. 1. And its design metrics are assessed and
compared with its differential counterpart standard 6T SRAM cell,
the W/L ratios (in nm scale) of which are shown in Fig. 2.
2.1. Device sizing of conventional 6T SRAM cell
The size ratio of pull-down device to the access device, referred
to as the cell ratio (CR) or bratio (bratio = bdriver/baccess) is critical in
case of 6T SRAM cell due to its direct read mechanism. The bratio
determines how high the node that stores ‘‘0’’ rises during read ac-
cess due to voltage dividing effect between driver and access MOS-
FETs. Typically, bratio of 1.2–3 is required to avoid read upset in
conventional 6T SRAM cell [4]. Write-ability of SRAM cell is deter-
mined by the pull-up ratio (PR) or cratio (cratio = bpull-up/baccess). Gen-
erally, cratio 6 1.8 is required to maintain good write-ability [5].
Therefore, for maintaining appreciable read stability, write-ability
and feed-back pull-up strength minimum width devices are typi-
cally not used in standard 6T SRAM cell. These strict constraints
on the device sizing of conventional 6T cell are maintained for fair
comparison with the proposed design (bratio = cratio = 1.33).
2.2. Device sizing of proposed design

⇑ Corresponding author. Tel./fax: +91 6512275231, mobile: +91 9471559180. Maintaining bratio is not a strict constraint in case of proposed
E-mail address: aminulislam@bitmesra.ac.in (A. Islam). bitcell as it does not face read-disturb during read access.

0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved.
doi:10.1016/j.microrel.2012.01.003
1248 A. Islam, Mohd. Hasan / Microelectronics Reliability 52 (2012) 1247–1252
Fig. 1. Fully differential low power 11-transistor SRAM cell (11T).
Fig. 2. Fully differential standard 6-transistor SRAM cell (6T).
Therefore, basic part (corresponding to 6T) of the 11T is designed
with minimum sized devices to reduce area overhead as far as pos-
sible, in view of the fact that the density is one of the most desired
SRAM design metrics in future SoC (system on chip) and NoC (net-
work on chip) cache. Read buffer of the cell (MN7/8/9) is designed
with up-sized devices to achieve shorter read delay and higher
read stability. Without this read buffer, such a compactly designed
cell would exhibit unacceptably low RSNM (read static noise
margin).
Critical piece of our design strategy is the series connection of
the MN5/6 to the drivers of the cross-coupled inverters. The gate
electrodes of these series connected MN5/6 are driven by bitlines.
The internal node X1 is raised during write operation (in this case
when ‘‘H’’ holds ‘‘1’’ prior to write operation; in other case X2 is
raised). This is because to write a ‘‘1’’ at ‘‘L’’ BLB (bitline bar) is dri-
ven high and BL (bitline) is pull-down to ground. This turns MN5
OFF, resulting in disconnection of pull-down path of InvL (left in-
verter) and quick charging of internal storage node ‘‘L’’ to high va-
lue. In a two device stack, if top device is ON and bottom device is
OFF, a voltage is developed at the internal node. Therefore, internal
node X1 in this case is raised. The positive VX1 offers stacking and
body effect that helps in reducing write delay during write opera-
tion by quickly charging storage node ‘‘L’’. As per our analysis, X1 is
found to rise gradually from 0 to 203 mV and drops to 127 mV at
write point when internal nodes are tripped.
3. Simulation results and discussion
The problem of variability (defined as standard deviation (r) to
mean (l) ratio of a design metric) and static power dissipation are
becoming severe with increased integration density. This paper at-
tempts to address these issues. This section presents comparison of
various design metrics which are estimated during Monte Carlo
(MC) simulation using 22 nm PTM [3].
Fig. 3. Read and write delay versus VDD.
3.1. Simulation setup
In this analysis, the channel length (L), channel doping concen-
tration (NDEP), oxide thickness (tox) and threshold voltage (Vt) are
assumed to have independent Gaussian distributions with 3r var-
iation of 10% [6].
Most of the design metrics are estimated by varying the supply
voltage by ±10% around the nominal VDD of 0.8 V, in view of the
anticipation of ITRS 2009 [7]. The sample size of 2000 ensures a
lower than 4% inaccuracy in the estimation of standard deviation
[8]. Design metrics in this work are estimated with 5000 MC run
[9] to achieve even higher accuracy. Unless specified otherwise,
all parameters are estimated under the above variation/simulation
setup.
3.2. Read access time
Our bitcell exhibits marginal (1.07) penalty in read delay at
nominal VDD (Fig. 3). Prior to read operation, in case of 6T, bitlines
are precharged, MN1 is ON, storage node ‘‘L’’ stores a ‘‘0’’ and ‘‘H’’
stores a ‘‘1’’ (assumed). When WL (word line) is activated BLB
drops through MN3/MN1. Prior to read operation, in case of 11T,
‘‘L’’ and H’’ are isolated by deactivating WWL (write word line),
‘‘0’’ in ‘‘L’’ turns MN7 OFF, ‘‘1’’ in ‘‘H’’ turns MN8 ON, which raises
the internal node voltage (X3 in Fig. 1) to a value higher than zero.
As per our simulation, X3 is raised to 573 mV and gradually drops
to 149 mV at read point (Fig. 4). When RWL (read word line) is acti-
vated, raised X3 offers body effect to MN8. Due to positive VX3,
body-to-source voltage Vbs,MN8 becomes negative, resulting in an
increase in threshold voltage (larger body effect) of MN8. This
results in reduction of its drive strength. And it takes longer time
to discharge BL. This is not the case with 6T cell. In 6T cell node
‘‘L’’ initially remains at ground level (as it is storing ‘‘0’’) and grad-
ually increases to higher value due to voltage dividing effect. As per
our simulation results, node ‘‘L’’ rises to only 106 mV at read point
when 50 mV differential is developed [9,10]. Therefore, body effect
offered to MN3 is much smaller comparatively. The read delay pen-
alty, though affected by larger body effect, is mostly due to in-
creased bitline capacitance. Bitlines of the proposed 11T cell has
increased drain diffusion capacitance of MN7 and MN8. However,
as only 50 mV differential between BL and BLB is required for sens-
ing, the read delay penalty is only 7%.
3.3. Write access time
Write operation involves mainly pull-up devices (MP1/MP2),
access devices (MN3/MN4) and write driver (not shown), while
WWL is activated and RWL is deactivated. Our bitcell achieves
1.24  shorter TWA (write access time or write delay) at nominal
 A. Islam, Mohd. Hasan / Microelectronics Reliability 52 (2012) 1247–1252
Fig. 4. Timing diagram of X3 while reading with internal node H storing 1 and L
storing 0.
VDD (Fig. 3) due to smaller cratio (cratio = 1 in case of 11T and cratio =
1.33 in case of 6T). Moreover, BL turns MN5 OFF disconnecting
pull-down path while writing ‘‘1’’ at ‘‘L’’ (prior to write ‘‘L’’ = ‘‘0’’
and ‘‘H’’ = ‘‘1’’ are assumed). This makes write operation faster
and improves write-ability of the cell (as explained in Section 3.4).
3.4. Write-ability
Write-ability of an SRAM cell is gauged by the WSNM (write
static noise margin) as shown in Fig. 5. The WSNM is a measure
of ability of the cell to pull down the node storing ‘‘1’’ to a voltage
less than the VM (switching threshold) of the other inverter storing
‘‘0’’ so that flipping of the cell state occurs. There is a ratioed fight
between the pull-up pMOSFET that tries to maintain a ‘‘1’’ and the
access nMOSFET that tries to pull it down [11].
The key to achieving a successful write is to ensure that the ac-
cess nMOSFET wins the fight with the pull-up pMOSFET inside the
bitcell. The primary reason for write failure is the inability of the
access nMOSFET to win the ratioed fight against the pMOSFET in-
side the bitcell while writing to the cell [11].
As mentioned, earlier the write-ability of the cell depends on
MP2 (MP1) to MN4 (MN3) strength ratio called pull-up ratio or
Fig. 5. Static voltage characteristics of SRAM cells during write operation.
1249
cratio. The write-ability of a cell is estimated using read and write
VTCs (voltage transfer curves) [12]. When WSNM falls below zero,
write VTC intersects read VTC, indicating positive write margin and
signifying write failure. As can be seen in Fig. 5, 11T and 6T show
288 mV and 214 mV WSNM respectively.
The proposed bitcell offers higher WSNM (by 1.07) due to its
lower cratio. As can be observed, the read VTC and write VTC con-
verge to a single stable point which indicates that the cross-cou-
pled inverters of the cell can function as monostable circuit
signifying the successful write [13,14].
3.5. Read stability
With technology scaling, process variations have made the pre-
diction of SRAM cell characteristics increasingly uncertain. Process
variations can result in device mismatch in a cell increasing failure
probability. Besides process variations, inherent to technology
scaling is the increase in SCE (short-channel effect) such as DIBL
(drain induced barrier lowering). Increasing DIBL can also result
in device mismatch in a cell resulting in an increase in failure prob-
ability [15]. In such a scenario, higher value of RSNM (read static
noise margin) of an SRAM cell is highly desirable. This is because
SRAM cell is most susceptible to noise during read operation since
the node storing ‘‘0’’ rises to a voltage higher than ground due to a
voltage dividing effect between the access device and inverter’s
pull-down nMOS driver.
To design cells for maximum RSNM (read static noise margin),
bdriver/baccess must be maximized [16]. However, this sizing con-
straint is not strictly applicable to 11T as it is read-decoupled. Its
write access nMOSFETs isolate the storage nodes from the BL/BLB
during read access, thereby avoiding read disturb. Fig. 6 plots the
‘‘butterfly curve’’ for RSNM of 11T and 6T. Our bitcell offers 2.8
higher RSNM compared to 6T due to isolation of storage node from
bitline.
A single root (or cross point defined as point of intersection of
VTC and VTC1 of cross-coupled inverters) of static voltage charac-
teristics during read operation implies its inability to function as a
bistable circuit. The RSNM VTCs of both the cells have three dis-
tinct roots assuring its functionality as a bistable circuit in read
and hold mode [13,14].
Our bitcell is WSNM limited as the value of WSNM (228 mV) is
smaller than the value of RSNM (235 mV). The use of appropriate
device sizes to closely match RSNM with WSNM is a critical piece
of our design strategy. It is to be noted that cells with RSNM of at
least 25% of VDD is generally considered to have excellent read sta-
bility [17].
Fig. 6. Static voltage characteristics of SRAM cells during read operation.
1250 A. Islam, Mohd. Hasan / Microelectronics Reliability 52 (2012) 1247–1252

3.6. Dynamic power dissipation

Dynamic power in an SRAM cell consists of two components –

read power and write power. During READ operation, the voltage
swing of the bitlines is limited to a smaller value whereas a WRITE
operation requires almost full voltage swing on the bitlines. The
charging and discharging of the high capacitive bitlines account
for the major proportion of the dynamic energy consumption. This
results in energy consumption of the WRITE operation to be much
higher compared to the READ operation [18]. However, this is not
the case with our bitcell. We simulated both the cells for estima-
tion of read and write power at 27 °C. The results are plotted in
Fig. 7. Our bitcell consumes 1.08 higher read power compared
Fig. 8. Standby leakage components in 6T in hold mode.
to 6T SRAM cell due to larger bitline capacitance. However, it con-
sumes 1.19 lower write power because to write a ‘‘1’’ at ‘‘L’’ BLB is
driven high and BL is driven low. This turns MN5 OFF, resulting in
disconnection of pull-down path of InvL (left inverter) and quick
charging of internal storage node ‘‘L’’ to high value. Similar situa-
tion occurs when a ‘‘1’’ is written to H. In this case, MN6 is turned
OFF by low BLB and high BL quickly charges H.

3.7. Standby power dissipation

Leakage in L1 and L2 caches is an alarming issue since several

tens of million identical cells are common in today’s caches. The
leakage current is one of the major contributors to the total power
dissipation in cache as whole part of the cache remains idle most of
the time except the row being accessed. The total leakage current
in an SRAM cell mainly (ignoring other minor leakage components
such as IGIDL and Ipunchthrough) consists of the subthreshold leakage
current (Isub), the gate leakage current (Ig) and the BTBT (band-to-
band tunneling) or junction leakage current (Ijn) through different
devices. The major leakage components in 6T SRAM cell in hold
mode are shown in Fig. 8 and given by:
Isub;6T ¼ IsubMN3 þ IsubMN2 þ IsubMP1 ð1Þ

IJN;6T ¼ IJNdMN4 þ IJNsMN4 þ IJNdMN3 þ IJNdMN2 þ IJNdMP1 ð2Þ

Ig;6T ¼ IgdMN4 þ IgsMN4 þ IgdMN3 þ IgdMP1 þ IgdMN1 þ IgsMN1 þ IgdMP2
þ IgsMP2 þ IgdMN2
Ileak;6T ¼ Isub;6T þ IJN;6T þ Ig;6T :
The current expressions are derived from the leakage current
expressions presented in [11,19–22]. The major leakage compo-
nents in proposed SRAM cell are shown in Fig. 9 and given by:
Isub;11T ¼ IsubMN3 þ IsubMN2 þ IsubMN7 þ IsubMN8 þ IsubMN9 þ IsubMP1
IJN;11T ¼ IJNdMN4 þ IJNsMN4 þ IJNdMN3 þ IJNdMN2 þ IJNdMP1 þ IJNdMN7
þ IJNsMN7 þ IJNdMN8 þ IJNsMN8 þ IJNMN9
Fig. 9. Standby leakage components in 11T in hold mode.
ð3Þ
Ig;11T ¼ IgdMN4 þ IgsMN4 þ IgdMN3 þ IgdMP1 þ IgdMN1 þ IgsMN1 þ IgdMP2
ð4Þ þ IgsMP2 þ IgdMN2 þ IgdMN5 þ IgsMN5 þ IgdMN6 þ IgsMN6 þ IgdMN7
þ IgsMN7 þ IgsMN8 þ IgdMN9 ð7Þ
Ileak;11T ¼ Isub;11T þ IJN;11T þ Ig;11T : ð8Þ
ð5Þ From Figs. 8 and 9, it may appear that 11T may consume higher
standby power as it has more leakage components. However, inter-
estingly, it consumes less hold power.
ð6Þ This occurs due to stacking effect. In a two device stack, if upper
device connected to VDD is ON and bottom device is OFF, the inter-
nal node voltage (X3 in Fig. 9) is raised to a value higher than zero.
In hold mode the combination of MN7/MN8 and MN9 resem-
bles this condition. And hence, X3 rises to 573 mV in hold mode.
This causes negative Vgs, negative Vbs and reduced Vds in top de-
vices. Positive VX3 have following three effects.

(1) Due to positive VX3, the gate-to-source voltage Vgs,MN7 of

MN7, become negative, thereby reducing its subthreshold
leakage (Isub) to some extent.
(2) Due to positive VX3, body-to-source voltages Vbs,MN7 and
Vbs,MN8 become negative, resulting in an increase in thresh-
old voltages (larger body effect) of MN7 and MN8 respec-
tively, and thereby reducing their subthreshold leakages
Fig. 7. Read and write power versus VDD. (Isub) to some extent.
 A. Islam, Mohd. Hasan / Microelectronics Reliability 52 (2012) 1247–1252 1251

60

H PWR (Hold Power) (nW)

11T VDD = 0.8 V
50 6T

40

30

20

10

0
20 40 60 80 100 120 140
Temperature (°C)
Fig. 10. Leakage or hold power and its variability versus VDD. 11T exhibits 2.37
reduction in hold power @ nominal VDD of 0.8 V. It also proves its robustness by Fig. 12. Leakage power (in hold mode) versus temperature.
showing 1.10 narrower spread in hold power distribution @ nominal VDD.

Table 1
Comparison of leakage power versus temperature @ 0.8 V.

Temperature (°C) 11T hold power (nW) 6T hold power (nW)

27 9.3 22
50 12 27.4
75 15 35
100 19 43.7
125 24 53.7
137 26 59

Fig. 11. Comparison of hold power (HPWR) distribution of 11T and 6T @ nominal
VDD = 0.8 V.

(3) Due to positive VX3, drain-to-source voltages Vds,MN7 and

Vds,MN8 decrease, resulting in an increase in the threshold
voltages (less DIBL) of MN7 and MN8 respectively, and
hence reducing their subthreshold leakage (Isub) to some
extent.

A two-device stack in a digital circuit exhibits an order of mag-

nitude less leakage than the leakage in a single device [23]. As sub-
threshold leakage is the major leakage components [11], which is
reduced due to stacking effect, the proposed design dissipates low-
er standby power compared to 6T, in spite of having more leakage
components in its leakage expressions and circuit diagram (Figs. 8
and 9). As observed from Fig. 10, proposed bitcell reduces leakage
power by 2.37 and exhibits 1.10 narrower spread in standby
power at nominal VDD compared to 6T SRAM cell. Comparison of
hold power (HPWR) distribution of 11T and 6T at nominal VDD is
shown in Fig. 11. Hold power distribution curves of the two mem-
ory cells cross at 13 nW. Based on the simulation data, our estima-
tion shows that 94% of statistical samples in case of 11T have HPWR
lower than 13 nW signifying its lower standby power dissipation
compared to 6T (96% of statistical samples in case of 6T have HPWR
higher than 13 nW).
3.8. Comparison of leakage power versus temperature
Since VLSI circuits often operate at elevated temperatures, we
have simulated the cells varying temperature in the range from
27 °C to 137 °C for estimation of leakage power, because leakage
power becomes incremental at higher temperature (Fig. 12 and Ta-
ble 1). This is because the Isub (subthreshold current) controlled by
the carrier diffusion, increases exponentially with temperature.
This happens because Vt (threshold voltage) of a device decreases
with temperature and Isub is exponentially dependent on tempera-
ture through VT (thermal voltage) (VT = kT/q = 26 mV at 300 K). Re-
verse biased junction leakage (IJN) is dependent on thermally
Fig. 13. Cell layout of 11T bitcell. WWL = write word line, RWL = read wordline,
BL = bit line, BLB = bit line bar, L and H are internal storage nodes.
generated minority carriers. An increase in operating temperature
increases the number of minority carriers and reduces band-gap of
Silicon. Due to band-gap narrowing, IJN (i.e. IBTBT) increases with
temperature.
As can be observed, our bitcell consumes lower leakage at all
temperatures ranging from 27 °C to 137 °C. This makes the pro-
posed cell suitable for low power cache design.
3.9. Area comparison
As 22-nm layout tool is not available, for fair area comparison,
layout was generated using generalized 45-nm design rule
(Fig. 13). Type ‘‘A’’ industry standard 6T layout topology was used
[24]. Although, these rules are consistent with those used in indus-
try, some differences may exist as the technology scales to 22 nm
to allow layout optimization. However, as we have used generic
scaling factor (k), the area and pitch comparison will remain valid.
The area of the generated proposed bitcell (11T) is found to be
42k  56k (column height  column pitch) against 32k  40k of
1252 A. Islam, Mohd. Hasan / Microelectronics Reliability 52 (2012) 1247–1252
6T. Thus, our bitcell adds 84% area overhead compared to 6T SRAM
cell. And, row pitch (column height) of our bitcell is 42k and bitline
pitch or column pith is 56k. Bitline pitch or column pitch is defined
as the width of the bitcell [25,26].
Although, our cell size expands by 84%, its overwhelming
improvement in RSNM, standby power and variability justifies
the additional overhead.
4. Conclusions
Due to exponential dependence of subthreshold current on
threshold voltage, subthreshold leakage is an alarming issue in
scaled technology, where threshold voltage is few hundred mV
above zero. This work proposes a power aware 11T SRAM cell. It
analyzes the impact of PVT variations on standby power. The re-
sults show significant improvement in most of the design parame-
ters over standard 6T SRAM cell demonstrating its reliability and
low power operability. The proposed design is therefore an attrac-
tive choice for low power applications in scaled technology in the
presence of PVT variations.
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