Vlsi Design Flow: RTL To GDS: Constraints I

VLSI DESIGN FLOW: RTL TO
GDS
Lecture 25
Constraints I
Sneh Saurabh
Electronics and Communications
Engineering
IIIT Delhi
Lecture Plan
▪ Basics of constraints
▪ Clock constraints
▪ Input/Output constraints
▪ Timing exceptions
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Constraints: Basics
Constraints are: create_clock -period 10 -waveform {5 10}
▪ Requirements of a design that needs to be [get_ports CLK]
honoured or attempted to be honoured by the set_clock_transition -rise 0.1 [get_clocks CLK]
CAD tools
set_clock_uncertainty 0.2 [get_clocks CLK]
▪ Information about a design that could
potentially be exploited by the CAD tools to set_input_delay -clock CLK 3.0 [get_ports
improve the PPA of the design INPA]
set_output_delay -clock CLK 3.0 [get_ports
▪ Constraints are normally specified in Synopsys INPA]
Design Constraints (SDC)
set_false_path –from [get_ports TE]
▪ ASCII format written in Tool Command
Language (TCL) set_multicycle_path –from [get_ports mult_out]

Constraints: Application
▪ Most of the constraints are related to timing of a design (also called timing constraints)
➢ Employed by implementation tool to gather information about the expected timing
behavior
➢ Employed by STA tool to verify timing

Constraints: What is the origin?
Constraints are normally manually written

▪ Designer have the knowledge of design goals and environmental constraints
▪ There are certain tools for automatic constraints generation
➢ Some user intervention is always required
It is important to write correct constraints

▪ Otherwise design implementation tools can produce unexpected results
▪ There should be consistency between different constraints
▪ Constraints should be consistent with design attributes

Constraints: Types
Clock signal
▪ Attributes of a clock signal such as frequency, duty cycle, skew, uncertainty and delay
Environment under which the design operates
▪ Attributes of external incoming signal and expected behavior of the signals produced by a
design
Functionality of the design (informative)
▪ Timing exceptions (paths that are false and paths that are allowed to behave differently
than traditional synchronous behavior), modes of design
Design rules and optimization constraints
▪ Maximum slew at the port, maximum capacitance at a pin, and soft constraints

Constraints
Clock Signal

Clock Constraints: Sources
Two types of clock sources
▪ Primary clock sources: waveform
independent of other clock sources
in that design
▪ Derived clock sources: waveform
depends on other clock sources
▪ Master clock: clock from which we

derive another clock is known as the
master clock of the derived clock
➢ CS1 is the master clock source
of CS2

Primary Clock Source Definition
create_clock: defines the primary clock source in a design
current_design MyComp
create_clock -name EXT_CLK -period 10 -waveform {0 4}
[get_ports clk_in]
create_clock -name INT_CLK -period 10 [get_pins CS1/clk_g]
-waveform: time when the clock edges occur, starting

from rise-edge

Derived Clock Source Definition
create_generated_clock: define derived clock sources
create_clock -name CLK -period 10 [get_pins

CS1/CLK]
create_generated_clock -name GCLK -divide_by 2
–source [get_pins CS1/CLK] [get_pins CS2/GCLK]

Attributes of Clock Signal: Latency
set_clock_latency: specify clock latency
create_clock -name CLK -period 200 [get_ports clk_port]

set_clock_latency 5 -source [get_clocks CLK]
set_clock_latency 10 [get_clocks CLK]

Attributes of Clock Signal: Uncertainty
set_clock_uncertainty: unpredictable deviation of the clock edges from the ideal value
Clock uncertainty can be used to model:
▪ Jitter: temporal variation
▪ Skew: spatial variation
▪ Safety margins

set_clock_uncertainty 15 -hold [get_clocks CLK]
set_clock_uncertainty 20 -setup [get_clocks CLK]

Attributes of Clock Signal: Transition
set_clock_transition: specify an estimated clock transition time

set_clock_transition 10 [get_clocks CLK]

References
▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,
2023.
▪ Bhasker, Jayaram, and Rakesh Chadha. Static timing analysis for nanometer designs: A
practical approach. Springer Science & Business Media, 2009.
inprotected.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

GDS
Lecture 26
Constraints II
Sneh Saurabh
Engineering
IIIT Delhi
Constraints
Environment

Static Timing Analysis: Environment of design
Environment of design puts additional constraints on the signal entering/leaving a design

▪ Signal entering the design at the input port encounters delay
▪ Signal leaving the design at the output port will encounter delay and get captured externally
➢ Should meet setup/hold requirements at FOUT
➢ Check for setup/hold must also be performed at the output port

Input Port Constraints: set_input_delay
▪ Signal gets delayed before entering the
design
➢ Lesser part of clock-period is available
for the signal to reach flip-flop within the
design
▪ Delay external to design at the input ports is

modelled using set_input_delay
▪ Value of input delay = Delay of 𝐶𝐸1 + CP → Q delay of 𝐹𝐼𝑁 + Delay of 𝐷𝐼𝑁
create_clock –name CLK –period 2000 [get_ports CLK_PORT]
set_input_delay –clock [get_clocks CLK] 100 [get_ports IN]

Transition at Input Port
▪ set_input_transition: model slew of
▪ set_driving_cell : driver of inputs
incoming signal
set_driving_cell -lib_cell BUF1X -library tech14nm

set_input_transition 10 -max -rise [get_ports IN]
[get_ports IN]

Output Port Constraints: set_output_delay
Output Delay: signal leaving a design must meet the setup/hold constraints of the flip-flop
that captures that signal
▪ Constraints of the external flip-flop is modelled using set_output_delay
▪ The delay of OD needs to be chosen such that the setup/hold requirements in the actual
circuit and equivalent circuit match
▪ Delay of OD is specified in set_output_delay command
Illustration: set_output_delay
𝑇𝑖𝑛𝑡 + 400 < 𝑇𝑐𝑙𝑘 + 20 − 30 𝑇𝑖𝑛𝑡 + 𝑇𝑂𝐷 < 𝑇𝑐𝑙𝑘
𝑇𝑂𝐷 = 400 − 20 + 30 = 410
create_clock -name SYS_CLOCK -period 2000 [get_ports CLK]

set_output_delay 410 -max -clock [get_clocks SYS_CLK] [get_ports OUT]

Load at Output Port
▪ set_load: load that will be driven by the

output port
set_load 0.039 [get_ports OUT]

Constraints
Functionality

Timing Exceptions
▪ set_false_path: To make exceptions from analysing certain paths that may not be exercised
▪ set_multicycle_path: To inform the STA tool that certain path may take more than one cycle
set_multicycle_path 4 -setup -from [get_pins FF1/CP]

-to [get_pins FF2/D]
set_multicycle_path 4 -setup -from [get_pins

FF1/CP] -to [get_pins FF2/D]
set_multicycle_path 3 -hold -from [get_pins

FF1/CP] -to [get_pins FF2/D]

Constant Value to Port/Pin
▪ set_case_analysis: assign constant value to some port/pin
set_case_analysis 1 [get_ports SCAN_ENABLE]
set_case_analysis 1 [get_ports SLEEP_MODE]

References
2023.
▪ Bhasker, Jayaram, and Rakesh Chadha. Static timing analysis for nanometer designs: A
practical approach. Springer Science & Business Media, 2009.
soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

GDS
Lecture 27
Technology Mapping
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Technology Mapping

Technology Mapping: Framework
Technology Libraries
▪ Cells with different logic functions
▪ Cells with same function, but of
different sizes
Unmapped Netlist:
▪ Netlist of generic logic gates
Constraints: Mapped Netlist:

▪ Synopsys Design Constraint (SDC) file ▪ Netlist consisting of library cells
▪ Objectives: ▪ Functionally equivalent to unmapped
➢ Minimize area under a given delay netlist
constraint
➢ Minimize delay under a given area
constraint

Illustration of Mapping: Given Problem
Logic Function:
′
▪ 𝑌 = 𝐴. 𝐵 + 𝐶

Illustration of Mapping: Solution 1
Given: 𝑌 = 𝐴. 𝐵 + 𝐶 ′
Logic Function:
′
𝑌 = ( 𝐴. 𝐵 ′ . 𝐶′)′
= 𝐴. 𝐵 ′ . 𝐶 ′
= 𝐴. 𝐵 + 𝐶 ′

Logic Function:
𝑌 = 𝐴. 𝐵 ′ . 𝐶′
= 𝐴. 𝐵 + 𝐶 ′

Logic Function:
′
𝑌 = ( 𝐴. 𝐵 ′ . 𝐶′)′

Summary of Solutions
Area Delay Power Comments
Solution 1 10 20 50 Minimum Area
Solution 2 13 17 55 Minimum Delay
Solution 3 12 28 22 Minimum Power

Technology Mapping: Approaches
Two approaches:
▪ Structural Mapping
▪ Boolean Mapping

References
▪ G. D. Micheli. “Synthesis and Optimization of Digital Circuits”. McGraw-Hill Higher Education,
1994.

2023.

GDS
Lecture 28
Timing-driven Optimizations
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Timing-driven Optimizations

Timing-driven Optimization: Flow

Timing Driven Optimization: Resizing
▪ Libraries contain cells of same functionality Resizing:
and different sizes ▪ Replace a cell C1 with another cell C2
➢ Size of the cell increases, delay that produces the same Boolean function
decreases but has a different size
Example: cell C1 replaced with a functionally

equivalent cell C2 of a larger size
Effects:
1. Delay and output slew of C2 can
reduce
➢ Delay of cells in the fanout of C2
can also reduce
2. Delay and output slew of the driver of
C2 can increase
➢ Delay of the cells in its fanout,
including that of C2, can increase

Timing Driven Optimization: Restructure (1)
Rewiring:
▪ Timing critical signals are moved closer to the sink in a cone of logic to reduce the overall
path delay

Timing Driven Optimization: Restructure (2)
Shannon Expansion
▪ 𝐹0 = 𝐹(0, 𝑥1 , 𝑥2 , … , 𝑥𝑁 )
▪ 𝐹1 = 𝐹(1, 𝑥1 , 𝑥2 , … , 𝑥𝑁 )
𝑌 = 𝐹(𝑥0 , 𝑥1 , 𝑥2 , … , 𝑥𝑁 )
▪ Let 𝑥0 be the signal that arrives last (AT

of 𝑥0 is greatest) and is on the critical
path
▪ How to restructure the circuit such that
the worst delay of the circuit improves?

Restructure: Illustration
Arrival Time: 145 ps
𝑍 = 𝐹 𝐴, 𝐵, 𝐶 = 𝐴𝐵 + 𝐶
Arrival Time: 130 ps
𝐹𝐵=0 = 𝐶
𝐹𝐵=1 = 𝐴 + 𝐶

Fanout Optimization
Fanout optimization: inserting buffers in a high-fanout

Retiming
Retiming: balance the amount of logic between registers

References
2023.

GDS
Lecture 29
Power Analysis
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Power Analysis:
▪ Components of Power Dissipation
▪ Power Models in Library
▪ Estimating Power Dissipation

Components of Power Dissipation
Power dissipation is broadly of two types:
1. Dynamic Power Dissipation:

➢ Occurs when a circuit performs computation actively
2. Static Power Dissipation:

➢ When the circuit is powered on (supply voltages are applied), but it does not perform
active computation

Dynamic Power Dissipation: Switching Power
Switching power dissipated in a

synchronous circuit:
2
𝑃𝑠𝑤 = 𝐶𝐿 𝑉𝐷𝐷 𝛼𝑓𝑐𝑙𝑘
where,
▪ 𝑓𝑐𝑙𝑘 =frequency of the clock in
the circuit
▪ 𝛼 =activity of the signal
➢ define 𝛼 = 1 when the output
completes one cycle of
transition (1→0→1) in one
▪ Energy dissipated in one
cycle of 0→1→0 clock period
transition:
2
𝐸𝑠𝑤 = 𝐶𝐿 𝑉𝐷𝐷

Dynamic Power Dissipation: Short circuit Power
▪ Short circuit power dissipation:

𝑃𝑠𝑐 = 𝑉𝐷𝐷 𝐼𝑆𝐶
▪ Power dissipated when short circuit condition

occur:
𝑃𝑑𝑦𝑛 = 𝑃𝑠𝑤 + 𝑃𝑠𝑐

Static Power Dissipation
▪ Static power dissipation occurs because of:

➢ Subthreshold current
➢ Gate Leakage
➢ Junction Leakage
▪ 𝑃𝑠𝑡𝑎𝑡 = 𝑉𝐷𝐷 𝐼𝑙𝑒𝑎𝑘
Total power dissipation in a circuit:

𝑃𝑡𝑜𝑡 = 𝑃𝑑𝑦𝑛 + 𝑃𝑠𝑡𝑎𝑡

Technology Library Models: Dynamic Power
Energy dissipated in one cycle of 0→1→0 transition:
2
𝐸𝑑𝑦𝑛 = 𝐶𝐿 𝑉𝐷𝐷 + 𝑉𝐷𝐷 𝐼𝑆𝐶 𝜏𝑆𝐶
2
𝐸𝑑𝑦𝑛 = (𝐶𝑑 +𝐶𝑤 + 𝐶𝐼 )𝑉𝐷𝐷 + 𝑉𝐷𝐷 𝐼𝑆𝐶 𝜏𝑆𝐶
We can write:
2 2
𝐸𝑑𝑦𝑛 = 𝐶𝑑 𝑉𝐷𝐷 + 𝑉𝐷𝐷 𝐼𝑆𝐶 𝜏𝑆𝐶 + (𝐶𝑤 +𝐶𝐼 )𝑉𝐷𝐷 = 𝐸𝑖𝑛𝑡 +𝐸𝑒𝑥𝑡
▪ Energy dissipated inside a cell 𝐸𝑖𝑛𝑡 is the property of the cell and
modelled in the library
▪ Energy dissipated outside a cell 𝐸𝑒𝑥𝑡 depends on the
environment (external load)
➢ Tools can compute it after (𝐶𝑤 +𝐶𝐼 ) is known
▪ Power can be estimated using energy per transition by
multiplying with activity and clock frequency

Non-linear Power Model (NLPM)
▪ Internal power dissipation depends on the
output-load and input slew u_table_template(index_1) {
▪ Modelled as two-dimensional table named variable_1 : input_net_transition ;
internal_power variable_2 : total_output_net_capacitance ;
index_1( "10, 20, 30" ) ;
➢ Referred to as Non-linear Power index_2( "1.2, 5.0,15.0, 37.5) ;
Model (NLPM) }
….
pin(Z) {
internal_power() {
related_pin : “A" ;
rise_power(index_1) {
values( "4, 5, 7, 12, …3x4 table);
}
▪ Rise and fall power can be represented as …
}
different arcs }
▪ Values represent energy dissipated per S. Saurabh, “Introduction to VLSI Design Flow”.Cambridge
University Press, 2023.
transition

Technology Library Models: Static Power
▪ Static power dissipated inside a CMOS

logic gate depends on the value (0 or 1) cell (NAND2) { ...
at its input pin cell_leakage_power : 125;
leakage_power () {
▪ Modeled using when condition in the when : “!A & !B”; value : 20; }
library leakage_power () {
when : “A & !B”; value : 150; }
leakage_power () {
when : “!A & B”; value : 200; }
leakage_power () {
when : “A & B”; value : 300; } ...
S. Saurabh, “Introduction to VLSI Design Flow”.Cambridge
University Press, 2023.

Estimating Power Dissipation
2
𝑃𝑡𝑜𝑡 = 𝐶𝐿 𝑉𝐷𝐷 𝛼𝑓𝑐𝑙𝑘 + 𝑉𝐷𝐷 𝐼𝑆𝐶 + 𝑉𝐷𝐷 𝐼𝑙𝑒𝑎𝑘
▪ Computing power dissipation is a
where, challenging problem.
▪ 𝑉𝐷𝐷 = supply voltage ➢ Capacitance estimation
▪ 𝐶𝐿 = load capacitance ➢ Accounting for the activity of signals
▪ 𝑓𝑐𝑙𝑘 = frequency of the clock in the circuit
▪ 𝛼 = activity of the signal
Activity of a signal depends on:
▪ Application being run on an IC
▪ Logical structure and the circuit topology

Estimation of Activity
Simulation-based Techniques (Vector-based Technique):
▪ Perform simulation using test bench.
▪ Simulator generates the output response for all the nets [value change dump (VCD) files]
➢ Convert a VCD file into a format from which the activity measures can be easily
extracted [switching activity interchange format (SAIF)]
➢ Provide the SAIF file to the power analysis tool
➢ Tools can also assume default activity [such as 0.2]
Probabilistic Techniques (Vector-less Technique):
▪ Propagate the activity measures through the circuit by considering the logic function of the
gates encountered in the path
▪ Example: Assume that static probabilities of signals A and B are 𝑃1𝐴 = 0.5 and 𝑃1𝐵 = 0.3
➢ If they propagate through an AND gate: 𝑃1𝐴.𝐵 = 𝑃1𝐴 . 𝑃1𝐵 = 0.5 × 0.3 = 0.15
➢ If they propagate through an OR gate: 𝑃1𝐴+𝐵 = 1 − (1 − 𝑃1𝐴 ) 1 − 𝑃1𝐵 = 1 − 0.5 × 0.7 =
0.65

References
▪ N. H. Weste and D. Harris. “CMOS VLSI Design: A Circuits and Systems Perspective”. Pearson
Education India, 2015.
2023.

GDS
Lecture 30
Power Optimizations
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Overview of power-driven optimizations

Strategies for Reducing Power Dissipation
2
𝑃𝑡𝑜𝑡 = 𝐶𝐿 𝑉𝐷𝐷 𝛼𝑓𝑐𝑙𝑘 + 𝑉𝐷𝐷 𝐼𝑆𝐶 + 𝑉𝐷𝐷 𝐼𝑙𝑒𝑎𝑘 Power saving strategies:
where, ▪ Reduce supply voltage
▪ 𝑉𝐷𝐷 = supply voltage ▪ Reduce clock frequency
▪ 𝐶𝐿 = load capacitance ▪ Reduce activity of the signal
▪ 𝑓𝑐𝑙𝑘 = frequency of the clock in the circuit ▪ Reduce load capacitance
▪ 𝛼 = activity of the signal

Dynamic Voltage Frequency Scaling (DVFS)
▪ Utilizes the strategy of reducing supply voltage and clock frequency
▪ Popular technique employed in processors:

➢ Exploit variations in workload to save energy
➢ Full speed of a processor is utilized by only a few tasks or for a small time duration.
➢ For the remaining period, the deadlines can be met at low speed and consuming
significantly less energy
Illustration:
▪ Consider a processor that can perform a task in 10 ms at 1.2 GHz and 1.2 V.
▪ Let us reduce the clock frequency and the supply voltage to half (600 MHz, 0.6 V),
➢ Task will now complete in double the original time, i.e., 20 ms.
➢ Will reduce the switching power dissipation by 1/8 (𝑃𝑡𝑜𝑡 ∝ 𝑉𝐷𝐷2
𝑓𝑐𝑙𝑘 )
➢ Will reduce the energy consumption by 1/4

Power Gating
▪ Utilizes the strategy of eliminating supply voltage
Power Gating:
▪ Switch off the power supply for a block
▪ Effective technique to tackle both static and dynamic components of power dissipation.
▪ Requires a careful circuit design and inserting specially designed circuit elements.

Power Gating: Circuit Elements
Circuit Elements
▪ Switch Cell
▪ Retention Cell
▪ Isolation Cell

Clock Gating
▪ Utilizes the strategy of reducing activity
Assume that there is a set of 𝑁 flip-flops that

captures new data conditionally
▪ Shut off the clock when that condition is
false
▪ Save power in charging/discharging
capacitors in the clock network, including
flip-flops
▪ Find enabling condition of clocking
▪ Simple AND of EN and CLK will lead to glitch

Clock Gating: Integrated Clock Gater
Integrated Clock Gater (ICG)
▪ Logic gate with an enable

signal so that clock is
propagated when the 𝐸𝑁 = 1
▪ Latch (negative sensitive)

allows EN to propagate only
when CLK is low
▪ When CLK is high, Latch (LT)

output is stable and glitch
cannot propagate

Resizing
▪ Resize cells to reduce power dissipation
➢ For example, we can use smaller cells in the noncritical path of a circuit
➢ Reduce the power dissipation due to the reduced load capacitances

References
2023.

GDS
Lecture 31
DFT: Basic Concepts
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Basic Concepts
related to DFT

Structural Testing
Consider a circuit that implements a Boolean function with 𝑁 inputs.
How to test the fabricated circuit?
Functional Testing:
▪ Apply all possible 2𝑁 input combinations and check output
▪ Becomes infeasible for large 𝑁 (say 50 or 100)
Structural Testing:
▪ Test the components that implements a logic function rather than testing the input–output
functionality
▪ The paradigm of structural testing is widely employed
➢ It reduces the number of test patterns required for good test quality

Functional Testing vs. Structural Testing
Functional Testing
▪ Will require 216 = 65536 input combinations
Structural Testing
▪ Test individual components of the circuit ( G1, G2, G3, G4,
and G5)
▪ Each gate will require 24 = 16 input combinations (total 80)
Assumptions
▪ Can observe the output pins for all the components
▪ Can write any value at the input pins of all the components
▪ There could be a problem in the integration of components
(need to tackle that also).
DFT techniques tries to make structural testing more effective

by ensuring the above assumptions.

Fault Models
Fault Model
▪ Represents a defect using a logical or electrical
model
Why do we use a Fault Model?

▪ Allows us to analyze the impact of a defect using
logic or circuit analysis techniques
▪ Allows deriving test patterns algorithmically for
detecting a given fault
➢ Quantitative assessment of testing
effectiveness using fault coverage
▪ Transforms the problem of defect detection to the

problem of fault detection

Stuck-at Fault Models
Stuck-at Fault Model
▪ Assumes that defects cause the signal to be
permanently stuck at a constant logic
▪ Transforms defects to a logical fault model
▪ Two types:
➢ Stuck at logic “0”: stuck-at-0 or SA0 fault
➢ Stuck at logic “1”: stuck-at-1 or SA1 fault
Single Stuck-at Fault Model

▪ Assumes that there is only one fault active at a
time
▪ Reduces the complexity of test pattern generation
significantly

Stuck-at Faults: Fault-site
Fault-site:
▪ The point where a fault exists or we assume it to exist
▪ Emulate a stuck-at fault by first disconnecting the corresponding signal source.
▪ Tie it to the constant logic (either 0 or 1 depending on the fault type)
Multi-fanout net (N>1):

▪ (N+1) fault sites
Fanout-free net:
▪ 1 fault site

Possible Stuck-at Faults: Illustration
▪ Consider the circuit alongside

▪ How many single stuck-at (0/1) faults are
possible in this circuit?
Answer: 18

Detecting a Fault: Test Vectors
Test Vectors
▪ Any input pattern, or sequence of input patterns, that produces a different output response
for a faulty circuit and a fault-free circuit
Exhaustive Testing for functionality
▪ Exponential number of test vectors required (2𝑁 ) to test the

functionality
Single stuck-at fault model makes the number of fault linear in the number of circuit elements

Design for Testability: Test Vectors
Stuck-at 0 Stuck-at 1
A B C D Z A/0 B/0 C/0 D/0 Z/0 A/1 B/1 C/1 D/1 Z/
1
0 0 0 0 1 1 1 1 1 0 1 1 1 1 1
0 0 0 1 1 1 1 1 1 0 1 1 1 1 1
0 0 1 0 1 1 1 1 1 0 1 1 1 1 1
Test Vectors 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1
0 1 0 0 1 1 1 1 1 0 1 1 1 1 1
▪ 1111 (A/0, B/0,
C/0, D/0, Z/1) 0 1 0 1 1 1 1 1 1 0 1 1 1 1 1
0 1 1 0 1 1 1 1 1 0 1 1 1 1 1
▪ 0111 (A/1, Z/0)
0 1 1 1 1 1 1 1 1 0 0 1 1 1 1
▪ 1011 (B/1, Z/0)
1 0 0 0 1 1 1 1 1 0 1 1 1 1 1
▪ 1101 (C/1, Z/0)
1 0 0 1 1 1 1 1 1 0 1 1 1 1 1
▪ 1110 (D/1, Z/0)
1 0 1 0 1 1 1 1 1 0 1 1 1 1 1
1 0 1 1 1 1 1 1 1 0 1 0 1 1 1
1 1 0 0 1 1 1 1 1 0 1 1 1 1 1
𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑡𝑒𝑠𝑡
𝑣𝑒𝑐𝑡𝑜𝑟𝑠 = 𝑛 + 1 1 1 0 1 1 1 1 1 1 0 1 1 0 1 1
1 1 1 0 1 1 1 1 1 0 1 1 1 0 1
1VLSI Design
1 1Flow: 1RTL to0GDS 1 1NPTEL 2023
1 1 S. Saurabh
0 0 0 0 0 1
Combinational Circuit: Controllability and
Observability
▪ If the NAND gate was lying too deep in a
circuit, it is difficult to apply the required test
vectors at the inputs
Controllability: ability to set any desired value (0

or 1) on the internal signals of a circuit by
applying an appropriate test-vector to the
primary inputs.
▪ Similarly the output of NAND gate will be

difficult to observe at any primary output if the
NAND gate is lying too deep in circuit
Observability: ability to examine any internal

signal by propagating its value to a primary
output by applying appropriate test vector to the
primary inputs.

Sequential Circuit: Controllability and Observability
Problem of controllability
▪ Setting a particular value at any pin in a sequential

circuit is more difficult
➢ Several cycles may be required to write a
particular value
➢ State traversal required
➢ Finding such a test sequence is time consuming
by sequential ATPG tool
Problem of observability
▪ Similar difficulty in examining the value at a

particular pin in the sequential circuit (requires state
traversal)

References
▪ M. Bushnell and V. Agrawal, “Essentials of electronic testing for digital, memory and mixed-
signal VLSI circuits”, Springer Science & Business Media, 2004.
2023.

GDS
Lecture 32
Scan Design Flow
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Scan Design Flow
▪ Design Modifications
▪ Mechanism of Testing
▪ Tasks

Scan Design Flow: Design Modifications
▪ Extra primary ports added
➢ TM (Test Mode)
➢ SE (Scan Enable)
➢ SI (Scan In)
➢ SO (Scan Out)
▪ D flip-flops replaced with
another memory elements
(scan cells)
▪ Scan cells are reconnected
to form shift register (scan
chain)
Effect
▪ Dramatically improve controllability and observability of memory elements (flip-flop) in a

sequential circuit

Scan Design Flow: Different Modes
Design works in three modes:
1. Normal Mode: functional mode in which chip
works
2. Shift Mode:
➢ Memory elements (i.e. scan cells) work as
shift registers
➢ Test vectors are shifted-in and responses
are shifted-out
3. Capture Mode: response of the fabricated
circuit is captured during testing
Mode TM SE
Normal 0 0
Shift 1 1
Capture 1 0
Scan Cells
▪ Different kinds of scan cell can be ▪ The multiplexer selects data between D and SI
used using the value at SE pin
▪ Most popular is MUXED-D Scan Cell
▪ In the normal/capture mode: SE=0
➢ Value at D is latched
▪ In the shift mode, SE=1

➢ Value at SI is latched
➢ Output pin produces the content of D flip-flop

➢ Next State could be of D-pin or SI-pin
▪ D, CLK, Q similar to D flip-flop

▪ SI ≡ scan input
▪ SE ≡ scan enable
▪ Q also works as SO≡ scan out

Scan Design Flow: Forming Scan Chain (Example)
▪ The SI pin of the first scan cell is
connected to the SI port
▪ Q/SO pin of one cell is connected to
SI pin of the next cell to form a chain
▪ Q/SO pin of the last scan cell is
connected to the SO port
▪ All SE pins of scan cells are connected
to the SE port
▪ Form a scan chain consisting of 𝑁 scan
cells
▪ Any test vector can be shifted-in from
SI port in 𝑁 clock cycles
▪ Any test response can be shifted-out
to SO port in 𝑁 clock cycles
▪ No changes made to the previous ▪ Without scan chain, it could take
connections of D, Q and CLK pins exponential number of cycles

Scan Design: Sequential to Combinational Circuit
Testing
▪ Pins of a flip-flop becomes
controllable/observable from
primary input/output
➢ Q-pin can be treated as
pseudo-primary input (PPI)
➢ D-pin can be treated as
pseudo-primary output (PPO)
Scan design eases of testing:

▪ Effectively transforms the problem of sequential circuit testing to combinational circuit
testing
▪ Automatic test pattern generation (ATPG) problem effectively changes from sequential to
combinational

Scan Design Flow: Mechanism
Shift Mode: set SE=1.

▪ Shift in the desired test vector using
port SI to the scan cells F1, F2, F3.
▪ Apply the required test vector at input
port also.
Capture Mode: set SE=0 for 1 clock cycle.

▪ If there was a fault for which test vector was applied, scan cells will capture the result of
fault and receive “fault” output
Shift Mode: switch back to shift mode (SE=1)

▪ Shift out the captured result to the port SO.
▪ The result is compared with the expected response
▪ Simultaneously, apply next test vector at port SI and allow it to scan-in through the scan
chain.
Scan Design Flow: Tasks
Design Preparation: Design becomes testable
▪ Guidelines that must be followed during designing such that scan design flow can be
used effectively
Scan Synthesis: Design becomes Scan Design
▪ Scan Configuration (During Synthesis)
➢ Decide number of scan chains, scan cells to be used, exclude certain elements
from being converted to scan cells
▪ Scan Replacement (During Synthesis)
➢ Replace Flip-Flops with Scan Cells
▪ Scan Reordering and Stitching (During Physical Design)
➢ Reorder scan cells based on physical location so that routing becomes easier
▪ Test Vector Generation

▪ Scan Verification
➢ Scan Shift/Capture Operation using logic simulator
➢ Verify Timing (STA): Hold Violations
Scan Design Flow: Cost
▪ Area Overhead: Scan Cell, Routing resource
▪ IO Pin Cost
▪ Performance degradation: added delay of multiplexor
▪ Design Effort Cost

References
2023.

GDS
Lecture 33
Automatic Test Pattern Generation (ATPG)
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Terminologies
▪ General approach to ATPG
▪ Redundant Faults

Talking to a kitten …
“… they always purr. ‘If they would only purr for “yes” and
mew for “no,” or any rule of that sort’ she had said, ‘so that
one could keep up a conversation!
But how can you talk with a person if they always say the
same thing?’
On this occasion the kitten only purred: and it was

impossible to guess whether it meant ‘yes’ or ‘no’.”
—Lewis Carroll, Through the Looking-Glass, Chapter

12, 1871
Source:
https://commons.wikimedia.org/wiki/File:Lew
isCarrollSelfPhoto.jpg Lewis Carroll, Public
domain, via Wikimedia Commons

ATPG: Objective, Challenges and Practical Solution
ATPG: Automatic Test Pattern Generator Challenges
▪ Objective: Generate test patterns (test ▪ For generalized sequential circuits,

vectors) that can be used to detect faults generating test vectors/sequences is very
difficult
▪ Desired: small set of test vectors that ➢ Reaching certain states may take
detect all faults considered for that exponential clock cycles
circuit
▪ Finding the test sequence that controls or
observes an internal point in the circuit is
runtime intensive
Practical Solution
▪ Sequential ATPG problem is transformed to Combinational ATPG problem by Scan Design
Flow
▪ Combinational ATPG problem, though NP-complete, has efficient algorithms

ATPG: Terminologies
▪ Path: sequence of pins in topological order

▪ On-path input or on-input: for a given path, the input pins lying on that path
▪ Side path inputs or side-inputs: The input pins other than the on-inputs of the instances lying
on that path

ATPG: Controlling/Non-controlling values
Type of Gate Controlling Non-
Controlling value of a multi-input gate
Value controlling
▪ Value that can be assigned to any input of value
the gate such that the output is known
irrespective of values on other inputs. AND 0 1
Non-controlling value of a multi-input gate NAND 0 1

▪ Value that can be assigned to any input of
the gate such that the output is decided OR 1 0
by the value on other inputs
NOR 1 0
XOR Not defined Any value

ATPG: General Approach
Path Sensitization Method
▪ Fault Sensitization
▪ Fault Propagation
▪ Line Justification

ATPG: Illustration of Path Sensitization Method
▪ Fault Sensitization: Find the value at input ports
that will set the value at the fault site opposite
of the fault value
▪ Find A, B, C, D such that G4/X1=0 (A=1,
B=1)
▪ Fault Propagation: For the path from the fault

site to the output port, set the value of side-
inputs to non-controlling inputs
➢ Set G4/X2 to non-controlling value
Given: Stuck-at 1 at G4/X1 (G4/X2=1)
To Find: A test vector (value of A, B, C, ▪ Line Justification: Find the value at input ports
D) which will be able to detect the that will set the side-inputs as found in fault
existence of SA1 at G4/X1 propagation
➢ Find A, B, C, D such that G4/X2=1 (C=0
D=0)
Test Vector: (1,1,0,0)

ATPG: Illustration of Backtracking
➢ Find A, B, C, D such that G3/Y=1 (B=1, C=0)
▪ Fault Propagation: Path to Y

➢ Set G5/X1 to non-controlling value (i.e. 1)
▪ Line Justification: A=0, B=0

➢ B=0 is in conflict!
➢ Must be Backtracked
Given: Stuck-at 0 at G3/Y ▪ Fault Propagation: Path to Z

➢ Set G6/X2 to non-controlling value (i.e. 0)
To Find: A test vector to detect this
fault. ▪ Line Justification: C=0 D=0
Test Vector: (x,1,0,0)

ATPG: Illustration of Redundant Fault
➢ Find A, B, C such that G3/X1=0 (B=0)
▪ Fault Propagation:
➢ For Propagation to Z: Set G3.X2=1
and G4/X1=0
▪ Line Justification:
➢ B=1 is in conflict with earlier B=0
Given: Stuck-at 1 at pin G3/X1 ▪ No test vector exists to detect this fault
To Find: A test vector to detect this fault ▪ This is known as redundant fault

ATPG: Redundant Fault based Optimization
▪ Redundant faults can be used to reduce the hardware
▪ Redundant fault means that the behavior of the circuit with/without fault is the same
▪ Assume that the fault site has constant 0/1 optimize out gates that are not required
▪ Assume that SA1 at G3/X1 is always present.
▪ G3/X1=1 implies that G3/Y =C

ATPG: Challenges and Solutions
Complications Backtracking Limit
▪ Primarily due to re-convergent fanouts ▪ Too many backtrack => possible
redundant fault
▪ Decisions required to be taken at a
particular point ▪ User defined Backtrack Limit employed by
tool
▪ Decision leads to implications
➢ Example Backtrack Limit = 1000
▪ Some decisions can be wrong (leading to ➢ Abort finding test vector when
conflicts in decisions) backtrack limit is hit, i.e. when 1000
➢ Backtracking required times backtracking has been done
Algorithmic Advancements
▪ D-algorithm: Roth 1966
▪ PODEM (Path-oriented Decision Making): Prabhu Goel 1981
▪ FAN (Fanout-oriented) Algorithm: Fujiwara

References
▪ M. Bushnell and V. Agrawal, “Essentials of electronic testing for digital, memory and mixed-signal
VLSI circuits”, Springer Science & Business Media, 2004.
▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023.

GDS
Lecture 34
Built-in Self-test (BIST)
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Distinguishing Features
▪ Architecture
▪ Random Test Pattern Generation
▪ Test Response Analyser

Built-in Self Test (BIST)
Drawbacks of ATE-based testing: BIST as a solution:

▪ Cost of testing high ▪ Test-oriented additional hardware and
➢ ATE cost software features inside a given IC
➢ Voluminous test data: increase test time ▪ Allows IC to test their own operation
▪ Can be done only in production test ▪ Reducing dependence on an external
environment ATE for testing
➢ Lacks capability of field testing ➢ Repair in the field possible
▪ At-speed test difficult
➢ Probe’s inductance/capacitance
bottleneck

Built-in Self Test (BIST): Distinguishing Features
1. Contains Pseudo-random pattern generator inside the chip

➢ Provides test vectors dynamically
➢ Avoids storing voluminous test vectors
2. Performs signature analysis for detecting failures

➢ Does not perform comparison of exact response
➢ Avoids storing voluminous expected response inside the chip

Testability: Fault Coverage vs. Random Test Pattern
Count
▪ Stuck-At Fault coverage rises to 100% logarithmically
▪ Reaching 90% coverage is easy using random patterns

BIST: Architecture
▪ Test Pattern Generator (TPG)
➢ Generates pattern for testing
➢ Can contain ROM
▪ Test Response Analyzer (TRA)
➢ Generates signature for the test
response and compare
➢ ROM stores golden signature
➢ Compares test signature with the
golden signature
▪ Test Controller
➢ Controls all the operations of
BIST
➢ Strategy for overall test control is
most difficult part of BIST

BIST: Test Pattern Generator
▪ Pseudo-Random Pattern Generator
➢ Linear Feedback Shift Register
(LFSR)
➢ Repeatable
➢ Small hardware can produce large
number of “random” test patterns
▪ We can tap the output of any flip-flop

to provide feedback. 𝑎0𝑘+1 = 𝑎1𝑘
▪ If we tap the output 𝑎𝑖 of the i-th flip- 𝑎1𝑘+1 = 𝑎2𝑘

flop, then ℎ𝑖 is taken as 1, else it is
taken as 0. ….
𝑘+1 𝑘
𝑎𝑛−2 = 𝑎𝑛−1
𝑘+1
𝑎𝑛−1 = 𝑎0𝑘 ⊕ ℎ1 𝑎1𝑘 ⊕ ℎ2 𝑎2𝑘 ⊕ … ⊕ ℎ𝑛−1 𝑎𝑛−1
𝑘

Pattern Generator: Illustration
𝑎0𝑘+1 = 𝑎1𝑘
𝑎1𝑘+1 = 𝑎2𝑘
𝑎2𝑘+1 = 𝑎0𝑘 ⊕ 𝑎1𝑘

Pattern Generator: Considerations
▪ LFSR
➢ Test patterns generated by an LFSR have most of the properties of random numbers
➢ Desirable to have long sequence so that good fault coverage is achieved
▪ Some faults may be not covered by random pattern generator

➢ Use ATPG to get deterministic test-vector and put those test-vectors in ROM
➢ Helps achieve high fault coverage with small number of test vectors

BIST: Test Response Analyzer (1)
▪ No. of test patterns can be large (e.g. 1 million) and there can be many outputs (e.g. 100)
➢ Too voluminous data to store in ROM (100 million bits)
▪ Compaction: method of reducing the number of bits in the circuit response
▪ Signature: a statistical property of a circuit, usually a number computed for a circuit from its
responses
▪ Signature Analysis: signature of a good circuit (“golden signature” ) compared with the
signature of a “potentially” faulty circuit (“test signature”)
➢ If “golden signature” matches “test signature” then the circuit is assumed to be good,
else faulty
➢ Desirable: signature of a good circuit and faulty circuits are different
▪ Aliasing: During testing, it is possible that the signature of “good” circuit and “faulty” circuit
match
➢ Due to information loss during compaction
BIST: Test Response Analyzer
▪ Techniques to compute
Signature
➢ Ones Counting: count
number of ones across all
circuit responses
❑ Different permutations
can yield same
signature
➢ Modular LFSR: Extra XOR
gate at the input
❑ Single Input Signature
Register (SISR)
❑ Need to start with a
seed value

Built-in Self Test (BIST)
Advantages Disadvantages
▪ Lower cost of test, since the need for ▪ Additional silicon area
external electrical testing using an ATE ➢ Yield and Reliability decrease
will be reduced
▪ Performance loss
▪ No need to store test patterns ➢ Extra delays
▪ At-speed test can be done ▪ Additional pin (and possibly bigger
package size) requirements
▪ Capability to perform tests outside the
production electrical testing
environment

References

2023.

GDS
Lecture 35
Basic Concepts for Physical Design - I
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Fabrication of IC
▪ Interconnects
▪ Parasitics in Interconnects

Physical Concepts for
Physical Design
IC Fabrication

IC Fabrication
▪ Photolithography is the key step in fabrication
Two phases:
1. Front End Of the Line (FEOL) processes: active elements (transistors, diodes,
capacitors)
2. Back End Of the Line (BEOL) processes: layers of wires

FEOL Processes (1)
▪ Doping with acceptor and donor atoms
▪ Ion Implantation:
➢ Appropriate ions created, using arc
discharge
▪ accelerated/filtered using
electric and magnetic fields
➢ Bombard the substrate through a thin
layer of screening silicon dioxide
▪ Annealing: activate dopants
▪ Threshold voltage adjustment implants
▪ Isolation: ensures that the transistors do

not interact through the substrate
▪ Shallow Trench Isolation (STI)

FEOL Processes (2)
Transistor formation (gate, source and
drain)
▪ High quality gate oxide

growth/deposition over silicon
channel
▪ Polysilicon deposition for gate

contact
➢ Chemical vapor deposition (CVD)
▪ Patterning
➢ Local interconnect
▪ Source-drain Ion Implantation and

annealing for NMOS and PMOS

BEOL Processes (1)
Back End Of the Line (BEOL):

▪ Layers of Wires
▪ Inter Layer Dielectric (ILD)
▪ Copper
➢ Dual Damascene Process
➢ Repeated for each layer

Physical Concepts for
Physical Design
Interconnects/Wires

Interconnect Layers (1)
Metal Layers Two Types:
➢ Wiring layers: metal layers making interconnection
o Parallel to wafer surface
➢ Via Layers: connects wiring layers
o Perpendicular to wafer surface
▪ Interconnects have uniform thickness (height)

➢ Can be represented as 2D polygons
▪ Shapes of wires in the layout decide where metal needs
to be deposited during fabrication

Interconnect Layers (2)
▪ High performance IC can use 15 metal layers
▪ Metal Layers are separated by dielectrics :

generally SiO2
➢ Low-k material can also be used
▪ Height of wiring layers can be different in

different layers
▪ In general: metal height increases from the

bottom to the top of an IC
▪ Each wiring layer has a preferred direction:

vertical or horizontal
▪ Each successive wiring layers alternate between
vertical and horizontal direction
➢ Can lead to increase in via count

Basic Concepts for
Physical Design
Interconnect
Parasitics

Interconnect: Resistance
▪ Resistance:
𝐿
𝑅=𝜌
𝑇𝑊
𝐿 𝜌
▪ 𝑅 = 𝑅𝑆 𝑊 where 𝑅𝑆 = 𝑇 is called the
sheet resistance
▪ Sheet resistance is defined in the
library
▪ At high frequency, the resistance of an interconnect tends to increase

➢ Skin effect: current tends to flow primarily on the conductor’s surface
➢ Important for wider and thicker wires at the top metal layers (clock lines that work at
high frequency)

Interconnect: Capacitance
Origin of interconnect Capacitance:
▪ Interconnects lie within a dielectric material
▪ Electric potential of interconnects changes during circuit operation
➢ Electric field and the stored charges in the surrounding dielectric material change.
➢ Consequently, an interconnect exhibits substantial capacitance
Factors influencing Interconnect Capacitance:

▪ Depends on their geometry, environment (the location and geometry of other
interconnects), and the property of the surrounding dielectric.
▪ The computation of interconnect capacitance is a nontrivial problem.

Interconnect: Capacitance of Strip
Two Components: ▪ Both these components can be added

𝜖𝑑 𝜖0
1. Parallel plate component: 𝐶𝑝𝑝 = 𝑊𝐿 together
𝑇𝐷
2. Fringe component: field lines that emanate ▪ With technology advancement, fringe
from the sidewalls capacitance is increasing

Multiple Interconnects: Capacitance
▪ Electric field lines emanating from
an interconnect are modified by
the neighboring interconnects in a
complicated manner
Three major components of

capacitance:
1. Overlap capacitance: due to the
overlap between two conductors
in different planes.
2. Lateral capacitance: formed by
two parallel edges of
nonoverlapping conductors in
the same plane.
3. Fringe capacitance: between two
conductors in different planes
due to electric fields originating
from the sidewalls
References
▪ J. M. Rabaey, A. Chandrakasan, and B. Nikolic. “Digital integrated circuit design: A Design

Perspective”, Prentice Hall, 2nd ed., 2002.
▪ N. D. Arora, K. V. Raol, R. Schumann, and L. M. Richardson. “Modeling and extraction of

interconnect capacitances for multilayer VLSI circuits.” IEEE Transactions on Computer-aided
Design of Integrated Circuits and Systems 15, no. 1 (1996), pp. 58–67.
2023.

GDS
Lecture 36
Basic Concepts for Physical Design - II
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Signal Integrity
▪ Antenna Effect
▪ Library Exchange Format (LEF) files

Signal Integrity

Effects of Coupling of Interconnects
Impact of coupling capacitance among interconnects
▪ Voltage in one interconnect can impact the voltage in the other
▪ Can create signal integrity problems in a circuit
Signal Integrity Issues
Dynamic Delay Variations Functional Issues

Signal Integrity
Dynamic Delay
Variations

What is base delay?
Consider the portion of a circuit
▪ Let us assume A is the victim
➢ The signal line at which we observe the signal
integrity issue is known as the victim line
▪ Assume gate G1 (driver of the victim net A) makes a
0→1 transition at the output.
➢ The driver G1 provides charge for the ground
capacitor CG to change from 0 to VDD.
Case1: B is held constant to 0

▪ G1 needs to provide a charge for the coupling ▪ The delay computed by assuming
capacitance Cc to change from 0 to VDD. aggressors are held to constant
▪ Hence, G1 needs to charge CG + Cc. logic is known as base delay.
▪ The base delay is same whether
Case2: B is held constant to 1 aggressor is at 0 or 1
▪ Initially charge on Cc is -VDD and finally 0
▪ Base delay is obtained by
▪ Hence, G1 needs to charge CG + Cc. ignoring SI effects
How is dynamic delay variations created?
▪ Assume gate G1 (driver of the victim net A)
makes a 0→1 transition at the output.
Case1: B also makes a 0→1 transition while A

was transitioning:
▪ Voltage across Cc is 0 V, both initially and
finally.
▪ Hence, less charge needs to be provided by
G1 for charging Cc
▪ Delay of G1 will decrease.
▪ This effect is modeled as negative

incremental delay over base delay

How is dynamic delay variations created?
▪ Assume gate G1 (driver of the victim net A)
makes a 0→1 transition at the output.
Case2: B makes a 1→0 transition while A was

transitioning:
▪ Voltage across Cc is -VDD initially and +VDD
finally.
▪ Hence, in effect, 2Cc needs to be charged by
G1
▪ Delay of G1 will increase.
▪ This effect is modeled as positive

incremental delay over base delay

Signal Integrity
Noise or Glitches

What is a Glitch?
▪ A glitch can occur in a victim net held at constant logic value due to a transition in the
aggressor net.
▪ Glitches are also known as crosstalk noises
Depending on the value of the victim net and the

type of transition at the aggressor nets, four
types of glitches are possible:
a. Logic 0 has a rise glitch,
b. Logic 0 has an undershoot
c. Logic 1 has a fall glitch
d. Logic 1 has an overshoot.

How are Glitches Created?
Consider the portion of a circuit
▪ Let us assume A is the victim
▪ Assume that A is at a steady state of 𝑉𝐷𝐷 [logic 1]
▪ Assume that line B is also at the steady state of 𝑉𝐷𝐷 [logic 1]
▪ Voltage across the coupling capacitor 𝐶𝐶 is 0 V.
▪ Assume that the neighboring line B makes a quick transition

from 𝑉𝐷𝐷 to 0 V
▪ The coupling capacitor 𝐶𝐶 now gets charged to +𝑉𝐷𝐷 due to
voltage difference in lines A and B
▪ The driver of the line A will supply this charge, and it will
cause a temporary dip in the voltage of the line A
▪ Similarly, when the aggressor (line B) makes a 0 to 𝑉𝐷𝐷

transition, there can be a bump in the voltage of the victim
(line A) that was held at logic 0

On what factors the magnitude of glitches depend?
Slew of the aggressor net
➢ Glitch increases when the aggressor
transitions quickly.
Coupling capacitance between the aggressor and
the victim net:
➢ Glitch increases with the increase in the
coupling capacitance.
Ground capacitance of the victim net

➢ Glitch decreases as the ground capacitance
of the victim increases.
Strength of the driver of the victim net

➢ Glitch decreases as the strength of the
driver of the victim net increases.

When does Glitches Cause Functional Problems?
▪ If the magnitude of the glitch is above a threshold, it can propagate to a sequential circuit
element.
▪ Consequently, a wrong value can get latched (0 instead of 1 or 1 instead of 0), leading to a
circuit failure.
▪ If the magnitude of the glitch is above a threshold, on clock/reset/control signal, a spurious

transition can get triggered in a sequential element.
▪ Need to propagate glitches

Basic Concepts for
Physical Design
Antenna Effect

Antenna Effect: Cause
▪ During fabrication before addition of Metal-2, long Metal-1 connected to the gate can
become charged and can destroy the gate
▪ Antenna Ratio: ratio of the conductor area to the gate oxide area
▪ High Antenna Ratio implies greater chance of damage

➢ Antenna Rules defined to allow Antenna Ratio to be within limits
➢ Design Goal: Fix Antenna DRC violations by keeping Antenna Ratio small
Basic Concepts for
Physical Design
Library Exchange
Format (LEF)

Library Exchange Format (2)
▪ LEF file generally divided into two files Technology LEF files:
▪ Information about the available layers and
vias, their properties.
▪ Sheet resistance and capacitance per unit
square for various layers
▪ Placement and routing design rules
▪ Antenna rules
Cell Library LEF files:

▪ Abstract information of the cell layout
relevant to the physical design,
➢ Cell boundary, list of pins and their
locations, and obstructions to
placement and routing.

References
▪ J. M. Rabaey, A. Chandrakasan, and B. Nikolic. “Digital integrated circuit design: A Design
Perspective”, Prentice Hall, 2nd ed., 2002.
▪ J. Bhasker and R. Chadha. “Static Timing Analysis for Nanometer Designs: A Practical Approach”.
Springer Science & Business Media, 2009.
▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023.

GDS
Lecture 37
Chip Planning - I
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Chip Planning
➢ Hierarchical Design Implementation
➢ Floorplanning
➢ Power Planning

Laying plans …
“…While times are quiet, it is easy to take action; ere (before) coming troubles have cast their
shadows, it is easy to lay plans.... A journey of a thousand miles began with a single step.”
—Lao Tzu (ancient Taoist philosopher)

Implementation Methodology
Implementation
Methodology
Hierarchical design
Flat Design Implementation
implementation
Tasks in hierarchical design implementation

1. Partitioning
2. Budgeting
3. Block Implementation
4. Top-level Assembly
Partitioning
How to partition?
▪ Partitions are called blocks
▪ Partition using logical functionality
Other approaches:
▪ Group modules into clusters
▪ Partition a netlist using partitioning algorithm
➢ Reduce the number of cuts or nets crossing blocks
Budgeting
▪ Process of allocating some fraction of a clock cycle to different blocks and the top-level
design for signals crossing block boundaries
▪ Create block level SDC

Block Implementation and Top-level Assembly
Block Implementation Top-level Assembly
➢ Implement each block separately ➢ Integrate all the blocks at the top-level
➢ Use allocated timing budgets and ➢ Carry out verification at the top-level
block constraints (verify at block level) ➢ Omit details of the timing paths
contained entirely within a block
Abstract Timing Model of Blocks:

▪ Retain information of interface
timing paths of the blocks
▪ Extracted Timing Model (ETM)
▪ Interface Library Model (ILM)

Hierarchical Design Methodology: Merits and
Challenges
Advantages:
▪ Physical implementation and other EDA tools need to handle smaller problems
▪ Multiple blocks can be concurrently implemented by different teams
➢ Overall design time decreases
Disadvantages:
▪ Challenging to partition a design optimally
▪ Loose some opportunities of inter-block optimizations

Floorplanning

Floorplanning: Basics
▪ Planning phase of the layout Major Tasks:
➢ Designer’s intent about physical 1. Define die/chip size and aspect ratio
design
2. I/O cell placement
▪ Prepares a design for other physical
design tasks 3. Hard macros/block placement
➢ Huge impact on the final FoM 4. Pin assignment
5. Create rows for standard cells
▪ Must consider routability, performance,
power, etc.

Die Size
Goal: choose smallest size of die that
can fit the design
Die area should include area for:

➢ IO Cells/IO Pads
➢ Standard Cells
➢ Macros + Halo
➢ Interconnects (utilization)
Rough Estimate based on:

𝐶𝑒𝑙𝑙 𝑎𝑟𝑒𝑎 + 𝑀𝑎𝑐𝑟𝑜 𝑎𝑟𝑒𝑎 + 𝐻𝑎𝑙𝑜 𝑎𝑟𝑒𝑎
𝑈𝑡𝑖𝑙𝑖𝑧𝑎𝑡𝑖𝑜𝑛 = ▪ Previous designs
𝐶𝑜𝑟𝑒 𝑎𝑟𝑒𝑎
▪ Available package size

IO Cells: Basics
▪ IO cells are special circuit elements through

which a chip communicates with the external
world
▪ Can be of type input, output, or
bidirectional
Other functions of IO cells

▪ Drive capability
▪ Voltage transformation
▪ Protection against ESD (Electro-Static
Discharge) [short high-voltage (several
kilovolt) pulses]

IO Cells: Connection with Package
▪ Metallic pad (MPAD) is connected to the package pins using
bonding wires
▪ Power pads: special cells that supply power to a chip
▪ IO Cells too need power and ground connections
Number of power pads:
▪ Target level of internal voltages
▪ Current capacity of the power pads
Placement of IO Cells are guided by heuristics

▪ Assign nearby positions to two primary inputs that jointly drive a multi-input logic gate
▪ Spread power-hungry I/O cells all over the die area to avoid creating voltage drop hotspots
▪ Avoid placing sensitive (such as clock signals) near IO cells
▪ Flip-chip technology offers more flexibility in placing macro cells.

References
2023.

GDS
Lecture 38
Chip Planning - II
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Chip Planning
➢ Hierarchical Design Methodology
➢ Floorplanning
➢ Power Planning

Large Object (Macro) Placement
▪ Placement of large objects undertaken during
floorplanning
➢ Blocks (obtained in partition), RAM, analog
blocks (such as PLL), etc.
▪ Placement of standard will be undertaken during
placement stage
▪ Initial macro placement is guided by connectivity
➢ Strongly connected macros placed close
together
➢ Fly lines can guide the floorplan
➢ Macros interacting with external world close
to I/O pads
▪ Predictive routing (rough routing) can be done to
get an initial idea of problem in the floorplan

Macros Placement: Guidelines (1)
▪ Some guidelines can help in obtaining good floorplan
▪ Allot contiguous region for

▪ Avoid narrow channels between macros
standard cells

Macros Placement: Guidelines (2)
▪ Add halos around corners
➢ Halos are placement blockages
Use flexibility of:

▪ Orientation: reflection, rotation by 90°
▪ Shapes: rectilinear
▪ Pin assignment: locations of movable pins

Floorplanning: Standard Cell Rows
▪ Height of standard cell rows is equal to the
height of the standard cells in the library
➢ Multiple rows of different heights
created can also be created
▪ Standard cell rows generally created by

abutment
▪ Rows are created oriented in alternating
180-degree rotation
▪ Routing channels can be created between

rows to avoid congestion

Power Planning

Power Planning: Components
▪ Power Pads: Supply power to the

chip from the external world
▪ Power Rings: carry power around the

periphery of the die
➢ Usually use top metal layers
➢ Power Delivery Network (PDN)
built in the core area

Power Delivery Network (PDN)
Mesh Grid Topology:
▪ Popular topology for PDN
▪ Rails and straps usually organized as a uniformly
spaced array
Advantages of mesh grid topology

▪ Provides low resistance
▪ Reliability increases
▪ Uniform current distribution
Design Parameters:
▪ Layers in which the grid spans
▪ Width and spacing of wires

Electromigration
Electromigration
▪ Flow of unidirectional current in a metal can causes transport of metal mass in the direction
opposite to current flow
▪ Ions gain momentum from electrons
▪ May eventually lead to shorts and open
▪ PDN prone to electromigration

▪ Current in PDN needs to be kept within limit defined by process technology
➢ Ensure conductor size is adequate
➢ Ensure there are no current density “hot spots”

Voltage Drop
Cause of Voltage Drop: Impact on Performance
▪ Resistance (𝑅): between supply voltage ▪ Slows down signal propagation along the
origin and load path
▪ Inductance (𝐿): mainly between package- ▪ Maximum frequency at which a circuit will
to-die interconnection operate is limited
▪ Static and Dynamic Voltage Drop ▪ Need to perform voltage drop analysis in
𝑑𝑖 both static and dynamic conditions
𝑉𝑜𝑙𝑡𝑎𝑔𝑒 = 𝑖𝑅 + 𝐿
𝑑𝑡 ➢ Fix IR drop hotspots
Decoupling Capacitors (Decap Cells)

▪ Capacitors inserted between power and
ground wires
➢ Acts as local charge storage
➢ Placed on die at strategic locations
▪ Demerits: increase die area and leakage
power dissipation
▪ Number of decap cells, size and
placement should be optimized
References
2023.

GDS
Lecture 39
Placement
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Placement
➢ Global Placement
➢ Legalization and Detailed Placement
➢ Scan Cell Reordering
➢ Spare Cell Placement

Placement: Basics
▪ Decide locations of standard cells
▪ Goal: to ensure routability of a design
▪ Metrics: total wirelength
➢ Other metrics: timing, congestion
▪ Global Placement
➢ Cells are spread over the core area
➢ Overlap may exist
▪ Legalization and Detailed Placement

➢ Overlap between cells removed
➢ Cells moved to “legal” positions (legalization)
▪ Post-Placement Optimizations
➢ Buffering, resizing, etc.
Placement: Wirelength Estimates
▪ Placer needs to compute the wirelength of Half-perimeter Wirelength (HPWL)
each net multiple times ▪ Easy to compute
▪ Ideally, estimated wirelength should match ▪ Half of the perimeter of the bounding
post-routing wirelength rectangle that encloses all the pins of a net
▪ Widely used
Half-perimeter wirelength=11

Global Placement Techniques
▪ Well-studied problem: since 1970s
▪ Various heuristics have been proposed
Analytical Placement Algorithm:

▪ Considers each cell as point object with co-ordinates (xi , yi )
▪ Cost function (such as wirelength) and constraints are defined mathematically
2 2
➢ Wirelength a function of xi − xj + yi − yj
▪ Use efficient solvers to obtain minimum cost for the mathematical formulations
➢ Suitable constraints of fixed entities
➢ Cost related to cell density added
▪ Cells allowed to overlap in global placement
➢ Legalization becomes necessary

Placement: Legalization and Detailed Placement
A placement is illegal if:
▪ Cells overlap
▪ Cells occupy illegal sites (for example between
placement rows)
Legalization:
▪ Removes all overlaps and snap cells to legal
sites
➢ With the minimum impact on the
wirelength, timing and congestion
Detailed placement:
▪ Improves the QoR by incremental changes to the cell location(s)
▪ Improves wirelength and routability by:
➢ Swapping location of neighboring cells
➢ Re-distributing free sites
➢ Moving cells to unused location
Timing-driven Placement
▪ Perform timing analysis internally and incrementally during placement
➢ Target Worst Negative Slack (WNS) and Total Negative Slack (TNS)
▪ Control the proximity of cells that are on critical paths
▪ Depending on placement algorithm, different approaches to obtain timing driven placement
is taken
▪ Additional weight is added to nets to indicate timing criticality
➢ Give more weights to nets that are timing critical
➢ Additional weights bias the placement engine to place timing critical objects together

Scan Chain Reordering
▪ Scan cells that are nearby form consecutive flip-flops in the scan chain

Spare Cell Placement
Spare cells:
▪ Extra cells put in the circuit in anticipation of later use
▪ After fabrication, if it is required that some cells need to be connected, then spare cells can
be used
➢ Only the top metal layers might need to be changed
▪ Cannot be anticipated where will be the spare cells be actually be required to be connected
➢ Place randomly over the unused placement area
▪ Tools must be informed that which are spare cells and should not be optimized out

References
2023.

GDS
Lecture 40
Clock Tree Synthesis (CTS)
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Clock Tree Synthesis (CTS):

➢ Terminologies
➢ Clock Distribution Networks
➢ Clock Network Architectures
➢ Useful Skews

Clock Tree Synthesis (CTS): Basics
Ideal clock signal:
▪ Has the same waveform (voltage vs. time relationship) at all the points in the circuit.
➢ No clock skew or no difference in the arrival time of the clock signal at the flip-flops
▪ Clock Tree Synthesis implements clock distribution structure on the layout having behavior
similar to the ideal clock
➢ Minimizes the clock skew
➢ Inserts clock buffers/inverters and performs routing of clock distribution network
▪ Targets power reduction

➢ Clock network consumes significant portion of total active power (25% − 70%)
▪ Fixes timing violations and signal integrity issues

CTS: Terminologies (1)
Source: starting point of clock
signal
Sinks: final receiving endpoints of
the clock signal
Clock Tree: clock distribution

network organized in the form of
a tree
Insertion Delay/delay/latency: time taken by the clock signal to propagate through a clock
tree and reach a clock sink

CTS: Terminologies (2)
Clock Skew between two sinks:
difference in the arrival time of
clock signal between a pair of
sinks 𝑆1 and 𝑆2 , i.e.,
𝛿𝑆1𝑆2 = 𝑡𝑆1 − 𝑡𝑆2
Global Clock Skew: maximum

value of clock skew between any
pair of sinks
∆𝑔𝑙𝑜𝑏𝑎𝑙 = 𝑀𝑎𝑥 𝛿𝑆1𝑆2 where 𝑆1 and

𝑆2 are sinks

Clock Distribution Network
Global Clock Distribution Local Clock Distribution

Distributes clock to various Distributes clock to smaller
parts of chips and over parts of circuits
large area
Clock Buffers are large and Clock Buffers are smaller
more and fewer
Consume large power Consume less power
Top-level Clock Distribution Automated Clock Tree

Network needs to be Synthesis can be used
planned

Symmetric Tree Architecture
▪ Clock is first routed to a central point in
the chip
▪ From central point another symmetric
architecture forks out
▪ Example: H-Tree, X-Tree
▪ Ideally if each path is balanced, skew will

be zero
▪ Due to PVT variations, skew is still
observed
▪ Non-tree architecture can reduce impact
of PVT variations

Mesh Architecture
▪ Create 2-D structure with redundant
wires and devices
▪ Ensures more paths between mesh

drivers and clock sinks
➢ Very small skew
➢ Decreased impact of process
induced variations
➢ Robust
Disadvantages:
➢ Increases total capacitance and the size of clock drivers
➢ Increases power consumption (due to increased capacitance and short-circuit power
dissipation)

Useful Skews
▪ Introducing well-controlled skews can improve the system performance (useful skews)
When can clock skews be useful? Technique:

▪ If a significant difference in the slack ▪ Allocate the excess margin on one side of
exists on the two sides of a flip-flop the flip-flop to the more critical path side
➢ `Provide more time for data to propagate
on the critical path

Useful Skews: Illustration
50 + 200 < 𝑇𝑝𝑒𝑟𝑖𝑜𝑑 + 50
⇒ 200 < 𝑇𝑝𝑒𝑟𝑖𝑜𝑑
50 + 300 < 𝑇𝑝𝑒𝑟𝑖𝑜𝑑 + 50

1
𝑓𝑚𝑎𝑥 = = 3.33 𝐺𝐻𝑧
300𝑝𝑠
100 + 200 < 𝑇𝑝𝑒𝑟𝑖𝑜𝑑 + 50

50 + 300 < 𝑇𝑝𝑒𝑟𝑖𝑜𝑑 + 100

1
𝑓𝑚𝑎𝑥 = = 4 𝐺𝐻𝑧
250𝑝𝑠

Obtaining Useful Skews
▪ CTS tools calculates useful skew targets for all critical registers
▪ Increase arrival time of the clock for target registers by addition of delay buffers or extra
wires
▪ Useful skew also helps in reducing voltage drop problems

➢ Registers do not switch at the same time
➢ Simultaneous current drawn is less

CTS: Post Optimization
▪ Before CTS clocks were ideal
set_propagated_clock [all_clocks]
▪ After CTS clock network is fully built
▪ Need to inform STA tool to use actual
delays on the clock path
▪ New timing violations may show up after CTS

➢ Due to additional skew
➢ Due to some logic in data path moved out (placement changed) due to addition of
buffers in clock network
▪ Clock Network is frozen after post-CTS optimization and very small ECO fixes are allowed

References
2023.

GDS
Lecture 41
Routing
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Routing
➢ Global Routing
➢ Detailed Routing
➢ Post-routing optimization

Routing: Basics
▪ Involves making physical interconnections between different components of a design
▪ Honor connectivity as in the given netlist
▪ Complicated and time-consuming task.
▪ Tight constraints (routing resources, design rules, timing, and signal integrity constraints)
Global Routing
▪ Creates the plan of routing for each net (in terms of routing regions)
▪ Actual layout of nets not created
Detailed Routing
▪ Decides actual layout of each net in the pre-assigned routing regions
Post-Routing Optimizations
▪ Localized changes to fix issues in the design

Global Routing: Goals and Objectives
Goal:
Provide complete instructions to the detailed router on where to route each net in a design
Objectives
▪ Maximize the probability that the detailed router can complete the routing
▪ Minimize Total Interconnect Length
▪ Minimize critical path delay
Desirable:
▪ Global Routing used in other design phases for estimates: prototyping, floorplanning,
placement etc.
➢ Need to be fast

Global Routing: Routing Model
▪ Routing area is divided into rectangular grids
▪ Each rectangular region is called Global Bin (GB or
global tile, routing tile global cell, or bucket)
Grid graph is built using GBs:

▪ Vertices (𝑣): GBs
▪ Edges (𝑒) : represent boundary between adjacent GBs
➢ Create edges between two adjacent vertices only if
they lie along the preferred direction of routing
➢ Create edges between two vertices that lie
vertically adjacent (for vias)
Determining a route for a net:

▪ Associate a pin with a vertex in the grid graph using the
GB in which the pin is placed
▪ Find an optimal path in the grid graph that contains all
the vertices for that net
Global Routing: Routing Model
▪ When a net crosses the boundary of two ▪ 𝑼𝑺𝑬(𝒆): number of nets utilized for an edge
GBs ➢ Also called demand for an edge
➢ Net utilized the corresponding edge
▪ 𝑪𝑨𝑷(𝒆): quantifies availability of routing
resources for an edge
➢ Also called supply for an edge
➢ Routing blockages limit the capacity
➢ Depends on layer and design rules
Capacity constraint: 𝑈𝑆𝐸(𝑒) ≤ 𝐶𝐴𝑃(𝑒)
Overflow 𝑂𝐹 𝑒 = 𝑈𝑆𝐸 𝑒 − 𝐶𝐴𝑃(𝑒)
𝑈𝑆𝐸(𝑒)
Congestion 𝐶𝐺 𝑒 = 𝐶𝐴𝑃(𝑒)
Global routing attempts to route all the nets

such that 𝑂𝐹 𝑒 = 0
Global Routing: Challenges
Runtime versus Accuracy
▪ Runtime improvement:
➢ Increased size of GBs
▪ Accuracy:
➢ Anticipate problems that will be encountered by detailed
routing (ease design closure)
➢ Better modelling of routing resources and design rules

Detailed Routing

Detailed Routing: Goals and Constraints
Goal: To determine the exact layout of each net, including all the attributes of wire segments
such as width and location
Constraints and Considerations:
▪ Connectivity, design rules
▪ Timing, Signal Integrity, Runtime
▪ More number of metal layers available
➢ Over-the-Cell (OTC) routing done
▪ Performed using a detailed routing grid
➢ Tracks with uniform spacing (routing pitch)
➢ Allows easy automation
▪ Routing pitch is defined as minimum spacing

allowed in a technology (design rules):
➢ Line on Line: can be too aggressive (DRCs)
➢ Via on Via: can be too conservative
➢ Line on Via: trade-off
Routing: Final Optimization
▪ Timing analysis with interconnect layout and parasitics taken into consideration
▪ Improve timing issues by:
➢ Gate upsizing, buffering, automatic/manual re-routing and wire widening
▪ Reduce power consumption: gate downsizing, removing buffers

➢ Cell change with similar footprint
▪ Fix signal integrity issues

➢ Increasing distance between wires

Antenna Effect
▪ Prone to antenna effect-induced gate damage
▪ Avoid long M1 line directly connected to the

gate terminal
➢ Instead use higher layer metal (M2) for
routing
▪ Add a jumper to fix antenna rule violation after

routing

Reliability Issues: Via Defects
Vias are prone to failure Solution: add redundant vias
▪ Can lead to open circuit defects
▪ Yield loss and reliability problem

Manufacturability Issues
▪ Difference in hardness of metal and
dielectric, CMP can produce irregular
topography
▪ Irregular topography can lead to yield

loss
▪ Add dummy metal fills during routing to ensure more uniform metal density
▪ The existence of dummy metal fills in the vicinity of current-carrying wires can affect the
coupling capacitance.
➢ Dummy metal fills can impact the timing of a circuit.

References
2023.

GDS
Lecture 42
Post-Layout Verification and Signoff
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Post-layout Verification
▪ Layout Extraction
▪ Physical Verification
▪ ECO and Signoff

Layout Extraction

Layout Extraction: Basics
▪ Layout describes the shapes required on each fabricated layer
➢ Difficult for other post-layout verification tools to work with this information
▪ Extract various information from the layout

➢ Problem for a verification tool is greatly simplified
Layout extraction consists of two major tasks:

1. Circuit Extraction: devices and interconnections
2. Parasitic Extraction: parasitic resistance, capacitance and inductance

Circuit Extraction
Inputs:
▪ Merged GDS: layout of the
design and standard
cells/macros
▪ Extraction rules: for
devices and connections
(comes from foundry)
Outputs:
▪ Layout Netlist: typically in
SPICE
▪ ERC Report

Parasitic Extraction
▪ Resistance: each net may be divided into Chip-level parasitic extraction:
multiple net segments
1. Technology pre-characterization
▪ Capacitance: need to account for various
components 2. Pattern Matching
Technology pre-characterization Pattern Matching

▪ Performed once for a given technology ▪ Partition a layout into smaller windows
▪ Enumerate millions of sample ▪ Match windows with pre-characterized
geometries/structures patterns
▪ Use accurate Field Solvers for ▪ Compute the capacitance with the help of
computation lookup tables or empirical formulae
➢ Values stored in lookup tables or ➢ Actual geometries of the layout used
empirical formulae created using
curve-fitting Inductance:
▪ Highly time consuming ▪ More challenging to extract
▪ Fortunately, can ignore for most nets
▪ Numerical techniques used

Physical Verification

Physical Verification

Physical Verification : DRC
Design Rule Check (DRC):
▪ Ensure that the layout meets the constraints required for
manufacturing
▪ Rules are defined by the respective foundry
➢ Achieve a good yield and improve reliability
➢ Vary with the technology
➢ Become more complicated with advancement in
technologies

Physical Verification : ERC
Electrical Rule Check (ERC):

▪ Check design for electrical connections that can be problematic
▪ Examples: Shorts/Open, Floating Gate, Floating Nets etc.

Physical Verification : LVS
Layout versus Schematic (LVS):
▪ Verifies whether the layout corresponds to the original schematic (netlist) of the design
Compares:
1. Layout netlist (extracted)
2. Source netlist (schematic):
logical netlist combined with
device information

Signoff

Signoff
Signoff:
▪ Series of verification steps that
must be carried out before
sending the layout (GDS) to a
foundry
▪ Ensures that the layout delivers
the intended functionality and
meets various figures of merit

Engineering Change Order (ECO)
▪ Sometimes last moment incremental changes in a design needed
➢ Fix issues discovered late or new incremental functionality
▪ Risky changes
➢ Incorporate them using Engineering Change Order (ECO)
ECO tools:
▪ Enable making targeted incremental changes, rather than re-
implementing the entire design
▪ Verify the correctness of the ECO changes.
➢ Saves designer time, effort, cost, and risk
Types of ECO changes

▪ Functional ECO: changes logic
➢ Logic re-synthesis or use spare cells
▪ Direct changes in layout to fix setup/hold time violations, SI-related
issues, and design rule violations.
Signoff and Tapeout
▪ Design Tapeout: send the GDS for

fabrication
▪ Occasion to celebrate !

References
2023.

Vlsi Design Flow: RTL To GDS: Constraints I

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VLSI DESIGN FLOW: RTL TO

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Constraints are normally manually written

It is important to write correct constraints

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Environment under which the design operates

Design rules and optimization constraints

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

▪ Master clock: clock from which we

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

-waveform: time when the clock edges occur, starting

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

create_clock -name CLK -period 10 [get_pins

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

create_clock -name CLK -period 200 [get_ports clk_port]

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Clock uncertainty can be used to model:

▪ Jitter: temporal variation

▪ Skew: spatial variation

create_clock -name CLK -period 200 [get_ports clk_port]

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

create_clock -name CLK -period 2000 [get_ports clk_port]

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

inprotected.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Environment of design puts additional constraints on the signal entering/leaving a design

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

▪ Delay external to design at the input ports is

▪ Value of input delay = Delay of 𝐶𝐸1 + CP → Q delay of 𝐹𝐼𝑁 + Delay of 𝐷𝐼𝑁

create_clock –name CLK –period 2000 [get_ports CLK_PORT]

set_input_delay –clock [get_clocks CLK] 100 [get_ports IN]

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

set_driving_cell -lib_cell BUF1X -library tech14nm

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

𝑇𝑖𝑛𝑡 + 400 < 𝑇𝑐𝑙𝑘 + 20 − 30 𝑇𝑖𝑛𝑡 + 𝑇𝑂𝐷 < 𝑇𝑐𝑙𝑘

𝑇𝑂𝐷 = 400 − 20 + 30 = 410

create_clock -name SYS_CLOCK -period 2000 [get_ports CLK]

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

▪ set_load: load that will be driven by the

set_load 0.039 [get_ports OUT]

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

set_multicycle_path 4 -setup -from [get_pins FF1/CP]

set_multicycle_path 4 -setup -from [get_pins

set_multicycle_path 3 -hold -from [get_pins

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

set_case_analysis 1 [get_ports SCAN_ENABLE]

set_case_analysis 1 [get_ports SLEEP_MODE]

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Constraints: Mapped Netlist:

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

Area Delay Power Comments

Solution 1 10 20 50 Minimum Area