IC Compiler

K-2015.06
Flat Flow Update Training

IC Compiler CAE

June 2015
 CONFIDENTIAL INFORMATION
The following material is confidential information of Synopsys
and is being disclosed to you pursuant to a non-disclosure
agreement between you or your employer and Synopsys.
The material being disclosed may only be used as permitted
under such non-disclosure agreement.

IMPORTANT NOTICE
In the event information in this presentation reflects Synopsys’
future plans, such plans are as of the date of this presentation
and are subject to change. Synopsys is not obligated to develop
the software with the features and functionality discussed in
these materials. In any event, Synopsys’ products may be
offered and purchased only pursuant to an authorized quote and
purchase order or a mutually agreed upon written contract.

© 2015 Synopsys, Inc. 2

 General Flat Flow Improvements

• Preroute Automatic Non Default Routing rule optimization

• Faster design closure

© 2015 Synopsys, Inc. 3

 IC Compiler
Preroute Automatic Nondefault Routing
Rule Optimization

IC Compiler CAEs

© 2015 Synopsys, Inc. 4

 Overview

• Wire Optimization approach

– Automatically generate nondefault routing rules on nets during pre-route
optimization
– Zroute to honor these nondefault routing rules downstream

• Technology will include the following steps

– Automatic nondefault routing rule definition
– Net assignment criteria
– Components that honor nondefault routing rules

© 2015 Synopsys, Inc. 5

 Overview
IC Compiler Preroute Automatic Nondefault Routing Rule
Solution
• Automatic nondefault routing rule rule generation:
– Wider spacing (2x) for routing layers as soft routing rules

• Considers congestion guidance and assigns timing critical nets with

nondefault routing rules

• Optimization, extraction and routing all honor nondefault routing rules

© 2015 Synopsys, Inc. 6

 Usage / User Interface

place_opt

set_preroute_focal_opt_strategy \
clock_opt
-congestion_effort high
Automatic preroute_focal_opt \
nondefault -auto_routing_rule *
routing rule

route_opt * 2014.09-SP1

• Automatic nondefault routing rule can be applied anywhere in

preroute optimization flow.
• In order to use routing resource only on the real critical paths, apply
the automatic nondefault routing rules after clock tree synthesis,
when the timing is close to final.

© 2015 Synopsys, Inc. 7

 Advanced Usage
Automatic Nondefault Routing Rule Net Selection Criteria

• Both timing and congestion are considered

• Violations in all active scenarios are considered

• No upper or lower limit. Automatic nondefault routing rule tries to

apply nondefault routing rule on all timing critical nets but will filter out
those in congested area.
set_preroute_focal_opt_strategy -congestion_effort high

• Does not overwrite existing nondefault routing rule on nets

© 2015 Synopsys, Inc. 8

 Advanced Usage
Automatic Nondefault Routing Rule Best Practice
• The automatically generated nondefault routing rule rule is named
“auto_ndr_rule”

• Use the report_net_routing_rule command or query the

var_route_rule attribute of a net

• You can define your own rule with the name “auto_ndr_rule” before
running this feature. This replaces the nondefault rule the tool
automatically derives, and the rule you define is applied on critical
nets.

• Automatically runs quick optimization to refine netlist based on

changed parasitics due to the automatic nondefault routing rule

© 2015 Synopsys, Inc. 9

 Summary

• Recommendation

Features Releases Target Recommended Usage

Automatic
nondefault
Performance
routing rule 2014.09-SP1 All Designs
and Area
wire
optimization

© 2015 Synopsys, Inc. 10

IC Compiler K-2015.06 Training
Faster Design Closure

IC Compiler CAE
June 2015
 Contents

• Improved postroute design closure flow

• License change for 8-core multiprocessing

© 2015 Synopsys, Inc. 12

 Background

• Advanced node technologies require more runtime intensive features

in the postroute stage
– Complicated manufacturing rules for placement and routing
– Advanced timer and extraction features for signoff correlation

• High performance designs, such as those using technology nodes

below 20 nm, ARM cores, or GPUs, use highly customized design
flows to achieve power, performance, and area targets
– Runtime expensive settings throughout the flow
– Repeated command sequence for design convergence

© 2015 Synopsys, Inc. 13 Confidential and Proprietary

 Faster Design Closure
Recommendations (I)

• Use the design closure flow tuned for high performance designs
– Use the design closure flow to perform sufficient postroute optimization,
and then try customization to meet targeted timing and power goals
– Make sure there is a sizeable QoR improvement to justify the runtime at
any stage of the flow

• Recommendations based on recent investigations for faster design

closure

© 2015 Synopsys, Inc. 14 Confidential and Proprietary

 Existing Design Closure Flow
Prior To Version J-2014.09

• Timing-driven routing
route_opt –initial_route_only

• First route_opt
route_opt –skip_initial_route \ – Crosstalk reduction
–effort medium –xtalk_reduction \ – On-route optimization
-power 1 – Leakage recovery

set_app_var \ • Second route_opt

routeopt_enable_aggressive_optimization \
true – On-route optimization
route_opt –incremental – More effort on hold and DRC fixing
2

• Third route_opt
set_app_var \ – On-route optimization
routeopt_restrict_tns_to_size_only true
route_opt –incremental – Limit TNS optimization to size-only for
3 better convergence

© 2015 Synopsys, Inc. 15

 Improved Design Closure Flow
Starting With Version J-2014.09-SP4

Changes in first route_opt

route_opt –initial_route_only
• Replace –skip_initial_route with
–incremental
– Faster runtime by skipping certain netlist
route_opt –incremental \ preconditioning steps
–effort medium –area_recovery 1
• Add –area_recovery

set_app_var \ • Remove -power

routeopt_enable_aggressive_optimization \ – Use focal_opt –power later
true
route_opt –incremental –xtalk_reduction 2 • Remove –xtalk_reduction
– Too early to apply to critical nets

set_app_var \ Changes in second route_opt

routeopt_restrict_tns_to_size_only true
route_opt –incremental • Add –xtalk_reduction
3 – Enable xtalk reduction to work on critical
nets

© 2015 Synopsys, Inc. 16

 Faster Design Closure
Recommendations (II)

• Defer advanced timer and extraction

features for faster design closure Advanced timer and extraction settings
– Timing windows
– Waveform propagation
route_opt –initial_route_only
– CCS static noise calculations
– Lower than default coupling
capacitance threshold etc. route_opt –incremental \
–effort medium –area_recovery 1
• Allow first route_opt to optimize
global timing with a simple timer set_app_var …
setup route_opt –incremental \
–xtalk_reduction 2
• Enable runtime expensive features
in second or later route_opt runs set_app_var …
to close the gap route_opt –incremental
3

© 2015 Synopsys, Inc. 17 Confidential and Proprietary

 Faster Design Closure
Recommendations (III)

• Leverage new features for faster QoR improvement

– High resistance optimization
– Postroute concurrent clock and data optimization
– High effort postroute TNS optimization

• Use the latest release for runtime improvement

– Bug fixes for known runtime issues

© 2015 Synopsys, Inc. 18 Confidential and Proprietary

 Faster Design Closure
Customer Design Results
200

150
Runtime

100 Baseline
Improved Flow
50

0
CPU GPU CPU Design 1
unknown

CPU GPU CPU Design 1

Cell # 852k 2.7M 1.9M 978k
Technology 16/14 nm 16/14 nm 16/14 nm 16/14 nm
Improved design closure flow Yes Yes Yes Yes

Advanced timer settings deferred Yes Yes No Yes

by user
New Features used by user No Yes No No

Postroute flow runtime 2.2X 2X 1.6X 1.7X

speed-up
Similar or Better QoR with Improved Flow
© 2015 Synopsys, Inc. 19 Confidential and Proprietary
 IC Compiler Multicore Licensing

• Change in IC Compiler licensing:

– In previous releases of IC Compiler, you needed one license for every
four parallel tasks
– For example, to run eight parallel tasks, you needed two IC Compiler licenses

– IC Compiler version J-2014.09-SP4 and later versions support 8-core

multiprocessing with a single license

© 2015 Synopsys, Inc. 20

 IC Compiler Packages and Multicore

Package Cores Description

Per License
IC Compiler Netlist to GDSII physical design solution for
8
(ICC) technology nodes >20 nm

IC Compiler-Advanced Geometry Netlist to GDSII physical design solution for

8
(ICC-AG) technology nodes ≤20 nm

IC Compiler-DP
8 Design planning solution for all technology nodes
(ICC-DP)
IC Compiler-PC Netlist to post-CTS placed gates solution for all
8
(ICC-PC) technology nodes

8 core place and

Netlist to GDSII physical design solution for
extract
IC Compiler-Express technology nodes ≥130 nm
ICC MR4:4 or 8:8
(ICC-XP)
needed to run
Uses classic router - no Zroute
distributed routing

Size-limited (50k instances) netlist to GDSII physical

IC Compiler-AMS design solution for technology nodes ≥28 nm. Also
8
(ICC-AMS) includes Custom Designer Layout Editing (Custom
Designer LE)

© 2015 Synopsys, Inc. 21