6.
5 Watt, 35 GHz Balanced Power Amplifier MMIC
using 6-inch GaAs pHEMT Commercial Technology
Simon J. Mahon, Alan C. Young, Anthony P. Fattorini and James T. Harvey
Mimix Asia
Level 13, 80 Mount Street, North Sydney, NSW 2060, Australia
Fax: +61 2 9956 3399. Email: smahon@mimixbroadband.com.au
Abstract— A 6.5 watt power amplifier MMIC has been developed
for the 35 GHz band. The amplifier exhibits high performance at
low processing cost through the use of a commercially available
6-inch, 0.15-µm pHEMT process with 100 µm thick substrate.
The balanced four stage amplifier MMIC has 23 dB of gain, 6.5
watts saturated output power (38.1 dBm) with high absorption
load for driving into a mismatch, and power added efficiency of
24%. In terms of output power, this is to the authors’ knowledge
the best reported for fully matched GaAs pHEMT MMICs on
100-µm substrates at millimetre-wave frequencies.
Index Terms — MMIC power amplifiers.
I. INTRODUCTION
There is ongoing demand for high power amplifier MMICs
at Ku-, Ka- and Q-bands with reduced cost [1]-[6]. The power
amplifier MMIC reported in this paper was designed to meet
this challenge in the 35 GHz (i.e. Ka) band. A standard
commercially available 6-inch GaAs pHEMT technology with
100 µm substrate was used in preference to thinner substrates.
This not only reduces cost; but it also provides higher wafer
robustness, easier die handling compared to thinner chips and
higher overall yield. Reasonable die area and broad bandwidth
were achieved with conventional technology by utilising novel
matching network topologies incorporating lumped elements,
designed with extensive use of electromagnetic simulations.
II. MMIC DESIGN
The MMIC was fabricated in the WIN Semiconductor
(Taiwan) standard 0.15 µm power pHEMT process on 6-inch
wafers with 100 µm thickness [7]. Rigorous design and layout
methods were used in the optimisation of stability, gain, power
transfer and lifetime. Layout parameters such as gate width,
gate-to-gate spacing and the number of gate fingers between
source vias influence the RF power available from a transistor,
its RF stability, channel temperature (hence reliability and
lifetime) and the size (cost) of the resulting amplifier. Load-
pull measurements of test pHEMTs with on-wafer pre- and
post-device matching quantify the effect of these layout
parameters on the available RF device power which varies
from 600 to 800 mW/mm while keeping gate currents within a
conservative range for reliable operation [8].
Infra-red thermal imaging was used to measure the peak
channel temperature of the different transistor layouts as a
978-1-4244-1940-1/08/$25.00 ©2008 IEEE
function of bias and RF drive. The thermal resistance was
found to vary by 15% between test pHEMTs with the same
gate width and transistor area [16]. This technique was used to
select an optimal transistor layout and to predict the amplifier’s
reliability, which is approximately one million hours MTTF
CW (continuous wave) operation at 55 °C backplate (Fig.1).
1E+08
Mean Time to Failure (Hours) 1E+07
1E+06
1E+05
1E+04
1E+03
30 40 50 60 70 80 90 100 110 120 130
Backplate Temperature (C)
Figure 1. Estimated CW Mean-Time-to-Failure (MTTF) for the balanced
power amplifier as a function of MMIC backplate temperature.
The design of the output stage transistor is a trade-off
between available RF power, thermal behaviour, physical size
and specified output match. The load-pull and thermal imaging
analysis is required for optimisation of the output stage and
combining manifold. For the input and interstage designs the
load-pull data was augmented by a non-linear device model [9]
and extraction methodology [10] to ensure optimal trade off
between power match for each stage and source impedance for
the following stage. Careful and extensive EM simulations
ensure phase and amplitude balance between the amplifier’s
inner and outer devices. RF ports and bias feeds were designed
for ESD robustness.
The output of each half of the four-stage, amplifier of the
balanced MMIC (Fig. 2) consists of eight 600-µm transistors
with optimised device geometry. These half-amplifiers are
combined in a novel asymmetric Lange coupler whose design
accommodates the high level of RF current present by varying
the metal width (and spacing to maintain Lange performance)
in each finger section to accommodate the maximum RF power
level in that finger as determined by equating the RF rms
current to the DC value [11]; both for operation into a normal
load and into an open circuit where 38 dBm of reflected power
1
is dissipated in the Lange termination and final amplifier stage.
The input Lange coupler is a conventional device. The output
stages of each half-amplifier are each driven by three stages
with a 1:2:4:8 periphery ratio.
B. Power Measurements on the Half Amplifier
For the power measurements the device was soldered onto
a copper block. A “fast” pulsed measurement was made with a
drain bias pulse 8 µs long with a 500 Hz repetition rate. The RF
input power and the gate voltage was applied continuously. A
voltage sense pad on the MMIC was used to maintain the
correct drain voltage in the presence of voltage drops in the
probes and associated cables. The power data was taken from
an average value over a window from 3 to 5 µs and the drain
current was measured in the middle of that window at 4 µs.
Fig. 4 shows an output power of up to 36 dBm (4 watts) for the
half-amplifier as a function of load impedance measured with
the fast drain pulse method.

(a)

Figure 2. Photograph of the 6.5 watt amplifier MMIC (area is 28.35 mm2 –
layout is larger than needed to allow for easier dicing on engineering retiucle).

III. MEASURED PERFORMANCE

A. Scattering Parameters for the Full Amplifier

The amplifier was tested in CW mode at reduced-bias for
small signal S-parameters yielding about 23 dB gain and input
and output matches of 16 and 10 dB, respectively (Fig. 3).

24 (b)
20
S21
16 Figure 4. Measured output power (Pout) with fast drain pulsing for the half-
S11, S22 and S21 (dB)

12 amplifier biased at Vd = 6 V and Vgs = -0.5 V (a) and Vgs = -0.7 V (b).
Vds Input power = 13 dBm in both cases.
8
4
0 “Slow” gate pulsing has also been explored. For this case
-4 the drain and the RF input are applied continuously and the
S22
-8 gate is pulsed on for 65 ms from an off stage of -2 V with a
-12 duty cycle of 50% (7.7 Hz repetition rate). The output power is
-16 measured as the average over the pulse. Fig. 5 compares the
-20 S11
two pulsing methods for the half-amplifier, showing a
-24
difference of about 0.5 dB in output power and 2 percentage
30 32 34 36 38 40
points in power added efficiency (PAE) due to heating.
Frequency (GHz)

Figure 3. Measured CW small-signal s-parameters for the amplifier biased at

Vd = 5.0 (red), 5.5 (green) and 6.0 (blue) V and Vgs = -0.9 V (Ids § 2.2 A).

978-1-4244-1940-1/08/$25.00 ©2008 IEEE 2

 32
coupler. After the initial burn-in period no further change was
Gain observed in output power or drain current.
28
PAE (%) and Gain (dB)

24 32
20
28
16

PAE (%) and Gain (dB)

24
12 Gain Vgs
PAE 20
8
16
4

0 12
18 20 22 24 26 28 30 32 34 36 Vgs
8
Output Power (dBm) PAE
4
Figure 5. Measured gain (red), output power and power added efficiency 0
(PAE, blue) with fast drain (solid lines) and slow gate (dashed) pulsing into a
24 26 28 30 32 34 36 38
50 ohm load for the half-amplifier biased at Vd = 5 V and Vgs = -0.7V.
Output Power (dBm)

C. Power Measurements on the Full Amplifier

Figure 7. Measured fast pulsed gain and power added efficiency (PAE) vs
The pulsed output power and PAE versus frequency at output power of the full amplifier at 35 GHz, Vd = 6 V and
optimal load impedance and at 50+j0 ohms and a drain bias of Vgs = -0.7 (blue), -0.8 (green) and -0.9 (red) V.
6 V and gate bias of -0.7 V is shown in Fig. 6. The pulsed
output power is near 38 dBm for both loads over the 34 to 35
GHz band. The PAE with the optimal load peaks at 22% (for
this gate bias) with a load near 30 ohms and is generally 1 to 2
percentage points higher than at 50 ohms across the measured
frequency range.

40
38
Max PAE (%) and Pout (dBm)

36
34 Pout
32
30
28
26
24
22
20
18 PAE
16 (a)
14
12
33 34 35 36 37
Frequency (GHz)

Figure 6. Measured fast pulsed output power (Pout, red) and power added
efficiency (PAE, blue) into the optimal load for power (solid lines) and
50+j0 (dashed) vs frequency for the full amplifier biased at Vd = 6 V and
Vgs = -0.7V with an input power of 16 dBm.

Fig. 7 shows the PAE and gain of the full-amplifier at 35

GHz as a function of output power at the optimal load
impedance for three gate biases.
The robustness of the asymmetrical output Lange coupler
and the internal termination resistor were tested by driving the
pulsed amplifier into compression for 70 hours with an open-
circuit output termination. Loadpull contours were measured
before and after the test – see Fig. 8. During burn-in a 0.18dB (b)
drop in output power was accompanied by a consistent 5%
Figure 8. Measured output power (Pout) with fast drain pulsing for the full-
drop in drain current suggesting that the degradation is amplifier biased at Vd = 6 V and Vgs = -0.7 V before (a) and after (b) burn-in.
occurring in the half-amplifier rather than the output Lange

978-1-4244-1940-1/08/$25.00 ©2008 IEEE 3

 The shift in the optimal load from the half-amplifier to the
full amplifier (Fig. 4 vs Fig. 8) is due in part to the
compromised RF performance of the ruggedised output Lange
coupler and in part due to the orthogonal trajectory of the loads
seen by the two half-amplifiers as the load seen by the full
amplifier varies creating a sub-optimal compromise between
the desired loads for each half.
The measured output power level of 38.1 dBm corresponds
to a power density of 675 mW/mm in the final stage. This
demonstrates effective use of the available device power seen
in the transistor load-pull measurements, although clearly some
reduction due to the Lange coupler loss is evident compared to
the higher value of 740 mW/mm for the half-amplifier.
Table 1 compares the results presented here with other
recent results for Ka-band HEMT power amplifiers, some
fabricated with thinner substrates and some with GaN, in the
reviewed literature.

TABLE I. BENCHMARK OF KA-BAND HPAS USING GAAS AND GAN HEMTS

Thickness Lg Freq. Gain (dB) / PAE Die area
Ref. Technology Psat (dBm)
(um) (nm) (GHz) No. stages (%) (mm2)
[1] GaAs pHEMT 50 250 27-31 24 / 3 35.3 (CW P1dB) 25 12.88
[2] GaAs pHEMT 100 250 27-32 20 / 3 33.1 25 6.16
[12] GaAs pHEMT 50 200 28-31 22 / 3 36.3 28 12.4
[13] GaAs pHEMT 50 200 42-46 15 / 3 36 20 15.9
[14] AlGaN/GaN HEMT 100 180 26-36 12 / 2 36 23 NA
[15] GaAs pHEMT 635 150 35 9/ 2 30.1 15 7.25
[16] GaAs pHEMT 100 150 34-36 22 / 4 35.5 25 12.75
This work GaAs pHEMT 100 150 33-37 23 / 4 38.1 24 28.35

[6] F. Y. Colomb, and A. Platzker, “2 and 4 watt Ka-band GaAs PHEMT

IV. CONCLUSION
The performance of a 6.5-watt, 35-GHz balanced power
amplifier MMIC has been presented. The circuit achieves a
pulsed output power of 38.1 dBm at 24% PAE with a gain of
23 dB. The P1dB is approximately 37.5 dBm. The saturated
output power represents a final-stage power density of 675
mW/mm. To the authors’ knowledge output power is the
highest reported for fully a matched GaAs pHEMT MMICs on
100-µm substrates at these millimetre-wave frequencies.
ACKNOWLEDGEMENT
The authors would like to acknowledge useful discussions
with A. Bessemoulin and A. Dadello, the contributions of S.
Hwang, M.G. McCulloch and R.G. Mould for measurements
and assembly. They also thank the reviewers for their useful
comments.
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