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CSE210 Mid Soln Spring 2023 (IUB)
CSE210 Mid Soln Spring 2023 (IUB)
CSE210 Mid Soln Spring 2023 (IUB)
Figure:1
2. Design a full-wave rectifier which has an average voltage of 9.55 V. Your 25
design should mention the following:
a) Full-wave Rectifier circuit with the polarity of vo mentioned.
b) Input sinusoidal wave with the value of Vm mentioned.
c) Output wave with the value of vo mentioned.
Consider the diodes to be ideal diodes.
3. Determine vo for the network of Fig.2 for the input given below. 25
Figure:2
4. Determine vo for the network of Fig.3 for the input given below: 25
Figure:3