Proceedings of the International Conference on Artificial Intelligence and Smart Systems (ICAIS-2021)

IEEE Xplore Part Number: CFP21OAB-ART; ISBN: 978-1-7281-9537-7

Comparative Study of THD in Multilevel Converter

Using Model Predictive Controller
S.Rajasekaran, CH.Mahendar
EEE,Vignana Bharathi Institute of Technology, Hyderabad, India.
2021 International Conference on Artificial Intelligence and Smart Systems (ICAIS) | 978-1-7281-9537-7/20/$31.00 ©2021 IEEE | DOI: 10.1109/ICAIS50930.2021.9395908

drsekar.ee@gmail.com

Abstract— The topology of comparing the performance of the Multilevel converters have many benefits like lower dv/dt
5 level multi-level inverter with the 3 level multi-level inverter is tension, lower harmonic distortion, lower electromagnetic
proposed in this article[1]. A multilevel converter is a power interference (EMI) and better performance relative to
electronic unit designed to examine a necessary AC voltage from conventional converters[4][9].
many DC . which generates the output voltage with reduced
complexity when regulating current and balancing the capacitor
voltages. A megawatt power level and medium voltage are
required for certain industrial drives. It is problematic for a
medium voltage to directly link just one power semiconductor
switch. As an option in low voltage and high power conditions, A
multilevel power converter system has been incorporated. In this
article, the five-level inverter is used to reduce the THD when
evaluating the 3-level inverter. For multilevel converters, The
strategy of the SVPWM control technique is used to bring down
the THD in the waveform of the output. The simulation takes
place in the framework of MAT LAB/Simulink.

Keywords— Multi-level converters, THD, SVPWM,

PowerQuality.

I. INTRODUCTION

A three phase five stage neutral point clamped multi-level

inverter is operated by this desired control system model
predictive control (FCSMPC) and contrasts the output to the
three-level multi-level inverter. Compared to standard and
well-known two-level converters [1][2], Great benefits are
provided by multilevel converters. Both benefits boost the
efficiency of the output signals and raise the converter's
nominal capacity. The power circuit of the attached Voltage
Source Inverter (VSI) of the simple 3-level Neutral Point
Clamped (NPC) is shown in Fig. 1.[9]. There are some
disadvantages, such as stability problems, gain, of traditional
linear converter with space vector modulation put-upon for
this kind VSIs. The inverter's neutral point voltage (NPV) is
regulated by inserting another lower-priority word in cost
feature that is intended to regulate current[15][16]. A
weighing factor specifies the priority level of managing the
NPV. No suitable-established law for calibration the weighing
factor till now, however and the inclusion of this additional
word in the cost part often constraint the THD of the particular
current [5]. Researchers are attempting to strengthen the
multilevel converter THD[12].The DC capacitor’s voltage
balance, the wave of load currents, etc.
Fig. 1.The five level NPC VSI
II. THE MULTI LEVEL CONVERTER
Multilevel inverters are power transition devices with the
variety of power devices and voltage sources that can create a
desired and viable frequency, phase, and magnitude multi-step
voltage waveform. This is attained with in the “multilevel
inverter” (MLI)[4].it provides the specified output voltage
along with multiple DC input voltages. More voltage level
combinations will supplies a smoother waveform[5][11].
when properly connected and controlled. By choosing distinct
voltage ratios, This synthesizes the stepped waveform.The
number of steps that the converter can generate between
theany reference node and output terminal within the inverter
is understand as the level of steps that the converter can
generate typically denoted by N and called neutral. Each step
in the converter needs to produce at least three stranded
voltage levels to be considered a multilevel converter. This is

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 Proceedings of the International Conference on Artificial Intelligence and Smart Systems (ICAIS-2021)
IEEE Xplore Part Number: CFP21OAB-ART; ISBN: 978-1-7281-9537-7

distinguished from the multilevel family by the classic five-

level voltage source converter (5L-VSC).
A amplitude voltage waveform and variable frequency can
be produced by multilevel converters. This is achieved using
the techniques of Space vector pulse-width modulation
(SVPWM)[3][6]. And other hand, a new degree of freedom is
added by multilevel converters, facilitating the use level of
voltages as an external control factor and offering more
options to produce the output[8] .
The inherently enhanced power efficiency of multilevel
converters is distinguished by lesser distortion of voltage,
decreased dv/dt, and lesser common-mode potential
differences , minimizing or removing the necessary filters in
out.
III. CONVERTER CONFIGURATION
Cascaded H-Bridge (CHB), Neutral point or diode
clamping[9], Clamping a capacitor or Flying
Capacitor(FLC)are the most recognized and proven
typologies. Fig. 2: Diode-Clamped Inverter Circuit
(a) 3-Level. (b) 5-Level.
Table I. Five Level Switching State
Terminal ( switching states) 1-ON, 0-OFF An important role in the FCSMPC architecture is played
SA SA SA SA SA SA SA SA by the complex Five-level inverter model shown in Fig.1. For
each PWM loop, the Space Vector PWM Module accepts
1 2 3 4 5 6 7 8
regulatory list orders and generates the right door drive
2VDC 1 1 1 1 0 0 0 0
waveforms. The operation and organization of the SVPWM
VDC 0 1 1 1 1 0 0 0 module is depicted in this area[3].A dc-interface configuration
0 0 0 1 1 1 1 0 0 inverter will have eight possible exchange states, producing
-VDC 0 0 0 1 1 1 1 0
the inverter's yield voltage[13]. Each state-exchanging inverter
generates a Vector voltage in Space Vector plane.
-2VDC 0 0 0 0 1 1 1 1
This is the safest way to achieve continuous battery
voltage charging by swapping the capacity gadgets of the
The voltage across each capacitor is Vdc/4. Each switch is surrounding planetary device controller. It is honestly obvious
restricted by clamping diodes to single capacitor voltage. The that because the voltage is at 12V for precisely as long as all
distortion in wave and efficiency of the inverter would aspects are called at 0v, a 'acceptable gadget' connected with
decrease if we increase the number of levels due to lesser its output would see the usual voltage at that stage and assume
switching errors. that 6v is taken care of - precisely 50 percent of 12V.
Switching times the conventional 2-level SVPWM can be
added to the inverter until the final stage corrected reference
IV. NEUTRAL POINT CLAMPED MULTILEVEL INVERTER voltage of 2 V and the accompanying hexagon are
The inverter, also referred to as the diode inverter clamped. calculated[3][6]. By combining states A,B and C, the
Discussed in references [7],[10], the fundamental reference voltage vector * 2 V is produced. The states A and B
configuration of this inverter. The staircase output voltage was represent the borders of the portion where the vector 2V falls,
received by the neutral clamped inverter. If m is the level there the state C symbolizes the middle of hexagon picked.
number, capacitors needed on the DC bus is (m-1), so, the Instead of each state's unneeded voltage vectors.
number of control switches per phase as 2(m-1) and diode is V. SIMULATION RESULT
2(m-2). Two C1 and C2 capacitors for three stages and four
C1, C2, C3 and C4 capacitors for five stages are used for the It is closer to the sinusoidal output voltage. Harmonic
DC bus voltage, as seen in Fig.1 [14]. voltage amplitudes are very small. The inverter output voltage
also has a low quality voltage that is demonstrated by a very
large Overall Harmonic Distortion.

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 Proceedings of the International Conference on Artificial Intelligence and Smart Systems (ICAIS-2021)
IEEE Xplore Part Number: CFP21OAB-ART; ISBN: 978-1-7281-9537-7

Fig.5. Output of the Five Level Clamped Converter by using

SVPWM A) Current B) Active power Regulation
C) Neutral Point Voltage
Fig.3. 5-Level Inverter-Vector

Table II. Switching operation of the Converter

S S
States S S S S S S
A A
Mode A3 A4 A5 A6 A7 A8
1 2
0 1 1 1 0 0 0 0 0
1 0 1 1 1 0 0 0 0
2 0 0 1 1 1 1 0 0
3 0 0 0 1 1 1 1 0
4 0 0 0 0 1 1 1 1
\

Fig.6.Simulation diagram of the Three Level Neutral

Clamped Converter
The three level multilevel THD is 2.3 percent from the
proposed paper [1]. But it is 0.17 percent when using a five
level multilevel inverter. The value of THD is given in
equation 1

THD=√ (V22+V32+V42‫)ڮ‬/V1 ……….. (1)

Where, THD= Total Harmonic distortion
Vn = nth harmonic VRMS
Fig.4. Simulation diagram of the Five Level Neutral V1 = fundamental frequency VRMS
Clamped Converter

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 Proceedings of the International Conference on Artificial Intelligence and Smart Systems (ICAIS-2021)
IEEE Xplore Part Number: CFP21OAB-ART; ISBN: 978-1-7281-9537-7

Fig.9. Three level Converter THD

Fig.7.Output of the 3 level neutral clamped Converter by Table III. Comparison of Three and Five Level Inverter
using SVPWM A) Current, B) Active power regulation C)
Neutral Point Voltage. 5 Level Inverter
Number of required switches
The total harmonic distortion in the 3-level inverter is are 8.
greater relative to the five-level inverter. The amount of The total harmonic distortion
increases in level, decreases in THD,which is shown in value of 5 level multilevel
Fig.8and Fig.9. output will be 0.17%.
Number of switching Modes
will be 5.
The THD Value is less
compared to three level
inverter.
3 Level Inverter
Number of required switches
are 4.
The total harmonic distortion
value of 3 level multilevel
output will be 2.3%
Number of switching Modes
Will be 3.
The THD value is high than
five level inverter.

VI. CONCLUSION
This paper analysis compared Simplified SVPWM based
neutral clamped five level inverter THD output wave forms
with the three level inverter THD output waveforms. Thus,
With the help of the suggested framework and the
understanding of the space vector diagram, The five level
inverter can be conveniently extended to any higher level
inverter. As only redundant Switches are used for voltage
balancing, By using the five level with neutral clamped
reduces the time and increases the performances of the
inverter also reduces the THD value of the system thereby
reducing the computational burden. Therefore in higher-level
inverters, the percentage decrease in execution time may be
further minimized.
Fig.8. Five level Converter THD
VII. REFERENCES

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 Proceedings of the International Conference on Artificial Intelligence and Smart Systems (ICAIS-2021)
IEEE Xplore Part Number: CFP21OAB-ART; ISBN: 978-1-7281-9537-7

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