This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2020.3019358, IEEE
Transactions on Industry Applications
Reliability and Real-Time Failure Protection of the
3-Phase 5-Level E-Type Converter
Marco di Benedetto, Member, IEEE, Alessandro Lidozzi, Member, IEEE, Luca Solero Member, IEEE, Fabio Crescimbini,
Member, IEEE, Petar J. Grbović, Senior Member, IEEE
Abstract—Power electronic converters have a heavily influence
in our life-style, as they are used today in several applications,
such as in-home and office appliances, electromedical
apparatus, industry machine tools, as well as in electrical energy
transmission and distribution systems. Power electronic
converters are based on using fast-switching power
semiconductors which allow the desired shaping of the output
electrical quantities waveforms but, however, these power
devices are also the most fragile component of the power
conversion apparatus. Thus, to ensure safety and reliability of
the power conversion system, a fault detection method must be
suitably embedded in the control system. When a failure occurs,
the fault detection and protection system become the most
important function of the converter control unit. This paper is
devoted to the theoretical analysis of all the possible faults
occurring in the 3-phase 5-level E-Type Converter (3Φ5L E-
Type Converter) and based on such an analysis a suitable fault
management strategy is proposed. Fault effects are initially
analyzed on the long-term time scale, from 10μs up to 100ms.
The fault effects, the detectability and the safety shutdown
actions are identified and summarized. The analysis is covered
by simulation results performed in MATLAB/Simulink.
Following the theoretical analysis, a control algorithm has been
implemented in FPGA using LabVIEW. Finally, experimental
tests have been performed on a prototype of the proposed
multilevel converter in order to validate the proposed approach
to management of the envisaged fault conditions.
Keywords—Fault tolerance, multilevel converters, short
circuit, open circuit, power semiconductors.
I. INTRODUCTION
Voltage source power converters play an important role in
most electrical power conversion applications, such as power
generation and transmission, industrial variable speed drives,
and traction applications [1]-[5]. Whenever the converter
operates in normal conditions, the fault detection and
protection circuit are a secondary function that many users
ignore or take for granted. However, when a failure occurs,
the fault detection and the protection system become the most
important functions of the converter control unit. If the
converter is equipped with an adequate fault management
system, the faults can be detected and cleared before
propagating through the converter and generating
catastrophic results. Thereby, it is possible to avoid material
and financial losses and, in the worst cases, environment and
safety issues. In consideration of that, the analysis of all the
possible failure modes and the resulting effects on the
converter operation is a key topic. In fact, it represents an
important step in the converter design providing grounds for
designing the fault detection and protection circuit.
For two-level voltage source converters the issues related to
fault detection and protection have been well addressed since
0093-9994 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Prince Edward Island. Downloaded on September 05,2020 at 16:29:16 UTC from IEEE Xplore. Restrictions apply.
the past in both academic and industrial research works [6]-
[10]. On the other hand, due to the higher number of
semiconductor switches and the multiple combinations of the
switching states, in multilevel topologies the analysis devoted
to fault detection and converter protection becomes more
difficult and challenging. Nevertheless, various studies
devoted to fault detection and protection in different
multilevel topology converters have been presented in
literature up to date [11]-[22]. In fact, a new diagnosis method
of an open-switch fault and fault-tolerant control strategy for
T-type three-level inverter has been presented in [11]. Further
to that, the open-circuit and short-circuit faults of a newly
conceived three-level converter have been discussed in [12].
In particular, the topology proposed in [12] is based on the T-
type topology converter and allows an increase of the
reliability of the converter. In [13] a modular multilevel
inverter has been analyzed by considering both open and
short circuit faults, whereas the analysis of failure modes in
the three-level neutral point clamped converter has been
presented in [14], [15], [16]. In [17] the fault analysis has
been investigated concerning a 5-level unidirectional T-
Rectifier being used in high speed electric generation and
then the study has been extended to a modified 5-level
topology that has been proposed in [18]. Further studies
devoted to multilevel converters that have fault-tolerant
capabilities include a newly-conceived five-level inverter
topology that can tolerate faults on its switches as proposed
in [22]-[26]. As known, the more suitable fault tolerance
multilevel topology is the CHB converter thanks to its large
number of redundant switching states, that allows the inverter
to keep normal operation under fault conditions [19]-[21]. In
[21] and [22] a new five-level H-bridge-based cascaded
inverter has been proposed to improve the reliability. Here,
the five-level transistor clamped H-bridge (TCHB) inverter
has been modified in order to tolerate the faults on the
switches of both its legs. The resulting fault tolerance
topology consists of two legs of H-bridge, one leg composed
of two series power devices and the other leg composed of
four series power devices and two diodes (NPC leg). This
topology makes use of many components as compared to the
5-Level E-Type converter; thanks to the use of two more
power devices per phase, it is possible to change the current
path in case of fault of one power device. A new topology
able to tolerate more than one power device fault, named
multilevel active clamped (MAC), has been proposed in [23],
[24]. However, the five levels MAC consists of at least 20
active devices per phase. Another fault tolerance five-level
nested neutral-point-pilot (NPP) topology is illustrated in
[25]. In case of failure, this topology can operate
continuously without stepping down the voltage level;
however, the number of the devices per phase is equal to 12.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2020.3019358, IEEE
Transactions on Industry Applications

Finally, in [26] the 5L NPC inverter, which has 20 devices semiconductor is equal to 1/4VBUS.
per phase, has been modified in order to mitigate short circuit This paper focuses on the fault detection and protection of the
faults. However, compared to the 5L E-Type inverter, the power devices being used in the 3Φ5L E-Type Converter.
reconfiguration of the NPC Inverter presents 26 power Starting from previously investigations on both three level
devices per phase. The numbers of power devices, including and five level converter topologies, the failure mode analysis
switches (IGBTs/MOSFETs and their antiparallel diodes) of the 3Φ5L E-Type Converter is addressed in this paper.
and diodes, DC-bus capacitors and flying capacitors for Comprehensive investigation of all the major failure modes
different single-phase five levels topologies are shown in that might occur during the converter operation. Particularly,
Table I. the power devices of the 3Φ5L E-Type Converter being
Table I. Main devices in single-phase 5-level inverter topologies. involved under either short-circuit or open-circuit failures on
Switches/ DC-bus Flying the long-term time scale (i.e., from 10μs to 100ms) are being
diodes capacitors capacitors
5L E-Type Inverter 8 4 - considered and analyzed in this paper. It must be clarified that
5L CHB Inverter [19]-[20] 8 2 - the analysis of faults being considered in this paper is referred
5L TCHB Inverter [21]-[22] 10 2 - only to a long-term time scale as defined in the following. On
5L MAC Inverter [23] 20 4 6 the other hand, the analysis related to the short-term time
Modified 5L MAC Inverter [24] 28 4 -
5L NPP Inverters [25] 12 2 2 scale would require a different approach and it will be
5L NPC Inverter [26] 20 4 - addressed in a future separate paper.
5L modified NPC Inverter [26] 26 4 - As an additional contribution of this paper, a suitable
As it can be seen, the 5L E-Type inverter and the based CHB strategy is proposed in order to identify the power
inverter make use of fewer devices compared to the other semiconductors’ faults and manage them running the
topologies; among these converters the 5L CHB inverter, the converter in a safe operating condition. In the 5L CHB
5L TCHB Inverter and the 5L NPP Inverters present fewer inverter there isn't a worse or a better failure cases; the failure
DC-bus capacitors. However, the proposed 5-L E-Type of a single device leads to the lack of a voltage level. In the
inverter may have better conduction and switching losses 5L E-Type topology, there are same catastrophic cases, but
compared to the other topologies including the 5L CHB there are other conditions in which the converter works in
Inverter. As it can be seen form Table II, in the worst “quasi-normal operation”. In order to improve the fault
conditions, during the peak (either positive or negative) of the tolerant capability, the topologies proposed in [21]-[26]
inverter modulation index, the current flows through two require a higher number of power devices when compared to
semiconductor power devices in the proposed 5L E-Type the 5L E-Type topology.
inverter, whereas the phase current flows through three or As the number of semiconductors increases the layout of the
even four semiconductor power devices into the other power board and the driver circuits must be carefully
converters. designed. In this case, a properly designed PCB power board
has been used for the 3Φ5L E-Type Inverter prototype in
Table II. Maximum voltage stress in 5-level inverter topologies. order to reduce the parasitic inductances. However, other
Current Power DC-bus Flying
path devices capacitors capacitors fault tolerance topologies show high number of the power
devices voltage voltage voltage semiconductors, thus, the cost to realize both power board
stress stress stress and gate driver board is greater than to the 5L E-Type
3 1
5L E-Type Inverter 2 /4VBUS /4VBUS -
5L CHB Inverter
Inverter. Furthermore, using less power devices compared to
4 VBUS VBUS - the other topologies, the 5L E-Type Inverter allows to
[19]-[20]
5L TCHB Inverter
3 VBUS 1
/2VBUS - improve the efficiency. Consequently, the heatsink size and
[21]-[22] weight for the three-phase 5L T-Type Inverter will be smaller
5L MAC Inverter 1 1 1
4 /4VBUS /2VBUS /4VBUS than the other three-phase 5L fault tolerant topologies.
[23]
Modified 5L MAC 1 1 - After having recalled in Section II various types of fault
4 /4VBUS /4VBUS
Inverter [24] being under consideration for the converter semiconductors,
5L NPP Inverters
[25]
4 1
/2VBUS 1
/2VBUS 1
/4VBUS in section III the 3Φ5L E-Type Converter is briefly discussed
5L NPC Inverter 1 1
and the different switch states are defined. In section IV, the
4 /4VBUS /4VBUS -
[26] converter under fault conditions on the long-term scale (from
5L modified NPC 1 1 10µs up to 100ms) is analyzed. Particularly, short-circuit and
4 /2VBUS /4VBUS -
Inverter [26]
open-circuit faults of the power semiconductors located in the
On the other hand, except for the 5L CHB Inverter and the 5L 3Φ5L E-Type Converter are investigated. Critical failure
TCHB Inverter, the voltage stress across the capacitors of the modes are identified and discussed and then a synthesis of all
5L E-Type inverter is greater than the other topologies. faults is given. The proposed failure detection algorithm and
Nevertheless, during the commutation each power the protection actions, as well as the achieved experimental
semiconductor is switched at 1/4VBUS, whereas, when the results are shown in section V and section VI. Finally,
device must withstand the maximum stress of 3/4VBUS the conclusions are given in section VII.
current through it is equal to zero. This means that the
switching overvoltage Δv, related to the commutated current, II. FAILURE MODES OF THE DEVICES
does not occur during the maximum voltage stress of the Failure modes for the power semiconductor devices can be
device, but it occurs only when the voltage across the power identified by two states: open-circuit and short-circuit device.

0093-9994 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Prince Edward Island. Downloaded on September 05,2020 at 16:29:16 UTC from IEEE Xplore. Restrictions apply.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2020.3019358, IEEE
Transactions on Industry Applications

The open-circuit faults in the active power devices such as much lower than 10μs. In fact, the short circuit withstand time
MOSFETs and IGBTs can happen due to gate driver of SiC MOSFETs is estimated to be approximately 3 µs [7]
malfunctions or in case of device bonding wire failure. The (i.e. strongly depending to the manufacturer). Thus, in this
reasons of the short-circuit faults in a voltage source case much faster detection and shut down actions are
converter are related to either malfunctions of the gate mandatory for a reliable operation of such devices. For the
drivers, which lead to the unexpected turn on of the devices, fault conditions considered in this paper, the long-term time
or to unexpected breakdown condition occurring into a device scale is defined as the time from 10μs up to 100ms since the
(MOSFET, IGBT and diode). There are different causes of a fault occurs. The upper limit of 100ms corresponds to the
device breakdown as briefly discussed in the following. expected reaction and opening time of the converter circuit
1) The device over-temperature breakers [8].
The device junction over-temperature is one of the most
common root-cause of the device breakdown. If the junction III. 3Φ5L E-TYPE CONVERTER TOPOLOGY
temperature is high, the device will not fail immediately. A. Modulation of the 3Φ5L E-Type Inverter
High junction temperatures will cause high leakage currents, The circuit diagram of the 3Φ5L E-Type Converter is
which in return will cause additional blocking losses. The shown in Fig. 1.
blocking losses will further increase the junction temperature.
At a certain point, the temperature will start increasing
exponentially due to the thermal runaway. Finally, the device
will fail once the junction temperature exceeds a certain limit
[27]-[29].
2) The IGBT latch–up
The IGBT is a four-layer structure, having a parasitic
thyristor. In some conditions, such as very high dv/dt and very
high collector current, the parasitic thyristor can be triggered.
The IGBT will lose its turn-off controllability and it will
remain permanently conducting [30]-[33].
3) The device over-voltage
Whenever the device is turning-off, an additional voltage
is induced across the commutation inductance. This voltage
appears as an over-voltage across the device that is turning
off. As a consequence, the voltage rating of the devices
should be calculated as the sum of two terms: the maximum Fig. 1. Circuit diagram of the 3Φ5L E-Type Inverter.
blocking voltage at steady state and the commutation over-
The single-phase converter is composed by three cells: two
voltage, as in (1). The commutation overvoltage is a function
single leg structures (CELL 1 and CELL 3) and one T-Type
of 1) coefficient kR that considers the resonance of the DC-
leg (CELL 2). Each phase leg is accomplished by means of
bus circuit, 2) commutation inductance Lξ, 3) device current
slope disw/dt and 4) forward recovery voltage of the eight semiconductor switches SIxy and their own freewheeling
freewheeling diode VFR. diodes DIxy, with x ∈ {A, B, C}, y ∈ {A, B, 11, 12, 21, 22, 31,
64TRANSIENT
47448 32}. Upper and lower mid-circuits are connected to the DC-
678
STEADY STATE
di bus mid-point (terminal N) via the two power devices SIx21
Vsw = VBL (max) + k R Lξ sw + VFR (1) and SIx22. The DC-bus capacitors are split into four series
dt
connected capacitors CB1, CB2, CB3, and CB4. The unbalancing
If the device voltage exceeds the limit, the device blocking
voltage capacitors issue is not addressed in this paper. The
voltage may collapse within 100ns and the device fails in
DC-bus partial voltages across the capacitors are balanced
short-circuit [34]. As it can be seen from (1), the device over-
through the Series Resonant Balancing Circuits (RSBC) as
voltage can be caused by the turning-off of over-currents and
shown in [4]. The power devices are driven by pulse width
commutation inductance. To prevent this fault, the
modulated signals in order to provide the desired output
commutation inductance must be as low as possible and the
voltage. The modulation principle of the 3Φ5L E-Type
appropriate gate driver must be used. Another case is the
converter is shown in Fig. 2, where GSIxA, GSIx11, GSIx12, GSIx21,
snap-off behavior of the freewheeling diode [9]. The diode
GSIx22, GSIx31, GSIx32, and GSIxB are the driving signals for the
may snap-off under different conditions, such as very low
active devices SIxA, SIx11, SIx12, SIx21, SIx22, SIx31, SIx32, and SIxB,
temperatures, low forward current, high slope of the
respectively. The signal pairs (GSIx12, GSIxA), (GSIx22, GSix11),
commutation current and turn-off after a short conduction
(GSIx31, GSIx21) and (GSIxB, GSIx32) are two complementary
period [35], [36].
driving signals. Additionally, during the commutations of the
Open- and short-circuit faults can be defined on short-term
switches SIx32, and SIxB (or SIx12, and SIxA), the switch SIx31 (or
time scale and long-term time scale. Short-term time scale is
SIx11) is always closed. It is possible to discriminate 512
defined as the time up to 10μs after the initial fault. This limit
different switching states. Only 5 of the 512 switching states
corresponds to standard IGBT short-circuit capabilities
are actively used in the output voltage synthesis in which one
defined by manufacturers [32]. Undeniably, when SiC
state is the safety state (shutdown state 00000000). Allowed
MOSFETs are considered, the short-term time scale would be
states and resulting output voltages are given in Table III

0093-9994 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Prince Edward Island. Downloaded on September 05,2020 at 16:29:16 UTC from IEEE Xplore. Restrictions apply.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2020.3019358, IEEE
Transactions on Industry Applications

Fig. 3. Simplified circuit diagram of the 3Φ5L E-Type Inverter.

Fig. 2. PWM modulation control strategy of the 3Φ5L E-Type Converter.

(a)
TABLE III. Summary of allowed states and output voltage of the 3Φ5L
E-type converter. the output voltage reference is the mid-point.
GSIxA 1 0 0 0 0
GSIx11 1 1 0 0 0
GSIx12 0 1 1 1 1
GSIx21 1 1 1 0 0
GSIx22 0 0 1 1 1
GSIx31 0 0 0 1 1
GSIx32 1 1 1 1 0
GSIxB 0 0 0 0 1 (c)
(b)
Output 1 1 1 1
- /2VBUS - /4VBUS 0 /4VBUS /2VBUS Fig. 4. Current paths of the half circuit single-phase 5L E-Type converter:
Voltage a) state 3 at iA>0 and iA<0, b) state 4 at iA>0, c) state 5 at iA>0.
State 1 2 3 4 5
IV. LONG-TERM FAILURE OF THE 3Φ5L E-TYPE
A. The faulure modes in a 3Φ5L E-Type Inverter
CONVERTER TOPOLOGY
As it can be seen from Fig. 3, eight basic faults can be
This section is devoted to discussing the behavior of the
identified in the 3Φ5L E-Type Inverter: 1) the inner switch or
3Φ5L E-Type converter in case of device failures such as
the diode open-circuits, 2) the external switch or the diode
either the short-circuit or the open-circuit condition. The
open-circuits, 3) the top switch or the diode open-circuits, 4)
current paths in the converter during the state 3, state 4 and
the bottom switch or the diode open-circuits, 5) the inner state 5 are highlighted in green in Fig. 4. The load current
switch or the diode short-circuits, 6) the external switch or the flowing out from the converter is considered positive (iA > 0).
diode short-circuits, 7) the top switch or the diode short-
circuits, 8) the bottom switch or the diode short-circuits. Each A. Open-Circuit fault
of the mentioned faults has different effects on the converter
1) Inner switch fault
behavior. Some of the them, such as short-circuit faults and
diode open-circuit faults, reflect on the converter The inner switch works during the state 3 (resulting state
immediately, while others, the switch open circuit faults for vector is 00111010) and the inverter provides 0-level voltage.
example, have no immediate effects. The 3Φ5L E-Type In such condition, when the load current is positive and the
open-circuit fault occurs at SIA21, the fault is very difficult to
Inverter is a symmetrical structure, where the symmetry axes
be detected, since the current flows through SIx22 and DIx21.
are three identical single-phase converters A, B and C and
When the load current is negative (iA < 0), the current will
two DC-bus sides, the top circuit (from neutral N and positive flow through DIA31 and SIA32 instead of SIA21 and SIA22, as
DC-bus) and the bottom circuit (from neutral N and negative highlighted in red in Fig. 5a. Consequently, the output
DC-bus). Thus, the failure of one switch in one phase, for switching voltage becomes 1/4VBUS rather than zero, as shown
example SIA31, can be analyzed and the results can be in Fig. 5b. It can be seen from Fig. 5b, the current flow in the
extended to the opposite switch (SIA11) and to the other phases. output filter inductance is slightly different compared to the
For this reason, only the half-top circuit of the 3Φ5L E-Type normal conditions and the partial DC-bus voltages remain
converter will be analyzed in the following section. unchanged.

0093-9994 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Prince Edward Island. Downloaded on September 05,2020 at 16:29:16 UTC from IEEE Xplore. Restrictions apply.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2020.3019358, IEEE
Transactions on Industry Applications

2) External switch fault

The external switch works during the state 4. In this case,
the state vector is 00101110 and the output switching voltage
is 1/4VBUS.

(a)

(a)

(b)
Fig. 5. Open-circuit of SIx21: a) normal current path (green line) and fault
current path (red line), b) waveforms of switching voltage, output phase
current and DC-bus partial voltages.

(b)
Fig. 7. Open-circuit of SIx31: a) normal current path (green line) and fault
current path (red line), b) waveforms of switching voltage, output phase
current and DC-bus partial voltages.

When the open-circuit fault happens at SIA31 and the load

current is positive, the output voltage level is equal to zero
and the current path will be through SIA21 and SIA22. Fig. 7a
shows the normal current path highlighted in green and the
fault current path highlighted in red. The load current is zero
during the positive interval and the partial DC-bus voltages
show diverging trends. In such condition, the converter
(a)
operation is seriously compromised. The open-circuit fault of
DIA31 becomes a problem when the PF is less than 1, because
the current flows through SIA21-DIA22 and the output switching
voltage is kept at zero, as depicted in Fig. 8.

(b) Fig. 8. Open-circuit of DIx31: normal current path (green line) and fault
Fig. 6. Open-circuit of DIx21: a) normal current path (green line) and fault current path (red line).
current path (red line), b) waveforms of switching voltage, output phase
current and DC-bus partial voltages. 3) Top switch fault
The symmetrical situation happens in case of freewheeling The top switch fault occurs during the state 4 (00101110
diode DIA21 open-circuit fault and the load current is positive state vector) and state 5 (00101101 state vector).
(iA > 0). In this condition, the current starts to flow in SIA12 and
DIA11 instead of SIA22 and DIA21, as shown in Fig. 6a.
Consequently, the output switching voltage, during the small-
time interval, is -1/4VBUS rather than zero, as depicted in Fig.
6b. In both situations, the partial DC-bus voltages don’t show
diverging trends and the total harmonic distortion output
current (THDi) is about equal to 4.85%. These faults are very (a) (b)
difficult to be recognized due to the quasi-normal operation Fig. 9. Open-circuit of SIx32: a) iA>0, b) iA<0. Normal current path (green
line) and fault current path (red line).
of the converter.

0093-9994 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Prince Edward Island. Downloaded on September 05,2020 at 16:29:16 UTC from IEEE Xplore. Restrictions apply.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2020.3019358, IEEE
Transactions on Industry Applications

Considering the state 4, in case of SIA32 open-circuit fault and
positive current (iA>0) the load current starts to flow in the
antiparallel diode DIA32 and the converter continues to operate
without any serious damages, as shown in Fig. 9a.
the normal operation of the converter. The open-circuit
failure of the freewheeling diode DIAB is relevant when the
load current becomes negative (iA<0) as well as for the
freewheeling diode DIA32. The current flows through the
middle leg and the output switching voltage is 0 V instead of
1
/2VBUS. In this case, no serious damages are reported at the
converter.

(a)

(a)

(b)
Fig. 10. Open-circuit of DIx32 during the dead-time: a) normal current path
(green line) and fault current path (red line), b) waveforms of switching
voltage, output phase current and DC-bus partial voltages.

When the load current is negative (iA<0), the current goes in

DIAB instead of SIA32 or DIA32, as illustrated in Fig. 9b. The fault
is very difficult to be detected due to the quasi-normal
operation of the converter and THDi is equal to 5%. As it can (b)
be seen from Fig. 10a, the open-circuit fault of DIx32 becomes Fig. 12. Waveforms of switching voltage, output phase current and DC-
important during the dead-time, because the current flows bus partial voltages under short-circuit of: a) SIx12, b) SIx31.
through the middle leg. Thus, during the transition from the
state 4 and state 5, the output switching voltage varies
between 1/4VBUS, 1/2VBUS, and 0, 1/2VBUS, as highlighted in Fig.
10b. During the state 5 the output switching voltage is 1/2VBUS.

(a)

(a)

(b)
Fig. 11. Open-circuit of SIxB: a) normal current path (green line) and fault
current path (red line), b) waveforms of switching voltage, output phase
current and DC-bus partial voltages.
If the open-circuit fault happens at SIAB, the output switching
voltage is saturated at 1/4VBUS, the load current appears to be
damped and the partial DC-bus voltages become unbalanced,
as shown in Fig. 11. This fault is particularly dangerous for
(b)
Fig. 13. Waveforms of switching voltage, output phase current and DC-bus
partial voltages under short-circuit of a) SIx32, b) SIxB.
The short-circuit faults at SIx21, SIx31, SIx32 and SIxB have strong
impact on the system, leading to high short-circuit current
flowing in both the power devices and DC-bus capacitors.
The waveforms of the devices SIx21, SIx31, SIx32 and SIxB under
normal and short-circuit fault operating modes are shown in
Fig. 12 and Fig. 13.

0093-9994 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Prince Edward Island. Downloaded on September 05,2020 at 16:29:16 UTC from IEEE Xplore. Restrictions apply.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2020.3019358, IEEE
Transactions on Industry Applications

TABLE IV. Faults summary on the half circuit of the 5l e-type inverter for
B. Short-Circuit fault long-term scale.
In these conditions, the converter operation can be Open-Circuit
State Fault Converter behavior Condition
seriously compromised, and an appropriate fault-tolerance SIx21 The zero-level is missing in the
strategy should be implemented. All possible faults and the output switching voltage when the Quasi-normal
converter behavior on long-term scale are summarized in current is negative.
1
Table IV. DIx21 The zero-level is missing in the
output switching voltage when the Quasi-normal
current is positive.
V. FAILURE DETECTION ALGORITHM SIx31 The positive level is missing in the
Dangerous
A failure detection control strategy is being proposed in order output switching voltage.
DIx31 During the DT the output switching
to achieve high reliability and fault ride-through performance voltage is kept to zero.
Dangerous
of the proposed multilevel topology. The control algorithm is 2
When the PF≤1 the output switching
SIx32 Quasi-normal
used to detect the fault and to manage it in such a way that voltage is kept to zero
the converter keeps feeding the load as long as possible. ¼VBUS level is missing in the output
DIx32 Quasi-normal
switching voltage during the DT.
According to the previous analysis, the fault in a device can
½VBUS level is missing in the output
be detected easily by monitoring the waveforms of the SIxB
switching voltage.
Dangerous
switching voltages, currents and DC-bus partial voltages. 3
½VBUS level is missing in the output
DIxB Quasi-normal
After the fault has been detected, the control algorithm can switching voltage when the PF≤1.
change the commutation paths of the faulty phase. In some Short-Circuit
SIx21
cases, the 5L E-Type Converter does not suffer of SIx31
The output switching voltage goes to
catastrophic damages when a failure occurs, and thereby it 1,2,3 zero and the DC-bus voltages Catastrophic
SIx32
strongly increases
can continue to feed the load. In other cases, the normal SIxB
operation of the converter requires that a supplementary
phase-leg is available whenever a failure occurs. The block
scheme of the proposed fault-tolerant control strategy when a
single failure occurs is shown in Fig. 14. The block diagram
of diagnosis strategy is shown Fig. 15. In order to detect the
open-circuit, the phase-to-neutral switching voltage and the
phase-to-neutral voltage have been measured. The switching
voltage is composed by six sectors, as shown in Fig. 16. In
each sector are switched two power devices in opposite phase
(Sector 1,3: SIA21 ↔ SIA31; Sector 2: SIAB ↔ SIA32; Sector 4,6: Fig. 16. Output switching voltage.
SIA11 ↔ SIA22; Sector 5: SIAA ↔ SIA12). One level (or more
levels) is missing in the phase-to-neutral switching voltage Based on the converter behavior listed in Table IV, an
when the open-circuit occurs. optimum threshold number ГSW,TH has been obtained for each
device. The open-circuit fault is detected monitoring both the
phase-to-neutral switching voltage Vx(sw) and the DC-bus
voltages VCB,L=VCB1+VCB2 and VCB,H=VCB3+VCB4. The
measured phase-to-neutral switching voltage Vsw is compared
to the sector threshold voltage. When the measured switching
voltage does not exceed the threshold voltage in a specific
sector and DC-bus voltages VCB,L, VCB,H are within the
voltage range VCB,L(TH)-VCB,H(TH) , the Open Circuit Fault
Indicator (OCFI) related to the device is set at low value, as
given in (2). The device fault is detected when the OCFI is
set at high value.
Fig. 14. Flowchart of the failure detection algorithm in a single device
 0 if V
 x ( sw ) < VTH ,1...,6 AND
failure.


=
OCFI  VCB,L(TH) ≤ VCB,L ≈ VCB,H ≤ VCB,H(TH) (2)
SW

1 otherwise

In order to detect the short-circuit, the number of the
commutation rising edges ГSW is considered. When the value
of ГSW in a specific sector is lower than the switching
threshold ГSW,TH, and VCB,L, VCB,H are within the voltage range
Fig. 15. Block scheme of the fault diagnosis strategy. VCB,L(TH)-VCB,H(TH) , the Short Circuit Fault Indicator (SCFI)
related to the switch is set at low state as shown in (3). The
Thus, a sector threshold voltage has been created in each
short-circuit is detected when the SCFI is set (state 1).
sector (VTH1,…,VTH6) of the phase-to-neutral switching
 0 if Γ SW < Γ SW ,TH AND
voltages. The measured switching voltage is compared to the 

threshold voltage in each sector. In this way, the number of =
SCFI  VCB,L(TH) ≤ VCB,L ≈ VCB,H ≤ VCB,H(TH) (3)
SW

the switching rising edges ГSW for each device can be 1 otherwise fault

calculated.

0093-9994 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Prince Edward Island. Downloaded on September 05,2020 at 16:29:16 UTC from IEEE Xplore. Restrictions apply.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2020.3019358, IEEE
Transactions on Industry Applications

VI. EXPERIMENTAL VALIDATION devices OCFISIx32, OCFISIxB are set to high logical value
The proposed failure detection algorithm has been tested on (5V/div), as shown in Fig. 20.
the multilevel converter prototype. A picture of the converter
prototype is shown in Fig. 17 with outer dimensions of 500
mm × 300 mm × 40 mm, a total volume of about 2 dm3, which
results in a power density of about 8 kW/dm3.

Fig. 18. Open-circuit fault detection of SIx21. Phase-to-neutral switching

voltage VA(sw) (200V/div) and phase-to-neutral voltage VAN (200V/div) under
Fig. 17. Hardware prototype of the 3Φ5L E-Type Converter. open circuit fault of SIx21.

As it can be seen from Fig. 17, only one phase has been
populated. Each phase is composed by two interleaving 5L
E-Type converter in back to back configuration [5]. The
single-phase 5L E-Type Inverter has eight discrete
components. The devices SIxA, SIx12, SIx32, SIxB are
OptiMOSFETs (manufacturer Infineon, part number
IPT210N25NFD), the devices SIx31, SIx11 are Si-MOSFETs
(manufacturer Wolfspeed, part number C3M0030090K) and
the devices SIx31, SIx32 are Si-IGBTs (manufacturer Infineon,
part number IKW20N60T). The control algorithm has been
verified only on the inverter side. The modulation and the Fig. 19. Normalized phase-to-neutral voltage harmonic content in case of
proposed algorithm of the converter have been implemented SIx12 open-circuit fault.
in LabVIEW environment and it runs on a dedicated control
board, which uses the National Instruments System-on-
Module (sbRIO-9651) [37]. The tests have been performed
considering four series programmable DC power supplies
with a total DC-bus voltage VBUS equal to 700V, RMS output
voltage Vout=230V, the switching frequency fsw=24kHz and
the fundamental frequency f0=50Hz. An appropriate voltage
measurement circuit, which uses a high bandwidth voltage
transducer (Entube Z), has been used to sense the switching
voltage. Current transducers (LAH 25-NP) have been utilized
to sense the phase current and the Yokogawa DL9140
oscilloscope has been used to analyses voltage and current
waveforms.
A. Fault detection (a)

Considering the single fault device, when the open-circuit

fault occurs at SIx21, SIx32 the interested phase operates at a
quasi-normal condition, feeding the load even at full power.
The control algorithm allows to identify the fault as soon as
it is possible before a catastrophic failure can occur, as shown
in Fig. 18. It can be seen from Fig. 18 that the OCFISIx21 is set
to high logical value (5V/div) when the fault is detected.
Furthermore, the fault is identified in one switching period
Tsw (41μs). Fig. 19 shows the normalized harmonic content of
the phase-to-neutral voltage VAN, where the magnitude is
normalized with respect to the fundamental. In case of open-
circuit fault concerning the switch SIx12, harmonics 2nd, 3rd,
5th, 7th, 8th, 10th show a relatively high tone compared to other
tones. In case of SIx31, SIxB open circuit, the fault can be (b)
dangerous for the system; thus, a proper action should be Fig. 20. Open-circuit fault detection of SIxB. Phase-to-neutral switching
taken. Once again, the proposed algorithm identifies the fault voltage VA(sw) (200V/div) and phase-to-neutral voltage VAN (200V/div) under
open circuit fault of a) SIx31 and b) SIxB.
as soon as possible and the fault indicators related to the

0093-9994 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Prince Edward Island. Downloaded on September 05,2020 at 16:29:16 UTC from IEEE Xplore. Restrictions apply.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2020.3019358, IEEE
Transactions on Industry Applications
The normalized harmonic content of the phase-to-neutral
voltages in case of SIx31 and SIx31 open-circuit faults are
illustrated in Fig. 21. The amplitude is normalized with
respect to the fundamental. It can be noticed that even
harmonics are not negligible, especially in case of failure of
SIx31, where the positive voltage is missing. Finally, Fig. 22
shows the short circuit of the device SIx31.
(a)
(b)
Fig. 21. Normalized phase-to-neutral voltage harmonic content in case of a)
SIx31 open-circuit fault, b) SIxB open-circuit fault.
Fig. 22. Short-circuit fault detection of SIx31. Phase-to-neutral switching
voltage VA(sw) (200V/div) and phase-to-neutral voltage VAN (200V/div) under
short circuit fault of SIx31.
Fig. 23. Normalized phase-to-neutral voltage harmonic content in case of
SIx31 short-circuit fault.
0093-9994 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Prince Edward Island. Downloaded on September 05,2020 at 16:29:16 UTC from IEEE Xplore. Restrictions apply.
It can be noticed that as soon as the short circuit happens, the
fault indicator SCFISIx31 changes to the high logical value and
all the switches are turned-off. Fig. 23 illustrates the
normalized harmonic content of the phase-to-neutral voltages
in case of SIx31 short-circuit fault. In this case, when the fault
occurs, the output voltage is equal to zero and the 2nd
harmonic has a high amplitude.
B. Fault management
It is possible to manage the open circuit fault in two different
cases: 1) the control can identify the fault safety shutdown
action (like open all the power devices) is applied, 2) the fault
can be recognized, and the redundant switches can be used to
assure the proper power supply to the load. For example, Fig.
24 shows the phase-to-neutral switching voltage VA(sw) and
the phase-to-neutral voltage VAN in case of open circuit fault
at SIx31. The fault is identified and the current starts flowing
through the device (SˈIx31) of the supplementary leg. When
the open-circuit fault happens at SIx32 (or SIxB), the fault can
be handled by a different control strategy as in the following.
Fig. 24. The open-circuit fault of SIx31 is detected and cleared by turning
parallel device (SˈIx31) on. Line-neutral switching voltage VA(sw) (200V/div),
phase-to-neutral voltage VAN (200V/div) and DC-bus voltages VCB,L and VCB,H
(100V/div).
Fig. 25. The open-circuit fault of SIxB is detected and cleared reducing the
amplitude of the modulating signal. Line-neutral switching voltage VA(sw)
(200V/div), phase-to-neutral voltage VAN (200V/div), and DC-bus voltages
VCB,L and VCB,H (100V/div).
Particularly, in order to avoid the redundant switches, the
control algorithm changes the current path, reducing the
modulating signal, and only three voltage levels are provided
at the output of the leg keeping to feed the load, as shown in
Fig. 25. The sort-circuit at SIx21, SIx31, SIx32 and SIxB is managed
by the control in two different cases. If the redundant leg is
not used, the control algorithm shuts down the converter as
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2020.3019358, IEEE
Transactions on Industry Applications
soon as the fault is identified, as shown in Fig. 22. If the
redundant leg is used and a short circuit occurs, all the
switches of the faulty leg are turned-off and the redundant leg
is activated.
Fig. 26. The short-circuit fault of SIx31 is detected and cleared by turning on
the devices located in the redundant leg and turning off the devices located
in the fault leg. Line-neutral switching voltage VA(sw) (200V/div), phase-to-
neutral voltage VAN (200V/div), and DC-bus voltages VCB,L and VCB,H
(100V/div).
Fig. 26 shows the voltage waveforms in case a short circuit at
SIx31 occurs. When the fault indicator SCFISIx31 is high, the
redundant phase is activated, and the fault is removed. As it
can be seen from Fig. 24 to Fig. 26, the partial DC-bus
voltages are still balanced since the failure detection
algorithm detects the fault and applies a proper action in one
switching period (41μs), before the failure can affect the DC-
bus capacitors voltages.
VII. CONCLUSIONS
This paper has discussed all the possible fault conditions
that might occur in the 3Φ5L E-Type Power Converter.
Effects of open-circuit and short-circuit faults on long-term
time scale of the power semiconductors that are being utilized
in the 3Φ5L E-Type inverter have been investigated. Table
IV summarizes the possible failure modes of the devices on
the long-term time scale. According to the performed
analysis, it is shown that in most cases the converter can be
kept in operation when the protection system reacts rapidly
selecting the right action to take. Hence, a suitable fault-
tolerant control strategy can be defined accordingly. The
effectiveness of the proposed failure detection control
strategy has been validated using a prototype of the newly
conceived multilevel converter. The experimental results
show that in some fault conditions the converter remains
capable to feeding the load, whereas in other fault conditions
the control algorithm is required to act in order to change the
current path for properly supplying the load. Further
development on this topic will include the analysis of
switches faults in the short-term time scale.
REFERENCES
[1] S. Y. Mousazadeh Mousavi, A. Jalilian, M. Savaghebi and J. M.
Guerrero, "Autonomous Control of Current- and Voltage-Controlled
DG Interface Inverters for Reactive Power Sharing and Harmonics
Compensation in Islanded Microgrids," in IEEE Transactions on Power
Electronics, vol. 33, no. 11, pp. 9375-9386, Nov. 2018.
[2] A. Verma, R. Krishan and S. Mishra, "A Novel PV Inverter Control for
Maximization of Wind Power Penetration," in IEEE Transactions on
Industry Applications, vol. 54, no. 6, pp. 6364-6373, Nov.-Dec. 2018.
[3] F. Ma, Z. He, Q. Xu, A. Luo, L. Zhou and M. Li, "Multilevel Power
Conditioner and its Model Predictive Control for Railway Traction
0093-9994 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Prince Edward Island. Downloaded on September 05,2020 at 16:29:16 UTC from IEEE Xplore. Restrictions apply.
System," in IEEE Transactions on Industrial Electronics, vol. 63, no.
11, pp. 7275-7285, Nov. 2016.
[4] M. di Benedetto, A. Lidozzi, L. Solero, F. Crescimbini and P. J.
Grbović, "Five-Level E-Type Inverter for Grid-Connected
Applications," in IEEE Transactions on Industry Applications, vol. 54,
no. 5, pp. 5536-5548, Sept.-Oct. 2018.
[5] M. Di Benedetto, L. Solero, F. Crescimbini, A. Lidozzi and P. J.
Grbović, "5-Level E-type back to back power converters—A new
solution for extreme efficiency and power density," 2017 13th
Conference on Ph.D. Research in Microelectronics and Electronics
(PRIME), Giardini Naxos, 2017, pp. 341-344.
[6] B. Lu and S. K. Sharma, “ A literature review of IGBT fault diagnostic
and protection methods for power inverters”, IEEE Transaction
Industry Applications, Vol. 24, No. 5, pp. 1770-1777,
September/October 2009.
[7] P. D. Reigosa, F. Iannuzzo, H. Luo and F. Blaabjerg, "A Short-Circuit
Safe Operation Area Identification Criterion for SiC MOSFET Power
Modules," in IEEE Transactions on Industry Applications, vol. 53, no.
3, pp. 2880-2887, May-June 2017.
[8] P. J. Grbović, F. Gruson, N. Idir and P LE Moigne, "Turn-on
Performance of Reverse Blocking IGBT (RB-IGBT) and Optimization
Using Advanced Gate Driver" IEEE Trans Power Electronics, Vol. 25,
No. 4, pp. 970-980, April 2010.
[9] M. T. Rahimo and N. Y.A. Shammas, “Freewheeling diode reverse
recovery failure modes in IGBT applications”, IEEE Trans Industry
Applications, Vol. 37, No. 2, pp 661-670, March/April 2001.
[10] Y. Chen, W. Li, F. Iannuzzo, H. Luo, X. He and F. Blaabjerg,
"Investigation and Classification of Short-Circuit Failure Modes Based
on Three-Dimensional Safe Operating Area for High-Power IGBT
Modules," in IEEE Transactions on Power Electronics, vol. 33, no. 2,
pp. 1075-1086, Feb. 2018.
[11] U. Choi, K. Lee and F. Blaabjerg, "Diagnosis and Tolerant Strategy of
an Open-Switch Fault for T-Type Three-Level Inverter Systems," in
IEEE Transactions on Industry Applications, vol. 50, no. 1, pp. 495-
508, Jan.-Feb. 2014.
[12] R. Katebi, J. He and N. Weise, "Investigation of Fault-Tolerant
Capabilities in an Advanced Three-Level Active T-Type Converter,"
in IEEE Journal of Emerging and Selected Topics in Power
Electronics, vol. 7, no. 1, pp. 446-457, March 2019.
[13] S. K. Maddugari, V. B. Borghate, S. Sabyasachi and R. R. Karasani,
"A fault tolerant cascaded multilevel inverter topology for open circuit
faults in switches," 2017 IEEE Transportation Electrification
Conference (ITEC-India), Pune, 2017, pp. 1-5.
[14] J. Lee and K. Lee, "Open-Circuit Fault-Tolerant Control for Outer
Switches of Three-Level Rectifiers in Wind Turbine Systems," in IEEE
Transactions on Power Electronics, vol. 31, no. 5, pp. 3806-3815, May
2016.
[15] P. Lezana, J. Pou, T. A. Meynard, J. Rodriguez, S. Ceballos and F.
Richardeau, "Survey on Fault Operation on Multilevel Inverters," in
IEEE Transactions on Industrial Electronics, vol. 57, no. 7, pp. 2207-
2218, July 2010.
[16] F. Wang, R. Lai, X. Yuan, F. Luo, R. Burgos and D. Boroyevich,
"Failure-Mode Analysis and Protection of Three-Level Neutral-Point-
Clamped PWM Voltage Source Converters," in IEEE Transactions on
Industry Applications, vol. 46, no. 2, pp. 866-874, March-april 2010.
[17] A. Lidozzi, M. Di Benedetto, L. Solero, F. Crescimbini and P. J.
Grbovic, "Fault tolerance analysis for the 5-level unidirectional T-
Rectifier," 2016 IEEE Energy Conversion Congress and Exposition
(ECCE), Milwaukee, WI, 2016, pp. 1-7.
[18] M. d. Benedetto, A. Lidozzi, L. Solero, F. Crescimbini and P. J.
Grbovic, "Failure Mode Analysis of the 3-Phase 5-Level E-Type
Converter," 2019 IEEE Energy Conversion Congress and Exposition
(ECCE), Baltimore, MD, USA, 2019, pp. 6396-6403.
[19] S. Kim, J. Lee and K. Lee, "A Modified Level-Shifted PWM Strategy
for Fault-Tolerant Cascaded Multilevel Inverters with Improved Power
Distribution," in IEEE Transactions on Industrial Electronics, vol. 63,
no. 11, pp. 7264-7274, Nov. 2016.
[20] S. Ouni et al., "Improvement of Post-Fault Performance of a Cascaded
H-bridge Multilevel Inverter," in IEEE Transactions on Industrial
Electronics, vol. 64, no. 4, pp. 2779-2788, April 2017.
[21] S. P. Gautam, S. Gupta and L. Kumar, "Reliability improvement of
transistor clamped H-bridge-based cascaded multilevel inverter," in
IET Power Electronics, vol. 10, no. 7, pp. 770-781, 10 6 2017.
[22] S. P. Gautam, L. Kumar, S. Gupta and N. Agrawal, "A Single-Phase
Five-Level Inverter Topology With Switch Fault-Tolerance
Capabilities," in IEEE Transactions on Industrial Electronics, vol. 64,
no. 3, pp. 2004-2014, March 2017.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2020.3019358, IEEE
Transactions on Industry Applications
[23] Alian Chen, Lei Hu, Lifeng Chen, Yan Deng and Xiangning He, "A
multilevel converter topology with fault-tolerant ability," in IEEE
Transactions on Power Electronics, vol. 20, no. 2, pp. 405-415, March
2005.
[24] J. Nicolas-Apruzzese, S. Busquets-Monge, J. Bordonau, S. Alepuz and
A. Calle-Prado, "Analysis of the Fault-Tolerance Capacity of the
Multilevel Active-Clamped Converter," in IEEE Transactions on
Industrial Electronics, vol. 60, no. 11, pp. 4773-4783, Nov. 2013.
[25] S. Ye, J. Jiang, J. Li, Y. Liu, Z. Zhou and C. Liu, "Fault Diagnosis and
Tolerance Control of Five-Level Nested NPP Converter Using Wavelet
Packet and LSTM," in IEEE Transactions on Power Electronics, vol.
35, no. 2, pp. 1907-1921, Feb. 2020.
[26] W. Chen, E. Hotchkiss and A. Bazzi, "Reconfiguration of NPC
multilevel inverters to mitigate short circuit faults using back-to-back
switches," in CPSS Transactions on Power Electronics and
Applications, vol. 3, no. 1, pp. 46-55, March 2018.
[27] M. D. Kelley, B. N. Pushpakaran and S. B. Bayne, "Single-Pulse
Avalanche Mode Robustness of Commercial 1200 V/80 mΩ SiC
MOSFETs," in IEEE Transactions on Power Electronics, vol. 32, no.
8, pp. 6405-6415, Aug. 2017.
[28] Y. Lee and J. Kim, "Monitoring ON-Resistance of MOSFET Devices
in Real Time for SVPWM-VSI With Direct Compensation," in
Canadian Journal of Electrical and Computer Engineering, vol. 41, no.
1, pp. 28-34, winter 2018.
[29] S. Lefebvre, Z. Khatir and F. Saint-Eve, "Experimental behavior of
single-chip IGBT and COOLMOS devices under repetitive short-
circuit conditions," in IEEE Transactions on Electron Devices, vol. 52,
no. 2, pp. 276-283, Feb. 2005.
[30] D. W. Brown, M. Abbas, A. Ginart, I. N. Ali, P. W. Kalgren and G. J.
Vachtsevanos, "Turn-Off Time as an Early Indicator of Insulated Gate
Bipolar Transistor Latch-up," in IEEE Transactions on Power
Electronics, vol. 27, no. 2, pp. 479-489, Feb. 2012.
[31] M. Trivedi and K. Shenai, "IGBT dynamics for clamped inductive
switching," in IEEE Transactions on Electron Devices, vol. 45, no. 12,
pp. 2537-2545, Dec. 1998.
[32] Kwang-Hoon Oh, Young Chul Kim, Kyu Hyun Lee and Chong Man
Yun, "Investigation of short-circuit failure limited by dynamic-
avalanche capability in 600-V punchthrough IGBTs," in IEEE
Transactions on Device and Materials Reliability, vol. 6, no. 1, pp. 2-
8, March 2006.
[33] Z. Khatir and S. Lefebvre, "Thermal analysis of power cycling effects
on high power IGBT modules by the boundary element method,"
Seventeenth Annual IEEE Semiconductor Thermal Measurement and
Management Symposium (Cat. No.01CH37189), San Jose, CA, USA,
2001, pp. 27-34.
[34] P. J. Grbovic and P. R. Field, "Analysis of the possibility to use 1200
V IGBT devices in snubberless medium power motor converters
supplied from the 600 V mains," 2005 European Conference on Power
Electronics and Applications, Dresden, 2005, pp. 10 pp.-P.10.
[35] F. Pulsinelli, M. di Benedetto, A. Lidozzi, L. Solero and F.
Crescimbini, "Power Losses Distribution in SiC Inverter Based Electric
Motor Drives," in IEEE Transactions on Industry Applications, vol. 55,
no. 6, pp. 7843-7853, Nov.-Dec. 2019.
[36] J. Chen, L. Cao and Y. Zang, "Turn-Off Over-Voltage character of
6500V/600A IGBT Module," 2019 IEEE International Conference on
Electron Devices and Solid-State Circuits (EDSSC), Xi'an, China,
2019, pp. 1-3.
[37] A. Lidozzi, M. Di Benedetto, V. Sabatini, L. Solero and F. Crescimbini,
"Towards LabVIEW and system on module for power electronics and
drives control applications," IECON 2016 - 42nd Annual Conference
of the IEEE Industrial Electronics Society, Florence, 2016, pp. 4995-
5000.
Marco di Benedetto (S’16–M’18) received the
M.Eng. degree in Electronic Engineering from the
University of Roma TOR VERGATA, Rome
(Italy), in 2014, and Ph.D. degree in Mechanical and
Industrial Engineering from ROMA TRE
University, in 2018.
Since November 2018, he is research fellow at
Center of Power Electronics and Drives (C-PED) at
the ROMA TRE University. His research interests
are mainly focused on hardware and FPGA control
design for multilevel power converter topologies.
0093-9994 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Prince Edward Island. Downloaded on September 05,2020 at 16:29:16 UTC from IEEE Xplore. Restrictions apply.
Alessandro Lidozzi (S’06–M’08) received the
Electronic Engineering degree and the Ph.D.
degree from the Roma Tre University, Rome, Italy,
in 2003 and 2007, respectively.
From 2010 to 2017, he was Researcher with the
Department of Engineering, ROMA TRE
University; where, since 2017, he has been
Associate Professor. His research interests are
mainly focused on power converter modeling and
control, control of permanent magnet motor drives,
control aspects for power electronics in diesel-electric generating units, four-
leg converters and development of high-performance control platforms
based on combined DSP-FPGA systems.
Luca Solero (M’98) received the Electrical
Engineering degree from the University of Rome
“La Sapienza,” Italy, in 1994. Since 1996 he has
been with the Department of Engineering,
University ROMA TRE where he currently is a
Full Professor in charge of teaching courses in the
fields of Power Electronics and Industrial Electric
Applications. His current research interests include
power electronic applications to electric and hybrid
vehicles as well to distributed power and
renewable energy generating units. He has
authored or coauthored more than 150 technical published papers. Since
2018, he serves as Vice-Chair the IEEE IAS Industrial Power Converter
Committee IPCC. He serves as an Associate Editor of IEEE Transaction on
Industry Applications. Prof. Solero is a member of the IEEE Industrial
Electronics, IEEE Industry Applications, and IEEE Power Electronics
Societies.
Fabio Crescimbini (M’90) received his degree in
Electrical Engineering and the Ph.D. from the
University of Rome “La Sapienza,” Rome, Italy, in
1982 and 1987, respectively. From 1989 to 1998,
he was with the Department of Electrical
Engineering, University of Rome “La Sapienza,”
as the Director of the Electrical Machines and
Drives Laboratory. In 1998, he joined the brand-
new University named ROMA TRE, Rome, Italy,
where he is currently a Full Professor of Power
Electronics, Electrical Machines and Drives in the
Department of Engineering. His research interests include newly conceived
electrical machines and novel topologies of power electronic converters for
emerging applications such as electric and hybrid vehicles and electric
energy systems for distributed generation and storage.
Prof. Crescimbini served as a member of the Executive Board of the IEEE
Industry Applications Society (IAS) from 2001 to 2004. In 2000, he served
as Cochairman of the IEEE-IAS “World Conference on Industrial
Applications of Electric Energy” and, in 2010, he served as Cochairman of
the 2010 International Conference on Electrical Machines (ICEM). He was
a recipient of awards from the IEEE-IAS Electric Machines Committee,
including the Third Prize Paper in 2000 and the First Prize Paper in 2004.
Petar J. Grbovic (M’05-SM’08) received the Dipl.
Ing. (B. Sc.) and the Magister (M.Sc.) degrees from
the School of Electrical Engineering, University of
Belgrade, Serbia, in 1999 and 2005, and the Doctor
(Ph.D) degree from the Laboratoire
’Électrotechnique et d’Électronique de Puissance
de Lille, l’Ecole Centrale de Lille, France in 2010.
From March 1999 until September 2018 he was
various worldwide R&D centers; RDA Co. Serbia,
CESET Italy, PDL Electronics Ltd. New Zealand,
Schneider Electric France, General Electric Germany and Huawei
Technologies Germany. Since March 2016 he member of the scientific
committee of Centre of Power Electronics and Drives, C-PED Lab., Roma
TRE University, Italy. In June 2018 he was appointed to position of Full
Professor at Innsbruck Power Electronics Laboratory (i-PEL), the University
of Innsbruck, Austria. The focus of his research is on cutting-edge
technology of power semiconductors and their applications, application of
energy storage devices, active gate driving for high power IGBTs and JFET
SiC, power converters & topologies and control of power converters and
power semiconductors.