1

A MINOR PROJECT REPOR

ON

TOPIC

Submitted in partial fulfillment

for the award of the degree of

Bachelor of Technology

In

Electronics & Communication Engineering

(Rajasthan Technical University, Kota)

SESSION (2023-2024)

SUPERVISOR SUBMITTED BY:

NAME Name of Student
Designation Branch & Semester
RTU, Roll No.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

UNIVERSITY DEPARTMENTS, KOTA-324010

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 AKNOWLEDGEMENT

This is opportunity to express my heartfelt words for the people who were part of this
seminar in numerous ways, people who gave me unending support right from
beginning of the seminar.
I want to give sincere thanks to the Supervisor Dr. ……… for his valuable support.
I extend my thanks to Prof. Mithilesh Kumar, Head of the Department for his
Constant support.
I express my deep sense of gratitude to ‘Name of Project Coordinator’ for continuous
cooperation encouragement and esteemed guidance.

Yours Sincerely,
(Student Name)
Roll No.

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 UNIVERSITY DEPARTMENTS,

RAJASTHN TECHNICAL UNIVERSITY, KOTA

(State Technical University)
Rawatbhata Road, Kota – 324010

CERTIFICATE

This is to certify that the Minor Project Report entitled “Project Topic Name” has
been submitted by Mr./Ms. “Student name” in partial fulfillment of the requirement of
the degree of B.Tech in Electronics & Communication Engineering for the academic
Session 2023– 2024.
She has undergone the requisite work as prescribed by Rajasthan Technical University
Kota (Rajasthan).

(Name of Supervisor)
Asst. Professor
Department of ECE
Place:-
Date:-

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 ABSRACT

The aim of this paper is to design 8-bit ALU to perform seven arithmetic and five logical
operation using VHDL Xilinx Synthesis tool ISE 13.1 and implementing it on SPARTAN 3E
FPGA board to simulate and synthesize the design. The ALU consists of two input register
to hold two 8-bit inputs data during operation and one 8-bits output to hold the result of the
operation, 8-bit full-adder with B-input logic to perform 2’s complement for subtractions
and logic gates to perform logical operation.

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 INDEX

Page NO.

LIST OF FIGURES 4

LIST OF TABLES 4

CHAPTER -1 INTRODUCTION 5

1.1 OVERVIEW OF ALU

1.2 BLOCK DIAGRAM OF ALU
1.3 ARITHMATIC UNIT
1.4 LOGICAL UNIT
1.5 INPUT/OUTPUT OF ALU
1.6 FUNCTION TABLE OF ALU

CHAPTER -2 SIMULATION AND SYNTHESIS on Xilinx ISE 9

2.1 OVERVIER OF Xilinx ISE

2.2 OVERVIEW OF VHDL

2.3 SYNTHESIS RESULT

2.3.1 RTL View
2.3.2 Technology view
2.3.3 SYNTHESIS REPORT
2.4 SIMULATION

CHAPTER-3 IMPLEMENTATION on SPARTAN-3 Kit 15

3.1 PROCESSOR: XC3S400PQ208 Features

CONCLUSION 17

REFERENCE 18

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 LIST OF FIGURES AND TABLES

Figures Page
1.1 Symbol of ALU 5

1.2 Block Diagram of ALU 6

2.1 RTL Design 11

2.2 RTL Design inside Entity 11

2.3 Technology View 12

2.4 Simulation waveform of AND operation 13

2.5 Simulation waveform of SUB operation 14

3.1 Circuit diagram of ALU 16

Tables Page

1.1 B-Input Logic 7

1.2 Function Table of ALU 8

2.1 Summary of Device Utilization 13

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 CHAPTER-1

INTRODUCTION

1.1 OVERVIEW OF ALU :

ALU is the integral part of the Central Processing Unit for which it performs
the arithmetic and logical operation. The ALU takes input as the data to be operated on
(called operands) and a code, from the control unit, indicating which operation to perform.

The main operation of any processor is mainly fetching, decoding and executing an
instructions. The fetching of instructions is perform by instruction fetch unit, the decoding of
instructions is perform by decode unit(or control unit) which generate appropriate control
signals for ALU to carry-out the operation of instruction. These control signals refer to as
selection lines for ALU to select particular operation.

Fig 1.1 : Symbol of ALU

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1.2 BLOCK DIAGRAM OF ALU:

Fig 1.2: Block Diagram of ALU

1.3 ARITHMATIC UNIT:

Arithmetic operations performed are 8-bit addition and subtraction. Logical

operations performed are AND, OR, XOR and NOT. ALU also calculates 1’s and 2’s
complement for the 8-bit input for subtraction.
Arithmetic unit contains two blocks: 1) B-input logic
2) 8-bit Full-adder.
B-input logic is used to obtain 2’s complement of input B when the subtraction is going to
perform. The B-input logic reduces the complexity of the circuit.

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 S1 S0 Y=s1B’ +s0B
0 0 0
0 1 B
1 0 B’
1 1 1

TABLE 1.1 INPUT LOGIC

And Full-adder is used to get addition of two operand with input carry and 8-bit sum and 1-
bit carry.

1.4 LOGICAL UNIT :

Logical operations performed are AND, OR, XOR and NOT. 4 to1 MUX selects the
logic operations based on the select lines in the logic unit.

Both arithmetic and logical unit are performed the operation in parallel. Finally a
2 to1 MUX selects between arithmetic and logic unit. Zero flag is obtain by applying all the
lines of result to Nor gate. And Negative flag is obtain by taking the 7th bit of the result.

1.5 INPUT/OUTPUT OF ALU:

Inputs of ALU:
1. Two 8-bit Outputs of ALU: 1. One 8-bit result operand,
Operands A &B
2. Z (Zero), Cout (carry-
out),N(negative flags).
2. Operation
Selection lines :
S0, S1

: Cin (carry-in)

3. Result
selection line: M
= 1 : Arithmetic
result

= 0 : Logical
result

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1.6 FUNCTION TABLE OF ALU:

M S1 S0 CIN Operation Function

OPCODE
1000 1 0 0 0 Out =A Transfer A
1001 1 0 0 1 Out=A+1 Increment A
1010 1 0 1 0 Out =A+B Addition
1011 1 0 1 1 Out=A+B+1 Add with Carry
1100 1 1 0 0 Out=A+B’ A plus 1’s
complement of B
1101 1 1 0 1 Out=A+B’+1 Subtraction

1110 1 1 1 0 Out=A−1 Decrement A

1111 1 1 1 1 Out=A Transfer A
000X 0 0 0 X Out=A & B AND
001X 0 0 1 X Out=A | B OR
010X 0 1 0 X Out=A^B XOR
0110 0 1 1 0 Out=A’ NOT A(1’sComplement)
0111 0 1 1 1 Out=B’ NOT B(1’sComplement)

Table 1.2 Function Table of ALU.

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 CHAPTER-2

SIMULATION AND SYNTHESIS on Xilinx ISE

2.1 OVERVIEW OF Xilinx ISE:

Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of
HDL designs, which enables the developer to synthesize ("compile") their designs, perform
timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and

configure the target device with the programmer.

ISE Design Suite -The ISE Design Suite: Embedded Edition includes all the
tools and capabilities of the Logic Edition with the added capabilities of the Embedded
Development Kit (EDK). This edition provides an integrated development environment of
embedded processing tools, processor cores, IP, software libraries, and design generators,
including the following:

Xilinx Platform Studio (XPS) - provides an integrated environment for creating software and
hardware specification flows for embedded processor systems based on MicroBlaze and
PowerPC processors. It also provides an editor and a project management interface to create
and edit source code. XPS allows you to customize tool flow configuration options and
provides a graphical system editor for connection of processors, peripherals, and buses.

Hardware Platform Generation Tool (PlatGen) - customizes and generates the embedded
processor system through the use of hardware netlist. Hardware Description Language
(HDL)
files. By default, PlatGen synthesizes each processor IP core instance found in your
embedded hardware design using Xilinx Synthesis Technology (XST). PlatGen also
generates the system-level HDL file that interconnects all the IP cores, which can then be
synthesized as part of the overall design flow.

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Simulation Model Generation Tool (SimGen) - generates simulation models of the
embedded hardware system, based either on your original, behavioral embedded hardware
design or your finished, timing-accurate device implementation. SimGen can also
incorporate your embedded software to run on the model.

2.2 OVERVIEW OF VHDL:

VHDL (VHSIC hardware description language) is a hardware description

language used in electronic design automation to describe digital and mixed-signal systems
such as field-programmable gate arrays and integrated circuits.

VHDL is commonly used to write text models that describe a logic circuit. Such
a model is processed by a synthesis program, only if it is part of the logic design. A
simulation program is used to test the logic design using simulation models to represent the
logic circuits that interface to the design. This collection of simulation models is commonly
called a test bench.
The key advantage of VHDL, when used for systems design, is that it allows the
behavior of the required system to be described (modeled) and verified (simulated) before
synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system.

VHDL is a dataflow language, unlike procedural computing languages such as BASIC, C,
and assembly code, which all run sequentially, one instruction at a time.

VHDL project is multipurpose. Being created once, a calculation block can be

used in many other projects. However, many formational and functional block parameters
can be tuned (capacity parameters, memory size, element base, block composition
and
interconnection structure).

In this paper, we have simulated and synthesized the various parameters of ALUs
by using VHDL on Xilinx ISE 13.1 and SPARTAN 3E FPGA board.

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