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 EPWave
Testbench
From: + Design 
SystemVerilog/Verilog
0ns
UVM / OVM  (http://eda-playground.readthedocs.org/en/latest/intro.html#libraries-methodologies)
To:
None
75ns
Other Libraries  (http://eda-playground.readthedocs.org/en/latest/intro.html#libraries-methodologies)
None 
OVL Get
2.8.1Signals Radix    100%   -   
SVUnit 2.11 
0 10 20 30
Enable TL-Verilog  (http://www.redwoodeda.com)
C
Enable Easier UVM  (http://www.doulos.com/easier)
MEnable VUnit  (https://vunit.github.io/index.html)
S
 Tools
a & Simulators  (http://eda-playground.readthedocs.org/en/latest/intro.html#tools-simulators)
b
Synopsys VCS 2021.09
c
Compile Options  (http://eda-playground.readthedocs.org/en/latest/compile_run_options.html)
Note: To revert to +vcs+flush+all
-timescale=1ns/1ns EPWave opening in a new-sverilog
+warn=all browser window, set that option on your user page.

Run Options  (http://eda-playground.readthedocs.org/en/latest/compile_run_options.html)

Run Options
Use run.do Tcl file
Use run.bash shell script
Open EPWave after run
Show output file after run
Download files after run

 Examples

 Community

 Collaborate

 Forum (https://groups.google.com/forum/#!forum/eda-playground)

Follow @edaplayground

211

testbench.sv testbenchs.sv 
1 // Code your testbench here SV/Verilog Testbench 
2 module t_full_adder;
3 wire S,C;
4
5 reg a,b,c,M;
6
7 full_adder FA1(S,C,a,b,c,M);
8 initial
9 begin
10 $dumpfile("t_full_adder.vcd");

11 $dumpvars();  
12 a=1'b0;b=1'b0;c=1'b0;M=1'b0;;
13 #5 a=1'b0;b=1'b0;c=1'b1;M=1'b0;
#5 a=1'b0;b=1'b1;c=1'b0;M=1'b0; 
14
15 #5 a=1'b0;b=1'b1;c=1'b1;M=1'b0;
16 #5 a=1'b1;b=1'b0;c=1'b0;M=1'b0;
EPWave #5
17 a=1'b1;b=1'b0;c=1'b1;M=1'b0;
#5 a=1'b1;b=1'b1;c=1'b0;M=1'b0;
18
19 #5 a=1'b1;b=1'b1;c=1'b1;M=1'b0;
20 #5 a=1'b1;b=1'b1;c=1'b0;M=1'b1; 
21 #5 a=1'b1;b=1'b1;c=1'b1;M=1'b1;
22 #5 a=1'b1;b=1'b1;c=1'b0;M=1'b1;
23 #5 a=1'b1;b=1'b1;c=1'b1;M=1'b1;
24 #5 a=1'b1;b=1'b1;c=1'b0;M=1'b1;
25 #5 a=1'b1;b=1'b1;c=1'b1;M=1'b1;
26 #5 a=1'b1;b=1'b1;c=1'b0;M=1'b1;
27 #5 a=1'b1;b=1'b1;c=1'b1;M=1'b1;
28 end
29
30 endmodule

design.sv designs.sv 
1 // Code your design here SV/Verilog Design 
2
3 // starting module and defining output and input variables
4
5 // here module defines a design component by defining the block ports and internal
behaviour . Higher level modules can embed lower level modules to create a heirarchial
designs . here we are first defining the a module for half adder and we will use it
latter in the module of full adder
6
7 module full_adder(
8
9 output sum,carry,
10
11 input A,B,C,
12 input M
13 );
14
15
16 // assigning the values of outputs as a function of inputs
17
18
19 assign sum = A^B^C ;
20
21 assign carry= ((A^M)&(B||C))||(B&C);
22
23
24 // ending the module
25
26
27 endmodule
28
29
30 // endmodule is used to end the module block
31
32

 Log  Share

[2023-10-17 08:28:03 UTC] vcs -licqueue '-timescale=1ns/1ns' '+vcs+flush+all' '+warn=all' '-sve 

Warning-[LINX_KRNL] Unsupported Linux kernel

Linux kernel '5.4.0-153-generic' is not supported.
Supported versions are 2.4* or 2.6*.

Chronologic VCS (TM)

Version S-2021.09 -- Tue Oct 17 04:28:04 2023 
 
Copyright (c) 1991 - 2021 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys,
EPWave
Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited. Licensed Products 
communicate with Synopsys servers for the purpose of providing software
updates, detecting software piracy and verifying that customers are using
Licensed Products in conformity with the applicable License Key for such
Licensed Products. Synopsys will use information gathered in connection with
this process to deliver software updates and pursue software pirates and
infringers.

Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on

Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)

Parsing design file 'design.sv'

Parsing design file 'testbench.sv'
Top Level Modules:
t_full_adder
TimeScale is 1 ns / 1 ns
Starting vcs inline pass...

1 module and 0 UDP read.

recompiling module t_full_adder
rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
if [ -x ../simv ]; then chmod a-x ../simv; fi
g++ -o ../simv -m32 -m32 -rdynamic -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-rpath=./simv.dai
../simv up to date
CPU time: .228 seconds to compile + .304 seconds to elab + .284 seconds to link
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09; Runtime version S-2021.09; Oct 17 04:28 2023
V C S S i m u l a t i o n R e p o r t
Time: 75 ns
CPU Time: 0.600 seconds; Data structure size: 0.0Mb
Tue Oct 17 04:28:05 2023
Finding VCD file...
./t_full_adder.vcd
[2023-10-17 08:28:06 UTC] Opening EPWave...
Done

 