Aclu7 Nm-A291 R0.1

A B C D E
1 1
LCFC Confidential
2
AMD 2 Chip M/B Schematics Document 2
AMD Kaveri Processor with DDR3L + Bolton FCH

AMD GPU JET PRO/TOPAZ XT S3
2013-09-25
REV:0.1
3 3
4 4
Security Classification LC Future Center Secret Data Title

Issued Date 2013/05/17 Deciphered Date 2012/12/21 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
ACLU7 0.1
Date: Monday. December 16. 2013 Sheet 1 of 52

A B C D E
A B C D E
LCFC confidential File Name: ACLU7 & 8

AMD JET PRO/TOPAZ XT S3
Memory Bus (DDR3L)
23mmX23mm Dual Rank PCI-Express Dual Channel DDR3L-SO-DIMM X2
Page 18 ~ 24
8x Gen2 Page 11, 12
1.35V DDR3L 1600 MT/s
VRAM 256MX128*16 PEG 0-7
1
DDR3L*4 4GB/2GB AMD FP3 APU UP TO 8G x 2 1
Page 25 ~ 26
HDMI Conn. HDMI Kaveri

Page 29 DP1 LAN Realtek
BGA 854 pin
RTL8111GUL (1G) RJ45 Conn.
eDP x2 Lane 29.15mm * 32.15mm RTL8106EUL (10M/100M)
eDP Conn. Page 38
DP0 Page 37 PCIe Port0
Int. Camera DPx4 Lane
USB2.0 Conn. PCIe x1
Int. Mic Conn. DP2
Page 5 ~ 10
Page 28
x4 UMI Gen. 2 NGFF Card
WLAN&BT Card
5.0GT/s per laneHz PCIe Port2
For VGA Translator Page 34 USB2.0 Port6
2 2
CRT Conn.
USB 2.0 1x USB Left
Page 30 USB 3.0 1x USB 3.0 Port1
USB2.0 1x USB 2.0 Port1
USB 2.0 2x USB 2.0 Port2
SATA HDD SATA Gen3 Bolton M3 Page 32
Page 33 SATA Port0

uFCBGA-656
USB 2.0 1x USB Right
USB 2.0 Port10
SATA ODD SATA Gen1 24.5mm * 24.5mm
SATA Port1
Page 33 Cardreader Realtek
USB 2.0 1x SD/MMC Conn.
RTS5170
SPI ROM USB 2.0 Port4
SPI BUS USB Board
8MB
Page 12
3 3
HD Audio USB 2.0 1x Touch Screen

Page 11 ~ 15 USB 2.0 Port8
Page 28
Codec SPK Conn.

Codec CX20752 Sub-Board ( 14" & 15")
Page 36 Page 36
POWER BOARD (for 14")
EC
ITE IT8586E LQFP
Page 41 I/O Board (USB, Audio, Card Reader)
HP&Mic Combo Conn.
Sub-Board ( Only 15")

USB Board
POWER BOARD (for 15")
Touch Pad Int. KBD Termal Sensor
NCT7718W I/O Board (USB, Audio, Card Reader)
Page 31 Page 31 Page 40
4
ODD Board 4

Issued Date 2013/05/17 Deciphered Date 2012/12/21 Block Diagram
Size Document Number Rev
Custom
ACLU7 0.1
Date: Monday, December 16, 2013 Sheet 2 of 52

A B C D E
A B C D E
Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+5VS STATE
+3VS
+1.5VS S0 (Full ON) HIGH HIGH HIGH HIGH ON ON ON ON
+VCCSA
power +1.5s_VCCP S1 (Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
plane B+ +5VALW +1.5V +CPU_CORE
+VGA_CORE S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1 1
+GFX_CORE
+3VALW S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+1.8VS
+1.05VS S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+0.75VS
State
+3.3VS_VGA
+1.5VS_VGA USB Port Table
+1.05VS_VGA
USB 2.0 USB 3.0 Port 4 External USB Port
S0 O O O O 1 0 Camera
EHCI1
xHCI
2 1 USB Port (Right Side) BOM Structure Table
S3 O O O X 3 2 USB Port (Left Side) BOM Structure BTO Item
4 3 Not stuff
@
S5 S4/AC Only O O X X 4
5 USB Port (Right Side) 100M@ 100M LAN part
6 For 14" part
S5 S4/ Battery only O X X X 7
14@
For 15" part
15@
EHCI2 8
S5 S4/AC & Battery
don't exist
X X X X 9 AOAC@ AOAC support part
10 Mini Card (WLAN) GIGA@ Giga LAN Part
2
11 JET@ For AMD Jet GPU part
2
12 ME@ ME Part (connector, hole)

13 Blue Tooth
DIS@ Discrete GPU SKU part
UMA@ UMA SKU part
TS@ Touch Screen SKU part
TPOAZ@ For AMD Topaz GPU part
A10@ For AMD Kaveri A10 (19W)S IC KAVERI
A4@ For AMD Kaveri A4 (17W)S IC KAVERI
SMBUS Control Table PCIE PORT LIST EMC@ EMC componets
WLAN Termal CP Port Device

SOURCE Main VGA 2nd VGA BATT IT8580E SODIMM PCH
WiMAX Sensor Module 1 LAN
2 WLAN
EC_SMB_CK1 3
EC_SMB_DA1
IT8580E
X X V X X X X X X
+3VALW +3VALW 4
5
3
EC_SMB_CK2
V 6 3
EC_SMB_DA2
IT8580E V X X X X V V X 7
+3VS +3VS +3VS +3VS +3V_PCH
8
APU_SCLK PCH
APU_SDATA +3V_PCH X X X X V V X V V
+3VS +3VS +3V_PCH +3VS
EC SM Bus1 address EC SM Bus2 address APU SM Bus address

Device Address Device Address Device Address
DDR DIMM0 1001 000Xb
Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001 101X b
DDR DIMM1 1001 010Xb
Master VGA 0x9E
Slave VGA 0x9C
4 4

Issued Date 2012/12/05 Deciphered Date 2014/12/05 Notes List
Size Document Number
Rev
Custom
ACLU7 0.4

A B C D E
5 4 3 2 1
RECOMMENDED SETTINGS
CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE X = DESIGN DEPENDANT
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
Power-Up/Down Sequence
"Topaz" has the following requirements with regards to power-supply sequencing to MLPS Bit Strap Name Description RECOMMENDED
SETTINGS
avoid damaging the ASIC: PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,
PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
PS_0[3] ROM_CONFIG[2] X
All the ASIC supplies must reach their respective nominal voltages within 20 ms 100 = 256MB
D of the start of the ramp-up sequence, though a shorter ramp-up duration is PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1 D
preferred. The maximum slew rate on all rails is 50 mV/μs. AUD_PORT_CONN_ The LSB (least significant bit) of the strap option that
It is recommended that the 3.3-V rail ramp up first. PS_0[5] PINSTRAP[0] indicates the number of audio-capable display outputs. 1
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 μs 1 = PCIe GEN3 is supported.
before VDDC, VDDCI, and VMEMIO start to ramp up. PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported. 0= Not support X
The power rails that are shared with other components on the system should be 0 = The CLKREQB power management capability is disabled
gated for the dGPU so that when the dGPU is powered down (for example PS_1[2] STRAP_BIF_CLK_PM_EN 1 = The CLKREQB power management capability is enabled 0
AMD PowerXpress idle state), all the power rails are removed from the dGPU. PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/μs). STRAP_TX_CFG_DRV_ 0 = The transmitter half-swing is enabled
For power down, reversing the ramp-up sequence is recommended. PS_1[4] FULL_SWING 1 = The transmitter full-swing is enabled 1
0 = Tx deemphasis disabled.
PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled. 1= Enable X
PS_2[1] N/A Reserved. 0
PS_2[2] N/A Reserved. 0

0 ~ 20ms
0 = Disable the external BIOS ROM device.
PS_2[3] STRAP_BIOS_ROM_EN 1 = Enable the external BIOS ROM device. 0= Disable X
VDDR3(+3VGS) 0 = VGA controller capacity enabled.

1 = The device will not be recognized as the system’s VGA controller.
0 ~ 20ms PS_2[4] STRAP_BIF_VGA_DIS 1
PS_2[5] N/A Reserved 1
C
VDD_CT(+1.8VGS) Board configuration related strapping, such as for memory ID
C
PS_3[1] BOARD_CONFIG[0] 000 = Hynix 256M*16 001 = Hynix 128M*16 X
PS_3[2] BOARD_CONFIG[1] 100 = Samsung 256M*16 011 = Samsung 128M*16
PS_3[3] BOARD_CONFIG[2] 010 = Micron 256M*16 111 = Micron 128M*16
PCIE_VDDC(+0.95VGS) Determines the maximum number of digital display audio endpoints

that will be presented to the OS and user.(Combine with PS_0[5])
10us min. 111 = No usable endpoints.
AUD_PORT_CONN_ 110 = One usable endpoint.
PS_3[4] PINSTRAP[1] 101 = Two usable endpoints. 111= No usable endpoints.
VDDR1(+1.35VGS) PS_3[5] AUD_PORT_CONN_
100 = Three usable endpoints.
011 = Four usable endpoints.
11
PINSTRAP[2] 010 = Five usable endpoints.
001 = Six usable endpoints.
000 = All endpoints are usable.
VDDC/VDDCI(+VGA_CORE) 100ms min.
PERSTb(GPU_RST#) 100us min. VRAM ID config

VRAM ID PU resistor PD resistor
Memory Type
REFCLK(CLK_PCIE_VGA) PS_3[3:1] RV33 RV36
Hynix
100 4.53K 4.99K
H5TC2G63FFR-11C
B B
128Mx16 Micron
111 4.75K NC
MT41J128M16JT-093G
Samsung
110 3.4K 10K
K4W2G1646Q-BC1A
Hynix
000 NC 4.75K
H5TC4G63AFR-11C
Micron
256Mx16 010 4.53K 2K
MT41J256M16HA-093G
Samsung
001 8.45K 2K
K4W4G1646D-BC1A
A A
Security Classification
Classification LC Future Center Secret Data Title
Issued Date 2013/08/08 Deciphered Date 2013/08/05 VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU7
5 4 3 2 1
5 4 3 2 1
PCIE_CRX_GTX_P[7..0]
PCIE_CRX_GTX_P[7..0] 5,17 PCIE_CTX_C_GRX_P[7..0]
PCIE_CRX_GTX_N[7..0] PCIE_CTX_C_GRX_P[7..0] 5,17
PCIE_CRX_GTX_N[7..0] 5,17 PCIE_CTX_C_GRX_N[7..0]
PCIE_CTX_C_GRX_N[7..0] 5,17
FP3 Kaveri APU supports

PCIE Gen2, AC copling capactiors value 0.1U.
UC1A PCIE GEN3, AC copling capactiors value 0.22U
D PCI EXPRESS D
PCIE_CRX_GTX_P0 Y8 P_GFX_RXP0/RSVD P_GFX_TXP0/DP6_TXP4 AB2 PCIE_CTX_GRX_P0 CC1 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_P0

5,17 PCIE_CRX_GTX_P0 PCIE_CTX_C_GRX_P0 5,17
PCIE_CRX_GTX_N0 Y9 P_GFX_RXN0/RSVD P_GFX_TXN0/DP6_TXN4 AB1 PCIE_CTX_GRX_N0 CC2 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_N0
5,17 PCIE_CRX_GTX_N0 PCIE_CTX_C_GRX_N0 5,17
PCIE_CRX_GTX_P1 Y4 P_GFX_RXP1/RSVD P_GFX_TXP1/DP6_TXP5 AB3 PCIE_CTX_GRX_P1 CC3 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_P1
PCIE_CRX_GTX_N1 W5 P_GFX_RXN1/RSVD P_GFX_TXN1/DP6_TXN5 AA2 PCIE_CTX_GRX_N1 CC4 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_N1
PCIE_CRX_GTX_P2 W7 P_GFX_RXP2/RSVD P_GFX_TXP2/DP6_TXP6 AA1 PCIE_CTX_GRX_P2 CC5 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_P2
PCIE_CRX_GTX_N2 W8 P_GFX_RXN2/RSVD P_GFX_TXN2/DP6_TXN6 Y1 PCIE_CTX_GRX_N2 CC6 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_N2
PCIE_CRX_GTX_P3 U5 P_GFX_RXP3/RSVD P_GFX_TXP3/RSVD Y2 PCIE_CTX_GRX_P3 CC7 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_P3
GPU 5,17 PCIE_CRX_GTX_P3 PCIE_CTX_C_GRX_P3 5,17
5,17 PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N3 V4 P_GFX_RXN3/RSVD P_GFX_TXN3/RSVD W2 PCIE_CTX_GRX_N3 CC8 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N3 5,17 GPU
PCIE_CRX_GTX_P4 U7 P_GFX_RXP4/RSVD P_GFX_TXP4/DP6_TXP0 V2 PCIE_CTX_GRX_P4 CC106 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_P4
PCIE_CRX_GTX_N4 U8 P_GFX_RXN4/RSVD P_GFX_TXN4/DP6_TXN0 V1 PCIE_CTX_GRX_N4 CC107 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_N4
PCIE_CRX_GTX_P5 T4 P_GFX_RXP5/RSVD P_GFX_TXP5/DP6_TXP1 V3 PCIE_CTX_GRX_P5 CC108 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_P5
PCIE_CRX_GTX_N5 R5 P_GFX_TXN5/DP6_TXN1 U2 PCIE_CTX_GRX_N5 CC109 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_N5
GRAPHICS
P_GFX_RXN5/RSVD
PCIE_CRX_GTX_P6 R7 P_GFX_RXP6/RSVD P_GFX_TXP6/DP6_TXP2 U1 PCIE_CTX_GRX_P6 CC110 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_P6
PCIE_CRX_GTX_N6 R8 P_GFX_RXN6/RSVD P_GFX_TXN6/DP6_TXN2 T1 PCIE_CTX_GRX_N6 CC111 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_N6
PCIE_CRX_GTX_P7 P8 P_GFX_RXP7/RSVD P_GFX_TXP7/DP6_TXP3 T2 PCIE_CTX_GRX_P7 CC112 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_P7
PCIE_CRX_GTX_N7 P7 P_GFX_RXN7/RSVD P_GFX_TXN7/DP6_TXN3 R2 PCIE_CTX_GRX_N7 CC113 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_N7
P4 P_GFX_RXP8/RSVD P_GFX_TXP8/DP5_TXP0 P2
P5 P_GFX_RXN8/RSVD P_GFX_TXN8/DP5_TXN0 P1
M8 P_GFX_RXP9/RSVD P_GFX_TXP9/DP5_TXP1 P3
M7 P_GFX_RXN9/RSVD P_GFX_TXN9/DP5_TXN1 N2
M5 P_GFX_RXP10/RSVD P_GFX_TXP10/DP5_TXP2 N1
M4 P_GFX_RXN10/RSVD P_GFX_TXN10/DP5_TXN2 M1
L6 P_GFX_RXP11/RSVD P_GFX_TXP11/DP5_TXP3 M2
L5 P_GFX_RXN11/RSVD P_GFX_TXN11/DP5_TXN3 L2
L8 P_GFX_RXP12/RSVD P_GFX_TXP12/DP4_TXP0 K2
L9 P_GFX_RXN12/RSVD P_GFX_TXN12/DP4_TXN0 K1
J5 P_GFX_RXP13/RSVD P_GFX_TXP13/DP4_TXP1 K3
K4 P_GFX_RXN13/RSVD P_GFX_TXN13/DP4_TXN1 J2
J7 P_GFX_RXP14/RSVD P_GFX_TXP14/DP4_TXP2 J1
J8 P_GFX_RXN14/RSVD P_GFX_TXN14/DP4_TXN2 H1
H4 P_GFX_RXP15/RSVD P_GFX_TXP15/DP4_TXP3 H2
H5 P_GFX_RXN15/RSVD P_GFX_TXN15/DP4_TXN3 G2
C C
PCIE_CRX_DTX_P0 AH4 P_GPP_RXP0 P_GPP_TXP0 AM2 PCIE_CTX_DRX_P0 CC9 1 2 0.1U_0402_10V7-K PCIE_CTX_C_DRX_P0
35 PCIE_CRX_DTX_P0 PCIE_CTX_C_DRX_P0 35
LAN 35 PCIE_CRX_DTX_N0 PCIE_CRX_DTX_N0 AH3 P_GPP_RXN0 P_GPP_TXN0 AM1 PCIE_CTX_DRX_N0 CC10 1 2 0.1U_0402_10V7-K PCIE_CTX_C_DRX_N0
PCIE_CTX_C_DRX_N0 35 LAN
AG7 P_GPP_RXP1 P_GPP_TXP1 AL2
AF6 P_GPP_RXN1 P_GPP_TXN1 AL1
33 PCIE_CRX_DTX_P2 PCIE_CRX_DTX_P2 AE8 P_GPP_RXP2 P_GPP_TXP2 AK2 PCIE_CTX_DRX_P2 CC13 1 2 0.1U_0402_10V7-K PCIE_CTX_C_DRX_P2
PCIE_CTX_C_DRX_P2 33
GPP
WLAN 33 PCIE_CRX_DTX_N2 AE7 P_GPP_RXN2 P_GPP_TXN2 AK1 PCIE_CTX_DRX_N2 CC14 1 2 0.1U_0402_10V7-K PCIE_CTX_C_DRX_N2 WLAN
PCIE_CRX_DTX_N2 PCIE_CTX_C_DRX_N2 33
AE5 P_GPP_RXP3 P_GPP_TXP3 AK3
AF4 P_GPP_RXN3 P_GPP_TXN3 AJ2
AC9 P_GPP_RXP4/RSVD P_GPP_TXP4/DP3_TXP0 AJ1
AC8 P_GPP_RXN4/RSVD P_GPP_TXN4/DP3_TXN0 AH1
AC6 P_GPP_RXP5/RSVD P_GPP_TXP5/DP3_TXP1 AH2
AC5 P_GPP_RXN5/RSVD P_GPP_TXN5/DP3_TXN1 AG2
AB9 P_GPP_RXP6/RSVD P_GPP_TXP6/DP3_TXP2 AF2
AB8 P_GPP_RXN6/RSVD P_GPP_TXN6/DP3_TXN2 AF1
AB4 P_GPP_RXP7/RSVD P_GPP_TXP7/DP3_TXP3 AF3
AB5 P_GPP_RXN7/RSVD P_GPP_TXN7/DP3_TXN3 AE2
UMI_CRX_FTX_P0 AJ7 P_UMI_RXP0 P_UMI_TXP0 AM9 UMI_CTX_FRX_P0 CC15 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_P0_C

12 UMI_CRX_FTX_P0 UMI_CTX_FRX_P0_C 12
UMI_CRX_FTX_N0 AJ8 P_UMI_RXN0 P_UMI_TXN0 AM10 UMI_CTX_FRX_N0 CC16 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_N0_C
12 UMI_CRX_FTX_N0 UMI_CTX_FRX_N0_C 12
UMI_CRX_FTX_P1 AK6 P_UMI_RXP1 P_UMI_TXP1 AN8 UMI_CTX_FRX_P1 CC17 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_P1_C
UMI_CRX_FTX_N1 AK7 AN9 UMI_CTX_FRX_N1 CC18 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_N1_C
12 UMI_CRX_FTX_N1 P_UMI_RXN1 P_UMI_TXN1
UMI_CTX_FRX_N1_C 12FCH
UMI_CRX_FTX_P2 AK5 AM7 UMI_CTX_FRX_P2 CC19 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_P2_C
UMI
FCH 12 UMI_CRX_FTX_P2 P_UMI_RXP2 P_UMI_TXP2
UMI_CTX_FRX_P2_C 12
UMI_CRX_FTX_N2 AJ5 P_UMI_RXN2 P_UMI_TXN2 AM8 UMI_CTX_FRX_N2 CC20 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_N2_C
UMI_CRX_FTX_P3 AL4 P_UMI_RXP3 P_UMI_TXP3 AN6 UMI_CTX_FRX_P3 CC21 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_P3_C
UMI_CRX_FTX_N3 AK4 P_UMI_RXN3 P_UMI_TXN3 AM6 UMI_CTX_FRX_N3 CC22 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_N3_C
+0.95VS_VDDP RC1 1 2 196_0402_0.5% P_ZVDDP AN18 P_ZVDDP P_ZVSS AM18 P_ZVSS RC2 1 2 196_0402_0.5%
FP3 REV 0.52
KAVERI-2M186092H4467_BGA854
A10@
B B
A A

Issued Date 2012/12/05 Deciphered Date 2014/12/05 APU PEG/PCIe/UMI
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.4
5 4 3 2 1
1 2 3 4 5
UC1B UC1C
DDRB_DQ[0..63] 11
10 DDRA_MA[0..15] 11 DDRB_MA[0..15] MB_DATA0 C18 DDRB_DQ0
MEMORY CHANNEL A DDRA_DQ[0..63] 10
A DDRA_MA0 AB31 MA_ADD0 MA_DATA0 H13 DDRA_DQ0 DDRB_MA0 AC36 MB_ADD0
MEMORY CHANNEL B MB_DATA1 B19 DDRB_DQ1 A
DDRA_MA1 U33 MA_ADD1 MA_DATA1 F13 DDRA_DQ1 DDRB_MA1 U36 MB_ADD1 MB_DATA2 C22 DDRB_DQ2
DDRA_MA2 U32 MA_ADD2 MA_DATA2 H16 DDRA_DQ2 DDRB_MA2 U37 MB_ADD2 MB_DATA3 A22 DDRB_DQ3
DDRA_MA3 R30 MA_ADD3 MA_DATA3 F16 DDRA_DQ3 DDRB_MA3 T35 MB_ADD3 MB_DATA4 A18 DDRB_DQ4
DDRA_MA4 T34 MA_ADD4 MA_DATA4 G11 DDRA_DQ4 DDRB_MA4 T37 MB_ADD4 MB_DATA5 B18 DDRB_DQ5
DDRA_MA5 R31 MA_ADD5 MA_DATA5 E11 DDRA_DQ5 DDRB_MA5 T36 MB_ADD5 MB_DATA6 A21 DDRB_DQ6
DDRA_MA6 R33 MA_ADD6 MA_DATA6 E14 DDRA_DQ6 DDRB_MA6 R36 MB_ADD6 MB_DATA7 B21 DDRB_DQ7
DDRA_MA7 P33 MA_ADD7 MA_DATA7 J14 DDRA_DQ7 DDRB_MA7 P37 MB_ADD7
DDRA_MA8 P32 MA_ADD8 DDRB_MA8 P36 MB_ADD8 MB_DATA8 B24 DDRB_DQ8
DDRA_MA9 P30 MA_ADD9 MA_DATA8 J17 DDRA_DQ8 DDRB_MA9 N36 MB_ADD9 MB_DATA9 A24 DDRB_DQ9
DDRA_MA10 AD34 MA_ADD10 MA_DATA9 F17 DDRA_DQ9 DDRB_MA10 AD36 MB_ADD10 MB_DATA10
B27 DDRB_DQ10
DDRA_MA11 P34 MA_ADD11 MA_DATA10 H21 DDRA_DQ10 DDRB_MA11 P35 MB_ADD11 MB_DATA11
A28 DDRB_DQ11
DDRA_MA12 M30 MA_ADD12 MA_DATA11 E21 DDRA_DQ11 DDRB_MA12 N37 MB_ADD12 MB_DATA12
B22 DDRB_DQ12
DDRA_MA13 AF33 MA_ADD13 MA_DATA12 E16 DDRA_DQ12 DDRB_MA13 AH37 MB_ADD13 MB_DATA13 B23 DDRB_DQ13
DDRA_MA14 M31 MA_ADD14 MA_DATA13 G17 DDRA_DQ13 DDRB_MA14 M36 MB_ADD14 MB_DATA14 B26 DDRB_DQ14
DDRA_MA15 L32 MA_ADD15 MA_DATA14 F19 DDRA_DQ14 DDRB_MA15 L36 MB_ADD15 MB_DATA15 C26 DDRB_DQ15
MA_DATA15 D20 DDRA_DQ15
DDRA_BA0# AC33 MA_BANK0 DDRB_BA0# AD35 MB_BANK0 MB_DATA16 A29 DDRB_DQ16
10 DDRA_BA0# 11 DDRB_BA0#
DDRA_BA1# AB30 MA_BANK1 MA_DATA16 D22 DDRA_DQ16 DDRB_BA1# AD37 MB_DATA17 B29 DDRB_DQ17
10 DDRA_BA1# 11 DDRB_BA1# MB_BANK1
DDRA_BA2# M34 MA_BANK2 MA_DATA17 E22 DDRA_DQ17 DDRB_BA2# M37 MB_BANK2 MB_DATA18 B32 DDRB_DQ18
10 DDRA_BA2# 11 DDRB_BA2#
MA_DATA18 D26 DDRA_DQ18 MB_DATA19 C32 DDRB_DQ19
10 DDRA_MA_DM[0..7] 11 DDRB_MB_DM[0..7]
DDRA_MA_DM0 E13 MA_DM0 MA_DATA19 E25 DDRA_DQ19 DDRB_MB_DM0 A20 MB_DM0 MB_DATA20 B28 DDRB_DQ20
DDRA_MA_DM1 D18 MA_DM1 MA_DATA20 G21 DDRA_DQ20 DDRB_MB_DM1 C24 MB_DM1 MB_DATA21 C28 DDRB_DQ21
DDRA_MA_DM2 H22 MA_DM2 MA_DATA21 F22 DDRA_DQ21 DDRB_MB_DM2 A30 MB_DM2 MB_DATA22 B31 DDRB_DQ22
DDRA_MA_DM3 H27 MA_DM3 MA_DATA22 G24 DDRA_DQ22 DDRB_MB_DM3 B35 MB_DM3 MB_DATA23 A32 DDRB_DQ23
DDRA_MA_DM4 AG30 MA_DM4 MA_DATA23 H24 DDRA_DQ23 DDRB_MB_DM4 AL35 MB_DM4
DDRA_MA_DM5 AK26 MA_DM5 DDRB_MB_DM5 AN32 MB_DM5 MB_DATA24
C34 DDRB_DQ24
DDRA_MA_DM6 AK20 MA_DM6 MA_DATA24 E27 DDRA_DQ24 DDRB_MB_DM6 AN26 MB_DM6 MB_DATA25
A34 DDRB_DQ25
DDRA_MA_DM7 AF14 MA_DM7 MA_DATA25 G27 DDRA_DQ25 DDRB_MB_DM7 AN21 MB_DM7 MB_DATA26 C36 DDRB_DQ26
F34 MA_DM8 MA_DATA26 E30 DDRA_DQ26 E37 MB_DM8 MB_DATA27 C37 DDRB_DQ27
MA_DATA27 G30 DDRA_DQ27 MB_DATA28
A33 DDRB_DQ28
DDRA_DQS0 F14 MA_DQS_H0 MA_DATA28 F25 DDRA_DQ28 DDRB_DQS0 C20 MB_DQS_H0 MB_DATA29 B33 DDRB_DQ29
10 DDRA_DQS0 11 DDRB_DQS0
DDRA_DQS#0 G14 MA_DQS_L0 MA_DATA29 H25 DDRA_DQ29 DDRB_DQS#0 B20 MB_DQS_L0 MB_DATA30
D35 DDRB_DQ30
10 DDRA_DQS#0 11 DDRB_DQS#0
DDRA_DQS1 H19 MA_DQS_H1 MA_DATA30 D30 DDRA_DQ30 DDRB_DQS1 B25 MB_DQS_H1 MB_DATA31 B37 DDRB_DQ31
DDRA_DQS#1 J19 MA_DQS_L1 MA_DATA31 H28 DDRA_DQ31 DDRB_DQS#1 A25
B 10 DDRA_DQS#1 11 DDRB_DQS#1 MB_DQS_L1 B
DDRA_DQS2 D24 MA_DQS_H2 DDRB_DQS2 C30 MB_DQS_H2 MB_DATA32
AL36 DDRB_DQ32
DDRA_DQS#2 E24 MA_DQS_L2 MA_DATA32 AJ31 DDRA_DQ32 DDRB_DQS#2 B30 MB_DQS_L2 MB_DATA33
AM37 DDRB_DQ33
DDRA_DQS3 F28 MA_DQS_H3 MA_DATA33 AK32 DDRA_DQ33 DDRB_DQS3 B36 MB_DQS_H3 MB_DATA34
AN34 DDRB_DQ34
DDRA_DQS#3 E28 MA_DQS_L3 MA_DATA34 AK28 DDRA_DQ34 DDRB_DQS#3 A36 MB_DQS_L3 MB_DATA35 AM34 DDRB_DQ35
DDRA_DQS4 AJ30 MA_DQS_H4 MA_DATA35 AF27 DDRA_DQ35 DDRB_DQS4 AN36 MB_DQS_H4 MB_DATA36 AK37 DDRB_DQ36
DDRA_DQS#4 AK30 MA_DQS_L4 MA_DATA36 AJ33 DDRA_DQ36 DDRB_DQS#4 AM36 MB_DQS_L4 MB_DATA37
AK36 DDRB_DQ37
DDRA_DQS5 AH24 MA_DQS_H5 MA_DATA37 AK33 DDRA_DQ37 DDRB_DQS5 AN31 MB_DQS_H5 MB_DATA38
AN35 DDRB_DQ38
DDRA_DQS#5 AG24 MA_DQS_L5 MA_DATA38 AH28 DDRA_DQ38 DDRB_DQS#5 AM31 MB_DATA39
AL34 DDRB_DQ39
10 DDRA_DQS#5 11 DDRB_DQS#5 MB_DQS_L5
DDRA_DQS6 AG19 MA_DQS_H6 MA_DATA39 AJ28 DDRA_DQ39 DDRB_DQS6 AM25
10 DDRA_DQS6 11 DDRB_DQS6 MB_DQS_H6
DDRA_DQS#6 AF19 MA_DQS_L6 DDRB_DQS#6 AL26 MB_DATA40 AL32 DDRB_DQ40
10 DDRA_DQS#6 11 DDRB_DQS#6 MB_DQS_L6
DDRA_DQS7 AH14 MA_DQS_H7 MA_DATA40 AF25 DDRA_DQ40 DDRB_DQS7 AM20 MB_DQS_H7 MB_DATA41 AM32 DDRB_DQ41
DDRA_DQS#7 AJ14 MA_DQS_L7 MA_DATA41 AH25 DDRA_DQ41 DDRB_DQS#7 AL20 MB_DQS_L7 MB_DATA42 AN29 DDRB_DQ42
G31 MA_DQS_H8 MA_DATA42 AG22 DDRA_DQ42 F37 MB_DQS_H8
MB_DATA43 AL28 DDRB_DQ43
F31 MA_DQS_L8 MA_DATA43 AJ22 DDRA_DQ43 F36 MB_DQS_L8
MB_DATA44 AM33 DDRB_DQ44
MA_DATA44 AH27 DDRA_DQ44 MB_DATA45 AN33 DDRB_DQ45
MB_CLK shift 0 to 1.from 1 to 2 Y30 MA_CLK_H0 MA_DATA45 AJ27 DDRA_DQ45 MB_CLK shift 0 to 1.from 1 to 2 AA37 MB_CLK_H0 MB_DATA46 AM30 DDRB_DQ46
Y29 MA_CLK_L0 MA_DATA46 AE24 DDRA_DQ46 AA36 MB_CLK_L0 MB_DATA47 AM29 DDRB_DQ47
DDRA_CLK0 Y32 MA_CLK_H1 MA_DATA47 AF22 DDRA_DQ47 DDRB_CLK0 Y37 MB_CLK_H1
10 DDRA_CLK0 11 DDRB_CLK0
DDRA_CLK0# Y33 MA_CLK_L1 DDRB_CLK0# Y36 MB_CLK_L1 MB_DATA48 AM27 DDRB_DQ48
10 DDRA_CLK0# 11 DDRB_CLK0#
DDRA_CLK1 W33 MA_CLK_H2 MA_DATA48 AH21 DDRA_DQ48 DDRB_CLK1 Y34 MB_CLK_H2 MB_DATA49 AM26 DDRB_DQ49
10 DDRA_CLK1 11 DDRB_CLK1
DDRA_CLK1# W34 MA_CLK_L2 MA_DATA49 AJ21 DDRA_DQ49 DDRB_CLK1# Y35 MB_CLK_L2 MB_DATA50 AN24 DDRB_DQ50
10 DDRA_CLK1# 11 DDRB_CLK1#
W30 MA_CLK_H3 MA_DATA50 AF17 DDRA_DQ50 V35 MB_CLK_H3 MB_DATA51 AM24 DDRB_DQ51
W31 MA_CLK_L3 MA_DATA51 AJ17 DDRA_DQ51 W36 MB_CLK_L3 MB_DATA52 AN28 DDRB_DQ52
MA_DATA52 AK22 DDRA_DQ52 MB_DATA53 AM28 DDRB_DQ53
DDRA_CKE0 L33 MA_CKE0 MA_DATA53 AF21 DDRA_DQ53 DDRB_CKE0 K36 MB_CKE0 MB_DATA54 AN25 DDRB_DQ54
10 DDRA_CKE0 11 DDRB_CKE0
DDRA_CKE1 L30 MA_CKE1 MA_DATA54 AJ19 DDRA_DQ54 DDRB_CKE1 K37 MB_CKE1 MB_DATA55 AL24 DDRB_DQ55
10 DDRA_CKE1 11 DDRB_CKE1
K34 MA_CKE2 MA_DATA55 AE17 DDRA_DQ55 K35 MB_CKE2
J30 MA_CKE3 J37 MB_CKE3 MB_DATA56 AN22 DDRB_DQ56
MA_DATA56 AF16 DDRA_DQ56 MB_DATA57 AL22 DDRB_DQ57
DDRA_ODT0 AH34 MA0_ODT0 MA_DATA57 AJ16 DDRA_DQ57 DDRB_ODT0 AH36 MB0_ODT0 MB_DATA58 AK18 DDRB_DQ58
10 DDRA_ODT0 11 DDRB_ODT0
DDRA_ODT1 AH33 MA0_ODT1 MA_DATA58 AF13 DDRA_DQ58 DDRB_ODT1 AJ37 MB0_ODT1 MB_DATA59 AL18 DDRB_DQ59
10 DDRA_ODT1 11 DDRB_ODT1
AE30 MA1_ODT0 MA_DATA59 AE13 DDRA_DQ59 AF35 MB1_ODT0 MB_DATA60 AM23 DDRB_DQ60
AJ34 MA1_ODT1 MA_DATA60 AH17 DDRA_DQ60 AK35 MB1_ODT1 MB_DATA61 AM22 DDRB_DQ61
MA_DATA61 AE16 DDRA_DQ61 MB_DATA62 AN20 DDRB_DQ62
C DDRA_CS0# AE31 MA0_CS_L0 MA_DATA62 AJ13 DDRA_DQ62 DDRB_CS0# AF36 MB0_CS_L0 MB_DATA63 AM19 DDRB_DQ63 C
10 DDRA_CS0# 11 DDRB_CS0#
DDRA_CS1# AG31 MA0_CS_L1 MA_DATA63 AG13 DDRA_DQ63 DDRB_CS1# AJ36 MB0_CS_L1
10 DDRA_CS1# 11 DDRB_CS1#
AC30 MA1_CS_L0 AE36 MB1_CS_L0 MB_CHECK0 E36
+1.35V_APU_VDDIO AF32 MA1_CS_L1 MA_CHECK0 E33 AH35 MB1_CS_L1 MB_CHECK1 F35
MA_CHECK1 F33 MB_CHECK2 H36
DDRA_RAS# AC32 MA_RAS_L MA_CHECK2 H31 DDRB_RAS# AE37 MB_RAS_L MB_CHECK3 H37
10 DDRA_RAS# 11 DDRB_RAS#
1
DDRA_CAS# AF34 MA_CAS_L MA_CHECK3 J31 DDRB_CAS# AG36 MB_CAS_L MB_CHECK4 D36
10 DDRA_CAS# 11 DDRB_CAS#
RC5 DDRA_WE# AE33 MA_WE_L MA_CHECK4 D32 DDRB_WE# AF37 MB_WE_L MB_CHECK5 D37
10 DDRA_WE# 11 DDRB_WE#
1K_0402_1% MA_CHECK5 D34 MB_CHECK6 G36
DDRA_RESET# J33 MA_RESET_L MA_CHECK6 H33 DDRB_RESET# J36 MB_RESET_L MB_CHECK7 H35
10 DDRA_RESET# 11 DDRB_RESET#
DDRA_EVENT# AB33 MA_EVENT_L MA_CHECK7 H34 DDRB_EVENT# AB36 MB_EVENT_L
10 DDRA_EVENT# 11 DDRB_EVENT#
2
M_VREF V36 M_VREF RSVD_11 A26

RC21 1 @ 2 0_0402_5% +VREF_DQA_C H11 E19 +VREF_DQB RC22 1 @ 2 0_0402_5% +VREF_DQB_C B17 MB_VREFDQ RSVD_12 B34
1000P_0402_50V7K
+VREF_DQA MA_VREFDQ RSVD_5
1 1 +1.35V_APU_VDDIO RC4 1 2 MA_ZVDDIO U30 MA_ZVDDIO RSVD_6 D28 +1.35V_APU_VDDIO RC3 1 2 MB_ZVDDIO V37 MB_ZVDDIO RSVD_13 AL30
1
39.2_0402_1% RSVD_7 AK24 RSVD_14 AM21

CC117
RC6 39.2_0402_1%
0.1U_0402_10V7-K M33 RSVD_3 RSVD_8 AG16 M35 RSVD_9
AB34 RSVD_4 AB35
1K_0402_1% 2 2
RSVD_10
CC116
FP3 REV 0.52

FP3 REV 0.52
2
add cap on 20131002
D D

Issued Date 2012/07/01 Deciphered Date 2014/07/01 APU DDRA/B
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
1 2 3 4 5
1 2 3 4 5
UC1D
EC_SMB_3 +3VS
ANALOG/DISPLAY/MISC RC71
1 2
APU_EDP_TX0+ AL6 DP0_TXP0 DP0_AUXP AG8 APU_EDP_AUX 33K_0402_5%

27 APU_EDP_TX0+ APU_EDP_AUX 27
APU_EDP_TX0- AM5 AG10 APU_EDP_AUX#
27 APU_EDP_TX0- DP0_TXN0 DP0_AUXN
APU_EDP_AUX# 27 EDP Please doucle confirm RC71 and RC72 value
EDP
1
OK APU_EDP_TX1+ AN5 DP0_TXP1 DP1_AUXP B2 APU_VGA_AUX
27 APU_EDP_TX1+ APU_VGA_AUX 13 EC_SMB_CK3
27 APU_EDP_TX1-
APU_EDP_TX1- AM4 DP0_TXN1 DP1_AUXN B1 APU_VGA_AUX#
APU_VGA_AUX# 13 FCH RC72
DISPLAY PORT 0
30K_0402_1%
AN4 DP0_TXP2 DP2_AUXP B6 APU_HDMI_CLK 1
APU_HDMI_CLK 28
AN3 DP0_TXN2 DP2_AUXN B7 APU_HDMI_DATA
APU_HDMI_DATA 28 HDMI CH87
2
@ 22P_0402_50V8-J
AM3 H7
DISPLAY PORT
DP0_TXP3 DP3_AUXP 2
AN2 G7
G
DP0_TXN3 DP3_AUXN
A 2 A
MISC.
CC31 1 2 0.1U_0402_10V7-K APU_VGA_TXP0_C F2 DP1_TXP0 DP4_AUXP Y6 EC_SMB_CK3 1 3 SIC
13 APU_VGA_TXP0 14,18,37,38 EC_SMB_CK3
CC32 1 2 0.1U_0402_10V7-K APU_VGA_TXN0_C F1 Y5
S
DP1_TXN0 DP4_AUXN
D
13 APU_VGA_TXN0 QC3 EC_SMB_DA3
CC33 1 2 0.1U_0402_10V7-K APU_VGA_TXP1_C F3 AD2
G
DP1_TXP1 DP5_AUXP BSS138_SOT23-3
13 APU_VGA_TXP1
CC34 1 2 0.1U_0402_10V7-K APU_VGA_TXN1_C E2 DP1_TXN1 DP5_AUXN AC2 2 1
DISPLAY PORT 1
13 APU_VGA_TXN1
EC_SMB_DA3 1 3
OK FCH CC35 1 2 0.1U_0402_10V7-K APU_VGA_TXP2_C E1 AH7 APU_EDP_HPD 14,18,37,38 EC_SMB_DA3
SID
@
CH88
22P_0402_50V8-J
S
DP1_TXP2 DP0_HPD
D
13 APU_VGA_TXP2 APU_EDP_HPD 27 QC12
CC36 1 2 0.1U_0402_10V7-K APU_VGA_TXN2_C D1 DP1_TXN2 DP1_HPD B3 APU_VGA_HPD
13 APU_VGA_TXN2 D7 APU_VGA_HPD 13 2
DP2_HPD APU_HDMI_HPD BSS138_SOT23-3
APU_HDMI_HPD 28
CC37 1 2 0.1U_0402_10V7-K APU_VGA_TXP3_C D2 DP1_TXP3 DP3_HPD F8
13 APU_VGA_TXP3
CC38 1 2 0.1U_0402_10V7-K APU_VGA_TXN3_C C1 DP1_TXN3 DP4_HPD AB6
13 APU_VGA_TXN3
DP5_HPD AD1
APU_HDMI_TX2+ A2 DP2_TXP0
28 APU_HDMI_TX2+ APU_HDMI_TX2- A3 D12 APU_ENBKL_R
DP2_TXN0 DP_BLON
28 APU_HDMI_TX2- B11 APU_ENVDD
DP_DIGON
B4 C12 APU_ENVDD 27
APU_HDMI_TX1+ DP2_TXP1 DP_VARY_BL APU_EDP_PWM_R
28 APU_HDMI_TX1+ APU_HDMI_TX1- A4
SPEC HDMI on Port 228 DP2_TXN1
DISPLAY PORT 2
APU_HDMI_TX1- D3 DP_AUX_ZVSS RC12 1 2 150_0402_1%
OK HDMI APU_HDMI_TX0+ C4 DP2_TXP2
DP_AUX_ZVSS
28 APU_HDMI_TX0+ APU_HDMI_TX0- B5 L27 APU_TEST6

DP2_TXN2 TEST6
28 APU_HDMI_TX0-
TEST9 P27 APU_TEST9 RC59 1 @ 2 1K_0402_1% APU_ENBKL_R
APU_HDMI_CLK+ A5 DP2_TXP3 TEST10 P28 APU_TEST10 +3VS
28 APU_HDMI_CLK+ APU_HDMI_CLK- A6 C10 APU_TEST14 RC60 1 @ 2 1K_0402_1%
DP2_TXN3 TEST14
28 APU_HDMI_CLK- B9 APU_TEST15
TEST15
APU_CLKP AM13 CLKIN_H TEST16 A10 APU_TEST16 RC61 1 @ 2 1K_0402_1%
12 OK APU_CLKP
CLK
APU_CLKN AN13 B10 APU_TEST17 RC62 1 @ 2 1K_0402_1%
TEST
2
CLKIN_L TEST17
12 APU_CLKN
TEST18 A12 APU_TEST18 RC63 1 2 1K_0402_1%
RC30
DISP_CLKP AM11 DISP_CLKIN_H TEST19 B12 APU_TEST19 RC64 1 2 1K_0402_1%
12 DISP_CLKP AN11 C8 1 2 2.2K_0402_5%
Follow Edge to delete RC7,RC8,RC9 OK DISP_CLKN APU_TEST20 RC65 1K_0402_1%
2
DISP_CLKIN_L TEST20
12 DISP_CLKN
AJ10 D8 APU_TEST24 RC66 1 2 1K_0402_1%
and reserve resisotr on PWR page 52 on 20131009 RSVD_16 TEST24
AM12 APU_TEST25_H RC35 1 2 510_0402_5%
RC31 RC29 1 2 0_0402_5% APU_ENBKL
APU_ENBKL 38
1
TEST25_H
100K_0402_5%
APU_SVC B16 SVC TEST25_L AN12 APU_TEST25_L RC36 1 2 510_0402_5% +0.95VS_VDDP
52 APU_SVC APU_BKOFF#
OK To Power schematics APU_SVD C16 SVD TEST28_H A8 APU_TEST28_H APU_BKOFF# 27
52 APU_SVD A16 B8
APU_SVT APU_TEST28_L
SER.
1
SVT TEST28_L
52 APU_SVT
AA27 APU_TEST30_H
1
TEST30_H D
RC10 1 @ 2 0_0402_5% SIC AL14 SIC TEST30_L AA28 APU_TEST30_L
2
14 EC_SMBLV_CK QC4
RC11 1 @ 2 0_0402_5% SID AK14 SID TEST31 V28 APU_TEST31
B 14 EC_SMBLV_DA G 2N7002KW_SOT323-3 B
TEST32_H Y27 APU_TEST32_H
AM14 Y28 S SB00000YY00
APU_RESET# APU_TEST32_L
3
1
RESET_L TEST32_L C
12OK APU_RESET# RC44
Check connect to FCH or EC 12,52 APU_PWROK
APU_PWROK AL12 PWROK
APU_ENBKL_R 1 2 2
CTRL
RC13 2 1 1K_0402_1%
+1.35V_APU_VDDIO B
APU_PROCHOT# AL10 PROCHOT_L RSVD_15 AK10 E
2.2K_0402_5%
THERMTRIP# AK11 AM15 ALLOW_STOP
3
2
THERMTRIP_L DMAACTIVE_L
AN15 ALLOW_STOP 12 QC7
ALERT# ALERT_L
RC43 MMST3904-7-F_SOT323-3
T27
MISC
TEST4
A14 T28 100K_0402_5%
APU_TDI TDI TEST5 RC42 1 2 300_0402_5%
+1.35V_APU_VDDIO
APU_TDO C14 TDO
APU_TCK B15 A9 APU_TEST35 RC20 1 2 300_0402_5%
1
TCK DP_STEREOSYNC
APU_TMS B14 TMS @
JTAG
APU_TRST# D14 TRST_L CORETYPE D16
APU_DBRDY A13 DBRDY
RSVD
APU_DBREQ# B13 DBREQ_L
RSVD_1 A17
+1.35V_APU_VDDIO
VSS_SENSE E10 VSS_SENSE_A RSVD_2 K28
52 VSS_SENSE
To Power schematics 52 VDD_SENSE
VDD_SENSE D9 VDD_SENSE
VDDNB_SENSE D10 VDDNB_SENSE
52 VDDNB_SENSE SENSE
F10 F7
1
VDDIO_SENSE RSVD_17
AE10
AF11
VDDP_SENSE
AUDIO
RSVD_18 E4
E5
APU_PROCHOT# RC23
Follow Edge to delete RC27,RC28,RC46 AF10
VDDR_SENSE RSVD_19
E7 1K_0402_1%
VSS_SENSE_B RSVD_20
and reserve resisotr on PWR page 52 on 20131009 D5
2
RSVD_21
Test_Point
2
FP3 REV 0.52
E
3 1 APU_PROCHOT#
38 H_PROCHOT#
C
QC1 RC45 1 2
VSS_SENSE TPC1 1 Test_Point_40MIL +1.35V_APU_VDDIO_RUN FCH_PROCHOT# 12
MMST3904-7-F_SOT323-3
VDD_SENSE TPC2 1 Test_Point_40MIL 0_0402_5%
VDDNB_SENSE TPC3 1 Test_Point_40MIL
+1.35V_APU_VDDIO APU_TEST6 TPC4 1 Test_Point_40MIL +1.35V_APU_VDDIO RPC1
APU_TEST10 TPC5 1 Test_Point_40MIL H_PROCHOT# pull up +3VS on VR_HOT# on PWR page 52
APU_TEST15 TPC6 1 Test_Point_40MIL 1 8
APU_TEST28_H TPC7 1 Test_Point_40MIL 2 7 +1.35V_APU_VDDIO
RC67 2 @ 1 39.2_0402_1% APU_TEST31 APU_TEST28_L TPC8 1 Test_Point_40MIL 3 6
APU_TEST30_H TPC9 1 Test_Point_40MIL 4 5
C APU_TEST30_L TPC10 1 Test_Point_40MIL +3VALW C
RC68 2 @ 1 39.2_0402_1% APU_TEST32_H TPC11 1 Test_Point_40MIL 10K_0804_8P4R_5%

APU_TEST32_L TPC12 1 Test_Point_40MIL
1
RC26
1K_0402_1%
VSS_SENSE 2 1 RC49 THERMTRIP#
2
B
2
100_0402_5%
1 3 THERMTRIP#
E
14,18 H_THERMTRIP#
C
QC2
+VDD_CORE MMST3904-7-F_SOT323-3
RC47 1 2 100_0402_5% VDD_SENSE

+3VS
+VDDNB_CORE HDT Debug conn To EDP_PWM Conn
2
RC48 1 2 100_0402_5% VDDNB_SENSE
OK RC34
4.7K_0402_5%
2
+1.35V_APU_VDDIO_RUN +1.35V_APU_VDDIO
mount RC57 and RC58 if need JHDT1 RC33
1
JHDT1 47K_0402_5%
RC14 1 2 300_0402_5% APU_RESET# 1 2 APU_TCK APU_EDP_PWM
1 2 APU_EDP_PWM 27
RC15 1 2 300_0402_5% APU_PWROK
1
3 4 APU_TMS
1
3 4 D
5 6 APU_TDI 2 QC9
+1.35V_APU_VDDIO 5 6 G 2N7002KW_SOT323-3
7 8 APU_TDO S SB00000YY00
3
1
RC17 1 2 1K_0402_1% SIC RC50 7 8 RC32 C
RC18 1 2 1K_0402_1% SID APU_TRST# 1 2 0_0402_5% HDT_TRST# 9 10 APU_PWROK APU_EDP_PWM_R 1 2 2
RC19 1 2 1K_0402_1% ALERT# 9 10 B
D RC37 1 2 1K_0402_1% APU_TDI RC51 1 2 10K_0402_5% 11 12 APU_RESET# 2.2K_0402_5% E D
3
2
RC38 1 2 1K_0402_1% APU_TCK 11 12 QC5
RC39 1 2 1K_0402_1% APU_TMS RC52 1 2 10K_0402_5% 13 14 APU_DBRDY RC74 MMST3904-7-F_SOT323-3
RC40 1 2 1K_0402_1% APU_TRST# 13 14 4.7K_0402_5%
RC41 1 2 1K_0402_1% APU_DBREQ# RC53 1 2 10K_0402_5% 15 16 HDT_DBREQ# 1 RC56 2 APU_DBREQ#
15 16 0_0402_5%
1
17 18 APU_TEST19
17 18
19 20 APU_TEST18
19 20

SAMTE_ASP-136446-07-B APU Msic
Issued Date 2012/07/01 Deciphered Date 2014/07/01
ME@
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.A
1 2 3 4 5
1 2 3 4 5
+VDD_CORE
CC44 CC45 CC46 CC47 CC48 CC49 CC42 CC43

A A
.01U_0402_16V7-K
.01U_0402_16V7-K
.01U_0402_16V7-K
0.22U_0402_10V6-K
0.22U_0402_10V6-K
180P_0402_50V7-K
180P_0402_50V7-K
180P_0402_50V7-K
1 1 1 1 1 1 2 2
2 2 2 2 2 2 1 1
+VDD_CORE UC1E +VDDNB_CORE +1.35V_APU_VDDIO UC1F
POWER POWER
T11 VDD_1 VDDNB_1 E8 L29 VDDIO_1

T14 VDD_2 VDDNB_2 F4 L31 VDDIO_2
T17 VDD_3 VDDNB_3 F5 L34 VDDIO_3
T21 VDD_4 VDDNB_4 G4 L37 VDDIO_4
+VDDNB_CORE
T24 VDD_5 VDDNB_5 G8 M29 VDDIO_5
V10 G10 M32 CC65 CC66 CC67 CC68 CC62 CC63 CC64
VDD_6 VDDNB_6 VDDIO_6
V13 VDD_7 VDDNB_7 H3 N27 VDDIO_7
0.22U_0402_10V6-K
0.22U_0402_10V6-K
0.22U_0402_10V6-K
V16 H6 N34
180P_0402_50V7-K
180P_0402_50V7-K
180P_0402_50V7-K
180P_0402_50V7-K
V19 VDD_9 VDDNB_9 H10 P29 VDDIO_9 1 1 1 1 2 2 2
V22 VDD_10 VDDNB_10 J10 P31 VDDIO_10
V24 VDD_11 VDDNB_11 J13 R29 VDDIO_11
Y7 VDD_12 VDDNB_12 J22 R32 VDDIO_12
Y10 J25 R34 2 2 2 2 1 1 1
Y13 VDD_14 VDDNB_14 K11 R37 VDDIO_14
Y16 K14 U29
Y19
VDD_15
VDD_16
VDDNB_15
VDDNB_16 K17 U31
VDDIO_15
VDDIO_16
22u 6.3V *11 @*2 Design Guide
Y22 VDD_17 VDDNB_17 K21 U34 VDDIO_17 0.22u 10V *2
Y25 K24 V27
AA4
VDD_18
VDD_19
VDDNB_18
VDDNB_19 L4 V34
VDDIO_18
VDDIO_19
+0.95VS_VDDR 0.01u 10V *3
AA11
AA14
VDD_20 VDDNB_20 L7
L10
W29
W32
VDDIO_20
CC81 CC82 CC83 CC84 CC23 CC24 CC25 CC26
180p *3
AA17 VDD_22 VDDNB_22 L13 W37 VDDIO_22
22U_0603_6.3V6-M
22U_0603_6.3V6-M
180P_0402_50V7-K
22U_0603_6.3V6-M
22U_0603_6.3V6-M
0.22U_0402_10V6-K
0.22U_0402_10V6-K
AA21 L16 Y31
22u 6.3V *10 @*2 Design Guide
180P_0402_50V7-K
B AA24 VDD_24 VDDNB_24 L19 AA34 VDDIO_24 1 1 1 1 2 2 1 1 B
AB7 VDD_25 VDDNB_25 L22 AB29 VDDIO_25 0.22u 10V *3
AC4 L25 AB32
AC10
VDD_26
VDD_27
VDDNB_26
VDDNB_27 M3 AB37
VDDIO_26
VDDIO_27
180p 10V *4
AC13 N11 AC29 2 2 2 2 1 1 2 2
AC16 N14 AC31
AC19
VDD_29
VDD_30
VDDNB_29
VDDNB_30 N17 AC34
VDDIO_29
VDDIO_30
22u 6.3V *3
AC22 VDD_31 VDDNB_31 N21 AC37 VDDIO_31 0.22u 10V *2
AC25 N24 AE32
AD4
VDD_32
VDD_33
VDDNB_32
VDDNB_33 P10 AE34
VDDIO_32
VDDIO_33
180p 10V *2
AD11 VDD_34 VDDNB_34 P13 AF30 VDDIO_34
+1.35V_APU_VDDIO
AD14 VDD_35 VDDNB_35 P16 AF31 VDDIO_35
AD17 P19 AG34 CC85 CC86 CC87 CC88 CC89 CC90 CC91 CC92 CC93
AD21
VDD_36
VDD_37
VDDNB_36
VDDNB_37 P22 AG37
VDDIO_36
VDDIO_37
22u 6.3V *4
0.22u 10V *2
4.7U_0603_6.3V6-K
4.7U_0603_6.3V6-K
22U_0603_6.3V6-M
22U_0603_6.3V6-M
4.7U_0603_6.3V6-K
22U_0603_6.3V6-M
4.7U_0603_6.3V6-K
4.7U_0603_6.3V6-K
4.7U_0603_6.3V6-K
AD24 VDD_38 VDDNB_38 P25
AE6 R4
AE22
VDD_39
VDD_40
VDDNB_39
VDDNB_40 R6
1 1 1 1 1 1 1 1 1 180p 10V *2
AE25 VDD_41 VDDNB_41 R9
AF5 T3
AF8
VDD_42
VDD_43
VDDNB_42
+0.95VS_VDDR 2 2 2 2 2 2 2 2 2 4.7u 6.3V *1
AG11 VDD_44
+0.95VS_VDDP 0.22u 10V *1
AH5
AH8
VDD_45
VDD_46
3.3n 10V *1
AH10 VDD_47 AK16 VDDP_1 VDDR_1 AK17
AK8 VDD_48 AL16 VDDP_2 VDDR_2 AM17
AM16 VDDP_3 VDDR_3 AN17
AN16 VDDP_4
+1.35V_APU_VDDIO
+VDDR_CAP CC94 CC95 CC96 CC97 CC98 CC99 CC100 CC101 CC102 CC103 CC104 CC105
+1.8VS_VDDA
0.22U_0402_10V6-K
0.22U_0402_10V6-K
180P_0402_50V7-K
0.22U_0402_10V6-K
0.22U_0402_10V6-K
0.22U_0402_10V6-K
0.22U_0402_10V6-K
0.22U_0402_10V6-K
0.22U_0402_10V6-K
0.22U_0402_10V6-K
0.22U_0402_10V6-K
180P_0402_50V7-K
FP3 REV 0.52 VDDR_CAP AC27 2 2 2 2 2 2 2 2 2 2 1 1
VDDA_1 AH11
KAVERI-2M186092H4467_BGA854 VDDA_2 AJ11
C 1 1 1 1 1 1 1 1 1 1 2 2 C
CC80 AC11 VDDP_CAP
22U_0603_6.3V6-M
22U_0603_6.3V6-M
1 1 RSVD_22 D6
CC79 @
FP3 REV 0.52
2 2 KAVERI-2M186092H4467_BGA854
+0.95VS_VDDP +1.8VS_VDDA +VDDR_CAP
CC69 CC70 CC71 CC72 CC73 CC74 CC75 CC76 CC77 CC78 CC27 @ CC28
0.22U_0402_10V6-K
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
0.22U_0402_10V6-K
4.7U_0603_6.3V6-K
0.22U_0402_10V6-K
3.3n_0402_50V6-K
22U_0603_6.3V6-M
22U_0603_6.3V6-M
180P_0402_50V7-K
1
180P_0402_50V7-K
1 1 1 2 2 1 1 2 2 1 1
2
2 2 2 1 1 2 2 1 1 2 2
3.3n need apply PN
D D

Issued Date 2012/07/01 Deciphered Date 2014/07/01 APU Power
1 2 3 4 5
1 2 3 4 5
UC1G UC1H
A A
VSS
VSS
A1 VSS_1 VSS_61 K13 AC1 VSS_121 VSS_181 AN10
A23 VSS_6 VSS_66 L1 AC24 VSS_126 VSS_186 AN30
A27 VSS_7 VSS_67 L11 AC28 VSS_127 VSS_187 AN37
A31 VSS_8 VSS_68 L14 AD3 VSS_128 VSS_188 AD27
A35 VSS_9 VSS_69 L17 AD10 VSS_129 VSS_189 K27
A37 VSS_10 VSS_70 L21 AD13 VSS_130 VSS_190 AE11
C2 VSS_11 VSS_71 L24 AD16 VSS_131
C3 VSS_12 VSS_72 L28 AD19 VSS_132
C6 VSS_13 VSS_73 M6 AD22 VSS_133
C35 VSS_14 VSS_74 M9 AD25 VSS_134
D4 VSS_15 VSS_75 N4 AD28 VSS_135
D11 VSS_16 VSS_76 N10 AE1 VSS_136
D13 VSS_17 VSS_77 N13 AE4 VSS_137
D15 VSS_18 VSS_78 N16 AE14 VSS_138
D17 VSS_19 VSS_79 N19 AE19 VSS_139
D19 VSS_20 VSS_80 N22 AE21 VSS_140
D21 VSS_21 VSS_81 N25 AE27 VSS_141
D23 VSS_22 VSS_82 N28 AE28 VSS_142
D25 VSS_23 VSS_83 P6 AF7 VSS_143
D27 VSS_24 VSS_84 P9 AF24 VSS_144
D29 VSS_25 VSS_85 P11 AF28 VSS_145
D31 VSS_26 VSS_86 P14 AG1 VSS_146
D33 VSS_27 VSS_87 P17 AG4 VSS_147
E17 VSS_28 VSS_88 P21 AG14 VSS_148
E31 VSS_29 VSS_89 P24 AG17 VSS_149
E34 VSS_30 VSS_90 R1 AG21 VSS_150
F11 VSS_31 VSS_91 T10 AG25 VSS_151
F21 VSS_32 VSS_92 T13 AG27 VSS_152
F24 VSS_33 VSS_93 T16 AG28 VSS_153
B B
F27 VSS_34 VSS_94 T19 AH13 VSS_154
F30 VSS_35 VSS_95 T22 AH16 VSS_155
G1 VSS_36 VSS_96 T25 AH19 VSS_156
G13 VSS_37 VSS_97 U4 AH22 VSS_157
G16 VSS_38 VSS_98 U6 AH30 VSS_158
G19 VSS_39 VSS_99 U9 AH31 VSS_159
G22 VSS_40 VSS_100 V11 AJ4 VSS_160
G25 VSS_41 VSS_101 V14 AJ24 VSS_161
G28 VSS_42 VSS_102 V17 AJ25 VSS_162
G34 VSS_43 VSS_103 V21 AK9 VSS_163
G37 VSS_44 VSS_104 V25 AK12 VSS_164
H8 VSS_45 VSS_105 W1 AK13 VSS_165
H14 VSS_46 VSS_106 W4 AK15 VSS_166
H17 VSS_47 VSS_107 W6 AK19 VSS_167
H30 VSS_48 VSS_108 W9 AK21 VSS_168
H32 VSS_49 VSS_109 Y3 AK23 VSS_169
J4 VSS_50 VSS_110 Y11 AK25 VSS_170
J6 VSS_51 VSS_111 Y14 AK27 VSS_171
J11 VSS_52 VSS_112 Y17 AK29 VSS_172
J16 VSS_53 VSS_113 Y21 AK31 VSS_173
J21 VSS_54 VSS_114 Y24 AK34 VSS_174
J24 VSS_55 VSS_115 AA10 AL3 VSS_175
J27 VSS_56 VSS_116 AA13 AL8 VSS_176
J28 VSS_57 VSS_117 AA16 AL37 VSS_177
J32 VSS_58 VSS_118 AA19 AM35 VSS_178
J34 VSS_59 VSS_119 AA22 AN1 VSS_179
K10 VSS_60 VSS_120 AA25 AN7 VSS_180
FP3 REV 0.52 FP3 REV 0.52
KAVERI-2M186092H4467_BGA854 KAVERI-2M186092H4467_BGA854
C C
D D

Issued Date 2012/07/01 Deciphered Date 2014/07/01 APU GND
1 2 3 4 5
5 4 3 2 1
DDR Decoupling
DDR3 SO-DIMM A DDRA_DQ[0..63] 6
+1.35V_DDR_VDDIOSUS
DDRA_DQS[0..7] 6
CD7
1uF *4, 10uF *7, 330uF *1
CD8 CD9 CD10
+1.35V_DDR_VDDIOSUS +1.35V_DDR_VDDIOSUS DDRA_DQS#[0..7] 6
+VREF_DQA_D 3A@1.5V DDRA_MA[0..15] 6 Layout Note :
0.1U_0402_10V7-K
0.1U_0402_10V7-K
1
0.1U_0402_10V7-K
1 1 1
1. Placed near JDDR3L
0.1U_0402_10V7-K
RD17 JDDR1
@
D
+VREF_DQA 1 2 1
3 VREF_DQ
VSS_1
VSS_2
DQ4
2
4 DDRA_DQ4 2 2 2 2
2. Place these 4 Caps near Command D
0_0402_5% DDRA_DQ0
DDRA_DQ1
5
7 DQ0
DQ1
DQ5
VSS_4
6
8
DDRA_DQ5
and Control signals of DIMMA
9 10 DDRA_DQS#0
DDRA_MA_DM0 11 VSS_3 DQS0# 12 DDRA_DQS0
6 DDRA_MA_DM0 DM0 DQS0
13 14
DDRA_DQ2 15 VSS_5 VSS_6 16 DDRA_DQ6
1 1 DQ2 DQ6
CD1 CD2 DDRA_DQ3 17 18 DDRA_DQ7
1000P_0402_50V7-K
0.1U_0402_10V7-K
19 DQ3 DQ7 20 @
DDRA_DQ8 21 VSS_7 VSS_8 22 DDRA_DQ12 @
@ CD11 CD12 CD47 CD15 CD16 CD18 CD42
2 2 DDRA_DQ9 23 DQ8 DQ12 24 DDRA_DQ13 CD13 CD17
DQ9 DQ13 CD14 CD19
25 26 @ @
VSS_9 VSS_10 @
DDRA_DQS#1 27 28 DDRA_MA_DM1
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
DDRA_MA_DM1 6 1
0.1U_0402_10V7-K
DQS1# DM1
0.1U_0402_10V7-K
DDRA_DQS1 29 30 DDRA_RESET#
10U_0603_6.3V6-M
330U_D2_2VM_R9M
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
DQS1 RESET# DDRA_RESET# 6 1 1 1 1 1 1 1 1 1 1
31 32 +
DDRA_DQ10 33 VSS_11 VSS_12 34 DDRA_DQ14 @
DDRA_DQ11 35 DQ10 DQ14 36 DDRA_DQ15
37 DQ11 DQ15 38 2 2 2 2 2 2 2 2 2 2 2
Close to JDDR3H.1 DDRA_DQ16 39 VSS_13 VSS_14 40 DDRA_DQ20
43 DQ17 DQ21 44
DDRA_DQS#2 45 VSS_15 VSS_16 46 DDRA_MA_DM2
DQS2# DM2 DDRA_MA_DM2 6
DDRA_DQS2 47 48
49 DQS2 VSS_18 50 DDRA_DQ22
DDRA_DQ18 51 VSS_17 DQ22 52 DDRA_DQ23
DDRA_DQ19 53 DQ18 DQ23 54
55 DQ19 VSS_20 56 DDRA_DQ28
VSS_19 DQ28 CD49 CD50 CD51 CD52
DDRA_DQ24 57 58 DDRA_DQ29
DDRA_DQ25 59 DQ24 DQ29 60
61 DQ25 VSS_22 62 DDRA_DQS#3
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
6 DDRA_MA_DM3 DM3 DQS3 1 1 1 1
65 66
71 DQ27 DQ31 72 2 2 2 2
C VSS_25 VSS_26 C
6 DDRA_CKE0 DDRA_CKE0 73 74 DDRA_CKE1

CKE0 CKE1 DDRA_CKE1 6
75 76
77 VDD_1 VDD_2 78 DDRA_MA15
DDRA_BA2# 79 NC_1 A15 80 DDRA_MA14
6 DDRA_BA2# BA2 A14
81 82
DDRA_MA12 83 VDD_3 VDD_4 84 DDRA_MA11
DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
87 A9 A7 88
DDRA_MA8 89 VDD_5 VDD_6 90 DDRA_MA6
DDRA_MA5 91 A8 A6 92 DDRA_MA4 +0.675VS
93 A5 A4 94
DDRA_MA3 95 VDD_7 VDD_8 96 DDRA_MA2 CD23
DDRA_MA1 97 A3 A2 98 DDRA_MA0 CD59 CD20 CD21 CD22
99 A1 A0 100 Layout Note : Placed near
4.7U_0603_6.3V6K
DDRA_CLK0 101 VDD_9 VDD_10 102 DDRA_CLK1
JDDR3L1.Pin203, 204
0.1U_0402_10V7-K
6 DDRA_CLK0 CK0 CK1 DDRA_CLK1 6
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
DDRA_CLK0# 103 104 DDRA_CLK1# 1 1 1 1 1
6 DDRA_CLK0# CK0# CK1# DDRA_CLK1# 6
105 106
DDRA_MA10 107 VDD_11 VDD_12 108 DDRA_BA1#
A10/AP BA1 DDRA_BA1# 6 @
DDRA_BA0# 109 110 DDRA_RAS# 2
6 DDRA_BA0# BA0 RAS# DDRA_RAS# 6 2 2 2 2
111 112
DDRA_WE# 113 VDD_13 VDD_14 114 DDRA_CS0#
6 DDRA_WE# WE# S0# DDRA_CS0# 6
6 DDRA_CAS# DDRA_CAS# 115 116 DDRA_ODT0
CAS# ODT0 DDRA_ODT0 6
117 118
DDRA_MA13 119 VDD_15 VDD_16 120 DDRA_ODT1
A13 ODT1 DDRA_ODT1 6
6 DDRA_CS1# DDRA_CS1# 121
123 S1# NC_2
122
124
All VREF traces should have 20 mil trace width
125 VDD_17 VDD_18 126
TEST VREF_CA +V_SM_VREF_CNT
127 128
133 DQ33 DQ37 134
DDRA_DQS#4 135 VSS_29 VSS_30 136 DDRA_MA_DM4 +1.35V_DDR_VDDIOSUS
B DDRA_DQS4 137 138 B
DDRA_DQ34 141 VSS_31 DQ38 142 DDRA_DQ39
DQ34 DQ39 1 1
DDRA_DQ35 143 144 CD5 CD6
0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
DQ35 VSS_34
1
145 146 DDRA_DQ44 +VREF_DQA_D
VSS_33 DQ44 +1.35V_DDR_VDDIOSUS
DDRA_DQ40 147 148 DDRA_DQ45 RD6
DDRA_DQ41 149 DQ40 DQ45 150 2 2 1K_0402_1%
151 DQ41 VSS_35 152 DDRA_DQS#5
1
6 DDRA_MA_DM5
2
155 DM5 DQS5 156 RD11
DDRA_DQ42 157 VSS_37 VSS_38 158 DDRA_DQ46 1K_0402_1% DDRA_EVENT#
161 DQ43 DQ47 162
2
close to JDDR3L.126
167 DQ49 DQ53 168
DDRA_DQS#6 169 VSS_41 VSS_42 170 DDRA_MA_DM6
DDRA_DQS6 171 172
1
VSS_43 DQ54 RD12
DDRA_DQ50 175 176 DDRA_DQ55 1K_0402_1%
DDRA_DQ51 177 DQ50 DQ55 178
179 DQ51 VSS_46 180 DDRA_DQ60
SPD setting (SA0, SA1) VSS_45 DQ60
181 182
2
PU/PD by Channel A/B DDRA_DQ56 DDRA_DQ61
DDRA_DQ57 183 DQ56 DQ61 184
->Channel A 00 185 DQ57 VSS_48 186 DDRA_DQS#7
->Channel B 01 DDRA_MA_DM7 187 VSS_47 DQS7# 188 DDRA_DQS7
6 DDRA_MA_DM7 DM7 DQS7
189 190
195 DQ59 DQ63 196
DDRA_SA0 197 VSS_51 VSS_52 198 DDRA_EVENT#
SA0 EVENT# DDRA_EVENT# 6
199 200 SMB0_DATA
+3VS VDDSPD SDA SMB0_DATA 11,14,33
DDRA_SA1 201 202 SMB0_CLK
SA1 SCL SMB0_CLK 11,14,33
1 1 203 204 +0.675VS
VTT_1 VTT_2
A CD3 CD4 205 206 A
2.2U_0603_6.3V6-K 0.1U_0402_10V6-K 207 GND1 GND2 208
2 2 BOSS1 BOSS2
RD167 10_0402_5% 2 DDRA_SA0
RD168 1 0_0402_5%2 DDRA_SA1 LCN_DAN06-K4406-0103

Issued Date 2012/12/05 Deciphered Date 2014/12/05 DDR3 SO-DIMMA/1
5 4 3 2 1
5 4 3 2 1
DDR3 SO-DIMM B DDRB_DQ[0..63] 6
DDRB_DQS[0..7] 6
+1.35V_DDR_VDDIOSUS DDRB_DQS#[0..7] 6
+VREF_DQB_D +1.35V_DDR_VDDIOSUS
3A@1.5V DDRB_MA[0..15] 6
RD18 JDDR2
1 @ 2 1 2
+VREF_DQB VREF_DQ VSS1
3 4 DDRB_DQ4
0_0402_5% DDRB_DQ0 5 VSS2 DQ4 6 DDRB_DQ5
D
DDRB_DQ1 7
9
DQ0
DQ1
DQ5
VSS3
8
10 DDRB_DQS#0
DDR Decoupling D
DDRB_MB_DM0 11 VSS4 DQS#0 12 DDRB_DQS0
6 DDRB_MB_DM0 DM0 DQS0 +1.35V_DDR_VDDIOSUS
13 14
DDRB_DQ2
DDRB_DQ3
15
17
VSS5
DQ2
VSS6
DQ6
16
18
DDRB_DQ6
DDRB_DQ7
1uF *4, 10uF *7, 330uF *1
DQ3 DQ7 CD30 CD31 CD32 CD33
1 1 19 20
CD24 CD25 DDRB_DQ8 21 VSS7 VSS8 22 DDRB_DQ12
1000P_0402_50V7-K
Layout Note :
0.1U_0402_10V7-K
DDRB_DQ9 23 DQ8 DQ12 24 DDRB_DQ13

25 DQ9 DQ13 26
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
@ 1 1 1 1
2 2 VSS9 VSS10
1. Placed near JDDR3H
0.1U_0402_10V7-K
DDRB_DQS#1 27 28 DDRB_MB_DM1 DDRB_MB_DM1 6
DDRB_DQS1 29 DQS#1 DM1 30 DDRB_RESET#
DDRB_DQ10
31
33
DQS1
VSS11
RESET#
VSS12
32
34 DDRB_DQ14
DDRB_RESET# 6
2 2 2 2 2. Place these 4 Caps near Command
DDRB_DQ11 35
37
DQ10
DQ11
DQ14
DQ15
36
38
DDRB_DQ15
and Control signals of DIMMA
DDRB_DQ16 39 VSS13 VSS14 40 DDRB_DQ20
Close to JDDR3L.1 43 DQ17 DQ21 44
DDRB_DQS#2 45 VSS15 VSS16 46 DDRB_MB_DM2
DQS#2 DM2 DDRB_MB_DM2 6
DDRB_DQS2 47 48
49 DQS2 VSS17 50 DDRB_DQ22
VSS18 DQ22 @
DDRB_DQ18 51 52 DDRB_DQ23 CD54 CD55 CD38 CD39 CD40 CD41
DDRB_DQ19 53 DQ18 DQ23 54 CD34 CD35 CD36 CD37
55 DQ19 VSS19 56 DDRB_DQ28 @ @ @ @
DDRB_DQ24 57 VSS20 DQ28 58 DDRB_DQ29
DQ24 DQ29
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
DDRB_DQ25 59 60
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
DQ25 VSS21 1 1 1 1 1 1 1 1
61 62 DDRB_DQS#3 1 1
6 DDRB_MB_DM3 DM3 DQS3
65 66
DDRB_DQ26 67 VSS23 VSS24 68 DDRB_DQ30 2 2 2 2 2 2 2 2
DDRB_DQ27 69 DQ26 DQ30 70 DDRB_DQ31 2 2
71 DQ27 DQ31 72
VSS25 VSS26
C C
DDRB_CKE0 73 74 DDRB_CKE1
6 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 6
75 76
77 VDD1 VDD2 78 DDRB_MA15
DDRB_BA2# 79 NC1 A15 80 DDRB_MA14 CD62 CD61 CD64 CD63
6 DDRB_BA2# BA2 A14
81 82
DDRB_MA12 83 VDD3 VDD4 84 DDRB_MA11
DDRB_MA9 85 A12/BC# A11 86 DDRB_MA7
A9 A7
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
87 88 1 1 1 1
DDRB_MA8 89 VDD5 VDD6 90 DDRB_MA6
DDRB_MA5 91 A8 A6 92 DDRB_MA4
93 A5 A4 94
VDD7 VDD8 2 2 2 2
DDRB_MA3 95 96 DDRB_MA2
DDRB_MA1 97 A3 A2 98 DDRB_MA0
99 A1 A0 100
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1
6 DDRB_CLK0 CK0 CK1 DDRB_CLK1 6
DDRB_CLK0# 103 104 DDRB_CLK1#
6 DDRB_CLK0# CK0# CK1# DDRB_CLK1# 6
105 106
DDRB_MA10 107 VDD11 VDD12 108 DDRB_BA1#
A10/AP BA1 DDRB_BA1# 6
6 DDRB_BA0# DDRB_BA0# 109 110 DDRB_RAS#
BA0 RAS# DDRB_RAS# 6
111 112
DDRB_WE# 113 VDD13 VDD14 114 DDRB_CS0#
6 DDRB_WE# WE# S0# DDRB_CS0# 6
6 DDRB_CAS# DDRB_CAS# 115 116 DDRB_ODT0
CAS# ODT0 DDRB_ODT0 6
117 118
DDRB_MA13 119 VDD15 VDD16 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 6
6 DDRB_CS1# DDRB_CS1# 121 122
123 S1# NC2 124 +0.675VS
125 VDD17 VDD18 126
NCTEST VREF_CA +V_SM_VREF_CNT
127 128
DDRB_DQ32 129 VSS27 VSS28 130 DDRB_DQ36 CD43 CD44 CD45 CD46
DDRB_DQ33 131 DQ32
DQ33
DQ36
DQ37
132 DDRB_DQ37 1 1 Layout Note : Placed near
4.7U_0603_6.3V6K
133 134 CD28 CD29
1000P_0402_50V7-K
JDDR3H.Pin203, 204
0.1U_0402_10V7-K
135 VSS29 VSS30 136
1U_0402_6.3V6-K
1U_0402_6.3V6-K
DDRB_DQS#4 DDRB_MB_DM4
1U_0402_6.3V6-K
1U_0402_6.3V6-K
DQS#4 DM4 DDRB_MB_DM4 6 1 1 1 1 1
DDRB_DQS4 137 138 CD58
139 DQS4 VSS31 140 DDRB_DQ38 2 2
DDRB_DQ34 141 VSS32 DQ38 142 DDRB_DQ39 @
B B
DDRB_DQ35 143 DQ34 DQ39 144 2 2 2 2 2
145 DQ35 VSS33 146 DDRB_DQ44
DDRB_DQ41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDRB_DQS#5
6 DDRB_MB_DM5
155 DM5 DQS5 156
Close to JDDR3H.126
DDRB_DQ42 157 VSS37 VSS38 158 DDRB_DQ46
161 DQ43 DQ47 162
VSS39 VSS40 +1.35V_DDR_VDDIOSUS +V_SM_VREF_CNT
DDRB_DQ48 163 164 DDRB_DQ52
DQ49 DQ53 +1.35V_DDR_VDDIOSUS
167 168
VSS41 VSS42
1
DDRB_DQS#6 169 170 DDRB_MB_DM6 DDRB_MB_DM6 6
DDRB_DQS6 171 DQS#6 DM6 172 RD5
173 DQS6 VSS43 174 DDRB_DQ54 1K_0402_1%
1
DQ50 DQ55 +1.35V_DDR_VDDIOSUS +VREF_DQB_D
DDRB_DQ51 177 178
DQ51 VSS45 RD8
2
179 180 DDRB_DQ60
VSS46 DQ60 1K_0402_1%
1
DDRB_DQ57 183 DQ56 DQ61 184
DQ57 VSS47 RD9
SPD setting (SA0, SA1) 185 186 DDRB_DQS#7
2
1K_0402_1%
1
PU/PD by Channel A/B 6 DDRB_MB_DM7 DM7 DQS7 DDRB_EVENT# RD7
->Channel A 00 189 190
VSS49 VSS50 1K_0402_1%
2
->Channel B 01 DDRB_DQ59 193 DQ58 DQ62 194 DDRB_DQ63
195 DQ59 DQ63 196
R167 10K_0402_5%
2
1 2 DDRB_SA0 197 VSS51 VSS52 198 DDRB_EVENT#
+3VS SA0 EVENT# 200 DDRB_EVENT# 6
199 SMB0_DATA
1
+3VS VDDSPD SDA SMB0_DATA 10,14,33
1 2 DDRB_SA1 201 202 SMB0_CLK
203 SA1 SCL 204 SMB0_CLK 10,14,33 RD10
1 1 RD170 0_0402_5% VTT1 VTT2 +0.675VS 1K_0402_1%
CD26 CD27 205 206
2.2U_0603_6.3V6-K 0.1U_0402_10V6-K G1 G2
2
A 2 2 LCN_DAN06-K4406-0102 A
CRB: DDRB_SA1 pull low / DDRB_SA0 pull high Security Classification LC Future Center Secret Data Title
Edge: DDRB_SA1 pull high / DDRB_SA0 pull low Issued Date 2012/12/05 Deciphered Date 2014/12/05 DDR3 SO-DIMMB/2
5 4 3 2 1
1 2 3 4 5
CH82
PLT_RST# 1 2 EC_A_RST#
1 2 +3VALW
RH91 0_0402_5%
150P_0402_50V8-J
CH15 CLK_PCI_EC RH99 1 @ 2 10K_0402_5%
1 2 @ UH2A
150P_0402_50V8-J BOLTON-M3
RH1 @ Part 1 of 5
A PLT_RST# 1 2 33_0402_5% PLT_RST_R# AE2 PCIE_RST# PCICLK0 AF3 PCICLK0 A
17,33,35 PLT_RST# RH2 PCICLK0 33 +3VS
EC_A_RST# 1 2 33_0402_5% A_RST# AD5 A_RST# PCICLK1/GPO36 AF1 PCICLK1
38 EC_A_RST# PCICLK1 16
PCICLK2/GPO37 AF5
UMI_CRX_FTX_P0 CH1 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_P0_C AE30 UMI_TX0P PCICLK3/GPO38 AG2 PCICLK3 PCH_BT_DISABLE# RH23 1 2 10K_0402_5%
5 UMI_CRX_FTX_P0 PCICLK3 16
UMI_CRX_FTX_N0 CH2 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_N0_C AE32 PCICLK4/14M_OSC/GPO39 AF6 PCICLK4
PCI CLKS
UMI_TX0N
5 UMI_CRX_FTX_N0 PCICLK4 16
UMI_CRX_FTX_P1 CH3 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_P1_C AD33 UMI_TX1P
5 UMI_CRX_FTX_P1
UMI_CRX_FTX_N1 CH4 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_N1_C AD31 UMI_TX1N PCIRST# AB5 TPV38 1 Test_Point_20MIL
5 UMI_CRX_FTX_N1
UMI_CRX_FTX_P2 CH5 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_P2_C AD28 UMI_TX2P
5 UMI_CRX_FTX_P2 +3VS
UMI_CRX_FTX_N2 CH6 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_N2_C AD29 UMI_TX2N AD0/GPIO0 AJ3
5 UMI_CRX_FTX_N2
UMI_CRX_FTX_P3 CH7 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_P3_C AC30 UMI_TX3P AD1/GPIO1 AL5
5 UMI_CRX_FTX_P3
UMI_CRX_FTX_N3 CH8 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_N3_C AC32 UMI_TX3N AD2/GPIO2 AG4 FCH_WLAN_OFF# RH25 1 2 10K_0402_5%
5 UMI_CRX_FTX_N3
AD3/GPIO3
AL6
UMI_CTX_FRX_P0_C AB33 UMI_RX0P AD4/GPIO4 AH3
5 UMI_CTX_FRX_P0_C
UMI_CTX_FRX_N0_C AB31 UMI_RX0N AD5/GPIO5 AJ5
5 UMI_CTX_FRX_N0_C
UMI_CTX_FRX_P1_C AB28 UMI_RX1P AD6/GPIO6 AL1
5 UMI_CTX_FRX_P1_C
UMI_CTX_FRX_N1_C AB29 UMI_RX1N AD7/GPIO7
AN5
5 UMI_CTX_FRX_N1_C
UMI_CTX_FRX_P2_C Y33 UMI_RX2P AD8/GPIO8 AN6
5 UMI_CTX_FRX_P2_C
UMI_CTX_FRX_N2_C Y31 UMI_RX2N AD9/GPIO9
AJ1
5 UMI_CTX_FRX_N2_C Spare one PCH pin to add FCH_WLAN_OFF#
UMI_CTX_FRX_P3_C Y28 UMI_RX3P AD10/GPIO10 AL8
5 UMI_CTX_FRX_P3_C
UMI_CTX_FRX_N3_C Y29 UMI_RX3N AD11/GPIO11 AL3
5 UMI_CTX_FRX_N3_C
AD12/GPIO12 AM7 FCH_WLAN_OFF#
FCH_WLAN_OFF# 33
PCI EXPRESS INTERFACES

RH4 1 2 590_0402_1% PCIE_CALRP AF29 PCIE_CALRP AD13/GPIO13 AJ6 PCH_BT_DISABLE#
PCH_BT_DISABLE# 33
+VDDAN_11_PCIE RH3 1 2 2K_0402_1% PCIE_CALRN AF31 PCIE_CALRN AD14/GPIO14 AK7
AD15/GPIO15 AN8
V33 GPP_TX0P AD16/GPIO16 AG9
V31 GPP_TX0N AD17/GPIO17 AM11
W30 GPP_TX1P AD18/GPIO18 AJ10
W32 GPP_TX1N AD19/GPIO19 AL12
AB26 GPP_TX2P AD20/GPIO20 AK11
AB27 GPP_TX2N AD21/GPIO21 AN12
AA24 GPP_TX3P AD22/GPIO22 AG12
AA23 GPP_TX3N AD23/GPIO23 AE12
PCI_AD23 16
AD24/GPIO24 AC12
PCI_AD24 16
AA27 AD25/GPIO25 AE13
PCI INTERFACE
GPP_RX0P
PCI_AD25 16
AA26 GPP_RX0N AD26/GPIO26 AF13
B PCI_AD26 16 B
W27 GPP_RX1P AD27/GPIO27 AH13
PCI_AD27 16
V27 GPP_RX1N AD28/GPIO28 AH14 DGPU_PWROK_R 1 2 DGPU_PWROK
DGPU_PWROK 38,51
V26 GPP_RX2P AD29/GPIO29 AD15 RH85 0_0402_5%
W26 GPP_RX2N AD30/GPIO30 AC15
W24 GPP_RX3P AD31/GPIO31 AE16
W23 GPP_RX3N CBE0# AN3
CBE1# AJ8 Change DGPU_PWROK_R from UH2.AG26 to UH2.AH14
CBE2# AN10
RH5 1 2 2K_0402_1% CLK_CALRN F27 CLK_CALRN CBE3# AD12
+VDDAN_11_CLK
FRAME# AG10
DEVSEL# AK9 LPC_CLK0
G30 PCIE_RCLKP IRDY# AL10
G28 PCIE_RCLKN TRDY# AF10
1
PAR AE10 CH22
RH6 1 2 0_0402_5% DISP_CLKP_R R26 DISP_CLKP STOP# AH1 @ 22P_0402_50V8-J
7 DISP_CLKP
OK APU 7 DISP_CLKN
RH7 1 2 0_0402_5% DISP_CLKN_R T26 DISP_CLKN PERR# AM9
2
SERR# AH8
H33 DISP2_CLKP REQ0# AG15
H31 DISP2_CLKN REQ1#/GPIO40 AG13
REQ2#/CLK_REQ8#/GPIO41 AF15
RH8 1 2 0_0402_5% APU_CLKP_R T24 APU_CLKP REQ3#/CLK_REQ5#/GPIO42 AM17 TPH2 1 Test_Point_12MIL
7 APU_CLKP
OK APU 7 APU_CLKN
RH9 1 2 0_0402_5% APU_CLKN_R T23 APU_CLKN GNT0# AD16
AD13 HOLD_RST#_R 0_0402_5% 2 DIS@ 1 RH88
GNT1#/GPO44 DGPU_HOLD_RST# 17
RH10 1 2 0_0402_5% GFX_CLKP_R J30 SLT_GFX_CLKP GNT2#/SD_LED/GPO45 AD21 DGPU_PWREN_R 0_0402_5% 2 DIS@ 1 RH90 DGPU_PWREN 17,24,51
17 GFX_CLKP
GPU 17 GFX_CLKN
RH11 1 2 0_0402_5% GFX_CLKN_R K29 SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46 AK17 TPH1 1 Test_Point_12MIL
CLKRUN# AD19 +3VS
RH12 1 2 0_0402_5% PCIE_LAN_CLK_P0_R H27 GPP_CLK0P LOCK# AH9
PCIE_LAN_CLK_P0
LAN35
35 PCIE_LAN_CLK_N0
RH13 1 2 0_0402_5% PCIE_LAN_CLK_N0_R H28 GPP_CLK0N
AF18
INTE#/GPIO32
J27 GPP_CLK1P INTF#/GPIO33 AE18 internal PU 8.2K
K26 GPP_CLK1N INTG#/GPIO34 AC16
AD18 ODD_DA_INTH# HOLD_RST#_R RH148 1 2 10K_0402_5%
INTH#/GPIO35
ODD_DA_INTH# 32
RH16 1 2 0_0402_5% PCIE_WLAN_CLK_P2_R F33 GPP_CLK2P
33 PCIE_WLAN_CLK_P2
WLAN RH17 1 2 0_0402_5% PCIE_WLAN_CLK_N2_R F31 Follow Edge to put pull down 10k for HOLD_RST#_R
Add ODD_DA_INTH# Core Power Well on 20130930
GPP_CLK2N
C
33 PCIE_WLAN_CLK_N2 C
E33 GPP_CLK3P
E31 GPP_CLK3N
33_0402_5% RH86
DGPU_PWREN_R RH146 1 2 100K_0402_5%
LPCCLK0 B25 LPC_CLK0 2 1
CLK_PCI_EC 16,38
M23 LPCCLK1 D25 LPC_CLK1
CLOCK GENERATOR
GPP_CLK4P
LPC_CLK1 16 @
PCH Crystal M24 GPP_CLK4N LAD0 D27 LPC_AD0
LPC_AD0 38
DGPU_PWROK_R RH147 1 2 100K_0402_5%
LAD1 C28 LPC_AD1
LPC_AD1 38
M27 GPP_CLK5P A26 LPC_AD2 Follow Edge to put pull down 100k for DGPU_PWROK_R
LPC
LAD2 LPC_AD2 38
M26 GPP_CLK5N LAD3 A29 LPC_AD3
FCH_XTAL25_IN LPC_AD3 38
LFRAME# A31 LPC_FRAME# Follow Edge to put pull down 100k for
LPC_FRAME# 38
N25 GPP_CLK6P LDRQ0# B27
FCH_XTAL25_OUT RH18 1 2 1M_0402_5%
N26 GPP_CLK6N LDRQ1#/CLK_REQ6#/GPIO49AE27
DGPU_PWREN_R
SERIRQ/GPIO48 AE19 SERIRQ
R23 GPP_CLK7P
SERIRQ 38 Check DGPU_PWREN_R and DGPU_PWROK_R pull up or down with AMD and PWR
YH1
R24 GPP_CLK7N
1 4
OSC1 GND2 N27 GPP_CLK8P DMA_ACTIVE#
G25 ALLOW_STOP
ALLOW_STOP 7
R27 GPP_CLK8N PROCHOT#
E28 FCH_PROCHOT#
2 3 FCH_PROCHOT# 7
E26 APU_PWROK
APU
GND1 OSC2 APU_PG

APU_PWROK 7,52
1 G26
10P_0402_50V8J
CH16 1
CH17 J26 14M_25M_48M_OSC
LDT_STP#
APU_RST# F26 APU_RESET# RTC Crystal FCH_XTAL32X1
25MHZ_10PF_7V25000014 APU_RESET# 7 RH31
10P_0402_50V8J
1 2 FCH_XTAL32X2
2
2 32K_X1 G2 FCH_XTAL32X1 VCCRTC
FCH_XTAL25_IN C31 25M_X1 20M_0402_5%
32K_X2 G4 FCH_XTAL32X2
H7 FCH_S5 Follow Edge to change UE1.Pin35 from VSB_ON to FCH_S5 on 0927

YH2 1 2
S5_CORE_EN FCH_S5 38
Change to 7V25000014 (TXC),. Cap 10pF*2 on 2013/12/5 FCH_XTAL25_OUT C33 25M_X2 RTCCLK
F1 RTC_CLK
RTC_CLK 16
S5 PLUS
INTRUDER_ALERT# F3 32.768KHZ_12.5PF_200458-PG14
E6 +RTCBATT_R 1 2 1 1
VDDBT_RTC_G CH19 CH20
1 W=20mils
2
1K_0402_1% JCMOS1 22P_0402_50V8-J 22P_0402_50V8-J
1U_0402_10V6-K CH18 SHORT PADS 2
218084401A1BOLTONM3_FCBGA656 RH21 2
D @ D
1
2

Issued Date 2012/07/01 Deciphered Date 2014/07/01 FCH PCIe/PCI/LPC/APU/S5+
1 2 3 4 5
1 2 3 4 5
Add table on 2013 1001
BOARD ID
Config. SKU ID Function PANEL ID Function
0 UMA@ 0 14@ +3VS
UH2B
1 DIS@ 1 15@
A BOLTON-M3 Part 2 of 5
A
SATA_FTX_DRX_P0 AK19 SATA_TX0P SD_CLK/SCLK_0/GPIO73 AL14
32 SATA_FTX_DRX_P0
2
SATA_FTX_DRX_N0 AM19 SATA_TX0N SD_CMD/SLOAD_0/GPIO74 AN14
32 SATA_FTX_DRX_N0 AJ12 SKU ID RH94 RH96
HDD SATA_FRX_DTX_N0 AL20 SATA_RX0N
SD_CD#/GPIO75
AH12 PANEL ID 10K_0402_5% 10K_0402_5%
32 SATA_FRX_DTX_N0 SD_WP/GPIO76
DIS@
32 SATA_FRX_DTX_P0 SATA_FRX_DTX_P0 AN20 SATA_RX0P SD_DATA0/SDATI_0/GPIO77 AK13 CMOS_ON#
CMOS_ON# 27 15@
SD_DATA1/SDATO_0/GPIO78 AM13
1
SATA_FTX_DRX_P1 AN22 AH15
SD CARD
SATA_TX1P SD_DATA2/GPIO79
32 SATA_FTX_DRX_P1 SATA_FTX_DRX_N1 AL22 AJ14
SATA_TX1N SD_DATA3/GPIO80
32 SATA_FTX_DRX_N1
ODD 32 SATA_FRX_DTX_N1 SATA_FRX_DTX_N1 AH20 SATA_RX1N GBE_COL AC4 SKU ID
32 SATA_FRX_DTX_P1 SATA_FRX_DTX_P1 AJ20 SATA_RX1P GBE_CRS AD3 delete BT_DET# on UH2.AM13 on 2013 0927
GBE_MDCK AD9 PANEL ID
AJ22 SATA_TX2P GBE_MDIO W10
AH22 SATA_TX2N GBE_RXCLK AB8
2
GBE_RXD3 AH7
AM23 SATA_RX2N GBE_RXD2 AF7 RH95 RH97
AK23 SATA_RX2P GBE_RXD1 AE7 10K_0402_5% 10K_0402_5%
GBE_RXD0 AD7 UMA@ 14@
AH24 SATA_TX3P GBE_RXCTL/RXDV AG8
1
AJ24 SATA_TX3N GBE_RXERR AD1
GBE LAN
GBE_TXCLK AB7
AN24 SATA_RX3N GBE_TXD3 AF9 delete PROJECT ID on UH2.AN14 on 2013 1001
AL24 SATA_RX3P GBE_TXD2 AG6 +3VALW
GBE_TXD1 AE8
AL26 SATA_TX4P GBE_TXD0 AD8 @
AN26 SATA_TX4N GBE_TXCTL/TXEN AB9 GBE_PHY_INTR RH82 1 2 10K_0402_5%
GBE_PHY_PD AC2
AJ26 SATA_RX4N GBE_PHY_RST# AA7
AH26 SATA_RX4P GBE_PHY_INTR W9 GBE_PHY_INTR
AN29 SATA_TX5P
AL28 SATA_TX5N SPI_DI/GPIO164 V6 SPI_SI
SPI_SI 38
SPI_DO/GPIO163 V5 SPI_SO
AK27 V3 SPI_SO 38
SATA_RX5N SPI_CLK/GPIO162 SPI_CLK
SPI_CLK 38
AM27 T6 SPI_CS1#
SERIAL ATA
SATA_RX5P SPI_CS1#/GPIO165
SPI_CS1# 38
ROM_RST#/SPI_WP#/GPIO161 V1 SPI_WP#
SPI ROM
AL29 NC6
B AN31 NC7 B
L30
AL31 NC8
VGA_RED
RH19 1 2 150_0402_5%
FCH_CRT_R 29 8M SPI ROM
AL33 NC9 VGA_GREEN L32
FCH_CRT_G 29
RH20 1 2 150_0402_5% SPI_SO RH70 1 2 0_0402_5% SPI_SO_8MB
AH33 NC10 VGA_BLUE M29
AH31 FCH_CRT_B 29
NC11 RH29 1 2 150_0402_5% SPI_SI RH71 1 2 0_0402_5% SPI_SI_8MB
AJ33 NC12 VGA_HSYNC/GPO68 M28 FCH_CRT_HSYNC SPI_CLK RH72 1 2 0_0402_5% SPI_CLK_8MB
AJ31 N30 FCH_CRT_HSYNC 29
NC13 VGA_VSYNC/GPO69 FCH_CRT_VSYNC
FCH_CRT_VSYNC 29
VGA DAC
SPI_CS1# RH73 1 2 0_0402_5% SPI_CS1#_8MB
M33 FCH_CRT_DDC_DATA
VGA_DDC_SDA/GPO70 FCH_CRT_DDC_DATA 29
VGA_DDC_SCL/GPO71 N32 FCH_CRT_DDC_CLK FCH_CRT_DDC_CLK 29
RH32 1 2 1K_0402_1% SATA_CALRP AF28 SATA_CALRP
RH33 1 2 931_0402_1% SATA_CALRN AF27 K31 RH151 1 2 715_0402_1%
+VDDAN_11_SATA SATA_CALRN VGA_DAC_RSET
short +3V_SPI and +3VALW directly
AUX_VGA_CH_P V28 APU_VGA_AUX_C CC115 1 2 .1U_0402_16V7K
APU_VGA_AUX 7
+3VS RH83 2 @ 1 10K_0402_5% FCH_GPIO67 AD22 SATA_ACT#/GPIO67 AUX_VGA_CH_N V29 APU_VGA_AUX#_C CC114 1 2 .1U_0402_16V7K +3VALW +3V_SPI
APU_VGA_AUX# 7
U28 RH150 1 2 100_0402_5%
RH108 1 2 10K_0402_5% FCH_GPIO67
AUXCAL VDDAN_11_ML
AF21 SATA_X1
ML_VGA_L0P T31 APU_VGA_TXP0
APU_VGA_TXP0 7
ML_VGA_L0N T33 APU_VGA_TXN0
APU_VGA_TXN0 7
ML_VGA_L1P T29 APU_VGA_TXP1 +3V_SPI
T28 APU_VGA_TXP1 7
ML_VGA_L1N APU_VGA_TXN1
APU_VGA_TXN1 7
ML_VGA_L2P R32 APU_VGA_TXP2 UH1
AG21 R30 APU_VGA_TXP2 7
APU_VGA_TXN2
VGA MAINLINK
SATA_X2 ML_VGA_L2N
APU_VGA_TXN2 7 SPI_CS1#_8MB 1 8
ML_VGA_L3P P29 APU_VGA_TXP3 CS# VCC
APU_VGA_TXP3 7
ML_VGA_L3N P28 APU_VGA_TXN3 SPI_SI_8MB 2 7 SPI_HOLD#_8MB
APU_VGA_TXN3 7 DO HOLD# SPI_HOLD#_8MB 14
ML_VGA_HPD/GPIO229 C29 FCH_CRT_HPD SPI_WP# 3 6 SPI_CLK_8MB
WP# CLK 2
AH16 FANOUT0/GPIO52 VIN0/GPIO175 N2 GPIO175 4 5 SPI_SO_8MB CH21
AM15 FANOUT1/GPIO53 VIN1/GPIO176 M3 GPIO176 Need to enable internal GND DI 0.1U_0402_10V7-K
AJ16 FANOUT2/GPIO54 VIN2/SDATI_1/GPIO177 L2 GPIO177 TPH43 1 Test_Point_12MIL pull down to leave 1
HW MONITOR VIN3/SDATO_1/GPIO178 N4 GPIO178 TPH44 1 Test_Point_12MIL unconnected W25Q64FVSSIG_SO8
32 ODD_EN AK15 P1 1
FANIN0/GPIO56 VIN4/SLOAD_1/GPIO179 GPIO179 TPH45 Test_Point_12MIL SA000039A2J
C
AN16 FANIN1/GPIO57 VIN5/SCLK_1/GPIO180 P3 GPIO180 TPH46 1 Test_Point_12MIL GPIO177~181 need bios C
AL16 FANIN2/GPIO58 VIN6/GBE_STAT3/GPIO181 M1 GPIO181 TPH47 1 Test_Point_12MIL Pull down internally
ODD_EN VIN7/GBE_LED3/GPIO182 M5 GPIO182
RPH3 K6 TEMPIN0/GPIO171 NC1 AG16 RPH2

1 8 GPIO172 K5 TEMPIN1/GPIO172 NC2 AH10 1 8
2 7 GPIO173 K3 TEMPIN2/GPIO173 NC3 A28 GPIO175 2 7
3 6 GPIO174 M6 TEMPIN3/TALERT#/GPIO174 NC4 G27 GPIO176 3 6
4 5 NC5 L4 GPIO182 4 5
10K_0804_8P4R_5% 10K_0804_8P4R_5%
218084401A1BOLTONM3_FCBGA656
To APU_VGA_HPD
Modify level shift on 2013 1001

+3VALW
+3VS
+3V_SPI
RPH6
SPI_WP# 1 8
2
2 7
2
SPI_HOLD#_8MB 3 6 RH122
SPI_CS1#_8MB 4 5 10K_0402_5% RH120
10K_0402_5%
2
10K_0804_8P4R_5%
G
1
1
FCH_CRT_HPD 1 3 APU_VGA_HPD
APU_VGA_HPD 7
S
2N7002KW_SOT323-3
QH4
D D
RH121 1 @ 2 0_0402_5%
Issued Date 2012/07/01 Deciphered Date 2014/07/01 FCH SATA/GBE/SPI

1 2 3 4 5
1 2 3 4 5
+3VS
RH53 1 2 10K_0402_5% WD_PWRGD
RPC14
1 8 FCH_SMB0CLK
delete EC_LID_OUT# from UE1.Pin21 and UH2.R2 ,add GPU_WAKE#_R on UH2.R2
GPU, EC, Thermal Sensor
2 7 FCH_SMB0DATA UH2D +3VS
+3VALW 3 6 FCH_SMB1CLK With S5 plus,PBTN_OUT# pull Up /Without S5 plus,PBTN_OUT# pull low
4 5 FCH_SMB1DATA AB6 PCIE_RST2#/GEVENT4# USBCLK/14M_25M_48M_OSC G8
GPU_WAKE# R2 RI#/GEVENT22# 2N7002KDWH
2
18 GPU_WAKE#
USB MISC
2.2K_0804_5% W7 B9 USB_RCOMP RH45 1 2 11.8K_0402_5%
G
SD30922018J PM_SLP_S3# 1 RH102 2 0_0402_5% PM_SLP_S3#_R T3
SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
Vth= min 1V, max 2.5V
A SLP_S3# A
38 PM_SLP_S3# PM_SLP_S5# 1 RH143 2 0_0402_5% PM_SLP_S5#_R W2 SLP_S5# USB_FSD1P/GPIO186 H1 ESD 2KV
38 PM_SLP_S5# PBTN_OUT# J4 H3
PWR_BTN# USB_FSD1N
38 PBTN_OUT# FCH_SMB1CLK 6 1 EC_SMB_CK3
FCH_PWROK 1 RH145 2 FCH_PWROK_R N7 BOLTON-M3
USB 1.1
S
38 FCH_PWROK PWR_GOOD EC_SMB_CK3 7,18,37,38
D
0_0402_5% USB_FSD0P/GPIO185 H6
5
1 TPH3 TEST0 T9 Part 4 of 5 H5 QH1A
G
@ Test_Point_12MIL TEST0 USB_FSD0N
RH38 1 2 10K_0402_5% WD_PWRGD 1 TPH4 TEST1 T10 2N7002KDWH_SOT363-6
Test_Point_12MIL TEST1/TMS
1 TPH5 TEST2 V9 H10 SB00000EO1J
Test_Point_12MIL TEST2 USB_HSD13P
RH87 2 1 10K_0402_5% GATEA20 AE22 GA20IN/GEVENT0# USB_HSD13N G10
ACPI / WAKE UP EVENTS

PBTN_OUT# 38 GATEA20 FCH_SMB1DATA 3 4 EC_SMB_DA3
KBRST# AG19
S
38 KBRST# KBRST#/GEVENT1# EC_SMB_DA3 7,18,37,38
D
RH37 1 @ 2 10K_0402_5% EC_WAKE# EC_SCI# R9 PME#/GEVENT3# USB_HSD12P K10
38 EC_SCI# QH1B
C26 LPC_SMI#/GEVENT23# USB_HSD12N J12
delete net name EC_SMI# on UH2.C26 on 20130928 T5 2N7002KDWH_SOT363-6
LPC_PD#/GEVENT5#
Change net name from PCIE_WAKE# to EC_WAKE# on 20130928 U4 SYS_RESET#/GEVENT19# USB_HSD11P G12 SB00000EO1J
EC_WAKE# K1 WAKE#/GEVENT8# USB_HSD11N F12
18,38 EC_WAKE#
V7 IR_RX1/GEVENT20#
RH98 2 @ 1 10K_0402_5% ODD_DA#_FCH H_THERMTRIP# R10 THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD10P K12 USB20_P12
7,18 H_THERMTRIP# USB20_P12 31
31 JUSB2(Left)
WD_PWRGD AF19 WD_PWRGD USB_HSD10N K13 USB20_N12
USB20_N12
RH100 1 2 10K_0402_5% AC_PRESENT
EC_RSMRST# U2 RSMRST# USB_HSD9P B11
38 EC_RSMRST#
RPH1 USB_HSD9N D11
1 8 FCH_SMB2CLK AG24 CLK_REQ4#/SATA_IS0#/GPIO64
2 7 FCH_SMB2DATA AE24 CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD8P E10
3 6 USB_OC1# Reserve CH9 and unmounted on 20130927 AE26 SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD8N F10
4 5 USB_OC0# LAN_CLKREQ# AF22 CLK_REQ0#/SATA_IS3#/GPIO60
35 LAN_CLKREQ#
AH17 SATA_IS4#/FANOUT3/GPIO55 USB_HSD7P C10
AG18 SATA_IS5#/FANIN3/GPIO59 USB_HSD7N A10
10K_0804_8P4R_5%
34 FCH_SPKR FCH_SPKR AF24 SPKR/GPIO66
USB 2.0
FCH_SMB0CLK AD26 SCL0/GPIO43 USB_HSD6P H9 USB20_P6
USB20_P6 33
FCH_SMB0DATA AD25 SDA0/GPIO47 USB_HSD6N G9 USB20_N6
USB20_N6 33 WLAN
RH68 1 @ 2 10K_0402_5% HDA_SDIN0 FCH_SMB1CLK T7 SCL1/GPIO227
RH67 1 @ 2 10K_0402_5% HDA_BITCLK_AUDIO FCH_SMB1DATA R7 SDA1/GPIO228 USB_HSD5P A8 USB20_P5
USB20_P5 27
RH105 1 @ 2 10K_0402_5% AZ_SDIN1 33 CLKREQ_WLAN#
CLKREQ_WLAN# AG25 CLK_REQ2#/FANIN4/GPIO62 USB_HSD5N C8 USB20_N5
USB20_N5 27 Camera
RH106 1 @ 2 10K_0402_5% AZ_SDIN2 AG22 CLK_REQ1#/FANOUT4/GPIO61
GPIO
RH107 1 @ 2 10K_0402_5% AZ_SDIN3 J2 F8 USB20_P8
B delete BATT_LEN# on UH1.J2 1 TPH27 AG26
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
USB_HSD4P
USB_HSD4N E8 USB20_N8
USB20_P8 27
Touch Screen(Reserved) B
Test_Point_12MIL USB20_N8 27
V8 DDR3_RST#/GEVENT7#/VGA_PD
W8 GBE_LED0/GPIO183 USB_HSD3P C6 USB20_P11
USB20_P11 31
31 JUSB1(Left)
RH77 1 2 0_0402_5% SPI_HOLD# Y6 SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD3N A6 USB20_N11
13 SPI_HOLD#_8MB USB20_N11
V10 GBE_LED2/GEVENT10#
AA8 GBE_STAT0/GEVENT11# USB_HSD2P C5 USB20_P4
USB20_P4 30
17 GPU_CLKREQ
GPU_CLKREQ AF25 CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD2N A5 USB20_N4
USB20_N4 30 Card Reader
C1
Change DGPU_PWROK_R from UH2.AG26 to UH2.AH14 M7 BLINK/USB_OC7#/GEVENT18#
USB_HSD1P
USB_HSD1N C3
ODD_DA#_FCH R8 USB_OC6#/IR_TX1/GEVENT6#
32 ODD_DA#_FCH
T1 USB_OC5#/IR_TX0/GEVENT17# USB_HSD0P E1 USB20_P10
USB20_P10 30
ODD_DETECT# P6 E3 USB20_N10
32 ODD_DETECT# USB_OC4#/IR_RX0/GEVENT16# USB_HSD0N
USB20_N10 30 USB/B (Right)
AC_PRESENT F5 USB_OC3#/AC_PRES/TDO/GEVENT15#
38 AC_PRESENT
USB OC
P5 USB_OC2#/TCK/GEVENT14# USBSS_CALRP C16 USBSS_CALRP RH46 1 2 1K_0402_1% +VDDAN_11_SSUSB_S
USB_OC1# J7 USB_OC1#/TDI/GEVENT13# USBSS_CALRN A16 USBSS_CALRN RH47 1 2 1K_0402_1%
31 USB_OC1#
USB_OC0# T8 USB_OC0#/GEVENT12#/TRST
RPH5 30 USB_OC0#
USB_SS_TX3P A14
34 HDA_BITCLK_AUDIO HDA_BITCLK_AUDIO 1 8 AZ_BITCLK
USB_SS_TX3N C14
34 HDA_SDOUT_AUDIO HDA_SDOUT_AUDIO 2 7 AZ_SDOUT
34 HDA_SYNC_AUDIO HDA_SYNC_AUDIO 3 6 AZ_SYNC
AZ_BITCLK AB3 AZ_BITCLK USB_SS_RX3P C12
34 HDA_RST_AUDIO# HDA_RST_AUDIO# 4 5 AZ_RST#
AZ_SDOUT AB1 AZ_SDOUT USB_SS_RX3N A12
HDA_SDIN0 AA2 AZ_SDIN0/GPIO167
33_0804_8P4R_5% 34 HDA_SDIN0
AZ_SDIN1 Y5 AZ_SDIN1/GPIO168 USB_SS_TX2P D15
SD300003700
AZ_SDIN2 Y3 AZ_SDIN2/GPIO169 USB_SS_TX2N B15
AZ_SDIN3 Y1 AZ_SDIN3/GPIO170
AZ_SYNC AD6 E14
HD AUDIO
AZ_SYNC USB_SS_RX2P
AZ_RST# AE4 AZ_RST# USB_SS_RX2N F14
USB 3.0
USB_SS_TX1P F15
Test_Point_12MIL 1 TPH6 K19 PS2_DAT/SDA4/GPIO187 USB_SS_TX1N G15
Test_Point_12MIL 1 TPH7 J19 PS2_CLK/CEC/SCL4/GPIO188
J21 SPI_CS2#/GBE_STAT2/GPIO166 USB_SS_RX1P H13
USB_SS_RX1N G13
C C
Test_Point_12MIL 1TPH30 D21 PS2KB_DAT/GPIO189 USB_SS_TX0P J16 USB30_TX_P1
USB30_TX_P1 31
Test_Point_12MIL 1TPH31 C20 PS2KB_CLK/GPIO190 USB_SS_TX0N H16 USB30_TX_N1
USB30_TX_N1 31
Test_Point_12MIL 1TPH26 D23 PS2M_DAT/GPIO191 JUSB2(Left)
Test_Point_12MIL 1TPH28 C22 PS2M_CLK/GPIO192 USB_SS_RX0P J15 USB30_RX_P1
USB30_RX_P1 31
USB_SS_RX0N K15 USB30_RX_N1
USB30_RX_N1 31
Test_Point_12MIL 1 TPH8 F21 KSO_0/GPIO209
Test_Point_12MIL 1 TPH9 E20 KSO_1/GPIO210 H19
SCL2/GPIO193 FCH_SMB2CLK
Test_Point_12MIL 1 TPH10 F20 KSO_2/GPIO211 G19
SDA2/GPIO194 FCH_SMB2DATA
Test_Point_12MIL 1 TPH11 A22 KSO_3/GPIO212 G22
SCL3_LV/GPIO195 EC_SMBLV_CK
EC_SMBLV_CK 7
Test_Point_12MIL 1 TPH12 E18 KSO_4/GPIO213 SDA3_LV/GPIO196 G21 EC_SMBLV_DA
EC_SMBLV_DA 7
Test_Point_12MIL 1 TPH13 A20 KSO_5/GPIO214 EC_PWM0/EC_TIMER0/GPIO197 E22 TPH29 1
Test_Point_12MIL
Test_Point_12MIL 1 TPH14 J18 KSO_6/GPIO215 EMBEDDED CTRL EC_PWM1/EC_TIMER1/GPIO198 H22 APU SIC/SIV
Test_Point_12MIL 1 TPH15 H18 KSO_7/GPIO216 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199J22 EC_PWM2
EC_PWM2 16
Test_Point_12MIL 1 TPH16 G18 KSO_8/GPIO217 EC_PWM3/EC_TIMER3/GPIO200 H21
Test_Point_12MIL 1 TPH17 B21 KSO_9/GPIO218
2
Test_Point_12MIL 1 TPH18 K18 KSO_10/GPIO219 KSI_0/GPIO201 K21
Test_Point_12MIL 1 TPH19 D19 K22 RH39 RH40
KSO_11/GPIO220 KSI_1/GPIO202
Test_Point_12MIL 1 TPH20 A18 KSO_12/GPIO221 KSI_2/GPIO203 F22 10K_0402_5% 10K_0402_5%
Test_Point_12MIL 1 TPH21 C18 KSO_13/GPIO222 KSI_3/GPIO204 F24
Test_Point_12MIL 1 TPH22 B19 KSO_14/XDB0/GPIO223 KSI_4/GPIO205 E24
1
Test_Point_12MIL 1 TPH23 B17 KSO_15/XDB1/GPIO224 KSI_5/GPIO206 B23
Test_Point_12MIL 1 TPH24 A24 KSO_16/XDB2/GPIO225 KSI_6/GPIO207 C24
Test_Point_12MIL 1 TPH25 D17 KSO_17/XDB3/GPIO226 KSI_7/GPIO208 F18
Follow Edge to connect with 0 ohm directly on 20131009

RH153
FCH_SMB0CLK 1 2 0_0402_5% SMB0_CLK
SMB0_CLK 10,11,33
FCH_SMB0DATA 1 2 0_0402_5% SMB0_DATA
SMB0_DATA 10,11,33
D D
RH154

Delete Security EEPROM USROM3 ,unused
Issued Date 2012/07/01 Deciphered Date 2014/07/01 FCH ACPI/USB/GPIO
1 2 3 4 5
1 2 3 4 5
VDDPL_33_SATA & PCIE & SYS

+3VS
+VDDPL_33_SATA
22u *1, 1u*1 for circuit check list LH12

1 2
+3VS UH2C +VDDCR_11 +1.1VS BLM15BD221SN1D_2P 1
2.2U_0402_6.3V6-M
CH72
RH78 0_0603_5% BOLTON-M3 Part 3 of 5 RH61
1 2VDDIO_33_PCIGP 102mA AB17 VDDIO_33_PCIGP_1 VDDCR_11_1 T14 1007mA CH40 CH41 CH42 CH43 CH44 2 1
2
10U_0603_6.3V6-M
1U_0402_10V6-K
1U_0402_10V6-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
AB18 VDDIO_33_PCIGP_2 VDDCR_11_2 T17
+VDDPL_33_PCIE
22U_0603_6.3V6-M
A 1 1 1 1 AE9 VDDIO_33_PCIGP_3 VDDCR_11_3 T20 1 1 1 1 1 0_0805_5% A
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
AD10 VDDCR_11_4 U16
CH23
VDDIO_33_PCIGP_4
PCI/GPIO I/O
AG7 VDDCR_11_5 U18 LH13
CH24
CH25
CH26
VDDIO_33_PCIGP_5
AC13 VDDCR_11_6 V14 1 2
CORE S0
VDDIO_33_PCIGP_6
2 2 2 2 AB12 2 2 2 2 2
VDDIO_33_PCIGP_7 VDDCR_11_7 V17
AB13 VDDIO_33_PCIGP_8 VDDCR_11_8 V20 BLM15BD221SN1D_2P 1
2.2U_0402_6.3V6-M
AB14 VDDCR_11_9 Y17
+VDDAN_11_CLK +1.1VS
CH73
VDDIO_33_PCIGP_9
AB16 VDDIO_33_PCIGP_10
RH63
47mA H24 2
+VDDPL_33_SYS VDDPL_33_SYS VDDAN_11_CLK_1 H26 CH45 CH46 CH47 CH48 CH49 1 2
+VDDPL_33_SYS
1U_0402_10V6-K
1U_0402_10V6-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
22U_0603_6.3V6-M
RH57 1 2 0_0402_5% VDDPL_33_DAC V22 VDDPL_33_DAC VDDAN_11_CLK_2 J25
VDDPL_33_DACML
RH58 1 2 0_0402_5% VDDPL_33_ML 20mA U22 VDDPL_33_ML VDDAN_11_CLK_3 K24 1 1 1 1 1 0_0603_5%
12mA T22 VDDAN_11_CLK_4 L22 LH14
CLKGEN I/O
VDDAN_33_DAC_R VDDAN_33_DAC
+VDDPL_33_SSUSB_S L18 VDDPL_33_SSUSB_S VDDAN_11_CLK_5 M22 1 2

+VDDPL_33_USB_S D7 VDDPL_33_USB_S VDDAN_11_CLK_6 N21
AH29 2 2 2 2 2
+VDDPL_33_PCIE VDDPL_33_PCIE VDDAN_11_CLK_7 N22 BLM15BD221SN1D_2P 1 1
0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
AG28 VDDAN_11_CLK_8 P22
+VDDAN_11_PCIE +1.1VS
CH74
+VDDPL_33_SATA VDDPL_33_SATA
CH75
RH84
M31 2 2
LDO_CAP VDDAN_11_PCIE_1 AB24 CH50 CH51 CH52 2 1
+1.1VS
1U_0402_10V6-K
0.1U_0402_10V7-K
22U_0603_6.3V6-M
@ CH27 1 2 2.2U_0402_6.3V6-M VDDAN_11_PCIE_2 Y21
V21 VDDPL_11_DAC VDDAN_11_PCIE_3 AE25 1 1 1 0_0805_5%
LH17
VDDAN_11_PCIE_4 AD24
1 2 1 2
226mA Y22
RH149 VDDAN_11_ML_1 VDDAN_11_PCIE_5 AB23
BLM18BB470SN1D_2P~D V23 VDDAN_11_ML_2 VDDAN_11_PCIE_6 AA22
2 2 2
MAIN LINK
CH14
0.1U_0402_10V7-K
CH13
4.7U_0603_6.3V6-K
CH12
0.1U_0402_10V7-K
0_0603_5% 2 1 2 V24 VDDAN_11_ML_3 VDDAN_11_PCIE_7 AF26
V25 VDDAN_11_PCIE_8 AG27
+VDDAN_11_SATA +1.1VS
PCI EXPRESS
VDDAN_11_ML_4
VDDCR_1.1V_USB
RH89
VDDAN_11_ML 1 2 1 AB10 2 1
VDDIO_33_GBE_S VDDAN_11_SATA_1 AA21 CH53 CH54 CH55 CH56
1U_0402_10V6-K
1U_0402_10V6-K
0.1U_0402_10V7-K
22U_0603_6.3V6-M
VDDAN_11_SATA_4 Y20
VDDAN_11_SATA_2 AB21 0_0805_5% +1.1VALW +VDDCR_1.1V_USB
1 1 1 1
VDDAN_11_SATA_3 AB22
SERIAL ATA
AB11 VDDCR_11_GBE_S_1 VDDAN_11_SATA_5 AC22 LH15
AA11 VDDCR_11_GBE_S_2 VDDAN_11_SATA_6 AC21 1 2
B 2 2 2 2 B
GBE LAN
VDDAN_11_SATA_7 AA20
VDDAN_11_SATA_8 AA18 BLM15BD221SN1D_2P 1 1 1
10U_0603_6.3V6-M
0.1U_0402_10V7-K
0.1U_0402_10V7-K
AA9 VDDIO_GBE_S_1 VDDAN_11_SATA_9 AB20
AA10 VDDAN_11_SATA_10 AC19
CH78
CH76
CH77
VDDIO_GBE_S_2
2 2 2
+3VALW +VDDAN_33_USB_S +3VALW +3VALW

LH7
LH1 RH79 CH67 1 2
2.2U_0402_6.3V6-M
1 2 CH28 CH29 CH30 CH31 CH32 470mA G7 VDDAN_33_USB_S_1 VDDIO_33_S_1 N18 VDDIO_33_S CH57 CH58 CH59 1 2
10U_0603_6.3V6-M
10U_0603_6.3V6-M
1U_0402_10V6-K
1U_0402_10V6-K
0.1U_0402_25V7-K
2.2U_0402_6.3V6-M
1U_0402_10V6-K
1U_0402_10V6-K
H8 VDDAN_33_USB_S_2 VDDIO_33_S_2 L19 BLM15BD221SN1D_2P
BLM15BD221SN1D_2P J8 M18 0_0603_5%
1 1 1 1 1
K8
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDIO_33_S_3
VDDIO_33_S_4 V12
1 1 1 1 VDDAN_11_USB_S
K9 VDDAN_33_USB_S_5 VDDIO_33_S_5 V13
3.3V_S5 I/O
M9 VDDAN_33_USB_S_6 VDDIO_33_S_6 Y12
2 2 2 2 2 M10 VDDAN_33_USB_S_7 VDDIO_33_S_7 Y13 2 2 2 2
N9 VDDAN_33_USB_S_8 VDDIO_33_S_8 W11 +1.1VALW +VDDAN_11_USB_S
N10 VDDAN_33_USB_S_9 LH16
USB
M12 VDDAN_33_USB_S_10
+1.1VALW 1 2
N12 VDDAN_33_USB_S_11 VDDXL_33_S G24 VDDXL_33_S RH80 0_0603_5%
M11 VDDAN_33_USB_S_12 CH65 CH66 1 2 BLM15BD221SN1D_2P 1 1 1
0.1U_0402_10V7-K
0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
1U_0402_10V6-K
1U_0402_10V6-K
CH79
U12 VDDCR_11_S_1 N20
CH80
CH81
+VDDAN_11_USB_S VDDAN_11_USB_S_1 1 1
U13 VDDAN_11_USB_S_2 VDDCR_11_S_2 M20 VDDCR_11_S
2 2 2
+VDDCR_1.1V_USB T12 VDDCR_11_USB_S_1 VDDPL_11_SYS_S J24 VDDPL_11_SYS_S
T13 2 2
VDDCR_11_USB_S_2
+1.1VALW +VDDAN_11_SSUSB_S
LH2 VDDAN_33_HWM_S M8
1 2 CH33 CH34 CH35 P16 VDDAN_11_SSUSB_S_1
VDDAN_33_HWM +3VALW
+1.1VALW
0.1U_0402_10V7-K
0.1U_0402_10V7-K
1U_0402_10V6-K
M14 VDDAN_11_SSUSB_S_2 LH9

BLM18BB470SN1D_2P~D 1 1 1 N14 VDDAN_11_SSUSB_S_3 VDDIO_AZ_S AA4 CH60 CH61 1 2 LH8
2.2U_0402_6.3V6-M
0.1U_0402_10V7-K
P13 CH63 CH64 1 2
VDDAN_11_SSUSB_S_4
VDDPL_33_USB_S
0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
C P14 VDDAN_11_SSUSB_S_5 1 1 BLM15BD221SN1D_2P C
1
BLM15BD221SN1D_2P
USB SS
2 2 2 1 1
RH62 N16 VDDCR_11_SSUSB_S_1
0_0402_5% N17 VDDCR_11_SSUSB_S_2
P17 2 2 +VDDAN_33_USB_S +VDDPL_33_USB_S
VDDCR_11_SSUSB_S_3
M17 2 2
VDDCR_11_SSUSB_S_4
2
LH10
1 2
+1.1VALW +VDDCR_11_SSUSB_S
LH3 BLM15BD221SN1D_2P 1 1
1U_0402_10V6-K
2.2U_0402_6.3V6-M
1 2 CH36 CH37 CH38 CH39 +3VS
CH68
POWER
0.1U_0402_10V7-K
1U_0402_10V6-K
10U_0603_6.3V6-M
0.1U_0402_10V7-K
CH69
BLM18BB470SN1D_2P~D RH81
VDDIO_AZ_S CH62 1 2 2 2
1 1 1 1
2.2U_0402_6.3V6-M
@
218084401A1BOLTONM3_FCBGA656 0_0402_5%
1 +1.5VS
2 2 2 2
@ RH101
1 2
2
0_0402_5% VDDPL_33_SSUSB_S
+3VS VDDAN_33_DAC_R VDDPL_33_DACML
+3VALW +VDDPL_33_SSUSB_S
LH18 RH152
1 2 1 2 LH11
Add RH101 to reserve power rail +1.5VS 1 2
0.1U_0402_10V7-K
0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
2.2U_0402_6.3V6-M
BLM18PG221SN1D_2P 1 1 0_0603_5% 1 1
BLM15BD221SN1D_2P
CH86
CH84
1 1
0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
CH70
CH85
CH83
CH71
2 2 2 2
2 2
D +3VALW +VDDAN_33_HWM,+VDDAN_33_USB_S,VDDPL_33_SSUSB_S,+VDDPL_33_USB_S D
+3VS +VDDPL_33_SATA,+VDDPL_33_PCIE,+VDDPL_33_SYS
+1.1VALW +VDDCR_11_SSUSB_S,+VDDAN_11_SSUSB_S,+VDDAN_11_USB_S,
+VDDAN_11_USB_S,+VDDCR_1.1V_USB Security Classification LC Future Center Secret Data Title
Issued Date 2012/07/01 Deciphered Date 2014/07/01 FCH POWER/GND
+1.1VS +VDDCR_11,+VDDAN_11_CLK,+VDDAN_11_PCIE,+VDDAN_11_SATA,
1 2 3 4 5
1 2 3 4 5
STRAP PINS DEBUG STRAPS

UH2E FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
BOLTON-M3
A3 VSS_1
Part 5 of 5
VSS_66 T25 PCI_CLK1 PCI_CLK3 PCI_CLK4 CLK_PCI_EC LPC_CLK1 EC_PWM2 RTC_CLK PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
A33 VSS_2 VSS_67 T27
B7 VSS_3 VSS_68 U6
B13 VSS_4 VSS_69 U14 PULL ALLOW USE NON_FUSION EC CLKGEN LPC ROM S5 PLUS USE PCI DISABLE USE FC USE DEFAULT DISABLE PCI
A D9 U17 PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED MODE PULL PLL ILA PLL PCIE STRAPS MEM BOOT A
D13
VSS_5 VSS_70
U20
HIGH
E5
VSS_6 VSS_71
U21
STRAPS DISABLED HIGH AUTORUN
VSS_7 VSS_72
E12 VSS_8 VSS_73 U30 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
E16 VSS_9 VSS_74 U32
E29 VSS_10 VSS_75 V11
F7 VSS_11 VSS_76 V16 PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS PULL BYPASS ENABLE BYPASS USE EEPROM ENABLE PCI
F9 V18 PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE PCI PLL ILA FC PLL PCIE STRAPS MEM BOOT
F11
VSS_12 VSS_77
W4
LOW LOW
F13
VSS_13 VSS_78
W6
STRAP MODE ENABLED AUTORUN
VSS_14 VSS_79
F16 VSS_15 VSS_80 W25 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
F17 VSS_16 VSS_81 W28
F19 VSS_17 VSS_82 Y14
F23 VSS_18 VSS_83 Y16 need confirm AD26
F25 VSS_19 VSS_84 Y18
F29 VSS_20 VSS_85 AA6
G6 VSS_21 VSS_86 AA12
H12 VSS_24 VSS_89 AA16
J6 VSS_27 VSS_92 AA28
J9 VSS_28 VSS_93 AA30 +3VALW +3VALW +3VALW
+3VS +3VS +3VS +3VALW 12 PCI_AD27
J10 AA32
GROUND
VSS_29 VSS_94
J13 VSS_30 VSS_95 AB25
12 PCI_AD26
RH128
RH132
RH134
RH136
RH133
RH138
RH135
J28 VSS_31 VSS_96 AC6
J32 VSS_32 VSS_97 AC18
12 PCI_AD25
1
K7 VSS_33 VSS_98 AC28
K16 VSS_34 VSS_99 AD27
@ 12 PCI_AD24
K27 VSS_35 VSS_100 AE6 @ @ @ @
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
K28 VSS_36 VSS_101 AE15
12 PCI_AD23
L6 VSS_37 VSS_102 AE21
2
L12 VSS_38 VSS_103 AE28
RH127
RH126
RH125
RH124
RH123
L13 VSS_39 VSS_104 AF8
B B
L15 VSS_40 VSS_105 AF12
12 PCICLK1
1
1
1
L16 VSS_41 VSS_106 AF16
L21 VSS_42 VSS_107 AF33
12 PCICLK3
M13 VSS_43 VSS_108 AG30 @ @ @ @ @
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
M16 VSS_44 VSS_109 AG32
12 PCICLK4
M21 VSS_45 VSS_110 AH5
2
2
2
M25 VSS_46 VSS_111 AH11
12,38 CLK_PCI_EC
N6 VSS_47 VSS_112 AH18
N11 VSS_48 VSS_113 AH19
12 LPC_CLK1
N13 VSS_49 VSS_114 AH21
N23 VSS_50 VSS_115 AH23
14 EC_PWM2
N24 VSS_51 VSS_116 AH25
P12 VSS_52 VSS_117 AH27
12 RTC_CLK
P18 VSS_53 VSS_118 AJ18
RH140
RH137
RH139
RH141
RH142
R156
RH144
P20 VSS_54 VSS_119 AJ28
P21 VSS_55 VSS_120 AJ29
1
P31 VSS_56 VSS_121 AK21
P33 VSS_57 VSS_122 AK25
R4 VSS_58 VSS_123 AL18 @ @
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
R6 VSS_59 VSS_124 AM21
R11 VSS_60 VSS_125 AM25
2
R25 VSS_61 VSS_126 AN1
R28 VSS_62 VSS_127 AN18
T11 VSS_63 VSS_128 AN28
T16 VSS_64 VSS_129 AN33
T18 VSS_65
VSSPL_DAC T21
N8 VSSAN_HWM VSSAN_DAC L28
VSSANQ_DAC K33
K25 VSSXL VSSIO_DAC N28
H25 VSSPL_SYS
C C
D D

Issued Date 2012/07/01 Deciphered Date 2014/07/01 FCH GND
1 2 3 4 5
1 2 3 4 5
UV3G
PCIE_CTX_C_GRX_N[0..7]
5 PCIE_CTX_C_GRX_N[0..7]
PCIE_CTX_C_GRX_P[0..7]
5 PCIE_CTX_C_GRX_P[0..7]
PCIE_CRX_GTX_N[0..7]
5 PCIE_CRX_GTX_N[0..7]
PCIE_CRX_GTX_P[0..7] PCIE_CTX_C_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0
5 PCIE_CRX_GTX_P[0..7] PCIE_RX0P PCIE_TX0P
PCIE_CTX_C_GRX_N0 AE31 AG31 PCIE_CRX_C_GTX_N0
PCIE_RX0N PCIE_TX0N
A A
PCIE_CTX_C_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1

PCIE_CTX_C_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PCIE_CRX_C_GTX_N1
PCIE_RX1N PCIE_TX1N
PCIE_CTX_C_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2

PCIE_CTX_C_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_CRX_C_GTX_N2
PCIE_RX2N PCIE_TX2N
DIS@
PCIE_CRX_GTX_P0 CV132 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CRX_C_GTX_P0 PCIE_CTX_C_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3
PCIE_CRX_GTX_N0 CV133 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CRX_C_GTX_N0 PCIE_CTX_C_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_CRX_C_GTX_N3
PCIE_CRX_GTX_P1 CV134 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CRX_C_GTX_P1 PCIE_RX3N PCIE_TX3N
PCIE_CRX_GTX_N1 CV135 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CRX_C_GTX_N1
PCIE_CRX_GTX_P2 CV136 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CRX_C_GTX_P2 PCIE_CTX_C_GRX_P4 AB30 AC25 PCIE_CRX_C_GTX_P4
PCIE_CRX_GTX_N2 CV137 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CRX_C_GTX_N2 PCIE_CTX_C_GRX_N4 AA31 PCIE_RX4P PCIE_TX4P AB25 PCIE_CRX_C_GTX_N4
PCIE_CTX_C_GRX_P5 AA29 Y23 PCIE_CRX_C_GTX_P5
PCIE_CTX_C_GRX_N5 Y28 PCIE_RX5P PCIE_TX5P Y24 PCIE_CRX_C_GTX_N5
PCIE_CRX_GTX_P5 CV159 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CRX_C_GTX_P5 PCIE_CTX_C_GRX_P6 Y30 AB27 PCIE_CRX_C_GTX_P6
PCIE_CRX_GTX_N5 CV175 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CRX_C_GTX_N5 PCIE_CTX_C_GRX_N6 W31 PCIE_RX6P PCIE_TX6P AB26 PCIE_CRX_C_GTX_N6
PCIE_CRX_GTX_P7 CV178 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CRX_C_GTX_P7 PCIE_CTX_C_GRX_P7 W29 Y27 PCIE_CRX_C_GTX_P7
PCIE_CRX_GTX_N7 CV179 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CRX_C_GTX_N7 PCIE_CTX_C_GRX_N7 V28 PCIE_RX7P PCIE_TX7P Y26 PCIE_CRX_C_GTX_N7
PCIE_RX7N PCIE_TX7N
+3VS_VGA
V30 W24
U31 NC_121 NC_137 W23
NC_122 NC_138
1
+3VS U29 V27 RV50
B +3VS_VGA T28 NC_123 NC_139 U26 10K_0402_5% B
NC_124 NC_140 @
2
PCI EXPRESS INTERFACE
T30 U24 RV49 @
RV42 @ R31 NC_125 NC_141 U23 2 1
NC_126 NC_142 12,24,51 DGPU_PWREN
1
1 2
CV140
0.1U_0402_10V7-K
RV43 10K_0402_5%
0_0402_5% 10K_0402_5% R29 T26 +3VS_VGA
NC_127 NC_143 1
5
UV4 @ P28 T27

NC_128 NC_144
VCC
1
@
@
PLT_RST# 1
12,33,35 PLT_RST# IN1 2
4 PLT_RST_VGA# P30 T24 RV52
OUT PLT_RST_VGA# 18,51 NC_129 NC_145
DGPU_HOLD_RST# 2 N31 T23 10K_0402_5%
GND
12 DGPU_HOLD_RST# IN2 NC_130 NC_146 QV7

2
2
@
2
MC74VHC1G08DFT2G_SC70-5 N29 P27
RV44
3
DIS@ 100K_0402_5% M28 NC_131 NC_147 P26 1 3 CLK_REQ_GPU#

NC_132 NC_148 14 GPU_CLKREQ CLK_REQ_GPU# 18
CV141
0.1U_0402_10V7-K
DIS@
S
1
1
2
M30 P24 2N7002KW_SOT323-3
L31 NC_133 NC_149 P23 SB00000YY00 RV53
NC_134 NC_150
@
10K_0402_5%
2 1 @ 2 @
L29 M27
1
K30 NC_135 NC_151 N26 RV51 0_0402_5%
NC_136 NC_152
CLOCK
GFX_CLKP AK30
12 GFX_CLKP PCIE_REFCLKP
GFX_CLKN AK32 +0.95VS_VGA
12 GFX_CLKN PCIE_REFCLKN
CALIBRATION
C Y22 RV47 1 DIS@ 2 1.69K_0402_1% C

PCIE_CALR_TX
RV40 1 DIS@ 2 1K_0402_5% N10 AA22 RV48 1 DIS@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
PLT_RST_VGA# RV41 1 DIS@ 2 0_0402_5% AL27

PERSTB
216-0858020-A0_FCBGA631
D D

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet PCIE
1 2 3 4 5
5 4 3 2 1
RV110 1 DIS@ 2
H_THERMTRIP# 7,14
UV3A 0_0402_5%
RV87 DIS@
RV86
1
C
GPIO19_CTF 1 DIS@ 2 47K_0402_5% 1 2 2 QV3
B MMST3904-7-F_SOT323-3
0.1U_0402_25V6-K
Test_Point_20MIL 1 TPV17 N9 AF2 2.2K_0402_5% E DIS@
3
2
CV148
Test_Point_20MIL 1 TPV18 L9 NC_DBG_DATA16 NC_13 AF4 DV1 1
Test_Point_20MIL 1 TPV19 AE9 NC_DBG_DATA15 NC_14 PLT_RST_VGA# 1 2 RV88
Test_Point_20MIL 1 TPV20 Y11 NC_DBG_DATA14 AG3 100K_0402_5%
Test_Point_20MIL 1 TPV21 AE8 NC_DBG_DATA13 NC_15 AG5 RB751V-40_SOD323-2 DIS@ 2
DIS@
Test_Point_20MIL 1 TPV22 AD9 NC_DBG_DATA12 NC_16 SCS00006S00
1
DBG_DATA11 NC_DPA DIS@
Test_Point_20MIL 1 TPV23 AC10 AH3
Test_Point_20MIL 1 TPV24 AD7 DBG_DATA10 NC_17 AH1
Test_Point_20MIL 1 TPV25 AC8 DBG_DATA9 NC_18
D +1.8VS_VGA +1.8VS_VGA Test_Point_20MIL 1 TPV26 AC7 DBG_DATA8 AK3 D
Test_Point_20MIL 1 TPV27 AB9 DBG_DATA7 NC_19 AK1
Test_Point_20MIL 1 TPV28 AB8 DBG_DATA6 NC_20
Test_Point_20MIL 1 TPV29 AB7 DBG_DATA5 DBG AK5 RV133 @
1 2 0_0201_5%
1
+3VS_VGA Test_Point_20MIL 1 TPV30 DBG_DATA4 NC_21 GPIO15_L SVI2_SVD_L
AB4 AM3
RV54 RV55 Test_Point_20MIL 1 TPV31 AB2 DBG_DATA3 NC_22 RV134 @
4.7K_0402_5% 4.7K_0402_5% Test_Point_20MIL 1 TPV32 DBG_DATA2 GPIO20_L 1 2 0_0201_5% SVI2_SVC_L
Y8 AK6
TOPAZ@ TOPAZ@ Test_Point_20MIL 1 TPV33 Y7 DBG_DATA1 NC_23 AM5
Test_Point_20MIL 1 TPV34 DBG_DATA0 NC_24 +1.8VS_VGA
AL9 Reserve RV133 RV134 if UV9 bypass not used on 20131205
2
NC_DBG_CNTL0 NC_DPB
AJ7
2
NC_25 +3VS_VGA
Test_Point_20MIL 1 TPV1 U1 AH6
RV128 Test_Point_20MIL 1 TPV2 U3 BP_0 NC_26
BP_1 +3VS_VGA
0_0402_5% AK8
CV150
0.1U_0402_10V7-K
Test_Point_20MIL 1 TPV35 AM26 NC_27 AL7
DIECRACKMON NC_28 1
CV149
0.1U_0402_10V7-K
@ W6
JET@
RV56 1 2 V6 NC_2 1
PLT_RST_VGA# 17,51 NC_3 2
V4
1
1
0_0402_5% AC6 NC_29 U5
JET@
+3VS_VGA NC_4 NC_30 RV91 RV92
AC5 2
2
RV57 @ NC_5 10K_0402_5% 10K_0402_5% UV9 JET@

G
QV2A 1 2 100K_0402_5% @ JET@

AA5 V2
SB00000EO1J AA6 NC_6 NC_31
2
2
NC_7 NC_DPC 1 8
Y4 VCC(A) VCC(B)
SMBCLK 1 6 NC_32 W5
S
EC_SMB_CK3 7,14,37,38 NC_33 GPIO15 RV89 1 JET@ 2 33_0402_5% GPIO15_L 2 7 SVI2_SVD_L RV96 1 JET@ 2 33_0402_5% SVI2_SVD
D
1A 1B
2N7002KDWH_SOT363-6
GPIO20 RV90 1 JET@ 2 33_0402_5% GPIO20_L 3 6 SVI2_SVC_L RV97 1 JET@ 2 33_0402_5% SVI2_SVC
Y2 2A 2B
NC_34
5 4
Y6 J8 DIR GND
1
+3VS_VGA NC_8 NC_35
RV58 @ RV93 RV94
5
1 2 100K_0402_5% 10K_0402_5% 10K_0402_5% 74AVCH2T45GD_XSON8_3X2

G
QV2B JET@ @
SB00000EO1J +3VS_VGA
RV95
2
SMBDAT 4 3 I2C 1 2
S
EC_SMB_DA3 7,14,37,38
D
R1
CV151
0.1U_0402_10V7-K
10U_0603_6.3V6-M
2N7002KDWH_SOT363-6 SCL 10K_0402_5%
R3 AL25
CV152
SDA NC_G 1 1 JET@
Pull high 2.2K to +3VS at EC SIDE
+3VS_VGA RV72 1 DIS@ 2 45.3K_0402_1% +1.8VS_VGA
+3VS_VGA AK26
JET@
C RV73 1 DIS@ 2 45.3K_0402_1% GENERAL PURPOSE I/O
NC_AVSSN_1 C
U6 VID CODES 2 2
JET@
GPIO_0 AJ25
NC_AVSSN_2 AH24
RV111 1 DIS@ 2 10K_0402_5% NC_B SVC SVD
SMBDAT U8
SMBDATA (GPIO20) (GPIO15) Boot Voltage
DV2 SMBCLK U7
SMBCLK
2
38 VGA_AC_BATT
VGA_AC_BATT 1 2 GPIO5_AC_BATT
GPIO6
GPIO5_AC_BATT T9
T8 GPIO_5_AC_BATT NC_AVSSN_3
AG25
0 0 1.1V RV121 RV125
T7 GPIO_6_TACH NC_DAC1 AH26
RB751V-40_SOD323-2
SCS00006S00 Test_Point_20MIL 1 TPV3 GPIO8_ROMSO P10 NC_GPIO_7 NC_HSYNC 0 1 1.0V 10K_0402_5%
@
10K_0402_5%
DIS@
1 TPV4 P4 GPIO_8_ROMSO
DIS@ Test_Point_20MIL GPIO9_ROMSI
GPIO_9_ROMSI 1 0 0.9V(Default)
1
Test_Point_20MIL 1 TPV5 GPIO10_ROMSCK P2
N6 GPIO_10_ROMSCK AD22
RV130 1 @ 2 0_0402_5% N5 NC_GPIO_11 NC_RSET 1 1 0.8V SVI2_SVD
N3 NC_GPIO_12 AG24
NC_GPIO_13 NC_AVDD AE22
GPIO15 N1 NC_AVSSQ
RV132 1 @ 2 0_0402_5% SVI2_SVC
M4 GPIO_15_PWRCNTL_0 AE23
TPV12 GPIO_16 NC_VDD1DI
Test_Point_20MIL 1 R6 AD23
Add net name GPU_VR_HOT for GPIO5 & GPIO6 of GPU and RV130,R131 on 1002 RV124 GPIO_17_THERMAL_INT NC_VSS1DI
2
+3VS_VGA 2 1 GPIO19_CTF M2 RV122 RV126
GPIO20 P8 GPIO_19_CTF AM12 10K_0402_5% 10K_0402_5%
P7 GPIO_20_PWRCNTL_1 NC_CEC_1
10K_0402_5% @
Test_Point_20MIL 1 TPV6 GPIO22_ROMCSB N8 GPIO_21 DIS@
@ GPIO_22_ROMCSB
1
AK10 AK12 RV107 1 TOPAZ@2 0_0402_5% SVI2_SVD
1
GPIO_29 GPIO_SVD SVI2_SVD 51

AM10 AL11 RV108 1 TOPAZ@2 0_0402_5% SVI2_SVT
RV61 RV112 1 @ 2 0_0402_5% GPIO_30 GPIO_SVT SVI2_SVT 51
17 CLK_REQ_GPU# N7 AJ11 RV109 1 TOPAZ@2 0_0402_5% SVI2_SVC
10K_0402_5% RV75 1 @ 2 100_0402_5% CLKREQB GPIO_SVC SVI2_SVC 51
TOPAZ@ Test_Point_20MIL 1 TPV7 JTAG_TRSTB +3VS_VGA
L6
Test_Point_20MIL 1 TPV8 JTAG_TDI L5 JTAG_TRSTB
2
@ RV62 TOPAZ@ Test_Point_20MIL 1 TPV9 JTAG_TDI

JTAG_TCK L3
GPU_VR_HOT# RV131 1 2 0_0402_5% 1 2 GPIO6 Test_Point_20MIL 1 TPV10 JTAG_TCK
38,51 GPU_VR_HOT# JTAG_TMS L1 AL13
MLPS&SVI2
Test_Point_20MIL 1 TPV11 JTAG_TDO K4 JTAG_TMS NC_GENLK_CLK AJ13
1K_0402_5% 1 JTAG_TDO NC_GENLK_VSYNC
K7
CV142 +3VS_VGA TESTEN
AF24
OCP_L deleted ,reserve for PCC for Topaz 0.1U_0402_16V7-K NC_9
2
2
AG13
TOPAZ@ RV76 1 @ 2 5.11K_0402_1% NC_SWAPLOCKA
2 RV118 RV119 RV120
AC19 PS_0 10K_0402_5% 10K_0402_5% 10K_0402_5%
RV99 1 DIS@ 2 1K_0402_5% W8 PS_0 @ @
NC_GENERICB @
+3VS_VGA
1
1
W7 AH12
AD10 NC_GENERICD NC_SWAPLOCKB SVI2_SVD
AJ9 NC_GENERICE_HPD4 AD19
1
PS_1
B RV67
NC_10 PS_1 SVI2_SVT Please check if change Bit4 and 5 value to 1 on PS2 B
10K_0402_5% AE17 PS_2
1 2 0_0402_5% AB16 PS_2
1
1
1
@ RV79 @ SVI2_SVC
+3VS_VGA PX_EN AE20 PS_3
RV104 RV64 RV65 RV66 PS_3 Bits5 Bits4 Bits3 Bits2 Bits1
2
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

TOPAZ@
PUll down RV106 for OBBF design AJ27
W AKEB
@ @ @ @
RV115 1 2 +3VS_VGA +1.8VS_VGA +1.8VS_VGA
TOPAZ@ PS0 1 1 0 0 1
2
2
2
AC16
2
4.7K_0402_5% QV4 RV103 1 2 4.7K_0402_5% NC_DBG_VREFG

G
JTAG_TRSTB
1
JTAG_TDI
JTAG_TCK 14,38 EC_WAKE#
EC_WAKE# RV129 1 2 0_0402_5% 1 3
RV71 RV74
PS1 1 1 0 0 0
TOPAZ@
D
JTAG_TMS @ 1 2 4.7K_0402_5% NC_DDC/AUX 8.45K_0402_1% 4.99K_0402_1%

RV106 PLL/CLOCK AE6
JTAG_TDO NC_DDC1CLK DIS@ @
2N7002KW_SOT323-3 AE5 PS2 0 0 0 0 0
RV123 1 @ 2 0_0402_5% SB00000YY00 1 TPV13 AA1 NC_DDC1DATA
2
Test_Point_20MIL
2
14 GPU_WAKE# TOPAZ@ PLL_ANALOG_IN CV15 PS_0 CV16 PS_1
AD2
TOPAZ@ NC_AUX1P AD4 PS3 1 1 ? ? ?
0.1U_0402_10V7-K
0.1U_0402_10V7-K
Add GPU_WAKE# RV81 1 2 16.2K_0402_1% AA3 NC_AUX1N RV77
1
PLL_ANALOG_OUT 1 1
2K_0402_1% RV80
DIS@ 4.75K_0402_1%
@
RV68 DIS@ XTALIN AM28 AD13 DIS@
2 2
XTALIN NC_AUX2P
1
XTALOUT AK28 AD11
2
1 2 XTALOUT NC_AUX2N
RV82 1 DIS@ 2 10K_0402_5% AC22
1M_0402_5% RV83 1 DIS@ 2 10K_0402_5% AB22 XO_IN
XO_IN2
DIS@
YV1 AE16
RV101 DIS@ 4 3 XTALIN NC_36 Update location number to sync with ALCU5 on 0927
AD16
NC2 OSC2 NC_37 +1.8VS_VGA +1.8VS_VGA
XTALOUT 1 2 1 2 TPV36 THERMAL AC1
OSC1 NC1 NC_DDCVGACLK
Test_Point_20MIL 1 GPU_DPLUS T4 AC3
0_0402_5% 27MHZ_10PF_7V27000050 DPLUS NC_DDCVGADATA
1
Test_Point_20MIL 1 GPU_DMINUS T2
1
1 1
DMINUS
TPV37 RV60 RV63
CV143 CV144 +1.8VS_VGA 4.99K_0402_1%
8.2P_0402_50V8-J 8.2P_0402_50V8-J 4.99K_0402_1%
FDO R5 @
2 DIS@ 2 DIS@ CV145 AD17 GPIO28_FDO X76@
TSVDD
2
AC17
2
CV18 PS_2 CV19 PS_3
TSVSS
1U_0402_10V6-K
AE19
0.1U_0402_10V7-K
1
0.1U_0402_10V7-K
TS_A
1
1 1
RV69 RV70
DIS@
216-0858020-A0_FCBGA631 4.75K_0402_1%
A modify YV1 to SJ10000GI00 S CRYSTAL 27MHZ 16PF +-10PPM 7V27000050 on 20131205 2 4.99K_0402_1% A
@
DIS@
@
2 X76@ 2
2
JET@
2
RV84 1 2 FDO
10K_0402_5%
Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet GPIO
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
5 4 3 2 1
1 2 3 4 5
+1.8VS_VGA
TPV14
Test_Point_32MIL CV26 CV27
Change power rail from +1.5VS_VGA to +1.35VS_VGA UV3B
10U_0603_6.3V6-M
1U_0402_10V6-K
+1.35VS_VGA 1 1
1
AM30
MEM I/O PCIE_PVDD
PCIE
DIS@
DIS@
A CV1 CV2 CV8 CV3 CV4 CV5 CV6 CV7 H13 AB23 A
H16 VMEMIO_1 NC_38 AC23 2 2
VMEMIO_2 NC_39
.01U_0402_16V7-K
0.1U_0402_10V7-K
10U_0603_6.3V6-M
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
H19 AD24
J10 VMEMIO_3 NC_40 AE24
1 1 1 1 1 1 1 1 VMEMIO_4 NC_41
J23 AE25
J24 VMEMIO_5 NC_42 AE26
VMEMIO_6 NC_43
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
J9 AF25 +0.95VS_VGA
2 2 2 2 2 2 2 2 K10 VMEMIO_7 NC_44 AG26
K23 VMEMIO_8 NC_45
K24 VMEMIO_9
K9 VMEMIO_10 L23 CV29 CV31 CV32 CV33 CV34 CV35 CV36
L11 VMEMIO_11 PCIE_VDDC_1 L24
VMEMIO_12 PCIE_VDDC_2
10U_0603_6.3V6-M
L12 L25
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
L13 L26 1 1 1 1 1 1 1
L20 VMEMIO_14 PCIE_VDDC_4 M22
L21 VMEMIO_15 PCIE_VDDC_5 N22
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
L22 N23
VMEMIO_17 PCIE_VDDC_7 N24 2 2 2 2 2 2 2
PCIE_VDDC_8 R22
+1.8VS_VGA PCIE_VDDC_9 T22
LEVEL PCIE_VDDC_10 U22
TRANSLATION PCIE_VDDC_11 V22 +VGA_CORE
CV9 AA20 PCIE_VDDC_12
AA21 VDD_GPIO18_1
AB20 VDD_GPIO18_2 AA15 CV37 CV38 CV39 CV40 CV41 CV42 CV43 CV44 CV45 CV46 CV47 CV48 CV49 CV50
VDD_GPIO18_3 CORE VDDC_1
1U_0402_10V6-K
1 AB21 N15
VDD_GPIO18_4 VDDC_2
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
N17
VDDC_3 R13
I/O VDDC_4 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DIS@
R16
2 AA17 VDDC_5 R18
VDD_GPIO33_1 VDDC_6
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
@
DIS@
DIS@
DIS@
DIS@
DIS@
AA18 Y21
AB17 VDD_GPIO33_2 VDDC_7 T12 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AB18 VDD_GPIO33_3 VDDC_8 T15
VDD_GPIO33_4 VDDC_9 T17
V12 VDDC_10 T20
B
Y12 NC_VDDR4_1 VDDC_11 U13 B
+3VS_VGA U12 NC_VDDR4_2 VDDC_12 U16
NC_VDDR4_3 VDDC_13 U18 CV51 CV52 CV53 CV54 CV55 CV56 CV57 CV58
VDDC_14 V21
VDDC_15
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
CV10 V15
VDDC_16 V17
VDDC_17 1 1 1 1 1 1 1 1
V20
VDDC_18
1U_0402_10V6-K
Y13
POWER
1 VDDC_19
DIS@
DIS@
DIS@
DIS@
DIS@
@
Y16
VDDC_20 Y18 2 2 2 2 2 2 2 2
VDDC_21
DIS@
AA12
2 VDDC_22 M11
VDDC_23 N12
VDDC_24 U11
VDDC_25 AB13
VDDC_26 U10
VDDC_27 W9
PLL
VDDC_28 Y9
VDDC_29 W10
VDDC_30 T10 +0.95VS_VGA
+1.8VS_VGA MPLL_PVDD VDDC_31 AC14
VDDC_32 AB12
LV3 VDDC_33 AB11 CV22
1 2 CV17 CV154 CV156
90mA L8 VDDC_34 AC11
MPLL_PVDD VDDC_35
1U_0402_10V6-K
AC13
VDDC_36 Only available on TOPAZ, NC balls on JET
1U_0402_10V6-K
10U_0603_6.3V6-M
10U_0603_6.3V6-M
BLM18PG221SN1D_2P SPLL_PVDD 1
1 1 1
AC20 TOPAZ_VDDC_SEN
DIS@ 75mA FB_VDDC
DIS@
H7 AD20 TOPAZ_VDDC_RTN
SPLL_PVDD FB_GND_1 2
DIS@
DIS@
DIS@
2 2 2 SPLL_VDDC
R21
BIF_VDDC_1 U21
100mA H8 BIF_VDDC_2
SPLL_VDDC +VGA_CORE
C C
J7 ISOLATED
+1.8VS_VGA SPLL_PVSS
CORE I/O
M13 CV59 CV60 CV61 CV62 CV63 CV64 CV65
LV4 VDDCI_1 M15
VDDCI_2
10U_0603_6.3V6-M
10U_0603_6.3V6-M
0.1U_0402_10V7-K
0.1U_0402_10V7-K
1 2 CV20 CV21 M16
VDDCI_3
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
M17 1 1 1 1 1 1 1
VDDCI_4
10U_0603_6.3V6-M
BLM18PG121SN1D_2P M18
VDDCI_5
1U_0402_10V6-K
1 1 M20
VDDCI_6
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@ M21
VDDCI_7 N20 2 2 2 2 2 2 2
VDDCI_8
DIS@
DIS@
2 2 W1
FB_VDDCI W3
FB_GND_2
216-0858020-A0_FCBGA631
+0.95VS_VGA
LV5
1 2 CV24 CV25
FOR JET,PUT VIAS UNDER ASIC +VGA_CORE
0.1U_0402_10V7-K
BLM18PG121SN1D_2P
1U_0402_10V6-K
1 1
DIS@ VDDC_SEN RV1 1 JET@ 2 0_0402_5%
51 VDDC_SEN
DIS@
DIS@
2 2 VDDC_RTN RV2 1 JET@ 2 0_0402_5%

51 VDDC_RTN
TOPAZ@
VDDC_SEN RV3 1 2 0_0402_5% TOPAZ_VDDC_SEN
D D
TOPAZ@
VDDC_RTN RV4 1 2 0_0402_5% TOPAZ_VDDC_RTN

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet Core Power
1 2 3 4 5
5 4 3 2 1
UV3C UV3D UV3E
DP POWER NC/DP POWER
AG15 AE11 AL15 AA27 A3

AG16 NC_DP_VDDR_1 NC_50 AF11 NC_UPHYAB_TMDPA_TX0N AB24 GND_1 GND_65 A30
AK14
AF16 NC_DP_VDDR_2 NC_51 AE13 NC_UPHYAB_TMDPA_TX0P AB32 GND_2 GND_66 AA13
AG17 NC_DP_VDDR_3 NC_52 AF13 AC24 GND_3 GND_67 AA16
D AH16 D
+1.8VS_VGA AG18 NC_DP_VDDR_4 NC_53 AG8 NC_UPHYAB_TMDPA_TX1N AC26 GND_4 GND_68 AB10
AJ15
AG19 NC_DP_VDDR_5 NC_54 AG10 NC_UPHYAB_TMDPA_TX1P AC27 GND_5 GND_69 AB15
CV66 CV67 AF14 NC_DP_VDDR_6 NC_55 AD25 GND_6 GND_70 AB6
AL17
DP_VDDR NC_UPHYAB_TMDPA_TX2N AD32 GND_7 GND_71 AC9
AK16
NC_UPHYAB_TMDPA_TX2P GND_8 GND_72
10U_0603_6.3V6-M
AE27 AD6
GND_9 GND_73
1U_0402_10V6-K
1 1 AH18 AF32 AD8
NC_UPHYAB_TMDPA_TX3N AG27 GND_10 GND_74 AE7
AJ17
AG20 AF6 NC_UPHYAB_TMDPA_TX3P AH32 GND_11 GND_75 AG12
NC_DP_VDDC_1 NC_56 GND_12 GND_76
DIS@
DIS@
AG21 AF7 AL19 K28 AH10

2 2 AF22 NC_DP_VDDC_2 NC_57 AF8 NC_TXOUT_L3P K32 GND_13 GND_77 AH28
AK18
AG22 NC_DP_VDDC_3 NC_58 AF9 NC_TXOUT_L3N L27 GND_14 GND_78 B10
AD14 NC_DP_VDDC_4 NC_59 M32 GND_15 GND_79 B12
DP_VDDC NC_TMDP N25 GND_16 GND_80 B14
N27 GND_17 GND_81 B16
P25 GND_18 GND_82 B18
AH20
AG14 AE1 NC_UPHYAB_TMDPB_TX0N P32 GND_19 GND_83 B20
AJ19
+0.95VS_VGA AH14 NC_DP_VSSR_1 NC_60 AE3 NC_UPHYAB_TMDPB_TX0P R27 GND_20 GND_84 B22
AM14 NC_DP_VSSR_2 NC_61 AG1 T25 GND_21 GND_85 B24
AL21
CV70 CV71 AM16 NC_DP_VSSR_3 NC_62 AG6 NC_UPHYAB_TMDPB_TX1N T32 GND_22 GND_86 B26
AK20
AM18 NC_DP_VSSR_4 NC_63 AH5 NC_UPHYAB_TMDPB_TX1P U25 GND_23 GND_87 B6
NC_DP_VSSR_5 NC_64 GND_24 GND_88
0.1U_0402_10V7-K
AF23 AF10 AH22 U27 B8

NC_DP_VSSR_6 NC_65 NC_UPHYAB_TMDPB_TX2N GND_25 GND_89
1U_0402_10V6-K
1 1 AG23 AG9 AJ21 V32 C1

AM20 NC_DP_VSSR_7 NC_66 AH8 NC_UPHYAB_TMDPB_TX2P W25 GND_26 GND_90 C32
AM22 NC_DP_VSSR_8 NC_67 AM6 W26 GND_27 GND_91 E28
AL23
NC_DP_VSSR_9 NC_68 NC_UPHYAB_TMDPB_TX3N GND_28 GND_92
DIS@
DIS@
AM24 AM8 AK22 W27 F10

2 2 AF19 NC_DP_VSSR_10 NC_69 AG7 NC_UPHYAB_TMDPB_TX3P Y25 GND_29 GND_93 F12
AF20 NC_DP_VSSR_11 NC_70 AG11 Y32 GND_30 GND_94 F14
AK24
AE14 NC_DP_VSSR_12 NC_71 NC_TXOUT_U3P GND_31 GND_95 F16
AJ23
DP_VSSR NC_TXOUT_U3N GND_96 F18
GND_97 F2
GND_98 F20
AF17 AE10 M6 GND_99 F22
NC_UPHYAB_DP_CALR NC_72 N13 GND_32 GND_100 F24
216-0858020-A0_FCBGA631 N16 GND_33 GND_101 F26
C
N18 GND_34 GND_102 F6 C
N21 GND_35 GND_103 F8
GND_36 GND GND_104
216-0858020-A0_FCBGA631 P6 G10
P9 GND_37 GND_105 G27
R12 GND_38 GND_106 G31
R15 GND_39 GND_107 G8
R17 GND_40 GND_108 H14
R20 GND_41 GND_109 H17
T13 GND_42 GND_110 H2
T16 GND_43 GND_111 H20
T18 GND_44 GND_112 H6
T21 GND_45 GND_113 J27
T6 GND_46 GND_114 J31
ASIC Ball Topaz Jet ASIC Ball Topaz Jet U15 GND_47 GND_115 K11
U17 GND_48 GND_116 K2
U20 GND_49 GND_117 K22
U10,T10 VDDC NC U1 BP_0 NC GND_50 GND_118
U9 K6
AB13,W9 V13 GND_51 GND_119
AB11,AB12 V16 GND_52
U3 BP_1 NC GND_53
AC11,AC13 V18
GND_54
Y10
AC14,Y9,W10 Y15 GND_55
AM26 DIECRACKMON NC GND_56
Y17
Y20 GND_57
R11 GND_58 A32
Y11 NC DBG_DATA13 GND_59 VSS_MECH_1
AC20 FB_VDDC NC T11 AM1
AA11 GND_60 VSS_MECH_2 AM32
M12 GND_61 VSS_MECH_3
AE9 NC DBG_DATA14 GND_62
AD20 FB_VSS NC N11
V11 GND_63
GND_64
L9 NC DBG_DATA15
W1 FB_VDDCI NC
N9 NC DBG_DATA16 216-0858020-A0_FCBGA631
B W3 FB_VSS NC B
AE8 NC DBG_DATA12
AJ11 GPIO_SVC NC_SVI2
AL9 NC DBG_CNTL0
AK12 GPIO_SVD NC_SVI2
H13,H16,H19,J10 VMEMIO VDDR1
AL11 GPIO_SVT NC_SVI2 J23,J24,J9,K10
K23,K24,K9,L11
N6 GPIO_11 NC_GPIO11 L12,L13,L20,L21
L22
N5 GPIO_12 NC_GPIO12
AA17,AA18 VDD_GPIO33 VDDR3
N3 GPIO_13 NC_GPIO13 AB17,AB18
AJ27 WAKEB NC_VSYNC

AA20,AA21 VDD_GPIO18 VDD_CT
AB20,AB21
T8 PCC/GPIO_6 GPIO_6
AA3 PLL_ANALOG_OUT NC
AA1 PLL_ANALOG_IN NC
A A
Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet DP Power/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
5 4 3 2 1
1 2 3 4 5
UV3F
FBA_MA[15..0] 22,23
FBA_BA[2..0] 22,23 GDDR5/DDR3 GDDR5/DDR3

A A
FBA_D0 K27 K17 FBA_MA0
22,23 FBA_DQS[7..0] J29 DQA0_0 MAA0_0 J20
FBA_D1 FBA_MA1
FBA_D2 H30 DQA0_1 MAA0_1 H23 FBA_MA2
22,23 FBA_DQM[7..0] H32 DQA0_2 MAA0_2 G23
FBA_D3 FBA_MA3
FBA_D4 G29 DQA0_3 MAA0_3 G24 FBA_MA4
22,23 FBA_DQS#[7..0] DQA0_4 MAA0_4
FBA_D5 F28 H24 FBA_MA5
FBA_D[0..63] FBA_D6 F32 DQA0_5 MAA0_5 J19 FBA_MA6
22,23 FBA_D[0..63] DQA0_6 MAA0_6
FBA_D7 F30 K19 FBA_MA7
FBA_D8 C30 DQA0_7 MAA0_7 G20 FBA_MA13
FBA_D9 F27 DQA0_8 MAA0_8 L17 FBA_MA15
FBA_D10 A28 DQA0_9 MAA0_9
FBA_D11 C28 DQA0_10 J14 FBA_MA8
FBA_D12 E27 DQA0_11 MAA1_0 K14 FBA_MA9
FBA_D13 G26 DQA0_12 MAA1_1 J11 FBA_MA10
FBA_D14 D26 DQA0_13 MAA1_2 J13 FBA_MA11
FBA_D15 F25 DQA0_14 MAA1_3 H11 FBA_MA12
FBA_D16 A25 DQA0_15 MAA1_4 G11 FBA_BA2
FBA_D17 C25 DQA0_16 MAA1_5 J16 FBA_BA0
DQA0_17 MAA1_6
MEMORY INTERFACE
FBA_D18 E25 L15 FBA_BA1
FBA_D19 D24 DQA0_18 MAA1_7 G14 FBA_MA14
FBA_D20 E23 DQA0_19 MAA1_8 L16
FBA_D21 F23 DQA0_20 MAA1_9
FBA_D22 D22 DQA0_21 E32 FBA_DQM0
FBA_D23 F21 DQA0_22 WCKA0_0 E30 FBA_DQM1
FBA_D24 E21 DQA0_23 WCKA0B_0 A21 FBA_DQM2
FBA_D25 D20 DQA0_24 WCKA0_1 C21 FBA_DQM3
FBA_D26 F19 DQA0_25 WCKA0B_1 E13 FBA_DQM4
FBA_D27 A19 DQA0_26 WCKA1_0 D12 FBA_DQM5
Change power rail from +1.5VS_VGA to +1.35VS_VGA DQA0_27 WCKA1B_0
FBA_D28 D18 E3 FBA_DQM6
FBA_D29 F17 DQA0_28 WCKA1_1 F4 FBA_DQM7
+1.35VS_VGA FBA_D30 A17 DQA0_29 WCKA1B_1
FBA_D31 C17 DQA0_30 H28 FBA_DQS0
FBA_D32 E17 DQA0_31 EDCA0_0 C27 FBA_DQS1
FBA_D33 D16 DQA1_0 EDCA0_1 A23 FBA_DQS2
FBA_D34 F15 DQA1_1 EDCA0_2 E19 FBA_DQS3
DQA1_2 EDCA0_3
1
FBA_D35 A15 E15 FBA_DQS4
RV5 FBA_D36 D14 DQA1_3 EDCA1_0 D10 FBA_DQS5
40.2_0402_1% FBA_D37 F13 DQA1_4 EDCA1_1 D6 FBA_DQS6
B B
DIS@ FBA_D38 A13 DQA1_5 EDCA1_2 G5 FBA_DQS7
FBA_D39 C13 DQA1_6 EDCA1_3
2
FBA_D40 E11 DQA1_7 H27 FBA_DQS#0

CV72 FBA_D41 A11 DQA1_8 DDBIA0_0 A27 FBA_DQS#1
FBA_D42 C11 DQA1_9 DDBIA0_1 C23 FBA_DQS#2
FBA_D43 F11 DQA1_10 DDBIA0_2 C19 FBA_DQS#3
DQA1_11 DDBIA0_3
2
1U_0402_10V6-K
1 FBA_D44 A9 C15 FBA_DQS#4
Change power rail from +1.5VS_VGA to +1.35VS_VGA
RV6 FBA_D45 C9 DQA1_12 DDBIA1_0 E9 FBA_DQS#5
DIS@ DQA1_13 DDBIA1_1
100_0402_1% FBA_D46 F9 C5 FBA_DQS#6
+1.35VS_VGA DQA1_14 DDBIA1_2
DIS@
FBA_D47 D8 H4 FBA_DQS#7
2 FBA_D48 E7 DQA1_15 DDBIA1_3
1
FBA_D49 A7 DQA1_16 L18 FBA_ODTA0

DQA1_17 ADBIA0 FBA_ODTA0 22
FBA_D50 C7 K16 FBA_ODTA1
F7 DQA1_18 ADBIA1 FBA_ODTA1 23
FBA_D51
DQA1_19
1
FBA_D52 A5 H26 FBA_CLKA0

E5 DQA1_20 CLKA0 H25 FBA_CLKA0 22
RV7 FBA_D53 FBA_CLKA0#
DQA1_21 CLKA0B FBA_CLKA0# 22
40.2_0402_1% FBA_D54 C3
DIS@ FBA_D55 E1 DQA1_22 G9 FBA_CLKA1
G7 DQA1_23 CLKA1 H9 FBA_CLKA1 23
FBA_D56 FBA_CLKA1#
FBA_CLKA1# 23
2
FBA_D57 G6 DQA1_24 CLKA1B

CV73 FBA_D58 G1 DQA1_25 G22 FBA_RASA0#
DQA1_26 RASA0B FBA_RASA0# 22
FBA_D59 G3 G17 FBA_RASA1#
DQA1_27 RASA1B FBA_RASA1# 23
FBA_D60 J6
2
DQA1_28
1U_0402_10V6-K
1 FBA_D61 J1 G19 FBA_CASA0#

DQA1_29 CASA0B FBA_CASA0# 22
DIS@ RV8 FBA_D62 J3 G16 FBA_CASA1#
J5 DQA1_30 CASA1B FBA_CASA1# 23
100_0402_1% FBA_D63
DQA1_31
DIS@
H22 FBA_CSA0#
2 CSA0B_0 FBA_CSA0# 22
K26 J22
1
J26 MVREFDA_1 CSA0B_1

MVREFSA_2 G13 FBA_CSA1#
J25 CSA1B_0 K13 FBA_CSA1# 23
RV14 1 DIS@ 2 120_0402_1% K25 NC_120 CSA1B_1
MEM_CALRP0 K20 FBA_CKEA0
CKEA0 J17 FBA_CKEA0 22
FBA_CKEA1
CKEA1 FBA_CKEA1 23
RV9 RV10 DIS@ G25 FBA_WEA0#
WEA0B FBA_WEA0# 22
FBA_RST# 1 2 DIS@ 1 2 L10 H10 FBA_WEA1#
C 22,23 FBA_RST# DRAM_RST WEA1B FBA_WEA1# 23 C
51.1_0402_1% 10_0402_5% K8
L7 CLKTESTA
1
CLKTESTB
1 1
CV74 RV11 CV75 TPV15 1 Test_Point_32MIL
120P_0402_50V8-J 4.99K_0402_1% 68P_0402_50V8-J
DIS@ DIS@ @ 216-0858020-A0_FCBGA631
2 2 TPV16 1 Test_Point_32MIL
2
0.1U_0402_25V6-K
0.1U_0402_25V6-K
CV76
CV77
1 1
2 2
@
@
1
RV12 RV13
51.1_0402_1% 51.1_0402_1%
@ @
2
D D
Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet MEM Interface
1 2 3 4 5
1 2 3 4 5
Memory Partition A - Lower 32 bits

FBA_MA[15..0] 21,23
UV6
UV5
FBA_BA[2..0] 21,23
+FBA_VREFC0_L M8 E3 FBA_D19
+FBA_VREFC0_U M8 E3 FBA_D1 +FBA_VREFD0_L H1 VREFCA DQL0 F7 FBA_D16
VREFCA DQL0 VREFDQ DQL1 FBA_DQS[7..0] 21,23
+FBA_VREFD0_U H1 F7 FBA_D6 F2 FBA_D23
VREFDQ DQL1 F2 FBA_D2 FBA_MA0 N3 DQL2 F8 FBA_D21
A
DQL2 A0 DQL3 Group2 (IN1) FBA_DQM[7..0] 21,23 A
FBA_MA0 N3 F8 FBA_D7 FBA_MA1 P7 H3 FBA_D22
FBA_MA1 P7 A0 DQL3 H3 FBA_D0 FBA_MA2 P3 A1 DQL4 H8 FBA_D18
A1 DQL4 Group0 (IN3) A2 DQL5 FBA_DQS#[7..0] 21,23
FBA_MA2 P3 H8 FBA_D5 FBA_MA3 N2 G2 FBA_D20
FBA_MA3 N2 A2 DQL5 G2 FBA_D3 FBA_MA4 P8 A3 DQL6 H7 FBA_D17
A3 DQL6 A4 DQL7 FBA_D[0..63] 21,23
FBA_MA4 P8 H7 FBA_D4 FBA_MA5 P2
FBA_MA5 P2 A4 DQL7 FBA_MA6 R8 A5
FBA_MA6 R8 A5 FBA_MA7 R2 A6 D7 FBA_D9
FBA_MA7 R2 A6 D7 FBA_D31 FBA_MA8 T8 A7 DQU0 C3 FBA_D10 VRAM SWAP on 20130930
FBA_MA8 T8 A7 DQU0 C3 FBA_D27 VRAM SWAP on 20130930 FBA_MA9 R3 A8 DQU1 C8 FBA_D13
FBA_MA9 R3 A8 DQU1 C8 FBA_D30 FBA_MA10 L7 A9 DQU2 C2 FBA_D12
A9 DQU2 A10/AP DQU3 Group1 (TOP)
FBA_MA10 L7 C2 FBA_D25 FBA_MA11 R7 A7 FBA_D8
FBA_MA11 R7 A10/AP DQU3 A7 FBA_D28 FBA_MA12 N7 A11 DQU4 A2 FBA_D14
A11 DQU4 Group3 (BOT) A12/BC DQU5
FBA_MA12 N7 A2 FBA_D24 FBA_MA13 T3 B8 FBA_D15
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D29 FBA_MA14 T7 A13 DQU6 A3 FBA_D11
FBA_MA14 T7 A13 DQU6 A3 FBA_D26 A14 DQU7
A14 DQU7 +1.35VS_VGA
+1.35VS_VGA
FBA_BA0 M2 B2
FBA_BA0 M2 B2 FBA_BA1 N8 BA0 VDD_1 D9
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA2 M3 BA1 VDD_2 G7
FBA_BA2 M3 BA1 VDD_2 G7 BA2 VDD_3 K2 +1.35VS_VGA +1.35VS_VGA
BA2 VDD_3 K2 VDD_4 K8
VDD_4 K8 VDD_5 N1
VDD_5 VDD_6
1
N1 FBA_CLKA0 J7 N9
FBA_CLKA0 J7 VDD_6 N9 FBA_CLKA0# K7 CK VDD_7 R1 RV18 RV20
21 FBA_CLKA0 CK VDD_7 CK VDD_8
FBA_CLKA0# K7 R1 FBA_CKEA0 K9 R9 4.99K_0402_1% 4.99K_0402_1%
21 FBA_CLKA0# CK VDD_8 CKE VDD_9
FBA_CKEA0 K9 R9 DIS@ DIS@
21 FBA_CKEA0 CKE VDD_9
2
FBA_ODTA0 K1 A1 +FBA_VREFC0_U CV101 +FBA_VREFC0_L
FBA_ODTA0 K1 A1 FBA_CSA0# L2 ODT VDDQ_1 A8
21 FBA_ODTA0 ODT VDDQ_1 CS VDDQ_2 CV100
0.1U_0402_10V7-K
0.1U_0402_10V7-K
FBA_CSA0# L2 A8 FBA_RASA0# J3 C1
21 FBA_CSA0# CS VDDQ_2 RAS VDDQ_3
1
FBA_RASA0# J3 C1 FBA_CASA0# K3 C9 1 1
21 FBA_RASA0# RAS VDDQ_3 CAS VDDQ_4
FBA_CASA0# K3 C9 FBA_WEA0# L3 D2 RV19 RV21
21 FBA_CASA0# CAS VDDQ_4 WE VDDQ_5
FBA_WEA0# L3 D2 E9 4.99K_0402_1% 4.99K_0402_1%
B 21 FBA_WEA0# WE VDDQ_5 VDDQ_6 B
DIS@
DIS@
E9 F1 DIS@ DIS@
VDDQ_6 F1 FBA_DQS2 F3 VDDQ_7 H2 2 2
2
FBA_DQS0 F3 VDDQ_7 H2 FBA_DQS1 C7 DQSL VDDQ_8 H9
FBA_DQS3 C7 DQSL VDDQ_8 H9 DQSU VDDQ_9
DQSU VDDQ_9
2
FBA_DQM2 E7 A9
FBA_DQM0 E7 A9 FBA_DQM1 D3 DML VSS_1 B3 RV78 RV98
FBA_DQM3 D3 DML VSS_1 B3 DMU VSS_2 E1 0_0402_5%
DMU VSS_2 VSS_3 0_0402_5%
E1 G8 DIS@
VSS_3 VSS_4 DIS@
G8 FBA_DQS#2 G3 J2
1
VSS_4 DQSL VSS_5
1
FBA_DQS#0 G3 J2 FBA_DQS#1 B7 J8
FBA_DQS#3 B7 DQSL VSS_5 J8 DQSU VSS_6 M1 +1.35VS_VGA +1.35VS_VGA
DQSU VSS_6 M1 VSS_7 M9
VSS_7 M9 VSS_8 P1
VSS_8 VSS_9
1
P1 FBA_RST# T2 P9
FBA_RST# T2 VSS_9 P9 RESET VSS_10 T1 RV22 RV24
21,23 FBA_RST# RESET VSS_10 VSS_11
T1 L8 T9 4.99K_0402_1% 4.99K_0402_1%
L8 VSS_11 T9 ZQ VSS_12 @ @
ZQ VSS_12
2
J1 B1 +FBA_VREFD0_U +FBA_VREFD0_L
NC1 VSSQ_1
1
1
J1 B1 L1 B9
NC1 VSSQ_1 NC2 VSSQ_2
0.1U_0402_10V7-K
0.1U_0402_10V7-K
RV15 RV16 L1 B9 RV17 J9 D1 CV102
NC2 VSSQ_2 NC3 VSSQ_3 CV103
1
10K_0402_5% 243_0402_1% J9 D1 243_0402_1% L9 D8 1 1
@ DIS@ L9 NC3 VSSQ_3 D8 DIS@ FBA_MA15 M7 NC4 VSSQ_4 E2 RV23 RV25
FBA_MA15 M7 NC4 VSSQ_4 E2 NC5 VSSQ_5 E8 4.99K_0402_1% 4.99K_0402_1%
2
2
NC5 VSSQ_5 VSSQ_6
@
E8 F9 @ @
VSSQ_6 F9 VSSQ_7 G1 2 2
2
VSSQ_7 G1 VSSQ_8 G9
VSSQ_8 G9 VSSQ_9
VSSQ_9 96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3 K4W4G1646B-HC11_FBGA96
K4W4G1646B-HC11_FBGA96
DIS@
C DIS@ C
FBA_CLKA0
+1.35VS_VGA UV6 SIDE +1.35VS_VGA UV7 SIDE
1
CV78 CV79 CV80 CV81 CV82 CV83 CV89 CV90 CV91 CV92 CV93 CV94 RV26
40.2_0402_1%
10U_0603_6.3V6-M
10U_0603_6.3V6-M
DIS@
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1 1 1 1 1 1 1 1 1 1 1 1
2
CV104 DIS@
1 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2 2 2 2 2 2 2 2 2 2 2 2 .01U_0402_16V7-K
1
RV27
40.2_0402_1%
DIS@
2
FBA_CLKA0#
CV84 CV85 CV86 CV87 CV88 CV95 CV96 CV97 CV98 CV99
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
1 1 1 1 1 1 1 1 1 1
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2 2 2 2 2 2 2 2 2 2
D D

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet DDR3 VRAM U
1 2 3 4 5
1 2 3 4 5
Memory Partition A - Upper 32 bits VRAM SWAP on 20130930
UV7
FBA_MA[15..0] 21,22
UV8
+FBA_VREFC1_U M8 E3 FBA_D38
VREFCA DQL0 FBA_BA[2..0] 21,22
+FBA_VREFD1_U H1 F7 FBA_D35 +FBA_VREFC1_L M8 E3 FBA_D56
VREFDQ DQL1 F2 FBA_D37 +FBA_VREFD1_L H1 VREFCA DQL0 F7 FBA_D59
A A
DQL2 VREFDQ DQL1 FBA_DQS[7..0] 21,22
FBA_MA0 N3 F8 FBA_D32 F2 FBA_D57
FBA_MA1 P7 A0 DQL3 H3 FBA_D36 FBA_MA0 N3 DQL2 F8 FBA_D61
A1 DQL4 Group4 (IN1) A0 DQL3 FBA_DQM[7..0] 21,22
FBA_MA2 P3 H8 FBA_D34 FBA_MA1 P7 H3 FBA_D60 Group7 (IN3)
FBA_MA3 N2 A2 DQL5 G2 FBA_D39 FBA_MA2 P3 A1 DQL4 H8 FBA_D62
A3 DQL6 A2 DQL5 FBA_DQS#[7..0] 21,22
FBA_MA4 P8 H7 FBA_D33 FBA_MA3 N2 G2 FBA_D63
FBA_MA5 P2 A4 DQL7 FBA_MA4 P8 A3 DQL6 H7 FBA_D58
A5 A4 DQL7 FBA_D[0..63] 21,22
FBA_MA6 R8 FBA_MA5 P2
FBA_MA7 R2 A6 D7 FBA_D40 FBA_MA6 R8 A5
FBA_MA8 T8 A7 DQU0 C3 FBA_D45 FBA_MA7 R2 A6 D7 FBA_D55
FBA_MA9 R3 A8 DQU1 C8 FBA_D43 FBA_MA8 T8 A7 DQU0 C3 FBA_D51
FBA_MA10 L7 A9 DQU2 C2 FBA_D44 FBA_MA9 R3 A8 DQU1 C8 FBA_D54
FBA_MA11 R7 A10/AP DQU3 A7 FBA_D42 FBA_MA10 L7 A9 DQU2 C2 FBA_D48
A11 DQU4 Group5 (TOP) A10/AP DQU3
FBA_MA12 N7 A2 FBA_D46 FBA_MA11 R7 A7 FBA_D52 Group6 (BOT)
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D41 FBA_MA12 N7 A11 DQU4 A2 FBA_D50 +1.35VS_VGA +1.35VS_VGA
FBA_MA14 T7 A13 DQU6 A3 FBA_D47 FBA_MA13 T3 A12/BC DQU5 B8 FBA_D53
A14 DQU7 FBA_MA14 T7 A13 DQU6 A3 FBA_D49
A14 DQU7
1
+1.35VS_VGA RV30
+1.35VS_VGA RV32
FBA_BA0 M2 B2 4.99K_0402_1% 4.99K_0402_1%
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA0 M2 B2 DIS@ DIS@
FBA_BA2 M3 BA1 VDD_2 G7 FBA_BA1 N8 BA0 VDD_1 D9
VRAM SWAP on 20130930
2
BA2 VDD_3 K2 FBA_BA2 M3 BA1 VDD_2 G7 +FBA_VREFC1_U CV128 +FBA_VREFC1_L
VDD_4 K8 BA2 VDD_3 K2
VDD_5 VDD_4
0.1U_0402_10V7-K
0.1U_0402_10V7-K
N1 K8
VDD_6 VDD_5
1
FBA_CLKA1 J7 N9 N1 CV127 1 1
21 FBA_CLKA1 CK VDD_7 VDD_6
FBA_CLKA1# K7 R1 FBA_CLKA1 J7 N9 RV31 RV33
21 FBA_CLKA1# CK VDD_8 CK VDD_7
FBA_CKEA1 K9 R9 FBA_CLKA1# K7 R1 4.99K_0402_1% 4.99K_0402_1%
21 FBA_CKEA1 CKE VDD_9 CK VDD_8
DIS@
DIS@
FBA_CKEA1 K9 R9 DIS@ DIS@
CKE VDD_9 2 2
2
2
FBA_ODTA1 K1 A1
21 FBA_ODTA1 ODT VDDQ_1
FBA_CSA1# L2 A8 FBA_ODTA1 K1 A1
21 FBA_CSA1# CS VDDQ_2 ODT VDDQ_1
FBA_RASA1# J3 C1 FBA_CSA1# L2 A8
21 FBA_RASA1#
2
RAS VDDQ_3 CS VDDQ_2
2
FBA_CASA1# K3 C9 FBA_RASA1# J3 C1
21 FBA_CASA1# CAS VDDQ_4 RAS VDDQ_3 RV102 RV105
FBA_WEA1# L3 D2 FBA_CASA1# K3 C9
B 21 FBA_WEA1# WE VDDQ_5 CAS VDDQ_4 0_0402_5% B
E9 FBA_WEA1# L3 D2 0_0402_5%
VDDQ_6 F1 WE VDDQ_5 E9 DIS@
VDDQ_7 VDDQ_6 DIS@
FBA_DQS4 F3 H2 F1
1
DQSL VDDQ_8 VDDQ_7
1
FBA_DQS5 C7 H9 FBA_DQS7 F3 H2 +1.35VS_VGA +1.35VS_VGA
DQSU VDDQ_9 FBA_DQS6 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9
1
1
FBA_DQM4 E7 A9
FBA_DQM5 D3 DML VSS_1 B3 FBA_DQM7 E7 A9 RV34 RV36
DMU VSS_2 E1 FBA_DQM6 D3 DML VSS_1 B3 4.99K_0402_1% 4.99K_0402_1%
VSS_3 G8 DMU VSS_2 E1 @ @
FBA_DQS#4 G3 VSS_4 J2 VSS_3 G8
2
2
FBA_DQS#5 B7 DQSL VSS_5 J8 FBA_DQS#7 G3 VSS_4 J2 +FBA_VREFD1_U CV130 +FBA_VREFD1_L
DQSU VSS_6 M1 FBA_DQS#6 B7 DQSL VSS_5 J8
VSS_7 DQSU VSS_6
0.1U_0402_10V7-K
0.1U_0402_10V7-K
M9 M1
VSS_8 VSS_7
1
P1 M9 CV129
VSS_9 VSS_8 1 1
FBA_RST# T2 P9 P1 RV35 RV37
21,22 FBA_RST# RESET VSS_10 VSS_9
T1 FBA_RST# T2 P9 4.99K_0402_1% 4.99K_0402_1%
VSS_11 RESET VSS_10
@
L8 T9 T1 @ @
ZQ VSS_12 L8 VSS_11 T9 2 2
2
ZQ VSS_12
1
J1 B1
NC1 VSSQ_1
1
RV28 L1 B9 J1 B1
243_0402_1% J9 NC2 VSSQ_2 D1 RV29 L1 NC1 VSSQ_1 B9
DIS@ L9 NC3 VSSQ_3 D8 243_0402_1% J9 NC2 VSSQ_2 D1
FBA_MA15 M7 NC4 VSSQ_4 E2 DIS@ L9 NC3 VSSQ_3 D8
2
NC5 VSSQ_5 E8 FBA_MA15 M7 NC4 VSSQ_4 E2
2
VSSQ_6 F9 NC5 VSSQ_5 E8
VSSQ_7 G1 VSSQ_6 F9
VSSQ_8 G9 VSSQ_7 G1
VSSQ_9 VSSQ_8 G9 FBA_CLKA1
96-BALL VSSQ_9
SDRAM DDR3 96-BALL
1
K4W4G1646B-HC11_FBGA96 SDRAM DDR3
K4W4G1646B-HC11_FBGA96 RV38
C DIS@ 40.2_0402_1% C
DIS@ DIS@
2
CV131 DIS@
1 2
.01U_0402_16V7-K
1
CV105 CV106 CV107 CV108 CV109 CV110 CV116 CV117 CV118 CV119 CV120 CV121
RV39
10U_0603_6.3V6-M
10U_0603_6.3V6-M
40.2_0402_1%
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1 1 1 1 1 1 1 1 1 1 1 1 DIS@
2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
FBA_CLKA1#
2 2 2 2 2 2 2 2 2 2 2 2

CV111 CV112 CV113 CV114 CV115 CV122 CV123 CV124 CV125 CV126
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
1 1 1 1 1 1 1 1 1 1
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2 2 2 2 2 2 2 2 2 2
D D

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet DDR3 VRAM L
1 2 3 4 5
1 2 3 4 5
Add 1.35VP to _+1.35VS_VGA on 20130925, RDS on less than 8,need to check, 4A for totally
A +0.95VS to +0.95VS_VGA Reserve for GPU/APU share +0.95V A
+/- 1.5% +0.95VS QV47 DIS@ +0.95VS_VGA AON4304

AON6414AL_DFN8-5 +/- 3% 2A VDS=30V VGS=20V, ID=18A, +1.35VP TO +1.35VS_VGA
Rds=6mohm @ VGS=10V +1.35VP +1.35VS_VGA
1 VGS(th)=2.4V Max Need OPEN
2 1 1 1
10U_0603_6.3V6M
1 5 3 7m OHM is requried ???
10U_0603_6.3V6M
CV181 CV174 CV182 CV183 JV5 1 2 @
1 2 CV210 CV211 CV212
10U_0805_25V6K 1U_0603_25V6M
2 DIS@ 2@ 2 DIS@ CV208 CV209 JUMP_43X118 1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
.1U_0402_16V7K
10U_0603_6.3V6M
DIS@
1
4
2 1 1 AON6414AL_DFN8-5 1 1 1
CV214 + RV114
1 @ 470_0603_5%
330U_D2_2V_Y
2 @
2 2 2 2 2 2
@
5 3
DIS@
DIS@
DIS@
DIS@
1 2
DIS@
D QV10
AON6414AL DIS@ RV210 QV9 DIS@ 2 DGPU_PWREN#
VDS=30V VGS=20V, ID=50A, RV85 1 2 0_0402_5% 2 1
4
+VSB +VSB G
Rds=8mohm @ VGS=10V 100K_0402_5%
VGS(th)=2.5V Max DIS@ RV113
1 2 S 2N7002KW_SOT323-3
1
D QV37
3
1 @
CV180 RV209 2 DGPU_PWREN# 180K_0402_1%
0.1U_0402_16V4Z 120K_0402_5% G
1
DIS@ DIS@ 1
1
2 S D RV127 CV213
2N7002KW_SOT323-3
3
DIS@ DGPU_PWREN# 2 QV11 120K_0402_5% 0.1U_0402_16V4Z
G DIS@ DIS@
2
2
DIS@ S
3
2N7002KW_SOT323-3
B B
Check if QV46 need to replaced by LP2301ALT1G_SOT23-3 .
+1.8VS to +1.8VS_VGA Reserve for GPU/APU share +1.8V

+/- 2% +1.8VS QV48 DIS@ +1.8VS_VGA
+3VS to +3VS_VGA +3VS
Need OPEN +3VS_VGA
AON6414AL_DFN8-5 +/- 3% 0.5A 36m OHM is requried
1 JV1 1 2 @
1 2
2
4.7U_0603_6.3V6-K
5 3 1 1 JUMP_43X39
10U_0603_6.3V6M
1
1
CV170 CV163 CV162 RV116
@ 1U_0603_25V6M 470_0603_5%
2 2@
4
D
QV6 1 DIS@ @ @
2
2
LP2301ALT1G_SOT23-3
G
2
1
+5VALW D QV12
AON6414AL 2 DGPU_PWREN#
DIS@ 1 DIS@ 2 RV59 DGPU_PWREN# 1 DIS@ 2 RV100 G
VDS=30V VGS=20V, ID=50A, DIS@
Rds=8mohm @ VGS=10V RV117 1 2 0_0402_5% 2 RV198 1 20K_0402_5% 20K_0402_5%
+VSB S 2N7002KW_SOT323-3
VGS(th)=2.5V Max 100K_0402_5% 1
3
1
CV147 @
1
1
RV197 D QV36 D 0.1U_0402_16V4Z

1
CV161 120K_0402_5% 2 DGPU_PWREN# 12,17,51 DGPU_PWREN DGPU_PWREN 2 QV8 DIS@
G G 2
0.1U_0402_16V4Z DIS@
DIS@
2
2 S 2N7002KW_SOT323-3 DIS@ S
3
C C
3
DIS@ 2N7002KW_SOT323-3
GPU Power Discharger
+1.8VS_VGA +0.95VS_VGA +VGA_CORE

1
@ RV172 RV168 RV167

150_0603_5% 470_0603_5% 10_0603_5%
@ @
2
1 2
1 2
1
QV32 D QV5 D QV19 D

DGPU_PWREN# 2 DGPU_PWREN# 2 DGPU_PWREN# 2
G G G
D D
@ S 2N7002KW_SOT323-3 @ S 2N7002KW_SOT323-3 @ S 2N7002KW_SOT323-3
3

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet SWITCH POWER
reserve RV167 change to 10 ohm to meet power off sequence on 1202 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
1 2 3 4 5
5 4 3 2 1
D D
C C
BLANK
B B
A A

Issued Date 2012/12/05 Deciphered Date 2014/12/05 Topaz & Jet BLANK
5 4 3 2 1
5 4 3 2 1
Kaveri CPU PN
PCB_MB
ZZZ1 UC1 A4@ UL1 100M@ TL1 100M@
PCB NM-A291 Kaveri A4(17W) RTL8106EUL-CG TST1284A LF

SP050008C00
DA60000UD00 SA000063G00 SA000060Q00 LAN chip Transformer
D D
C C
B B
Board ID
BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 Description Stuff Resistor
0 0 0 0 BDW + Jet-LE sku RC107,RC108,RC109,RC123
0 0 1 0 BDW + Topaz-XT sku RC107,RC108,RC102,RC123
0 1 0 0 BDW + N15V-GM sku RC107,RC101,RC109,RC123
0 1 1 0 BDW + N15S-GT sku RC107,RC101,RC102,RC123
1 0 0 0 HSW + Jet-LE sku RC100,RC108,RC109,RC123

A
* A
1 0 1 0 HSW + Topaz-XT sku RC100,RC108,RC102,RC123
1 1 0 0 HSW + N15V-GM sku RC100,RC101,RC109,RC123
1 1 1 0 HSW + N15S-GT sku RC100,RC101,RC102,RC123
0 0 0 1 BDW + UMA sku RC107,RC108,RC109,RC121 Security Classification LC Future Center Secret Data Title
1 0 0 1 HSW + UMA sku RC100,RC108,RC109,RC121

Issued Date 2013/08/05 Deciphered Date 2013/08/05 Virtual Symbol
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
5 4 3 2 1
5 4 3 2 1
+3VS
LCD POWER CIRCUIT
2
+3VS +LCDVDD_CON
D
R13
4.7K_0402_5% 5
U7
1 +LCDVDD_CON
CMOS Camera +3VS +3VS_CMOS
D
2
IN2 OUT
R9 2
1 1 R82 1 2 0_0805_5%
1
100K_0402_5% GND 4.7U_0603_6.3V6-K
LCD_ENVDD C1 4 3 LCD_ENVDD C2
IN1 EN @ Q23
1U_0402_6.3V6-K
1
2 2 W=40 mils AO3413_SOT23-3 W=40mils
From PCH G5243AT11U_SOT23-5
1
D
SA00005XJ00
D
3 1
2 Q17
G 2N7002KW_SOT323-3
S SB00000YY00 1
LED POWER
3
1
G
R7 C
2
C6 @
APU_ENVDD 1 2 2 +LEDVDD 0.1U_0402_10V7-K
7 APU_ENVDD B R6 @
B+ 1 2 2
2.2K_0402_5% E 13 CMOS_ON#
3
2
Q2 2A 80 mil R47 1 2 0_0805_5% +LEDVDD 2A 80 mil 100K_0402_5%
R8 MMST3904-7-F_SOT323-3 1
1 @
100K_0402_5%
C4
C8 0.1U_0402_10V7-K
1 4.7U_0805_25V6-K 2
2
Follow CRB and Edge schematic to enable LCD_ENVDD
+3VS_TS
JEDP1 ME@
R48 1 @ 2 0_0402_5%
eDP Conn +LEDVDD 1
2 1
W=80mils 3 2
3
C
LP2301ALT1G_SOT23-3 Touch Screen 7 APU_EDP_TX0+
C17 1 2 0.1U_0402_10V7-K EDP_TX0+
4
5 4
C
C18 1 2 0.1U_0402_10V7-K EDP_TX0- 6 5

7 APU_EDP_TX0-
S
D
R22 1 TS@ 2 0_0402_5% 3 1 7 6
+3VS
Q5 TS@ C16 1 2 0.1U_0402_10V7-K EDP_TX1+ 8 7
R24 1 @ 2 0_0402_5% 7 APU_EDP_TX1+ 8
+3VALW C19 1 2 0.1U_0402_10V7-K EDP_TX1- 9
7 APU_EDP_TX1- 9
G
10
2
C20 1 2 0.1U_0402_10V7-K EDP_AUX 11 10

R19 1 TS@ 2 7 APU_EDP_AUX 11
38 EC_TS_ON# C21 1 2 0.1U_0402_10V7-K EDP_AUX# 12
100K_0402_5% 1 7 APU_EDP_AUX# 13 12
2 C25 DISPOFF# 14 13
0.1U_0402_10V7-K 15 14
C23 @ APU_EDP_PWM 16 15
2 7 APU_EDP_PWM 16
0.1U_0402_10V7-K 17
1 17
TS@ +3VS R148 1 2 100K_0402_5% 18
19 18
7 APU_EDP_HPD 1 2 0_0402_5% 20 19
R18 @
21 20
1 +LCDVDD_CON 21
W=60mils 22
C22 23 22
+3VS 23
680P_0402_50V7K 34 DMIC_DATA 24
24
Touch Screen reserved @ 2 25

34 DMIC_CLK 25
26 31
27 26 G1 32
R183 1 2 0_0402_5% USB20_P5_CONN 28 27 G2 33
14 USB20_P5 28 G3
R186 1 2 0_0402_5% USB20_N5_CONN 29 34
14 USB20_N5 30 29 G4 35
+3VS_CMOS 30 G5
W=40mils ACES_50406-03071-001
+3VS_TS +3VS_TS
JTS1@
1
R69 2 @ 1 10K_0402_5% TS_RS 2 1
3 2
@
R20 1 TS@ 2 0_0402_5% USB20_N8_CONN 4 3
14 USB20_N8 R11 1 2 0_0402_5%
R21 1 TS@ 2 0_0402_5% USB20_P8_CONN 5 4 7 7 APU_BKOFF#
14 USB20_P8 6 5 GND1 8
B 6 GND2 B
ACES_87213-00601-P01 R12 1 2 0_0402_5% DISPOFF#

38 EC_BKOFF#
2
Touch Screen R10
100K_0402_5%
add Pull down R14 100k on EC_BKOFF#
1
USB20_P5_CONN
EMI request
+3VS_TS USB20_N5_CONN
3
+3VS_CMOS
L17 DMIC_CLK DISPOFF#
1
@ L18
4 3 1 2
C12
C11
D2 USB20_N8 USB20_N8_CONN USB20_P5 USB20_P5_CONN
1
470P_0402_50V7K
100P_0402_50V8J
4 3 1 2
1 1 2
D1 USB20_P8 1 2 USB20_P8_CONN USB20_N5 4 3 USB20_N5_CONN C24
1 2 4 3
2
AZC199-02S.R7G_SOT23-3 0.047U_0402_16V7K
@ @ @ WCM2012F2S-900T04_0805 2 2 1
2
AZ5215-01F_DFN1006P2E2 WCM2012F2S-900T04_0805 @ @
A A
1
Issued Date 2013/08/08 Deciphered Date 2013/08/05 eDP/ CMOS/Touch screen

5 4 3 2 1
5 4 3 2 1
+3VS +3VS +5VS_HDMI +3VS

D D
2
1
2
R44 R45 R27
R25 R26
2
4.7K_0402_5% 4.7K_0402_5% 1M_0402_5%
G
2.2K_0402_5% 2.2K_0402_5%
Q7
2
G
1
2N7002KW_SOT323-3
1
SB00000YY00
APU_HDMI_CLK 1 6 HDMI_CLK_CON APU_HDMI_HPD 3 1 HDMI_DET_CON
S
7 APU_HDMI_CLK 7 APU_HDMI_HPD
D
5
2
Q43A
G
2N7002KDWH_SOT363-6 R46
SB00000EO1J 20K_0402_1%
APU_HDMI_DATA 4 3 HDMI_DAT_CON
S
7 APU_HDMI_DATA
1
D
Q43B
2N7002KDWH_SOT363-6
SB00000EO1J
+CRT_VCC_CON and +5VS_HDMI trace width 100 mils

+CRT_VCC_CON
APU_HDMI_CLK+ C26 1 2 0.1U_0402_10V7-K HDMI_CLK+_C R32 1 @ 2 0_0402_5% HDMI_CLK+_CON +5VS U6 +5VS_HDMI

7 APU_HDMI_CLK+
R23
0.1U_0402_10V7-K
4 3 3 1 1 2
4 3 VOUT
C EMC@ 1 0_0805_5% C
L2 HDMI2012F2SF-900T04_4P
1 2 VIN SA00004ZB0J C34
1 2 2 2
APU_HDMI_CLK- C27 1 2 0.1U_0402_10V7-K HDMI_CLK-_C R35 1 @ 2 0_0402_5% HDMI_CLK-_CON GND
7 APU_HDMI_CLK-
1 1
APL3517AI-TRG_SOT23-3
C36 C35
APU_HDMI_TX0+ C28 1 2 0.1U_0402_10V7-K HDMI_TX0+_C R36 1 @ 2 0_0402_5% HDMI_TX0+_CON 2200P_0402_50V7-K 0.1U_0402_10V7-K
7 APU_HDMI_TX0+ 2 2
4 3
4 3
EMC@ L3 HDMI2012F2SF-900T04_4P
1 2
1 2
APU_HDMI_TX0- C29 1 2 0.1U_0402_10V7-K HDMI_TX0-_C R37 1 @ 2 0_0402_5% HDMI_TX0-_CON
7 APU_HDMI_TX0-
APU_HDMI_TX1+ C30 1 2 0.1U_0402_10V7-K HDMI_TX1+_C R38 1 @ 2 0_0402_5% HDMI_TX1+_CON JHDMI1 ME@

7 APU_HDMI_TX1+
HDMI_DET_CON 19
4 3 18 HP_DET
4 3 +5VS_HDMI +5V
17
EMC@ L4 HDMI2012F2SF-900T04_4P HDMI_DAT_CON 16 DDC/CEC_GND
1 2 HDMI_CLK_CON 15 SDA
1 2 14 SCL
APU_HDMI_TX1- C31 1 2 0.1U_0402_10V7-K HDMI_TX1-_C R39 1 @ 2 0_0402_5% HDMI_TX1-_CON 13 Reserved
7 APU_HDMI_TX1- CEC
HDMI_CLK-_CON 12 20
11 CK- GND1 21
APU_HDMI_TX2+ C32 1 2 0.1U_0402_10V7-K HDMI_TX2+_C R41 1 @ 2 0_0402_5% HDMI_TX2+_CON HDMI_CLK+_CON 10 CK_shield GND2
7 APU_HDMI_TX2+ CK+
HDMI_TX0-_CON 9 22
4 3 8 D0- GND3 23
4 3 7 D0_shield GND4
HDMI_TX0+_CON
B EMC@ L5 HDMI2012F2SF-900T04_4P 6 D0+ B
HDMI_TX1-_CON
1 2 5 D1-
1 2 4 D1_shield
HDMI_TX1+_CON
APU_HDMI_TX2- C33 1 2 0.1U_0402_10V7-K HDMI_TX2-_C R42 1 @ 2 0_0402_5% HDMI_TX2-_CON HDMI_TX2-_CON 3 D1+
7 APU_HDMI_TX2- D2-
2
HDMI_TX2+_CON 1 D2_shield
D2+
FOX_QJ111A1-RC0AH1-8H
HDMI_CLK-_CON R28 1 2 665_0402_1% HDMI_GND

HDMI_CLK+_CON R29 1 2 665_0402_1% For ESD
HDMI_TX0-_CON R30 1 2 665_0402_1%
HDMI_TX0+_CON R31 1 2 665_0402_1%
D3 @ D4 @ D5 @
+5VS_HDMI 1 1 10 9 +5VS_HDMI HDMI_CLK-_CON 1 1 10 9 HDMI_CLK-_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON
HDMI_DET_CON 2 2 9 8 HDMI_DET_CON HDMI_CLK+_CON 2 2 9 8 HDMI_CLK+_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON
HDMI_TX1-_CON R33 1 2 665_0402_1% HDMI_DAT_CON 4 4 7 7 HDMI_DAT_CON HDMI_TX0-_CON 4 4 7 7 HDMI_TX0-_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

HDMI_TX1+_CON R34 1 2 665_0402_1%
HDMI_TX2-_CON R43 1 2 665_0402_1% HDMI_CLK_CON 5 5 6 6 HDMI_CLK_CON HDMI_TX0+_CON 5 5 6 6 HDMI_TX0+_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON
HDMI_TX2+_CON R40 1 2 665_0402_1%
3 3 3 3 3 3
8 8 8
1
A D A
2 Q6 AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
+3VS
G 2N7002KW_SOT323-3
S SB00000YY00
3
Issued Date 2013/08/08 Deciphered Date 2013/08/05 HDMI_CONN

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
5 4 3 2 1
5 4 3 2 1
CRT Connector
+5VS +CRT_VCC +CRT_VCC_CON
@
D18
2 F2 @
1 1 2 +CRT_VCC_CON
3 1
D D
PMEG2010ET_SOT23-3 0.5A_8V_KMC3S050RY C155 @
0.1U_0402_10V7-K
2
W=40mils
check GPIO pin JCRT1 ME@

6
@ PAD TVG1 1 CRT_DET# 11
L6 1 2 BLM18BB470SN1D_2P~D CRT_R_CON 1
13 FCH_CRT_R 7
CRT_DDC_DAT_CON 12
L7 1 2 BLM18BB470SN1D_2P~D CRT_G_CON 2
13 FCH_CRT_G 8
HSYNC_CON 13
L8 1 2 BLM18BB470SN1D_2P~D CRT_B_CON 3
13 FCH_CRT_B 9
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
VSYNC_CON 14
2
2
1 1 1 1 1 1 4
RH129 RH130 RH131 10 G 16
C43
C44
C45
C46
C47
C48
150_0402_1% 150_0402_1% 150_0402_1% CRT_DDC_CLK_CON 15 G 17
5
2 2 2 2 2 2
100P_0402_50V8J
1
SUYIN_070546HR015M25KZR
1
C49
2
C C
+CRT_VCC_CON
@ 1
C50 OE# +CRT_VCC_CON
0.1U_0402_10V7-K
2 U1
5
74AHCT1G125GW_SOT353-5
L9
NBQ100505T-800Y-N_2P
OE#
P
2 4 CRT_HSYNC_1 1 2 HSYNC_CON
13 FCH_CRT_HSYNC A Y
1
G
10P_0402_50V8J
R52 R53
1 4.7K_0402_5% 4.7K_0402_5%
3
C51
EMC@
2
+CRT_VCC_CON 2
13 FCH_CRT_DDC_DATA R93 1 2 0_0402_5% CRT_DDC_DAT_CON
OE#
U2
5
74AHCT1G125GW_SOT353-5
L10
NBQ100505T-800Y-N_2P
OE#
P
2 4 CRT_VSYNC_1 1 2 VSYNC_CON 13 FCH_CRT_DDC_CLK R94 1 2 0_0402_5% CRT_DDC_CLK_CON

13 FCH_CRT_VSYNC A Y
10P_0402_50V8J
G
B B
1 1 1
3
C53
@ C54 @ C55
EMC@ 100P_0402_50V8J 100P_0402_50V8J
2 2 2
D20 D22
CRT_R_CON 1 1 10 9 CRT_R_CON VSYNC_CON 1 1 10 9 VSYNC_CON
CRT_G_CON 2 2 9 8 CRT_G_CON HSYNC_CON 2 2 9 8 HSYNC_CON
CRT_B_CON 4 4 7 7 CRT_B_CON CRT_DDC_CLK_CON 4 4 7 7 CRT_DDC_CLK_CON
CRT_DET# 5 5 6 6 CRT_DET# CRT_DDC_DAT_CON 5 5 6 6 CRT_DDC_DAT_CON

3 3 3 3
8 8
A A
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
@ @
For EMC
Issued Date 2013/08/08 Deciphered Date 2013/08/05 CRT_CONN

5 4 3 2 1
5 4 3 2 1
ON/OFF switch
+3VL +3VALW K/B Connector
2
@ KSI[0..7]
KSI[0..7] 38
R90 R91
100K_0402_5% 100K_0402_5% KSO[0..17]
KSO[0..17] 38
+3VS
1
D15
NOVO# 2
38 NOVO# OK OK
1 NOVO_BTN# 14" 15"
1
3
JKB2 R96 R97
ON/OFF R102 1 2 0_0402_5% DAN202UT106_SOT323-3 300_0402_5% 300_0402_5%
27 JKB1
GND1 28 NUM_LED# 30 31
D 38 NUM_LED# D
2
CAPS_LED# 26 GND2 PWR_NUM_LED 29 30 GND1 32
38 CAPS_LED# 26 29 GND2
PWR_CAPS_LED 25 CAPS_LED# 28
Power Button KSO15
KSO10
24
23
25
24
PWR_CAPS_LED
KSO17
27
26
28
27
Reserved SW5 for debug on 20130926 KSO11 22 23 KSO16 25 26
22 25
ON/OFF switch KSO14
KSO13
21
20 21
KSO15
KSO10
24
23 24
SW5 KSO12 19 20 KSO11 22 23
1 3 +3VALW +3VL KSO3 18 19 KSO14 21 22
KSO6 17 18 KSO13 20 21
2 4 17 20
Power Button KSO8 16 KSO12 19
2
16 19
TOP Side KSO7 15 KSO3 18
SMT1-05_4P R121 R122 KSO4 14 15 KSO6 17 18
6
5
@ 100K_0402_5% 100K_0402_5% KSO2 13 14 KSO8 16 17

KSI0 12 13 KSO7 15 16
KSO1 11 12 KSO4 14 15
J19
1
KSO5 10 11 KSO2 13 14
R127
1 2 ON/OFFBTN# 1 2 0_0402_5% ON/OFF 10 13
Bottom Side ON/OFF 38 KSI3 9 KSI0 12
KSI2 8 9 KSO1 11 12
SHORT PADS KSO0 7 8 KSO5 10 11
@ KSI5 6 7 KSI3 9 10
KSI4 5 6 KSI2 8 9
KSO9 4 5 KSO0 7 8
KSI6 3 4 KSI5 6 7
KSI7 2 3 KSI4 5 6
KSI1 1 2 KSO9 4 5
1 KSI6 3 4
ACES_88514-02601-071 KSI7 2 3
KSI1 1 2
ME@ 1
ACES_50504-3041-001
ME@
TP/B Connector USB I/O Connector
+USB_VCCB
C +5VS TP_PWR C
TP_CLK
TP_DATA JUSB3
+3VS 18 20
R170 1 @ 2 18 G2
17 19
2
+3VS 0_0402_5% 17 G1
JTP1 DT1 16
USB20_P10 15 16
R169 1 2 1
1
OK14 USB20_P10
USB20_N10 14 15
0_0402_5%
38 TP_CLK
TP_CLK 2
2
OK14 USB20_N10
13 14
TP_DATA 3 13
0.1U_0402_10V7-K
38 TP_DATA 3 USB20_P4 12
1 4
4
OK 14 USB20_P4
USB20_N4 11 12
@ 1 @ 1 TP_P5 5 OK14 USB20_N4 11
100P_0402_50V8J
100P_0402_50V8J
TP_P6 6 5 7 10
6 GND1 9 10
8 9
2 GND2 8
C114
HP_OUTR 7 8
2 2 ACES_50503-0060N-001 34OK HP_OUTR
C115
C116
HP_OUTL 6 7
ME@ @ AZC199-02S.R7G_SOT23-3 34OK HP_OUTL 6
1
5
For EMC RING2_CONN 4 5
34 OK RING2_CONN 3 4
RING3_CONN 2 3
34 OK RING3_CONN 1 2
34 PLUG_IN PLUG_IN
1
TP_LEFT Button TP_LEFT Button OK ACES_50505-0184N-P01
TP_P5 TP_P5
ME@
5
1
AZ5215-01F_DFN1006P2E2
AZ5215-01F_DFN1006P2E2
SW1 SW2
EVQPLHA15_4P
EVQPLHA15_4P
A1
GND2 GND1
A1
GND2 GND1
A
A
1
1
DT2 DT3
For 14" For 15" PWR/B Connector
1
1
1 VDD 1 VDD
B1
B1
B
B
2
2
14@ 15@ +3VL

@ @
3
6
3
2
4
JPWRB1
2 CLK 2 CLK 1
1
NOVO_BTN# 2
ON/OFFBTN# 3 2
3
OK TP_RIGHT Button TP_RIGHT Button LID_SW# 4
3 DAT 3 DAT TP_P6 TP_P6 5 4
5
AZ5215-01F_DFN1006P2E2
6 7
6 GND1
1
8
D17 GND2
4 GND 4 GND
1
1
AZ5215-01F_DFN1006P2E2
AZ5215-01F_DFN1006P2E2
ACES_50503-0060N-001
SW3 SW4 ME@
EVQPLHA15_4P
EVQPLHA15_4P
A1
GND2 GND1
A1
GND2 GND1
A
B B
1
1
DT4 DT5
2
1
1
5 TP-L 5 TP-L @
2
LID_SW# 38
B1
B1
B
2
2
14@ 15@
6 TP-R 6 TP-R @ @
3
2
4
For EMC
For 14" For 15"
Right Side USB2.0 Port X 1 (USB/B)
+5VALW U5 +USB_VCCB
LED Add LED4,LED5,LED6 for 15" Delete JLED1 on due to both G14 and G15 move LED to MB 1
GND VOUT3
8
14@
C130 1 2 2 7
PWR_LED# LED1 1 2 1 2 300_0402_5% VIN1 VOUT2
38 PWR_LED# +5VALW
2.2U_0603_10V6-K 3 6
LTW-C193TS5 R150 VIN2 VOUT1
15@ 31,38 USB_ON# USB_ON# 4 5 USB_OC0#
EN/EN FLAG USB_OC0# 14
LED4 1 2
1
AP2820CMMTR-G1_MSOP8 C131
LTW-C193TS5 1000P_0402_50V7K
14@ Low Active 2A @
2
38 BATT_LOW_LED# BATT_LOW_LED# LED2 1 2 1 2 470_0402_5% +3VALW
LTST-C193KFKT-LC R151
15@
LED5 1 2
LTST-C193KFKT-LC
A A
38 BATT_CHG_LED# BATT_CHG_LED# LED3 1 2 14@ R152 1 2 300_0402_5% +5VALW
LTW-C193TS5
LED6 1 2 15@
LTW-C193TS5
Issued Date 2013/08/08 Deciphered Date 2013/08/05 KBD/PWR/IO/LED/TP Conn

5 4 3 2 1
A B C D E
USB20_P11_R
+USB_VCCA
LEFT SIDE USB3.0 PORT X2 USB20_N11_R
AZ5425-01F_DFN1006P2E2
AZ5425-01F_DFN1006P2E2
AZ5425-01F_DFN1006P2E2
1
1
U4 +USB_VCCA D9 D10 D11
+5VALW
1
1 8
GND VOUT3
1 2.2U_0603_10V6-K 2 7 1
VIN1 VOUT2
2
C69 1 2 3 6
VIN2 VOUT1 @ @ @
2
30,38 USB_ON# USB_ON# 4 5 USB_OC1#
EN/EN FLAG USB_OC1# 14
1
AP2820CMMTR-G1_MSOP8 C72
1000P_0402_50V7K
Low Active 2A @ USB20_P12_R
2 D12 @
USB30_RX_R_N1 9 10 1 1USB30_RX_R_N1 USB20_N12_R
AZ5425-01F_DFN1006P2E2
AZ5425-01F_DFN1006P2E2
USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1
1
D13 D14
USB30_TX_R_N1 7 7 4 4 USB30_TX_R_N1
1
USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1
3 3
2
8 @ @
2
AZ1045-04F_DFN2510P10E-10-9
2 2
+USB_VCCA
C66 1 2
+
220U_6.3V_M
L13
C67 1 2
USB20_N11 1 2 USB20_N11_R @ 1U_0603_25V6M
1 2
C68 1 2
USB20_P11 4 3 USB20_P11_R @ 470P_0402_50V7K
4 3
CMM21T-900M-N_4P
EMC@ JUSB1 ME@
1
USB20_N11 R72 1 @ 2 0_0402_5% USB20_N11_R 2 VBUS
14 USB20_N11 D-
USB20_P11 R71 1 @ 2 0_0402_5% USB20_P11_R 3
14 USB20_P11 D+
4 5
GND GND1 6
GND2 7
GND3 8
L14 GND4
3 C-K_20267-5K11-02 3
HDMI2012F2SF-900T04_4P
USB30_RX_P1 2 1 USB30_RX_R_P1
2 1
USB30_RX_N1 3 4 USB30_RX_R_N1
3 4 +USB_VCCA
EMC@
C73 1 2
L15 @ 1U_0603_25V6M
DLW21SN900HQ2L_4P
USB30_TX_C_P1 2 1 USB30_TX_R_P1 C74 1 2
2 1 @ 470P_0402_50V7K
USB30_TX_C_N1 3 4 USB30_TX_R_N1
3 4 JUSB2 ME@
EMC@ USB30_TX_P1 C75 1 2 0.1U_0402_10V7-K USB30_TX_C_P1 R75 1 @ 2 0_0402_5% USB30_TX_R_P1 9
L16 14 USB30_TX_P1 StdA_SSTX+
1
USB30_TX_N1 C76 1 2 0.1U_0402_10V7-K USB30_TX_C_N1 R76 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
USB20_N12 4 3 USB20_N12_R 14 USB30_TX_N1 StdA_SSTX-
USB20_P12 R77 1 @ 2 0_0402_5% USB20_P12_R 3
4 3 14 USB20_P12 D+
7
USB20_N12 R78 1 @ 2 0_0402_5% USB20_N12_R 2 GND_DRAIN 10
USB20_P12 1 2 USB20_P12_R 14 USB20_N12 D- GND_1
USB30_RX_P1 R79 1 @ 2 0_0402_5% USB30_RX_R_P1 6 11
1 2 14 USB30_RX_P1 StdA_SSRX+ GND_2
4 12
USB30_RX_N1 R80 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_5 GND_3 13
CMM21T-900M-N_4P 14 USB30_RX_N1 StdA_SSRX- GND_4
EMC@ SUYIN_020053GR009M2736L
4 4
For EMC
Issued Date 2013/08/08 Deciphered Date 2013/08/05 USB 3.0 PORT (LEFT)
A B C D E
A B C D E F G H
SATA HDD Conn.

ME@ FOR 14"
JHDD2
1
SATA ODD Conn.
SATA_FTX_DRX_P0 C77 1 2 .01U_0402_16V7-K SATA_FTX_C_DRX_P0 2 GND_1
13 SATA_FTX_DRX_P0 A+
13 SATA_FTX_DRX_N0 SATA_FTX_DRX_N0 C78 1 2 .01U_0402_16V7-K SATA_FTX_C_DRX_N0 3
4 A-
1 SATA_FRX_DTX_N0 C79 1 2 .01U_0402_16V7-K SATA_FRX_C_DTX_N0 5 GND_2 1
13 SATA_FRX_DTX_N0 SATA_FRX_DTX_P0 C80 1 2 .01U_0402_16V7-K SATA_FRX_C_DTX_P0 6 B- JODD1
13 SATA_FRX_DTX_P0 7 B+ 1
GND_3 SATA_FTX_DRX_P1 14@ C81 1 2 .01U_0402_16V7-K SATA_FTX_C_DRX_P1_14 2 GND_1
13 SATA_FTX_DRX_P1 RX+
13 SATA_FTX_DRX_N1 SATA_FTX_DRX_N1 14@ C82 1 2 .01U_0402_16V7-K SATA_FTX_C_DRX_N1_14 3
8 4 RX-
9 V33_1 SATA_FRX_DTX_N1 14@ C83 1 2 .01U_0402_16V7-K SATA_FRX_C_DTX_N1_14 5 GND_2
10 V33_2 13 SATA_FRX_DTX_N1 SATA_FRX_DTX_P1 14@ C84 1 2 .01U_0402_16V7-K SATA_FRX_C_DTX_P1_14 6 TX-
11 V33_3 13 SATA_FRX_DTX_P1 7 TX+
Need short 12 GND_4 GND_3
J4 @ 13 GND_5 ODD_DETECT#_R 8
1 2 +5VS_HDD 14 GND_6 9 DP
+5VS 1 2 V5_1 +5V_1
15 +5V_ODD 10
JUMP_43X79 16 V5_2 ODD_DA#_R 11 +5V_2 14
17 V5_3 12 MD GND1 15
18 GND_7 13 GND_4 GND2
19 DAS/DSS GND_5
20 GND_8 SUYIN_127382FB013S255ZL
+5VS 21 V12_1 ME@
22 V12_2
V12_3
@ 1 1 1 @ 1 1
C85 C86 C87 C88 C89 @ SUYIN_127043HR022M32QZR
1000P_0402_50V7K 0.1U_0402_10V7-K 1U_0603_25V6M 10U_0805_25V6K 10U_0805_25V6K
2 2 2 2 2
FOR 15"
2 2
For EMC
SATA ODD FFC Conn
Need open
J5 @
1 2
1 2
JODD2
JUMP_43X79 SATA_FTX_DRX_P1 15@ C90 1 2 .01U_0402_16V7-K SATA_FTX_C_DRX_P1_15 1
SATA_FTX_DRX_N1 15@ C91 1 2 .01U_0402_16V7-K SATA_FTX_C_DRX_N1_15 2 1
+5VALW +5VS +5V_ODD 3 2
LP2301ALT1G_SOT23-3 SATA_FRX_DTX_N1 15@ C92 1 2 .01U_0402_16V7-K SATA_FRX_C_DTX_N1_15 4 3
SATA_FRX_DTX_P1 15@ C93 1 2 .01U_0402_16V7-K SATA_FRX_C_DTX_P1_15 5 4
3 1 Q12 5
S
R81 6
1 2 ODD_DETECT#_R 7 6
1
14 ODD_DETECT# 7
10U_0805_25V6K
0.1U_0402_10V7-K
8
R83 R84 0_0402_5% 8
G
1 1 +5V_ODD 9
2
10K_0402_5% 10K_0402_5% ODD_DA#_R 10 9
0_0402_5%
2
1 10
@
R155
C156 @ 11
2
1
2 2 GND_1
C96
C97
1U_0603_10V6-K @ 12
R86 1 2 ODD_EN# R87 2 GND_2
100K_0402_5% 1 470_0603_5% ACES_51524-01001-003
1
C98 @ ME@
.01U_0402_16V7-K
2
1
Q13 D
2 2
13 ODD_EN
G
1
3 Q14 D 3
+3VS
2
S 2N7002KW_SOT323-3 ODD_EN# 2
3
R89 G
100K_0402_5% R85 @
@ S 2N7002KW_SOT323-3 1 2
3
1
10K_0402_5%
2
G
Q15
@
SUS Power Well
ODD_DA#_R 3 1
ODD_DA#_FCH 14
D
2N7002KW_SOT323-3
SB00000YY00
Core Power Well
R74 1 2
ODD_DA_INTH# 12
0_0402_5%
R158 1 @ 2 ODD_DA_EC#
ODD_DA_EC# 38
0_0402_5%
Follow Edge ODD_DA#_R schematic and reserve ODD_DA_EC# on 20130930
4 4
Issued Date 2013/08/08 Deciphered Date 2013/08/05 HDD/ODD CONN

A B C D E F G H
A B C D E
1 1
Mini-Express Card(WLAN/WiMAX) +3VS_WLAN
+3VS +3VS_WLAN
J3
@
1 2
1 2
JWLAN1
1 2 JUMP_43X79
3 GND1 3.3VAUX1 4
14 USB20_P6 USB_D+ 3.3VAUX2 +3VALW
5 6 1 @ T15 LP2301ALT1G_SOT23-3
14 USB20_N6 USB_D- LED#1
7
GND2 NC 8
D
Q10 3 1 AOAC@
9 NC NC 10
11 NC NC 12
13 NC NC 14 1
16 1 @ T16 C64
G
15
2
17 NC LED#2 18 0.1U_0402_10V7-K
19 MLDIR_SENSE GND16 20 AOAC@
21 DP_ML3N DP_AUXN 22 2
23 DP_ML3P DP_AUXP 24 R60 1 AOAC@ 2
38 AOAC_ON#
2 25 GND3 GND13 26 1
2
27 DP_ML2N DP_ML1N 28 100K_0402_5% C65
29 DP_ML2P DP_ML1P 30 0.1U_0402_10V7-K
31 GND4 GND14 32 AOAC@
33 DP_HPD DP_ML0N 34 2
35 GND5 DP_ML0P 36
5 PCIE_CTX_C_DRX_P2
37 PETP0 GND15 38 EC_TX_RSVD R64 1 @ 2 0_0402_5% EC_TX_R
5 PCIE_CTX_C_DRX_N2 39 PETN0 RESERVED1 40 1 2 0_0402_5%
EC_RX_RSVD R88 @ BT_OFF#
41 GND6 RESERVED2 42
5 PCIE_CRX_DTX_P2 43 PERP0 RESERVED3 44
5 PCIE_CRX_DTX_N2
45 PERN0 COEX3 46
47 GND7 COEX2 48
12 PCIE_WLAN_CLK_P2 49 REFCLKP0 COEX1 50 1 2 22_0402_5%
SUSCLK_R R61
12 PCIE_WLAN_CLK_N2 PCICLK0 12
51 REFCLKN0 SUSCLK 52 PLT_RST#
53 GND8 PERST0# 54 R62 1 2 PLT_RST# 12,17,35
WLAN_CLKREQ_Q# BT_OFF# 1K_0402_1%
PCH_BT_DISABLE# 12
R99 1 2 0_0402_5% WLAN_WAKE#_R 55 CLKREQ0# RESERVED/W_DISABLE#2 56 WLAN_OFF# R63 1 2 0_0402_5% FCH_WLAN_OFF#
38 WLAN_WAKE# FCH_WLAN_OFF# 12
57 PEWAKE0# W_DISABLE#1 58 SMB_DATA_S3_R R65 1 @ 2 0_0402_5%
59 GND9 I2C_DATA 60 1 2 SMB0_DATA 10,11,14
SMB_CLK_S3_R R66 @ 0_0402_5%
SMB0_CLK 10,11,14
61 PETP1 I2C_CLK 62 1
63 PETN1 I2C_ALERT# 64 T17 @
EC_TX_R
+3VALW R147 1 2 10K_0402_5% 65 GND10 RESERVED4 66
67 PERP1 PERST1# 68 +3VS_WLAN
R157 1 @ 2 10K_0402_5% 69 PERN1 CLKREQ1# 70
+3VS_WLAN
+3VS_WLAN 71 GND11 PEWAKE1# 72 follow edge to add debug port on 20131001
+3VS 73 REFCLKP1 3.3VAUX4 74
75 REFCLKN1 3.3VAUX5
GND12 EC_TX_R R184 1 2 100_0402_1% EC_TX
EC_TX 38
76 77
PEG1 PEG2
2
BT_OFF# R185 1 2 100_0402_1%

EC_RX 38
2
R67
G
Q11 10K_0402_5% JAE_SM3ZS067U410BAR1000
1
@
R187
1
1 3 WLAN_CLKREQ_Q# 100K_0402_5%
14 CLKREQ_WLAN#
D
2N7002KW_SOT323-3
2
3 3
1 2
R68 0_0402_5%
Connect CLKREQ_WLAN# and WLAN_CLKREQ_Q# directly and reserve Q11 on 20131004
Change R67 power rail from 3VS to +3VS_WLAN on 20131011
4 4
Issued Date 2013/08/08 Deciphered Date 2013/08/05 NGFF-Card / SSD

A B C D E
5 4 3 2 1
+3VS
RA2 1 2 0_0603_5% +3.3VD
+5VS
RA7 1 2 0_0603_5% +5VA 'delete 1.5VS power rail on DVDD_IO on 2013/10/9

+3VS
D D
RA10 1 2 0_0603_5% +5VD RA11 1 2 0_0402_5% DVDD_IO
0.1U_0402_10V7-K
Follow common design on 2013/10/9 Short GND and GNDA on groud layer of layout on 2013/11/17
2
CA1 RA1 1 2 0_0402_5%
@
1
GND GNDA
DA1
2 Close to Pin7 Close to Pin3
38 BEEP#
.1U_0402_10V6-K
1 PC_BEEP1 CA2 1 2 PC_BEEP
1
3
14 FCH_SPKR
RA14
0.1U_0402_10V7-K
4.7U_0603_10V6-K
BAT54CW_SOT323-3 10K_0402_5% CA16 close to Pin18
2 1 CA17 close to Pin2
Close to Pin27
2
1 2
CA3
1U_0402_6.3V6K
0.1U_0402_10V7-K
CA4
CA7
CA8
2 1
0.1U_0402_10V7-K
2.2U_0603_6.3V6K
UA1
2 1
CA5
CA6
HDA_RST_AUDIO# 9 3 FILT_1.8V
+3.3VD
14 HDA_RST_AUDIO# RESET# FILT_1.8V 7 DVDD_IO 1 2

VDD_IO 2
VDDO_3.3 1 2 +5VA
HDA_BITCLK_AUDIO 5 18 +3.3VD
0.1U_0402_10V7-K
14 HDA_BITCLK_AUDIO BIT_CLK DVDD_3.3
CA11
2
C HDA_SYNC_AUDIO 8 27 AVDD_3.3 2 C
RA15 14 HDA_SYNC_AUDIO RA16 SYNC AVDD_3.3 29 VREF_1.65V
5.11K_0402_1% 33_0402_5% 1 2 SDATA_IN 6 VREF_1.65V 28 +5VA
14 HDA_SDIN0 SDATA_IN AVDD_5V
1U_0402_6.3V6K
0.1U_0402_10V7-K
HDA_SDOUT_AUDIO 4 1
14 HDA_SDOUT_AUDIO SDATA_OUT
CA10
CA9
MICBIASB
CX20751-11Z 2 1
1
PC_BEEP 10 12 SPK_L+
RA17 1 2 JSENSE SPKR_MUTE# 39 PC_BEEP LEFT+ 14 SPK_L-
30 PLUG_IN SPKR_MUTE# LEFT-
39.2K_0402_1% DA5
JSENSE 38 17 SPK_R+ BAT54AWT1G_SOT323-3 1 2
LINE_B_R
Close to Pin28
LINE_B_L
JSENSE RIGHT+
1
RA36 1 2 37 15 SPK_R-
20K_0402_1% GPIO1/PORTC_R_MIC RIGHT-
36 35 Close to Pin29
33_0402_5% 1 RA18 2 DMIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34 MICBIASB
27 DMIC_CLK 1 DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB
0_0402_5% 1 RA19 2 DMIC_DATA_R
27 DMIC_DATA DMIC_DAT/GPIO1
1
33 LINE_B_R
2
0.1U_0402_10V7-K PORTB_R_LINE 32 LINE_B_L
+5VD 1 2 11 PORTB_L_LINE RA43 RA40
CA13 CLASS-D_REF 30 PORTD_A_MIC 100_0402_5% 100_0402_5%
13 PORTD_A_MIC 31 PORTD_B_MIC
2
LPWR_5.0 PORTD_B_MIC
2.2K_0402_1%
2.2K_0402_1%
16
RPWR_5.0
1
+5VD 25 RING2_CONN 1 1
HGNDA
RA37
RA38
CA14 1 2 1U_0402_6.3V6K 19 26 RING3_CONN +3VALW
20 FLY_P HGNDB CA35 CA38
FLY_N
CA16
CA19
CA15
CA18
4.7U_0603_10V6-K
0.1U_0402_10V7-K
4.7U_0603_10V6-K
0.1U_0402_10V7-K
24 4.7U_0603_10V6-K 4.7U_0603_10V6-K
CA17 1 2 2.2U_0603_6.3V6K 21 AVDD_HP 2 2
1 1 2 2
2
AVEE 23 HPOUT_R RA20 1 2 75_0402_1%
41 PORTA_R 22 HPOUT_L RA21 1 2 75_0402_1% HP_OUTR 30
GND PORTA_L HP_OUTL 30
2 2 1 1
CX20752-21Z_QFN40_5X5
RA22
B 1 2 100_0402_5% B
PORTD_A_MIC CA20 1 2 2.2U_0603_6.3V6K
0.1U_0402_10V7-K
1 2 100_0402_5% RING3_CONN 30
PORTD_B_MIC CA21 1 2 2.2U_0603_6.3V6K
CA12
2 RING2_CONN 30
RA23
Close to Pin11,13,16
1
HDA_RST_AUDIO#
Close to Pin24
+3.3VD
@ JSPK1 ME@
15_0402_5% 1 2 RA25 SPK_R+ RA26 1 2 0_0603_5% SPK_R+_CONN 1
1
1
RA27 1 @ 2 HDA_BITCLK_AUDIO 15_0402_5% 1 @ 2 RA29 SPK_R- RA31 1 2 0_0603_5% SPK_R-_CONN 2

RA28 27_0402_5% 15_0402_5% 1 2 RA32 SPK_L+ RA30 1 2 0_0603_5% SPK_L+_CONN 3 2
47K_0402_5% 15_0402_5% 1 @ 2 RA33 SPK_L- RA34 1 2 0_0603_5% SPK_L-_CONN 4 3
@ 4
CA25
CA22
5
@
2
@ GND1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
@
33P_0402_50V8J
22P_0402_50V8-J
CA31
CA32
CA33
CA34
RB751V-40_SOD323-2 @ 6
@ GND2
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
CA30
CA27
CA28
CA29
DA4 1 2 SPKR_MUTE# 1 1
2 2 2 2 1 1 1 1 ACES_88231-04001
EC_MUTE#
38 EC_MUTE#
2 2
1 1 1 1 2 2 2 2
@
@
@
RA35 1 2
0_0402_5%
A A
For EMI
Mounted DA4 for EC mirror function on 2013/12/5
Issued Date 2013/08/08 Deciphered Date 2013/08/05 Codec_CX20752

5 4 3 2 1
5 4 3 2 1
+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%):
+3VALW +3VALW_LAN
0.5msˉspecˉ100ms +3VALW_LAN +LAN_VDDREG
JUMP_43X79
JL1 1 2 width : 40 mils RL1 1 2 0_0603_5%
1 2
D D
@ 1 1
CL2 CL3
0.1U_0402_10V7-K
0.1U_0402_10V7-K
CL1 CL5
4.7U_0603_6.3V6-K
4.7U_0603_6.3V6-K
1 1 1 1 4.7U_0603_6.3V6K 0.1U_0402_10V7-K
CL6 CL7
2 2
@ 2 @ 2 2 2
Close to Pin11 +3VS

Close to Pin11
Close to Pin32 Close to Pin32

LAN_CLKREQ# RL4 1 2 4.7K_0402_5%
+3VALW_LAN
Vendor recommand reseve the
2 UL1 PU resistor close LAN chip
RL5
4.7K_0402_5%
@
1
33
LAN_WAKE# 32
+3VALW_LAN GND 16 PCIE_LAN_CLK_N0
C 38 LAN_WAKE# PCIE_LAN_CLK_N0 12
C
RL7 1 2 31
RSET AVDD33_2 REFCLK_N 15 PCIE_LAN_CLK_P0
RSET REFCLK_P PCIE_LAN_CLK_P0 12
2.49K_0402_1% 30
+LAN_VDD10 14 PCIE_CTX_C_DRX_N0
29 AVDD10 HSIN 13 PCIE_CTX_C_DRX_N0 5
LAN_XTALO PCIE_CTX_C_DRX_P0
CKXTAL2 HSIP PCIE_CTX_C_DRX_P0 5
28
LAN_XTALI 12 LAN_CLKREQ#
CKXTAL1 CLKREQB LAN_CLKREQ# 14
27 11 +3VALW_LAN
26 LED0 AVDD33_1 10 LAN_MDI3-
25 LED1/GPIO MDIN3 9 LAN_MDI3- 36
LAN_MDI3+
24 LED2 MDIP3 8 LAN_MDI3+ 36
+LAN_REGOUT +LAN_VDD10
+3VS +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
VDDREG MDIN2 LAN_MDI2- 36
+LAN_VDD10 22 6 LAN_MDI2+
LAN_WAKE# 21 DVDD10 MDIP2 5 LAN_MDI2+ 36
LAN_MDI1-
1
LANW AKEB MDIN1 LAN_MDI1- 36

ISOLATE# 20 4 LAN_MDI1+
RL9 19 ISOLATEB MDIP1 3 LAN_MDI1+ 36
PLT_RST# +LAN_VDD10
1K_0402_1% 12,17,33 PLT_RST# PERSTB AVDD10_1
5 PCIE_CRX_DTX_N0 CL10 1 2 0.1U_0402_10V7-K PCIE_CRX_C_DTX_N0 18 2 LAN_MDI0-
HSON MDIN0 LAN_MDI0- 36
5 PCIE_CRX_DTX_P0 CL11 1 2 0.1U_0402_10V7-K PCIE_CRX_C_DTX_P0 17 1 LAN_MDI0+
HSOP MDIP0 LAN_MDI0+ 36
2
ISOLATE#
1
RL11 RTL8111G-CG_QFN32_4X4
15K_0402_5% GIGA@
2
B delete LAN_PWR_ON# on 20131003 B
LAN_XTALI Reserve for RTL8111GS (SWR mode)

+LAN_VDD10
YL1 LAN_XTALO Close to Pin8,30 Close to Pin3,22
1 4
OSC1 GND2 +LAN_REGOUT LL1 1 2
2 3
GND1 OSC2 2.2UH_NLC252018T-2R2J-N_5% 1 1 1 1 1 1
1 1
CL15 CL16 CL17 CL18 CL19 CL20
CL12 25MHZ_10PF_7V25000014 CL13 4.7U_0603_6.3V6K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K
12P_0402_50V8-J 12P_0402_50V8-J 2 2 2 2 2 2
2 2
Layout Note: LL1 must be

within 200mil to Pin36,
CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil
A A

Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_RTL8106E/8111G
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
5 4 3 2 1
5 4 3 2 1
DL1/DL2 24
TL1 GIGA@
1 MCT
1'S PN:SC300003M00 LAN_MDI0- 23
MCT1 TCT1
2 LAN_MDO0-
35 LAN_MDI0- MX1+ TD1+
LAN_MDI0+ 22 3 LAN_MDO0+
35 LAN_MDI0+ MX1- TD1-
1
21 4 MCT RL20
D MCT2 TCT2 D
75_0603_5%
1
LAN_MDI1- 20 5 LAN_MDO1-
35 LAN_MDI1- MX2+ TD2+
DL1 DL4
1
2
LAN_MDI2+ 9 3 LAN_MDI3+ LAN_MDI1+ 19 6 LAN_MDO1+ BS4200N-C-LV_SMB-F2
2 I/O4 I/O2 35 LAN_MDI1+ MX2- TD2-
NC1
2
10 EMC@ 18 7 MCT
4 NC5 MCT3 TCT3
2
5 NC2 11 LAN_MDI2+ 17 8 LAN_MDO2+
+3VALW_LAN VDD GND 35 LAN_MDI2+ MX3+ TD3+
6 8 LAN_MDI2- 16 9 LAN_MDO2-
NC3 NC4 35 LAN_MDI2- MX3- TD3-
LAN_MDI2- 7 1 LAN_MDI3- 15 10 MCT
I/O3 I/O1 MCT4 TCT4
1 1
AZ3033-04F_DFN2525P10E10 LAN_MDI3+ 14 11 LAN_MDO3+ CL33
35 LAN_MDI3+ MX4+ TD4+
0.1U_0603_25V7K
10P_0603_50V8-J CL32
1 LAN_MDI3- 13 12 LAN_MDO3- @ 1000P_1206_2KV7-K
35 LAN_MDI3- MX4- TD4- 2 2
Place Close to TL1
BOTH_GST5009-E-LF
2
CL24
DL2
LAN_MDI1+ 9 3 LAN_MDI0+
2 I/O4 I/O2
NC1 10
C EMC@ C
4 NC5 CHASSIS1_GND
5 NC2 11
+3VALW_LAN VDD GND
6 8
NC3 NC4
LAN_MDI1- 7 1 LAN_MDI0-
I/O3 I/O1
AZ3033-04F_DFN2525P10E10
Place Close to TL2
SANTA_130460-3 ME@
12
GND_4
11
GND_3
10
LAN_MDO0+ 1 GND_2
PR1+ 9
B B
LAN_MDO0- 2 GND_1
PR1-
LAN_MDO1+ 3
PR2+ CHASSIS1_GND
LAN_MDO2+ 4
PR3+
LAN_MDO2- 5
PR3-
LAN_MDO1- 6
PR2-
LAN_MDO3+ 7
PR4+
LAN_MDO3- 8
PR4-
@ CL26 1 2 470P_0402_50V7K
JRJ1
@ CL27 1 2 10U_0805_10V6K
CL28 1 2 0.1U_0603_25V7K
CL29 1 2 0.1U_0603_25V7K
@ CL30 1 2 10U_0603_6.3V6-M
A A
@ CL31 1 2 470P_0402_50V7K

CHASSIS1_GND
Reserve for EMI go rural solution
Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_Transformer
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
5 4 3 2 1
5 4 3 2 1
D Close U3 D
REMOTE+_R SMSC thermal sensor

1
C57
2200P_0402_50V7K
placed near DIMM
2 REMOTE-_R +3VS
U3
1 8 EC_SMB_CK3
VDD SCL EC_SMB_CK3 7,14,18,38
1 REMOTE+_R 2 7 EC_SMB_DA3
D+ SDA EC_SMB_DA3 7,14,18,38
C59 REMOTE-_R 3 6
0.1U_0402_10V7-K D- ALERT#
2 R54 2 @ 1 4 5
+3VS T_CRIT# GND
10K_0402_5%
NCT7718W _MSOP8
Address 1001_101xb
REMOTE1+
Near GPU&VRAM
C C
1
1
DIS@ C58 C
REMOTE1+ R55 1 2 0_0402_5% 100P_0402_50V8J 2 Q9
UMA@ DIS@ B MMST3904-7-F_SOT323-3
REMOTE2+ R56 1 2 0_0402_5% REMOTE+_R 2 E DIS@
3
UMA@ REMOTE1-
REMOTE2- R57 1 2 0_0402_5% REMOTE-_R
REMOTE1- R58 1 DIS@ 2 0_0402_5%
REMOTE2+
Near CPU core
1
1
C70 C
100P_0402_50V8J 2 Q16
B MMBT3904W H_SOT323-3
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: 2 E
3
Trace width/space:10/10 mil REMOTE2-
Trace length:<8"
FAN Conn
B B
+5VS
JFAN1
R59 1 2 +5VS_FAN 1
0_0603_5% 2 1
38 EC_FAN_SPEED 2
2 1 38 EC_FAN_PW M 3
C60 C61 4 3
10U_0805_25V6K 0.1U_0402_10V7-K 5 4
@ 6 GND1
1 2 GND2
ACES_85205-04001
ME@
A A

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Thermal sensor/FAN CONN
5 4 3 2 1
5 4 3 2 1
+3VALW_R +3VALW_EC
RE1 1 2 0_0603_5%
+3VL
LE1 1 2 BLM18PG181SN1D_0603
@ 1 1
RE3 1 2 0_0603_5% CE4
Close EC +3VALW
0.1U_0402_10V7-K CE5
1000P_0402_50V7K
CE3 +3VALW_R LE2 1 2 2
BLM18PG181SN1D_0603 EC_AGND 2
D 1 2 VCOREVCC D
0.1U_0402_10V7-K +3VALW_R All capacitors close to EC EC_AGND
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
1 1 1 1 1 1
+3VS +3VALW_EC CE6 CE7 CE8 CE9 CE10 CE11
Dlete +RTCBATT at UE1.3 on 1003 @

2 2 2 2 2 2 +3VALW_R
RE6 1 2 0_0402_5%
LAN_WAKE# RE5 1 2 10K_0402_5%
@
SUSP# RE18 1 @ 2 100K_0402_5%
minimum trace width 12 mil
114
121
127
Change RE6 to 0ohm jump RPC15
12
26
50
92
74
11
3
UE1 EC_SMB_CK1 1 8
EC_SMB_DA1 2 7
AVCC
VCC
VCORE
VBAT
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY(PLL)
EC_SMB_CK3 3 6
Please change net name VGA_AC_DET on page51 EC_SMB_DA3 4 5
+3VS
to another net name XXX and spare one EC pin for this pin name XXX !!! 2.2K_0804_5%
SD30922018J
KBRST# 4 24 Follow Edge to change UE1.Pin120 from LAN_WAKE# to BATT_LEN# on 0927
+3VALW_R 14 KBRST# KBRST#/GPB6 PWM0/GPA0 PWR_LED# 30
SERIRQ 5 25
12 SERIRQ SERIRQ/GPM6 PWM1/GPA1 BATT_CHG_LED# 30
LPC_FRAME# 6 28
12 LPC_FRAME# LFRAME#/GPM5 PWM2/GPA2 BATT_LOW_LED# 30
LPC_AD3 7 29 VGA_AC_BATT
1 2 12 LPC_AD3 8 LAD3/GPM3 PWM3/GPA3 30 VGA_AC_BATT 18 EC_FAN_SPEED RE10 1 2 10K_0402_5%
DE1 LPC_AD2 PWM
12 LPC_AD2 9 LAD2/GPM2 PWM4/GPA4 31 ODD_DA_EC# 32
LPC_AD1 EC_FAN_PWM
12 LPC_AD1 LAD1/GPM1 PWM5/GPA5 EC_FAN_PWM 37 BATT_LEN# for S5 plus function on 20130927 EC_FAN_PWM RE11 1 @ 2 10K_0402_5%
LPC_AD0 10 32
RB751V-40_SOD323-2 12 LPC_AD0 LAD0/GPM0 PWM6/SSCK/GPA6 BEEP# 34 Follow Edge to change UE1.Pin29 from BATT_LEN# to VGA_AC_BATT on 0927
CLK_PCI_EC 13 LPC 34 S5_1.1V_EN
12,16 CLK_PCI_EC LPCCLK/GPM4 PWM7/RIG1#/GPA7 S5_1.1V_EN 49 LPC_FRAME# RE7 1 2 10K_0402_5%
RE8 1 2 100K_0402_5% WRST# 14 120
1 RE4 @ 2 15 WRST# TMRI0/GPC4 124 BATT_LEN# 44
18,51 GPU_VR_HOT# GPU_VR_HOT# SUSP#
16 ECSMI#/GPD4 TMRI1/GPC6 SUSP# 39,47,48,50,51
1 EC_RX 0_0402_5%
33 EC_RX PWUREQ#/BBO/SMCLK2ALT/GPC7
EC_TX 17 66 NTC_V 43
CE12 33 EC_TX LPCPD#/GPE6 ADC0/GPI0 Delete TURBO_V on UE1.67 ,PWR unused TP_CLK RE12 2 1 4.7K_0402_5%
EC_A_RST# 22 67
1U_0402_6.3V6K 12 EC_A_RST#
EC_SCI# 23 LPCRST#/GPD2 ADC1/GPI1 68 BATT_TEMP
2 14 EC_SCI# 126 ECSCI#/GPD3 ADC2/GPI2 69 BATT_TEMP 44,45 TP_DATA RE13 2 1 4.7K_0402_5%
GATEA20 ADC Board_ID
14 GATEA20 GA20/GPB5 ADC3/GPI3 70
delete net name EC_SMI# on UE1.Pin15 on 20130928
IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
Need to check with PWR and Edge schematic if change net name ADAPTER_ID to ADP_ID!!
ADP_I 45 check with AMD one EC pin to add VGA_IMON,change VGA_IMON to APU_IMON on 1003
30 KSI[0..7]
Add GPU_VR_HOT on UE1.Pin15 on 20130930
KSI[0..7] KSI0 58
KSI0/STB#
LQFP-128L ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73
APU_IMON
ADAPTER_ID
52
43 +3VL
KSI1 59 78
KSO[0..17] KSI1/AFD# DAC2/TACH0B/GPJ2 IMVPPOK 52 Follow Edge to change UE1.Pin78 from 1V_ALW_EN to IMVPPOK on 0927 ON/OFF RE35 1 @ 2 10K_0402_5%
KSI2 60 79
30 KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 MAINPWON 43,46
KSI3 61 DAC 80 H_PROCHOT#_EC
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81
KSI4 DAC5/RIG0#/GPJ5 APU_ENBKL 7
C KSI5 63 C
KSI6 64 KSI5 85 DGPU_PWROK_E 2 RE109@1 DGPU_PWROK LID_SW# RE38 1 2 10K_0402_5%
KSI6 PS2CLK0/TMB0/CEC/GPF0 0_0402_5% DGPU_PWROK 12,51
KSI7 65 86
KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# 14 +5VALW
KSO0 36
KSO0/PD0 GPF2
87
delete PM_SLP_SUS# on UE1.87 ,this net for Intel deep sleep ,no need
add DGPU_PWROK to UE1.85
EC_SMB_CK1 PAD 1 @ KSO1 37 Int. K/B PS2 88
1 IT1 38 KSO1/PD1 GPF3 89
EC_SMB_DA1 PAD @ KSO2 TP_CLK
PAD 1 @
IT2
KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 TP_DATA
TP_CLK 30 USB_ON# RE15 1 210K_0402_5%
1 IT3 KSO3/PD3 PS2DAT2/GPF5 TP_DATA 30
CE90 PAD 1 @ KSO4 40
IT4 KSO4/PD4
22P_0402_50V8-J @ PAD 1 @ KSO5 41 EXTERNAL SERIAL FLASH 96 CAPS_LED#
IT5 KSO5/PD5 GPH3/ID3 CAPS_LED# 30
KSO6 42 97
2 43 KSO6/PD6 GPH4/ID4 98 APUPWR_EN 52
KSO7
44 KSO7/PD7 GPH5/ID5 99 ACOFF 45 SUSP# RE19 1 2 100K_0402_5%
KSO8
KSO8/ACK# GPH6/ID6 FCH_PWROK 14
KSI7 PAD 1 @ KSO9 45
IT6 KSO9/BUSY Follow Edge to change UE1.Pin97 from FCH_PWR_EN to APUPWR_EN SYSON RE21 1 @ 2 100K_0402_5%
KSI6 PAD 1 @ KSO10 46 101 EC_SPI_CS1#
IT7 KSO10/PE NC1
WRST# PAD 1 @ KSO11 51 102 EC_SPI_SI
IT8 52 KSO11/ERR# NC2 103
KSO12 SPI Flash ROM EC_SPI_SO
reserved CE90 for EMC request KSO13 53 KSO12/SLCT NC3 105 EC_SPI_CLK
KSO14 54 KSO13 NC4
For factory EC flash KSO14 Follow Edge to change UE1.Pin108 from ACIN# to ACPRN on 20131003
KSO15 55
KSO16 56 KSO15 108 ACPRN
KSO16/SMOSI/GPC3 AC_IN# ACPRN 45
KSO17 57 UART 109 LID_SW#
KSO17/SMISO/GPC5 LID_SW# LID_SW# 30
Follow Edge to change UE1.Pin117 from PECI_EC to VDDAPWROK on 0927 Delete VDDQ_PGOOD EC pin83 and VGA_GATE# pin82 to add FCH_PWR_EN BATT_TEMP @ CE16 1 2 100P_0402_50V8J
0_0402_5% RE16 @
30 ON/OFF ON/OFF 110 82 2 1 VDDQ_PGOOD
PWRSW# EGAD/GPE1 VDDQ_PGOOD 47
EC_ON 1 @ RE42 2 111 SM Bus 83 EC_ON_R 2 RE50 1 EC_ON
0_0402_5% 115 XLP_OUT EGCS#/GPE2 84 0_0402_5% EC_ON 46,49
EC_SMB_CK1 ADAPTER_ID_ON# 43
44,45 EC_SMB_CK1 116 SMCLK1/GPC1 EGCLK/GPE3 ON/OFF @ CE18 1 2 1U_0402_6.3V6K
EC_SMB_DA1
44,45 EC_SMB_DA1 SMDAT1/GPC2
50,52 VDDAPWROK VDDAPWROK 117 GPIO 77 PM_SLP_S5#
SMCLK2/PECI/GPF6 GPJ1 PM_SLP_S5# 14
delete LAN_PWR_ON# on 20131003 118 100 EC_MUTE#
SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 EC_MUTE# 34
EC_SMB_CK3 94 106 FCH_PWR_EN
7,14,18,37 EC_SMB_CK3 95 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 104 FCH_PWR_EN 44
EC_SMB_DA3
+3VL 7,14,18,37 EC_SMB_DA3 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 Delete BATT_OUT EC pin106 and add FCH_PWR_EN on UE1.106
SYSON
Delete LAN_PWR_ON# at UE1.118 on 20131003 DTR1#/SBUSY/GPG1/ID7 SYSON 47
119 EC_BKOFF#
CRX0/GPC0 EC_BKOFF# 27
RE27 1 @ 2 0_0402_5% +3VL_VSTBY0 123
CTX0/TMA0/GPB2 AOAC_ON# 33
112 18
VSTBY0 RI1#/GPD0 PM_SLP_S3# 14
Change RE24 to 0ohm jump 35 LAN_WAKE# LAN_WAKE# 125
GPE4 RI2#/GPD1
21
76 delete EC_LID_OUT# from UE1.Pin21 and UH2.R2 ,due to EC_WAKE# can handle its function,too AC IN
WAKE UP TACH2/GPJ0 NOVO# 30
48
TACH1A/TMA1/GPD7 EC_TS_ON# 27 +3VL
47 EC_FAN_SPEED EC_FAN_SPEED 37
USB_ON# 33 TACH0A/GPD6 19 WLAN_WAKE# @
30,31 USB_ON# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 WLAN_WAKE# 33 ACPRN RE25 1 2 10K_0402_5%
FCH_S5 35 GPIO 20
12 FCH_S5 93 RTS1#/GPE5 L80LLAT/GPE7 NUM_LED# 30
EC_RSMRST#
14 EC_RSMRST# CLKRUN#/GPH0/ID0
Follow Edge to change UE1.Pin35 from VSB_ON to FCH_S5 on 0927
EC_WAKE# 2 delete VGA_AC_DET from UE1.Pin19 ,change to net name to WLAN_WAKE# .And change to VGA_AC_BATT control
14,18 EC_WAKE# 1 2 0_0402_5% 128 CK32KE/GPJ7 Mounted for EC mirror function on 2013/12/5 +3VL
AC_PRESENT Clock
14 AC_PRESENT CK32K/GPJ6
RE33 RE54 @
Follow Edge to delete VGA_AC_DET on 0927 EC_ON 1 2
B B
100K_0402_5%
AOAC_ON# RE23 1 2 100K_0402_5%
EC_RSMRST#
AVSS
VSS2
VSS3
VSS4
VSS5
VSS6
VSS1
Mounted for EC mirror function on 2013/12/5
1
IT8586E-AX_LQFP128_14X14 RE51
27
49
91
113
122
75
1
Follow Edge to add PL resistor 100K for AOAC_ON# on 20130929 100K_0402_5% @
2
+5VS +3VS
EC_AGND
RE37 1 2 0_0402_5% RE34 1 2 0_0402_5% H_PROCHOT# 7
J80P1 ME@ 52 VR_HOT#
RE39 1 @ 2 0_0402_5%
1
1 QE1 D 1
EC_TX 2 1 H_PROCHOT#_EC 2 CE14
EC_RX 3 2 G 47P_0402_50V8J
4 3 @
4
1
5 2N7002KW_SOT323-3 S 2
3
RE41 6 GND1
100K_0402_5% @ GND2
ACES_85205-04001
2
when mirror, RE45 RE47 RE48 RE49 mounted

Add Board ID ,please check with Edge
when no mirror, RE45 RE47 RE48 RE49 reserved
@ 3.3V +/- 5%
EC_SPI_CS1# RE45 2 1 0_0402_5% SPI_CS1#
SPI_CS1# 13 +3VL
Vcc
RE33 100K +/- 1%
EC_SPI_SI RE47 2 @ 1 0_0402_5% SPI_SI
SPI_SI 13 Board ID min typ
RE34 VAD_BID V AD_BID VAD_BID max Phase
2
@
EC_SPI_SO RE48 2 1 0_0402_5% SPI_SO RE52 0 0K +/- 5% 0 V 0 V 0 V SDV
SPI_SO 13 10K_0402_5%
@
@ 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
EC_SPI_CLK RE49 2 1 0_0402_5% SPI_CLK
1
SPI_CLK 13 18K +/- 5%

Mounted RE43 for EC mirror function on 2013/12/5 Board_ID
2 0.436 V 0.503 V 0.538 V
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
2
A A
when mirror, GPG2 pull high EMI/ESD RE53 4 4.7K +/- 5% 0.141 V 0.148 V 0.155 V
when no mirror, GPG2 pull low 10K_0402_5%
24K +/- 5%
EC_A_RST# CLK_PCI_EC RE2 1 @ 2 10_0402_5% SYSON +3VS @ 5 0.612 V 0.638 V 0.664 V
Mounted RE43 for EC mirror function on 2013/12/5
1
@ 1 1
EC_MUTE# RE43 2 1 10K_0402_5% +3VL 1 1
CE1 CE2 CE19
RE46 2 @ 1 10K_0402_5% 220P_0402_50V7K 10P_0402_50V8J CE13 @ 0.1U_0402_10V7-K
+3VALW_R 2 2
@ 0.1U_0402_10V7-K
1 2 2 2
RE44 100K_0402_5%
Issued Date 2013/08/08 Deciphered Date 2013/08/05 EC ITE8586LQFP

5 4 3 2 1
A B C D E
1 1
R164
Load Switch 1
0_0402_5%
2 3VSON
+5VALW To +5VS +5VS, C159 --> 1.5ms

+3VALW To +3VS +3VS, C160 --> 2.5ms C146
1
1U_0402_6.3V6-K
+3VALW VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm +3VS
2
U13 J9 @
1 14 +3VS_LS 1 2
2 VIN1_1 VOUT1_2 13 1 2
VIN1_2 VOUT1_1 JUMP_43X118
1 1
3VSON 3 12 C160 1 2 1000P_0402_25V7-K R165
C162 @ ON1 CT1 C159 @ SUSP# 1 2 5VSON
1U_0402_6.3V6-K 4 11 0.1U_0402_10V7-K 0_0402_5%
2 +5VALW VBIAS GND 2
5VSON 5 10 C157 1 2 2200P_0402_25V7-K
+5VALW
6
7
ON2
VIN2_1 VOUT2_2
CT2
9
8 +5VS_LS 1
J10 @
2
+5VS
C147
1U_0402_6.3V6-K
1
Delete +3VALW To +3VALW_FCH on 20131001
VIN2_2 VOUT2_1 1 2
2
1 15 JUMP_43X118 1
GPAD
C161 @ TPS22966DPUR_WSON14_2X3 C158 @
1U_0402_6.3V6-K 0.1U_0402_10V7-K
2 2
R164 and R165 to adjust 3VALW and 5VALW timing

2 2
1.1VS :4A Update Load Switch +1.1VALW to +1.1VS to AON6414AL on 20130926 +VDDIO to +VDDIO_RUN
Load Switch
+1.1VALW to +1.1VS +1.1VALW
Need OPEN +1.1VS
J20 1 2 @ Need OPEN

1 2 C166 C233
C167 JUMP_43X118 +1.35V_APU_VDDIO +1.35V_APU_VDDIO_RUN
.1U_0402_16V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1 AON6414AL_DFN8-5 1 1
R162
1 470_0603_5% J11 1 2 @
1 2
2 @
2 5 3 2 2 JUMP_43X39
.1U_0402_16V7K
1
1 2
1
D Q22 R163
C234 @ @ 470_0603_5%
U14 2 SUSP
4
D
+VSB G Q27 3 1
2
1 2
1 2 R161 S 2N7002KW_SOT323-3 LP2301ALT1G_SOT23-3
3
D Q24
G
100K_0402_5% @
2
2 SUSP
1
R154 @ G
1
1
D R160 C168 SUSP 1 2

SUSP 2 Q21 120K_0402_5% 0.1U_0402_16V4Z S 2N7002KW_SOT323-3
From FCH 0_0402_5%
3
G 1 0.1U_0402_10V7-K
2
2
S C128
3
2N7002KW_SOT323-3
2
3 For DisCharge 3
+5VALW +0.675VS
1
R153 R149
100K_0402_5% 22_0805_5%
2
+0.95VS +0.95VS_VDDP +1.8VS +1.8VS_VDDA

J18 @
SUSP 1 2 1
R159
2 0.5A
1 2
0_0805_5%
JUMP_43X118
6
D D Q44B
SUSP# 2 Q44A 5 SUSP
38,47,48,50,51 SUSP# G G
+0.95VS +0.95VS_VDDR
S S 2N7002KDWH_SOT363-6 J15 @ +1.35V_DDR_VDDIOSUS +1.35V_APU_VDDIO
2N7002KDWH_SOT363-6
1
SB00000EO1J 1 2
SB00000EO1J 1 2
JUMP_43X118
Short +1.35V_DDR_VDDIOSUS & +1.35V_APU_VDDIO directly on 20130930
4 4
www.vinafix.vn
Issued Date 2013/08/08 Deciphered Date 2013/08/05 DC V TO VS INTERFACE

A B C D E
1 2 3 4 5
A A
CPU Plate
H7 H8 H9 NH5 NH6 NH7 NH1
HOLEA H10 HOLEA HOLEA HOLEA HOLEA
HOLEA HOLEA HOLEA
1
1
1
1
PAD_C2P3D2P3N PAD_O2P3X2P8D2P3X2P8N PAD_O2P3X2P8D2P3X2P8N PAD_C2P3D2P3N
PAD_CT6P5B5P0D4P0 PAD_CT6P5B5P0D4P0
PAD_CT6P5B5P0D4P0
PAD_CT6P5B5P0D4P0
Close to H7
H25 H26
HOLEA HOLEA
1
Pad_C6P0D3P3 Pad_C6P0D3P3
PCH Plate H1 H2 H3 H4 H5 H6 H11 H12

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
B B
1
pad_sht7p0x6p65b10p66x9p9d2p8 PAD_CT6P0B7P0D2P3 Pad_ct8p0b9p0d2p8 Pad_ct8p0b9p0d2p8 PAD_SHAPET8P8X8P0B9P0D2P8 PAD_SHAPET8P8X8P0CB9P0D2P8 pad_ct6p0d4p3 Pad_ct6p0b8p0d4p6
H19
HOLEA
H13 H14 H15 H16 H17 H18 H20 H22 H23 H24 H21
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
1
1
PAD_SHAPET5P0X6P0-D
CHASSIS1_GND
pad_cb8p0d7p0 pad_ct6p0shapeb8p0x6p75d2p3 PAD_CT6P0shapeb10p04x10p0d2p8 pad_ct6p0b7p0d2p3 pad_shapet6p8x8p0cb8p0d2p5 PAD_SHAPET5P0X6P0-U PAD_CT5P5B6P0D3P3 PAD_CT5P5B6P0D3P3 PAD_CT5P5B6P0D3P3 PAD_CT5P5B6P0D3P3
PAD_CT5P5B8P0D2P5
C C
PCB Fedical Mark PAD

FD1 FD2 FD3 FD4 FD5 FD6
1
D D

Issued Date 2012/07/01 Deciphered Date 2014/07/01 SCREW
1 2 3 4 5
5 4 3 2 1
D D
AMD Kaveri Platform G3 1.+RTCBATT

System power on G3 --> S5 --> S0 BTY 2.+VIN
BTY Charger 2
3.B+
Singnal VIN GATE 4.+3VL/+VL
PBT +VIN AC in
5.ACPRN (BTY Charger to EC)
Power 3 S5
B+ 6.EC_ON (EC to Power IC)
7.FCH_S5(FCH to EC)
11 9 9
RTC BTY ON/OFFBTN# +5VALW 8.S5_1.1_EN(EC to Power IC)
5
+3VALW PU6 PU5 9.+5VALW/+3VALW/+1.1VALW
1
+RTCBATT ACPRN
10.EC_RSMRST#(EC to FCH)
4
9
System Ready!! +3VL/+VL PU10 +1.1VALW 11.ON/OFFBTN# (PBTN to EC)
C
10 EC_RSMRST# 12.PBTN_OUT# (EC to FCH) C
13.PM_SLP_S5# (FCH to EC)

12 PBTN_OUT# 6 EC_ON 14.PM_SLP_S3# (FCH to EC)
AMD FCH 8 S5_1.1_EN
15.SYSON (EC to Power IC)
Bolton 13 PM_SLP_S5# 16.+1.35VS/+0.675VS
+1.35VS
14 PM_SLP_S3# 15 SYSON 16
+0.675VS 17.SUSP# (EC to Power IC)
EC PU7
18.+3VS/+5VS
ITE IT8586E-CX
BGA-656 23 FCH_PWROK +3VS 18.+1.5VS
24.5mm*24.5mm 17 SUSP# 18
S0
+5VS 18.+1.1VS
U13
7 FCH_S5 18.+1.8VS
18
19.VDDAPWROK(Power IC to EC)
+1.5VS
PU8 20.APUPWR_EN(EC to VRM)
21.+0.95VS
B
18
+1.1VS 21.+VDD_VORE/+VDDNB_VORE B
PU10 22.IMVPPOK (VRM to EC)

APU_PWROK 22 IMVPPOK 23.FCH_PWROK(EC to FCH)
24
18 24.APU_PWROK(FCH to APU)
+1.8VS
25 PLT_RST AMD APU PU15
25.PLT_RST (FCH to APU)
Kaveri 21 +VDD_CORE
19 26.APU_RESET(FCH to APU)
APU_RESET VDDAPWROK
26 BGA-631 PU14
32mm*29mm 21 +VDDNB_CORE
20 APUPWR_EN 21 +0.95VS
PU9
A A
Issued Date 2013/08/08 Deciphered Date 2013/08/05 Power sequence block

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Virtual symbol
5 4 3 2 1
5 4 3 2 1
PL28
HCB2012KF-121T50_0805
VIN RTC_VCC +3VL VCCRTC
1 2
PL27
2
JDCIN1 PF1 HCB2012KF-121T50_0805
1 APDIN 1 2 APDIN1 1 2 PD1
1 2
D
2 RB751V-40_SOD323-2 D
3 7A_24VDC_429007.W RML
3 4 JRTC1 PR1 PR4
470P_0402_50V7K
470P_0402_50V7K
1000P_0402_50V7K
1
4 5 560_0603_5% 560_0603_5%
1000P_0402_50V7K
5 ADAPTER_ID 38
1
2 1 1 2 1 2 BAT_D 2 1
PC3
PC4
1
1
PC1
PC2
ACES_50299-00501-003
ME@ PD2
2
@ RB751V-40_SOD323-2
2
@ FDK_ML1220-TT28
<BOM Structure>
+3VALW
VIN
C C
1
PR79 PR80 PH1 under CPU botten side :

750_0603_1% 1M_0402_5%
CPU thermal protection at 92+-3 degree C
Recovery at 56 +-3 degree C
2
+5VLP
2
PR84
D
2 ADAPTER_ID_ON#_G +3VALW +3VL
0_0402_5% G 2
1
@
1
S PQ28A PC12 @ PR30 @
1
2N7002KDW H_SOT363-6 0.1U_0402_25V6-K 47K_0402_1% PR18 @ PR19

1 13.7K_0402_1% 61.9K_0402_1%
ADAPTER_ID
SDV
2
1
D PU2
2
2 ADAPTER_ID_ON# 38 1 8 NTC_V_1
VCC TMSNS1
1
PR89 G
1M_0402_5% 2 7 OTP_N_002 2 1
SDV
0.1U_0402_25V6
S PQ27A GND RHYST1

2
1
1
2N7002KDW H_SOT363-6 2 1 OTP_N_003 3 6 PR21 @

PC45
PD6 38,46 MAINPWON OT1 TMSNS2 10K_0402_1%
1
B AZ5425-01F_DFN1006P2E2 @ PR29 4 5 B
2
OT2 RHYST2
2
2
0_0402_5%
G718TM1U_SOT23-8 PR82
2
@ 0_0402_5%
2
PH1
1
100K_0402_1%_NCP15W F104F03RC
38 NTC_V
A A
Issued Date 2013/08/15 Deciphered Date 2013/08/15 DCIN / RTC

5 4 3 2 1
5 4 3 2 1
SDV
VMB PL29
HCB2012KF-121T50_0805
VMB2
SDV
VMB2 1 2
JBATT2
PF2 PL30 1
JBATT1 8A_24V_F1206HI8000V024T HCB2012KF-121T50_0805 1 2
1 1 2 1 2 2 3 EC_SMCA
1 2 BATT+ 3 4 EC_SMDA
2 3 EC_SMCA PR16 1 2 100_0402_1% 4 5 BATT_TEMP_IN
3 EC_SMB_CK1 38,45 5
D 4 EC_SMDA PR15 1 2 100_0402_1% EC_SMB_DA1 38,45 6 D
4 6
2
5 7
5 6 PR23 PC11 PC10 7 8
6 7 100K_0402_1% 1000P_0402_50V7K 0.01U_0402_25V7K GND1 9
2
7 8 1 2 GND2
GND1 +3VALW
1
9
GND2 SUYIN_200082GR007G232ZR
1
BATT_TEMP_IN 1 2 ME@
BATT_TEMP 38,45
SUYIN_200082GR007G232ZR PD10 @
ME@ PR27 AZC199-02S.R7G_SOT23-3
2
10K_0402_5%
For 15
2
@ PD9
For 14
1
AZ5215-01F_DFN1006P2E2
C C
P2 +3VALW +3VALW PR40 @

0_0603_5%
1 2
1
VMB2 PC15
2
0.01U_0402_25V7K 2
PR41 PR42 3 1
B+ +VSBP
2
100K_0402_1% 100K_0402_1%
PR72
100K_0402_1%
0.22U_0603_25V7K
1
1
10M_0402_5%
1
1
PR44 1 2
PR43
PC16
BATT_OUT 45
220K_0402_1% PC17
0.1U_0603_25V7-M
2
8
1 2
2
2
3
3 D PR46
P
PR45 +_1 1 DC_UVP_2 5 22K_0402_1%

O1
PC18 @
10K_0402_1% 2 G 1 2 VSBP_3
0.1U_0402_25V6
-_1
G
1
PU3A PQ4
VSBP_2
1
PR47 AS393MTR-G1_SO8 PQ25B S TP0610K-T1-E3_SOT23-3

4
150K_0402_1% 2N7002KDW H_SOT363-6

2
PJ1
2
+3VALW @ PR48 JUMP_43X39
1
B 1 2 0_0402_5% D 1 2 B
+3VL 46,48,50 ALW _PW RGD
1 2 VSBP_1 2 +VSBP 1 2 +VSB
PR49 G
10K_0402_1% PQ5
2
1
PR51 S 2N7002KW _SOT323-3
3
PR50 1K_0402_1% PC19 @
100K_0402_1% 1 2 1U_0402_6.3V6K
38 FCH_PW R_EN
2
1
PR52
6
10K_0402_1% D
1 2 2
38 BATT_LEN# G
PQ25A S
1
2N7002KDW H_SOT363-6
A A

Issued Date 2013/08/15 Deciphered Date 2013/08/15 BATTERY CONN/OTP
5 4 3 2 1
5 4 3 2 1
B+
SDV
PL34
P2 P3 HCB2012KF-121T50_0805
PQ6 PQ7 1 2
AO4407AL_SO8 SI4483_SO8 PR53
8 1 1 8 PL33 0.01_1206_1%
7 2 2 7 HCB2012KF-121T50_0805
6 3 3 6 1 2 1 4 PQ8
VIN 5 5 AO4407AL_SO8
2 3 1 8
SDV
2
D D
2 7
10U_0805_25V6K
10U_0805_25V6K
4
2
PC22 3 6
PC21
PC23
SDV 2200P_0402_50V7K 5
2200P_0402_50V7K
0.1U_0402_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
PQ9 1 2 2
1
1
2
@ @
PC20
PC25
PC26
PC27
PC28
4
1
PR54 LTA044EUBFS8TL_UMT3F-3 2 DISCHG_G
3
200K_0402_5% PR55
737_ACN
737_ACP
SDV
1
200K_0402_1% 1 PR56
@ @ 47K_0402_1%
2
2 1 1 2
VIN
2
1P2_G2 PC24
SDV
2ACOFF-1
2
0.1U_0402_25V6-K 2 1
PR57
DISCHG_G-1
PC29 PC30 10K_0402_1%
2
0.1U_0402_25V6-K 0.1U_0402_25V6-K
P2-1 1 2 PR58
1
2 PD3 200K_0402_1%
1
PQ10 1SS355_SOD323-2
LTC015EUBFS8TL_UMT3F-3 PR59
1
20K_0402_1% 1 2
P2_G1
PC32
P2
3
3
0.1U_0402_25V6-K PQ26B D
2
2N7002KDWH_SOT363-6 5 PACIN_N 1 2 PACIN_P
PR61 G
1
3
6
D D 10_1206_5% BQ24737_VDD PD4
1
5 PR60 2 2 1 S 1SS355_SOD323-2
1M_0402_5%
BATT_OUT 44
4
G 68K_0402_1% G
PR62
PQ30B PC31 PC34
6
S 2N7002KDWH_SOT363-6 S PQ30A 1U_0603_25V6M 1U_0603_25V6M 2 D
2
4
1
2N7002KDWH_SOT363-6 2 1 737_VCC 1 2 PC33 2 PACIN
2
0.1U_0402_25V6-K G
1
P2-2
PD5 S PQ26A
1VIN
1
RB751V-40_SOD323-2 2N7002KDWH_SOT363-6
PR63 2 1
3
5
6
7
8
47K_0402_1% D PQ29B PR64 PQ11
SDV SDV
20
14
2
3
C PACIN 1 2 5 2N7002KDWH_SOT363-6 390K_0603_1% C
G AO4466L_SO8
VCC
ACN
GND
CMPOUT
ACP
PACIN_G
PR65 PR66 PC36
2
S 59K_0402_1% 2.2_0603_5% 0.047U_0603_25V7-K
4
1 2 737_ACDET 6 17 BST_CHG 1 2 2 1 4
SDV PC35 ACDET BTST
0.1U_0402_25V6-K
1 2 ACPRN 5 16
PR67 ACOK REGN
3
2
1
PR68 0_0402_5% PU4
6
10K_0402_5% D 38,44 EC_SMB_CK1 1 2 737_SCL 9 18 DH_CHG PR70

1 2 ACOFF-1 2 SCL HIDRV PL3 0.01_1206_1%
38 ACOFF G BQ24737RGRR_VQFN20_3P5X3P5 4.7UH_PCMB063T-4R7MS_5.5A_20%
1 2 PR69 737_SDA 8 19 LX_CHG 1 2 CHG 1 4
S
38,44 EC_SMB_DA1
0_0402_5% SDA PHASE BATT+
1
2 3
5
6
7
8
PQ29A ADP_I 7 15
38 ADP_I IOUT LODRV
1
2N7002KDWH_SOT363-6 PQ12
CMPIN
PR71
SRN
BM#
SRP
ILIM
2
PC37 21 AO4466L_SO8 2.2_0805_5%
10U_0805_25V6K
10U_0805_25V6K
100P_0402_50V8J PAD
1
1
DL_CHG 4
1
2
11
10
12
13
3
PC39
PC38
D
BATT_OUT 5
2
2
1
BM#
1 SRN_1
G
SRP_1
PC40
SDV
737_ILIM
PQ28B 1500P_0402_50V7K
3
2
1
S 2N7002KDWH_SOT363-6
4
2
1
1M_0402_5%
6.8_0603_5%
1
1
2
PR73
10_0603_5%
@ PR85 PR74
PR77
PR76
0_0402_5% 40.2K_0402_1% SDV
2
2
2
2
1
2
PC41
38,44 BATT_TEMP PR78 0.1U_0402_25V6-K
316K_0402_1% 1
1 2
+3VALW 1 2 737_SRP
B B
1
PC42
PR75 0.1U_0402_25V6-K
90.9K_0402_1% 2 737_SRN
PC43
2
0.1U_0402_25V6-K
1
SDV
co-work with EE(Neil) for layout reserve.

B+
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
BQ24737_VDD 2 2 2 2 2 2 2 2 2 2
PC72
PC71
PC125
PC126
PC127
PC128
PC129
PC131
PC132
PC130
+3VL
1 1 1 1 1 1 1 1 1 1
1
@ @ @ @ @ @ @ @ @ @
PR83
SDV
10K_0402_1%
2
PR81
2
10K_0402_1% PACIN
1
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
1
PR88 2 2 2 2 2
3
D 12K_0402_1%
PC133
PC134
PC135
PC136
PC163
ACPRN 5
38 ACPRN G
2
1 1 1 1 1
PQ27B S @ @ @ @ @
4
2N7002KDWH_SOT363-6
A A
Issued Date 2013/08/15 Deciphered Date 2013/08/15 CHARGER

5 4 3 2 1
5 4 3 2 1
D +3VALW D
SDV
TDC:6A
B+ @ PU5 OCP:8A
PJ3
1 2 +3V_VIN 7 2 +3V_PWRGD
1 2 EN2 PG PR280 PC48
2200P_0402_25V7-K
SY8206BQNC_QFN10_3X3
JUMP_43X79 2.2_0603_5% 0.1U_0603_25V7-M
1M_0402_5%
+3VALW
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
1
1
8 6 1 2 1 2
PR91
PC255
PC250
IN BS PL4 @
PC46
PC47
2.2UH_PCMB063T-2R2MS_8A_20% PJ4
2
@ 9 10 +3VLX 1 2 +3VALW_P 1 2
2
PR92 GND LX 1 2
0_0402_5% JUMP_43X79
2
EC_ON 1 2 +3VALW_EN 1 4 +3VALW_P @ PR93
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
EN1 OUT 4.7_0603_5%
0.1U_0402_25V6
2200P_0402_25V7-K
100mA +3VLP
PC253
PC254
3 5
PC49
PC50
PC52
PC51
FB LDO
+3VALW_FB
+3VLP +3VL
1 1
2
MAINPWON 1 2 PJ5 @
4.7U_0603_6.3V6K
1
1
@ PC55 JUMP_43X39
@ PC53 PR94 680P_0402_50V7K 1 2
PC54
PD14 0.1U_0402_25V6 1M_0402_5% 1 2
2
RB751V-40_SOD323-2
PTP1
2
PAD
PC56
PR95
1 2 1 2
SDV
0.01U_0402_25V7K 1K_0402_1%
C C
+5VALW
TDC:6.5A
OCP:11A
B+ @ PU6
PJ7
1 2 +5V_VIN 8 2 +5V_PWRGD
1 2 IN PG PR281 PC60
SDV
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_25V7-K
1
1
1
SY8208CQNC_QFN10_3X3
JUMP_43X79 2.2_0603_5% 0.1U_0603_25V7-M

PC58
PC59
PC256
9 6 1 2 1 2 +5VALW
PC57
GND BS PL5
2
2
2
PC61 3.3UH_PCMB063T-3R3MS_6.5A_20% PJ8

1 2+5VVCC 5 10 +5VLX 1 2 +5VALW_P 2 1
PR99 VCC LX 2 1
0_0402_5% 1U_0603_25V6M @ JUMP_43X118
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
2200P_0402_25V7-K
2
1 2 +5VALW_EN 1 4 +5VALW_P @ PR100
38,49 EC_ON
0.1U_0402_25V6
EN OUT
1
1
1
4.7_0603_5%
PC252
PC251
100mA +5VLP
B B
PC63
PC62
PC64
PC65
+5VFB 3 7
2
2
2
FB LDO
1 1
1 2
1M_0402_5%
38,43 MAINPWON
4.7U_0603_6.3V6K
1
@ PC68
1
680P_0402_50V7K
PC67
PR101
PD13 PC66
2
RB751V-40_SOD323-2 0.1U_0402_25V6
2
@
2
PC69 PR102
6800P_0402_25V7-K 1K_0402_1%
1 2 1 2
+3VALW
2
PR96 @
100K_0402_5%
PR97 @
0_0402_5%
1
A +3V_PWRGD 1 2 A
ALW_PWRGD 44,48,50
PR98 @
0_0402_5%
+5V_PWRGD 1 2
Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_3VALW/5VALW

5 4 3 2 1
A B C D
PJ10
2 1
2 1
@ JUMP_43X118
PJ11
+1.35VP 2 1 +1.35V_DDR_VDDIOSUS
2 1
@ JUMP_43X118
1 1
PJ12
2 1
+1.35VP +0.675VSP 2 1 +0.675VS
PJ13
10U_0603_6.3V6M
B+ @ JUMP_43X39
1
2 1
PC70
B+_1.35V
2 1
2200P_0402_25V7-K
@ JUMP_43X79
0.1U_0402_25V6
2
10U_0805_25V6-K
10U_0805_25V6-K
1
1
PC73
PC74
PC75
PC76
PR105
PR103 205K_0402_1%
@ 100K_0402_1%
2
2 1
+3VALW
+0.675VSP
PR104
100K_0402_1%
+1.35VP
1 2 +0.675VSP
0.1U_0402_10V6-K
10U_0603_6.3V6M
2
1
PC77
PC78
+0.675VSP
5
TDC:1.3A
14
11
13
19
20
2
AON6414AL_DFN
PQ13
PGND
VID
CS
VLDOIN
VTT
PR106 21
+1.35VP PC79 2.2_0603_5% PAD
4 1 2 1 2 18 1
FSW=285KHz BOOT VTTGND
TDC:11A 0.22U_0603_25V7K
DH_1.35V 17 2 +0.675VSP
UGATE VTTSNS
OCP:13A
1
2
3
PL6
2
SDV 0.68UH_PCMB063T-R68MS_16A_+-20% PU7 3
2
1 2 LX_1.35V 16 GND VTTREF_0.675V

+1.35VP PHASE
4 VTTREF_0.675V
VTTREF
2
PQ14 RT8231AGQW_WQFN20_3X3 PR108
5
2200P_0402_25V7-K
PR107 AON6414AL_DFN DL_1.35V 15 5.1_0603_5%

LGATE
1
@ 4.7_0603_5% 12 2 1
470P_0402_50V7K
0.1U_0402_25V6
1 VDD +5VALW
1
PGOOD
PR109
330U_2.5V_M
1
1
+
PC80
PC82
PC81
PC84
7.87K_0402_1% 5 1 PC83
TON
1
VDDQ 0.047U_0402_16V7K
FB
S5
S3
2
4 PC85
2
2 2 1U_0402_6.3V6K
10
1
2
PC86
@ @ 680P_0402_50V7K
2 TON_1.35V
S5_1.35V
S3_1.35V
2
1
2
3
PR111
1
100K_0402_1%
PR110 1 2
10K_0402_1% +3VALW
887K_0402_1%
2
PR112
FB_1.35V 2 1
VDDQ_PGOOD 38
PR819
1
B+_1.35V 0_0402_5%
3 3
PR113
0_0402_5%
1 2
38,39,48,50,51 SUSP#
1 2 S3_1.35V
PR114
@ 0_0402_5%
1
PC87
2 0.1U_0402_10V6-K
1 2 S5_1.35V
38 SYSON
PR115
1
0_0402_5%
PC88
0.1U_0402_10V6-K
2
4 4
Issued Date 2013/08/01 Deciphered Date 2014/08/01 +1.35VP/+0.675VSP

A B C D
A B C D
1 1
+5VALW
SDV
+1.5VSP
1
PC89 @
1U_0402_6.3V6K
2
+3VALW PU8 @ 300mA
PR116 @ 6
5 VCNTL 3
300mA 0_0603_5%
VIN VOUT1
PJ15 @
1 2 1.5VS_VIN 9 4 2 1
TP VOUT2 +1.5VSP 2 1 +1.5VS
1
1
1
8
PC90 @ 7 EN 2 PR117 @ PC91 @ JUMP_43X39
GND
4.7U_0603_6.3V6K POK FB 21.5K_0402_1% 10U_0603_6.3V6M
2
1 2
1.5VS_FB
1
APL5930KAI-TRG_SO8
SUSP# 1 2 EN_1_5VSP PR119 @ VFB=0.8V
1
24K_0402_1%
@ PR118 PR120 @ Vo=VFB*(1+PR613/PR615)
1
0_0402_5% 100K_0402_5% OCP:Min 4A
2
PC92 @
0.1U_0402_10V6-K
2
+3VS
PR121 @
2 0_0402_5% 2
1 2
44,46,50 ALW_PWRGD
PR122
0_0402_5%
1 2 0.95VS_EN
38,39,47,50,51 SUSP#
1M_0402_5%
1
PR142
PC93
0.1U_0402_10V6-K
2
@
2
+0.95VSP
TDC:9.5A
PJ16
OCP:12A
2 1 B+_0.95VS 8 1 PR123 PC94
B+ 2 1 IN EN 0_0603_5% 0.1U_0603_25V7K
JUMP_43X79 6 1 2 1 2 PL7
BS 0.68UH_PCMB063T-R68MS_16A_+-20%
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
9 10 0.95VS_LX 1 2
PC97
@ GND LX +0.95VSP
PC95
PC96
PU9 4
2
FB
2
3
2200P_0402_25V7-K
ILMT 7 +3VALW @ PR124 @
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_25V6
BYP
1
4.7_0603_5%
SDV SYX198DQNC
PC98
PC99
PC101
PC102
PC103
PC104
PC100
PC124
2
330P_0402_50V8J
2
1SNUB_0.95V 1
2
PG 5 0.95VS_LDO
LDO
1
1 2 0.95VS_LIMT
PC107
+3VALW
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
PR125
2
1
1
100K_0402_5%
PC105
PC106
@ PR126 @ PR127
2
3
1M_0402_5% 20K_0402_1% 3
2
@ PC108
SDV
2
PR129 680P_0402_50V7K
1K_0402_1%
2
2
10K_0402_5%
PR128
PJ17 @
1
1
0.95VS_FB 2 1
+0.95VSP 2 1 +0.95VS
JUMP_43X118
+3VALW
1
PR130
34K_0402_1%
2
Current limit setting pin. The current limit is set to
8A, 12A or 16A when this pin is pull low, floating
or pull high respectively.
4 4
Issued Date 2013/08/15 Deciphered Date 2013/08/15 +1.35VS_VGA/+1.5VS

A B C D
5 4 3 2 1
PR131
0_0402_5%
1 2
D 38 S5_1.1V_EN D
1 2
38,46 EC_ON
1K_0402_1%
2
PR132
1
@
@ PR143 PC109 @ PR133
100K_0402_1% 0.1U_0402_10V6-K 1M_0402_5%
2
+1.1VALWP
1
FSW=800KHz
PJ18
TDC:5A
10U_0805_25V6-K
2 1 8 1 PR134 PC110
B+ 2 1 IN EN 0_0603_5% 0.1U_0603_25V7K OCP:8A
@ JUMP_43X79 6 BS_1.1VS 1 2 1 2 PL8
1 BS
1
PC111
0.68UH_PCMB063T-R68MS_16A_+-20%
PC112 9 10 SW_1.1VS 1 2
0.1U_0402_25V6 GND LX +1.1VALWP
2
2
PU10 4 FB_1.1VS
C
+3VALW 3
ILMT
FB
C
2
7
BYP +3VALW PR135
2200P_0402_25V7-K
PR136 SYX198DQNC @ 4.7_0603_5%
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
0.1U_0402_25V6
@ 0_0402_5% 2 1 1 1 1
PG
1
1 2 5
1 1
LDO
PC114
PC116
PC117
PC119
PC115
PC118
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
PR137
2
1
1
2 1 PC121 2 2 2 2
PC120
PC113
@ 680P_0402_50V7K
2
100K_0402_5%
2
2
PR138 SDV
0_0402_5%
330P_0402_50V7-K
1
2
PC122
PR139
100K_0402_1%
1
2
PR140
B 1K_0402_1% B
1
PJ19
PR141 2 1
115K_0402_1% +1.1VALWP 2 1 +1.1VALW
@ JUMP_43X79
2
A A

Issued Date 2013/08/01 Deciphered Date 2014/08/01 +1.1VALWP
5 4 3 2 1
5 4 3 2 1
+3VS
D D
1
PR255
100K_0402_1%
PR296
2
0_0402_5%
1 2
38,52 VDDAPWROK +1.8VS
TDC: 1 A
SY8032ABC_SOT23-6 OCP: 4.5 A
PL19
1UH_PH041H-1R0MS_3.8A_20%
4 3 1.8VSP_LX 1 2
+3VALW IN LX +1.8VSP
1
5 2
PG GND
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_25V7-K
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
0.1U_0402_10V6-K
0.1U_0402_25V6
1 1 @ PR284 1 1
1
1
PC249
PC257
PC262
PC264
PC123
6 1 4.7_0603_5%
FB EN
PC265
PC258
PC261
PC259
PC266
1
PU15 68P_0402_50V8J
2
1 2
2
2 2 2 2
2
PR285
@ PC263 20K_0402_1%
SDV 680P_0402_50V7-K
2
C C
@
PR287 @
0_0402_5%
1 2
44,46,48 ALW_PWRGD
1
PR282
0_0402_5% PR283
1 2 EN_1.8VSP 10K_0402_1%
38,39,47,48,51 SUSP#
2
2
PR286
1M_0402_5% PC260
0.1U_0402_10V6-K
2
1
PJ20
2 1
+1.8VSP 2 1 +1.8VS
JUMP_43X39
B B
@
A A

Issued Date 2013/08/15 Deciphered Date 2013/08/15 +1.05VS/+1.05VS_VGA
5 4 3 2 1
5 4 3 2 1
+VGA1_B+
PL25 DIS@
HCB2012KF-121T50_0805
1 2
B+
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
1
PC137
PC138
PC139
5
2
AON6414AL_DFN
D +VGA_CORE D
PQ15
SVI2_SVC_P
DIS@
SVI2_SVD_P
UGATE1 4 TDC :20A
10P_0402_50V8J
10P_0402_50V8J
DIS@ OCP :35A
2
DIS@ DIS@
PC290
PC291
PL10 DIS@
1
3
2
1
0.36UH_PCMB063T-R36MS_20A_20%
+VGA_CORE
PR155 @
10K_0402_5%
10K_0402_5%
PR156 DIS@
PR157 DIS@
PHASE1 1 2
1
10K_0402_5%
@ @
1
PR159 DIS@
5
@ PR154 2.2_0603_5% PQ16
2
0_0402_5% BOOT1 1 2 1 2
AON6554_DFN
PR158 DIS@ PR160
0.1U_0402_25V6
330U_D2_2V_Y
330U_D2_2V_Y
0_0402_5% PC140 DIS@ 4.7_0603_5% 1 1
2
2 1 0.22U_0603_25V7K
1
PC141
PC268
PC142
LGATE1 4 + +
1
40
39
38
37
36
35
34
33
32
31
2
1
PU12 2 2
DIS@ PC143 PR163 DIS@ @
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
3
2
1
+3VS_VGA 1000P_0402_50V7-K
SDV 10K_0402_1% SDV
2
ISEN1 1 2
PR161 DIS@ 100K_0402_1% DIS@ DIS@
1
1 2 1 30 BOOT2 PR164 DIS@

PR86 @ PR162 DIS@ 100K_0402_1% NTC_NB BOOT2 3.65K_0402_1%
1 2 2 29 UGATE2 VSUM+ 1 2
10K_0402_5%
IMON_NB UGATE2 SDV
PR288 2 DIS@ 1 0_0402_5% SVI2_SVC_P 3 28 PHASE2
2
18 SVI2_SVC SVC PHASE2 PR165 DIS@

PR166 2 DIS@ 1 0_0402_5% VRHOT_L 4 27 LGATE2 DIS@ PR169 PR168 DIS@ 10_0402_1%
8 GPU_VR_HOT# VR_HOT_L LGATE2 VSUM- 1 2
1_0603_5% 0_0402_5%
PC167 @ 2 1.1U_0402_10V6-K PR173 2 DIS@ 1 0_0402_5% SVI2_SVD_P 5 26 62771_VDDP 2 1
18 SVI2_SVD SVD VDDP
+5VS
PR298 2 DIS@ 1 0_0402_5% 6 25 62771_VDD 1 2
+1.8VS_VGA VDDIO VDD
C PR299 2 @ 1 0_0402_5% PR289 2 DIS@ 1 0_0402_5% 7
ISL62771HRTZ_TQFN40_5X5
24 LGATE1
+VGA2_B+ C
+3VS_VGA 18 SVI2_SVT SVT LGATE1
1
1 2
SDV ENABLE 8 23 PHASE1 PC144 PC145
PL21 DIS@
HCB2012KF-121T50_0805
2,17,24 DGPU_PWREN ENABLE PHASE1 1U_0603_25V6M 1U_0603_25V6M 1 2
2
DIS@ PR170
17,18 PLT_RST_VGA#
2 DIS@ 1 PWROK 9
PWROK UGATE1
22 UGATE1 DIS@ DIS@ B+
0_0402_5%
10U_0805_25V6K
2 1 PR171 VGA_IMON 10 21 BOOT1
38,39,47,48,50 SUSP# IMON BOOT1
2
10U_0805_25V6K
PC146 DIS@
.1U_0402_10V6-K
0.1U_0402_25V6
@ 0_0402_5%
PGOOD
PR172 PR822
ISUMN
ISUMP
COMP
1
ISEN2
ISEN1
PC149
PC147
PC148
VSEN
0_0402_5% 1.91K_0402_1% PR174 @
NTC
RTN
1
AON6414AL_DFN
DIS@ 100K_0402_1%
FB
TP
PQ17
2 1
1
2
2
+3VS
DIS@
+3VS_VGA 11
12
13
14
VGA_CORE_SUMN 15
VGA_CORE_SEN 16
17
18
19
20
41
PR211 DIS@
100K_0402_1% UGATE2 4 DIS@ DIS@
2
62771_COMP
2 1 DIS@
VGA_VSS_SEN
+3VS_VGA
62771_FB
2
PR175 DIS@ PR176 PC150

27.4K_0402_1% SDV 130K_0402_1% 0.1U_0402_25V6-K
1
3
2
1
1 2 62771NTC DIS@ DIS@ 2 1 PL11 DIS@
1
DGPU_PWROK 12,38
0.36UH_PCMB063T-R36MS_20A_20%
DIS@ PR290 PHASE2 1 2
DIS@ 0_0402_5%
6277_NTC_1 1 2 PR177 DIS@
5
PH2 2.2_0603_5% PQ18
2
470K_0402_3%_NCP15WM474E03RC SDV SDV BOOT2 1 2 1 2
1
AON6554_DFN
PR178
0.1U_0402_25V6
330U_D2_2V_Y
330U_D2_2V_Y
PR179 PC151 DIS@ 4.7_0603_5% 1 1
10.7K_0402_1% 62771NTC 0.22U_0603_25V7K
1
PC152
PC153
PC267
4 + +
DIS@ +5VS LGATE2
1
PR181 @
2
10K_0402_5% PR182 DIS@
2
2 1 10K_0402_1% 2 2
1
DIS@ ISEN2 1 2
3
2
1
PC154
1000P_0402_50V7-K PR183 DIS@
2
ISEN2 3.65K_0402_1% DIS@ DIS@ DIS@
VSUM+ 1 2
B B
ISEN1
SDV
PR180 DIS@
1
PR184 @2 1 PC155 PC156

PC157
0.1U_0402_25V6DIS@
SDV PC158 DIS@ PR185 DIS@ PC159 DIS@ PR187 @ VSUM-
10_0402_1%
1 2
10K_0402_5% 0.22U_0402_10V6K 0.22U_0402_10V6K 1 2 100P_0402_50V8J 499_0402_1% 100P_0402_50V8J 32.4K_0402_1%
2
DIS@ DIS@ PR186 DIS@ 1 1

2 62771_FB_2 2 1 2 1 2
VSUM- 1 2
1
330P_0402_50V8J
1.02K_0402_1% PR188 DIS@ PR189 DIS@ PC160 DIS@

PR190 619_0402_1% 30K_0402_1% 150P_0402_50V8-J
1
PC161 DIS@
2.61K_0402_1% @ PR193 1 2 1 26277_FB_11 2

1
DIS@ 2 1 1 2
PR192
2 2
11K_0402_1%
DIS@
10K_0402_5% PC162 @
0.22U_0402_10V6K
+VGA_CORE PR194 DIS@
2K_0402_1%
PC165 DIS@
680P_0402_50V7K
1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PH3 DIS@ 2 16277_FB_3 1 2
2
10K_0402_NTC DIS@ PC166 PC164 DIS@

0.033U_0402_16V7K 0.033U_0402_16V7K PR293
2
1
1
PC174
PC175
PC172
PC173
10_0402_1%
1
DIS@ DIS@ PR291

0_0402_5%
2
1
2
VSUM+ 2 1
VDDC_SEN 19
@ @ DIS@ DIS@
1
DIS@
PC176
330P_0402_50V8J
2
2 1
VDDC_RTN 19
2
DIS@ PR292
1
PR294 0_0402_5%
PC177 10_0402_1%
1000P_0402_50V7K
DIS@
2
DIS@
1
A A

Issued Date 2013/08/15 Deciphered Date 2013/08/15 +VGA_CORE
5 4 3 2 1
5 4 3 2 1
VDDNB1_B+
PL20
HCB2012KF-121T50_0805
1 2
B+
5
+VDDNB_CORE
2200P_0402_50V7K
0.01U_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
1
2
+5VS PQ31 FSW=300KHz
PC178
PC179
PC180
AON6414AL_DFN
PC181
TDC=32A
1
1
UGATE_NB1 4
PR195
PC182
680P_0402_50V7K
PR196
2K_0402_1%
OCP=50A
0_0402_5% 2 1 2 1
@
PR198 PC183 +VDDNB_CORE
3
2
1
ISEN2_NB PR197 1.21K_0402_1% 150P_0402_50V8-J PL13
100_0402_1%
SDV 1 2 1 2 1 2 1 2 0.36UH 20% PDME064T-R36MS1R405 24A
1 2
+VDDNB_CORE
0.22U_0402_10V6K
ISEN1_NB PR199 PR200 @ PHASE_NB1 1 4
0.22U_0402_10V6K
1
PR203 137K_0402_1% 32.4K_0402_1%
PC184
1
2
0_0402_5% PR201 2 3
5
1 2 1 2 1 2 1 2 PC188 2.2_0603_5% PQ32 @ PR202
PC186
7 VDDNB_SENSE
2
D PR204 47P_0402_50V8J BOOT_NB1 1 2BOOT_NB1_R 1 2 4.7_0603_5% PR205 D
AON6554_DFN
VSUMN_NB PC187 499_0402_1% 10K_0402_1% 1 1
100P_0402_50V8J PC185 ISEN1_NB 1 2
NB1_SNB
1
1
0.22U_0603_16V7K PC189 PC190 + PC191 +
1 2 LGATE_NB1 4 PR206 +
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
3.65K_0402_1%
PC192 @ VSUMP_NB 1 2 VSUMP_NB1_R 2 2
1
1000P_0402_50V7K @ PC193 2
VSUMP_NB 680P_0402_50V7K PR207
3
2
1
1
10_0402_1%
.1U_0402_10V6-K
2
VSUMN_NB 1 2 VSUMN_NB1_R
.1U_0402_10V6-K
1
1
PR208 PGOOD_NB 1 PTP2 PAD
PC195
PC194
2.61K_0402_1% PR209 @
1
10K_0402_1%
2
2
ISEN2_NB 2 1
PW M2_NB
2
PH4
SDV LGATE_NB1
2
10K_0402_NTC PR210
2
11K_0402_1% PR212 PHASE_NB1
VDDNB2_B+
40 57.6K_0402_1%
590_0402_1%
PR213
1
VSUMN_NB 1 2 UGATE_NB1 PL22
HCB2012KF-121T50_0805
2
ISEN1_NB @ 1 2
1
PC197 B+
5
2
1 2 2 1
1000P_0402_50V7K
+5VALW PC198
2200P_0402_50V7K
1
0.01U_0402_25V7K
0.22U_0603_25V7K
48
47
46
45
44
43
42
41
39
38
37
10U_0805_25V6K
10U_0805_25V6K
1
1
2
PR216 PC199 @ PR214 @ PU14 PQ33
PC201
PC202
PC200
1
27.4K_0402_1% 0.22U_0402_10V6K 10K_0402_5% AON6414AL_DFN
PC203
ISEN1_NB
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
FCCM_NB
PWM2_NB
LGATEX
PHASEX
UGATEX
1 2
B+
2
2
1
PR215 1 2 0_0402_5% 6 1 UGATE_NB2 4
PR218 ISEN2_NB 1 36 BOOT_NB1 PR221 VCC UGATE
10.7K_0402_1% ISEN2_NB BOOTX 0_0603_5% PR217 2 1 0_0402_5% 7 2 BOOT_NB2 1 2 1 2
1 2 1 2 2 35 2 1 FCCM BOOT
PH7 NTC_NB VIN PW M2_NB 3 8 PR220 PC204 +VDDNB_CORE
3
2
1
PWM PHASE
1
470K_0402_3%_NCP15W M474E03RC IMON_NB 3 34 BOOT2_APU 2.2_0603_5% 0.22U_0603_16V7K PL14
IMON_NB BOOT2 PC205 4 5 0.36UH 20% PDME064T-R36MS1R405 24A
PR219 2 1 APU_SVC_P 4 33 UGATE2_APU 0.22U_0603_25V7K 9 GND LGATE
7 APU_SVC
2
0_0402_5% SVC UGATE2 TP PHASE_NB2 1 4
PR222 2 1 5 32 PHASE2_APU 2 1 PU13
38 VR_HOT# 0_0402_5% VR_HOT_L PHASE2 +5VALW ISL6208BCRZ-T_QFN8_2X2 2 3
1
2
PR227 2 1 APU_SVD_P 6 31 LGATE2_APU PR223 PQ34
7 APU_SVD SVD LGATE2
2
PR225 0_0402_5% ISL6277AHRZ_QFN48_6X6 0_0402_5% @ PR224

0.1U_0402_25V6-K
AON6554_DFN
130K_0402_1% PR226 PR228 2 1 7 30 6277A_VDDP 2 1 4.7_0603_5%
PC206
+1.35V_APU_VDDIO_RUN VDDIO VDDP +5VS 1
2
10K_0402_1% 0_0402_5% PR229 @ PC207 PC208 PC209
1
PR231 2 1 APU_SVT_P 8 29 6277A_VDD 1 2 0_0402_5% +
NB2_SNB
7 APU_SVT
2
1
0_0402_5% SVT VDD PR232 LGATE_NB2 4
+1.35V_APU_VDDIO_RUN .1U_0402_10V6-K
1
10U_0603_6.3V6M
330U_D2_2V_Y
EN_+VDD PR233 2 1 9 28 1_0603_5% PR230
2
0_0402_5% ENABLE PWM_Y 10K_0402_1% 2
PR235 2 1 10 27 LGATE1_APU ISEN2_NB 1 2
7,12 APU_PWROK PWROK LGATE1
1
C 0_0402_5% @ PC210 C
1U_0603_10V6K
1U_0603_10V6K
1
3
2
1
2 1 11 26 PHASE1_APU 680P_0402_50V7K PR234
PC211
PC212
38 APU_IMON IMON PHASE1 3.65K_0402_1%
SDV
2
1
PR295 1 2 12 25 UGATE1_APU VSUMP_NB 1 2 VSUMP_NB2_R

NTC UGATE1
2
PGOOD
0_0402_5% PR297
PR236
BOOT1
ISUMN
ISUMP
130K_0402_1%
COMP
0.1U_0402_25V6-K
ISEN3
ISEN2
ISEN1
VSEN
27.4K_0402_1% 49 PR237
PC213
RTN
FB2
PAD 10_0402_1%
FB
1
1 2 VSUMN_NB 1 2 VSUMN_NB2_R
2
PH5
13
14
15
16
17
18
19
20
21
22
23
24
1
470K_0402_3%_NCP15W M474E03RC PR238 @

PR239 10K_0402_1%
10.7K_0402_1% ISEN1_NB 2 1
6277A_VSEN
PRE-PWROK METAL VID CODES
6277A_FB
6277A_RTN
6277A_ISUMN
6277A_FB2
6277A_COMP
+5VS BOOT1_APU
SDV
2
SVC SVD Boot Voltage PR240

0_0402_5%
VDD1_B+
2 1
0 0 1.1V +3VS PL23
HCB2012KF-121T50_0805
PR241 @ 1 2
0 1 1.0V(Default) 0_0402_5% B+
1
1 2
1 0 0.9V 1 1
2200P_0402_50V7K
0.01U_0402_25V7K
PR242
68U_25V_M
68U_25V_M
10U_0805_25V6K
10U_0805_25V6K
2
1
1
1
+ +
PC214
PC215
PC216
PC244
PC242
1 1 0.8V 100K_0402_1%
PC217
5
2
1
2
2
PR243 2 2
0_0402_5% PQ35
ISEN2_APU 2 1 ISEN2_6277A IMVPPOK 38 AON6414AL_DFN
+VDD_CORE
ISEN1_APU 2 1 ISEN1_6277A
UGATE2_APU 4 FSW=300KHz
PR245 TDC=30A
0_0402_5% PR244 PC218 PL16
OCP=46A
10K_0402_5%
0.22U_0402_10V6K
0.22U_0402_10V6K
1 2 0_0402_5% @ PC222 10P_0402_50V8J 0.36UH 20% PDME064T-R36MS1R405 24A

38 APUPWR_EN
3
2
1
0.1U_0402_25V6 1 2
1
PHASE2_APU 1 4
PC219
PC220
PR246
1 2 EN_+VDD 1 2
SDV +VDD_CORE
38,50 VDDAPWROK
2
PR248 2 3
2
5
PR247 PR251 2.2_0603_5% PQ36 @ PR249
@ 10K_0402_1% 619_0402_1% 1 2 1 2 1 2 1 2 1
BOOT2_APU 2 1 2 4.7_0603_5% 1 1 1
1
AON6554_DFN
VSUM-_APU 1 2 PC227 PR252 PC223 PC221
2
1
PC228 100P_0402_50V8J 499_0402_1% 47P_0402_50V8J PR250 @ 0.22U_0603_16V7K PR253 PC226 + PC224 + PC225 +
1APU_SNB11
1
.1U_0402_10V6-K PR254 32.4K_0402_1% 10K_0402_1% PC229

2
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
2.61K_0402_1% 2 1 1 2 LGATE2_APU 4 ISEN2_APU 1 2 .1U_0402_10V6-K
1
1 2 1 2 1 2 2 2 2
2
1
PR259 @ PC232 @ PR257 PC230 PR258

11K_0402_1%
2
10K_0402_5% 0.22U_0402_10V6K PR256 137K_0402_1% 150P_0402_50V8-J @ PC231 3.65K_0402_1%

PR260
330P_0402_50V8J
.1U_0402_10V6-K
.1U_0402_10V6-K
1.5K_0402_1% 680P_0402_50V7K VSUM+_APU 1 2VSUM+_APU1_R
3
2
1
PC233
2
2 1 1 2 PR261
SDV
2
1
2
B PR262 10_0402_1% B
PC237
PC236
PH6 PR264 2K_0402_1% PC235 VSUM-_APU 1 2VSUM-_APU1_R

10K_0402_NTC 10_0402_1% 680P_0402_50V7K
2
2 1 PR263 @
+VDD_CORE 10K_0402_1%
1
VSUM+_APU PR265 ISEN1_APU 1 2

0_0402_5%
+1.35V_APU_VDDIO_RUN 2 1
VDD_SENSE 7
PR266
0_0402_5%
2 1
VSS_SENSE 7 VDD2_B+
1
1
1
PR267 @ @ PL24
1
1K_0402_1% PR268 PR269 @ PC238 HCB2012KF-121T50_0805

1K_0402_1% 1000P_0402_50V7K 2 1 1 2
B+
1K_0402_1%
PR270
2200P_0402_50V7K
2
2
2
0.01U_0402_25V7K
10_0402_1%
10U_0805_25V6K
10U_0805_25V6K
1
2
PC239
PC243
PC240
PC241
5
APU_SVC_P
2
2
1
APU_SVD_P PQ37
AON6414AL_DFN
APU_SVT_P
UGATE1_APU 4
1
PL18
@ PR271 PR272 PR273 0.36UH 20% PDME064T-R36MS1R405 24A
3
2
1
220_0402_5% @ @ 220_0402_5%
PHASE1_APU 1 4
+VDD_CORE
220_0402_5%
2
2
PR274 2 3
5
2.2_0603_5% PQ38 @ PR275
BOOT1_APU 1 2 1 2 4.7_0603_5% 1
AON6554_DFN
PC245
1
0.22U_0603_16V7K PC246 + PC247
1APU_SNB21
10U_0603_6.3V6M
330U_D2_2V_Y
LGATE1_APU 4 PR276
2
10K_0402_1% 2
ISEN1_APU 1 2
@ PC248
680P_0402_50V7K PR277
3
2
1
3.65K_0402_1%
2
VSUM+_APU 1 2VSUM+_APU2_R
PR278
A 10_0402_1% A
VSUM-_APU 1 2VSUM-_APU2_R
PR279 @
10K_0402_1%
ISEN2_APU 2 1
Issued Date 2013/08/05 Deciphered Date 2013/08/05 PWR_CPU Core

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
5 4 3 2 1
5 4 3 2 1
D D
+VDDNB_CORE
1 1 1 1 1
PC269 PC270 PC271 PC272 PC273
22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M
2 2 2 2 2
1 1 1 1 1
PC274 PC275 PC276 PC277 PC278
2 2 2 2 2
C C
+VDD_CORE
1 1 1 1 1
PC279 PC280 PC281 PC282 PC283
2 2 2 2 2
1 1 1 1 1
PC284 PC285 PC286 PC287 PC288
2 2 2 2 2
B B
1
PC289
22U_0805_6.3V6-M
2
A A

Issued Date 2013/08/01 Deciphered Date 2014/08/01 VCCCPUCORE DECOUPLING
5 4 3 2 1

Aclu7 Nm-A291 R0.1

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A B C D E

AMD Kaveri Processor with DDR3L + Bolton FCH

Security Classification LC Future Center Secret Data Title

Date: Monday. December 16. 2013 Sheet 1 of 52

LCFC confidential File Name: ACLU7 & 8

HDMI Conn. HDMI Kaveri

SATA HDD SATA Gen3 Bolton M3 Page 32

Page 33 SATA Port0

HD Audio USB 2.0 1x Touch Screen

Codec SPK Conn.

Sub-Board ( Only 15")

Security Classification LC Future Center Secret Data Title

Date: Monday, December 16, 2013 Sheet 2 of 52

Voltage Rails ( O --> Means ON , X --> Means OFF )

12 ME@ ME Part (connector, hole)

WLAN Termal CP Port Device

EC SM Bus1 address EC SM Bus2 address APU SM Bus address

Security Classification LC Future Center Secret Data Title

Date: Monday, December 16, 2013 Sheet 3 of 52

PS_2[1] N/A Reserved. 0

PS_2[2] N/A Reserved. 0

VDDR3(+3VGS) 0 = VGA controller capacity enabled.

PS_2[5] N/A Reserved 1

PCIE_VDDC(+0.95VGS) Determines the maximum number of digital display audio endpoints

PERSTb(GPU_RST#) 100us min. VRAM ID config

FP3 Kaveri APU supports

PCIE_CRX_GTX_P0 Y8 P_GFX_RXP0/RSVD P_GFX_TXP0/DP6_TXP4 AB2 PCIE_CTX_GRX_P0 CC1 DIS@ 1 2 0.1U_0402_16V7-K PCIE_CTX_C_GRX_P0

UMI_CRX_FTX_P0 AJ7 P_UMI_RXP0 P_UMI_TXP0 AM9 UMI_CTX_FRX_P0 CC15 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_P0_C

Security Classification LC Future Center Secret Data Title

M_VREF V36 M_VREF RSVD_11 A26

+VREF_DQA MA_VREFDQ RSVD_5

39.2_0402_1% RSVD_7 AK24 RSVD_14 AM21

FP3 REV 0.52

add cap on 20131002

Security Classification LC Future Center Secret Data Title

APU_EDP_TX0+ AL6 DP0_TXP0 DP0_AUXP AG8 APU_EDP_AUX 33K_0402_5%

28 APU_HDMI_TX0+ APU_HDMI_TX0- B5 L27 APU_TEST6

RC68 2 @ 1 39.2_0402_1% APU_TEST32_H TPC11 1 Test_Point_40MIL 10K_0804_8P4R_5%

RC47 1 2 100_0402_5% VDD_SENSE

Security Classification LC Future Center Secret Data Title

CC44 CC45 CC46 CC47 CC48 CC49 CC42 CC43

T11 VDD_1 VDDNB_1 E8 L29 VDDIO_1

+0.95VS_VDDP +1.8VS_VDDA +VDDR_CAP

3.3n need apply PN

Security Classification LC Future Center Secret Data Title

FP3 REV 0.52 FP3 REV 0.52

Security Classification LC Future Center Secret Data Title

6 DDRA_CKE0 DDRA_CKE0 73 74 DDRA_CKE1

Security Classification LC Future Center Secret Data Title

DDR3 SO-DIMM B DDRB_DQ[0..63] 6

DDRB_DQ9 23 DQ8 DQ12 24 DDRB_DQ13

PCI EXPRESS INTERFACES

GND1 OSC2 APU_PG

H7 FCH_S5 Follow Edge to change UE1.Pin35 from VSB_ON to FCH_S5 on 0927

Security Classification LC Future Center Secret Data Title

Add table on 2013 1001

0 UMA@ 0 14@ +3VS

RPH3 K6 TEMPIN0/GPIO171 NC1 AG16 RPH2

Modify level shift on 2013 1001

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 FCH SATA/GBE/SPI

RH53 1 2 10K_0402_5% WD_PWRGD

RH87 2 1 10K_0402_5% GATEA20 AE22 GA20IN/GEVENT0# USB_HSD13N G10

22u 1, 1u1 for circuit check list LH12