A B C D E

1 1

Compal Confidential
2
M/B Schematics Document 2

AMD Picasso FP5 APU with DDR4

EL4C2/EL452
LA-H091P
Vinafix.com
3

Rev : 1.0 3

2018-12-20

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Thursday, December 20, 2018 Sheet 1 of 41
A B C D E
 A B C D E

DDR4 2400MHz CH-A on board RAM x4

NGFF (Key M) CH-B DDR4-SO-DIMM X1
PCIe x4 , Gen3 8Gb/s , SATA x1 , Gen3 6Gb/s
PCIE/SATA SSD
2242/2280 conn.
1

PCIe x1 , Gen1 2.5Gb/s

USB2.0 x1, 480Mb/s USB Charger USB2.0 x1, 480Mb/s
1

NGFF (Key E) TI SN1702001RTER

WLAN/BT USB2.0 x1, 480Mb/s USB3.0 Conn.
2230 conn. with AOU
USB3.1 x1, 5Gb/s USB3 redriver USB3.1 x1, Gen1 5Gb/s
NGFF (Key M) Parade PS8713B
PCIE SSD PCIe x2 , Gen3 8Gb/s
2242 conn.
For S540-14 only
USB3.1 x1, 5Gb/s USB3 redriver USB3.1 x1, Gen1 5Gb/s

eDP Panel Parade PS8713B USB3.0 Conn.

eDP x4 HBR2 5.4Gb/s USB2.0 x1, 480Mb/s
FHD LCD
QHD For S540-14
AMD Picasso Ridge
On Sub Board
USB2.0 x1, 480Mb/s
HDMI Conn. Parade DDI x4 , 2.97GT/s 1140pin BGA Int. Camera
HDMI1.4b PS8407A
2 2

USB2.0 x1, 480Mb/s

USB2.0 Hub
I2C For C340-14
For S540-14

FingerPrint TouchPanel

PCIe x1 , Gen1 2.5Gb/s Card Reader SDIO

Realtek RTS5232S
SD Card Conn.

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VBus
5V Switch
Type-C Conn. USB2.0 x1, 480Mb/s On Sub Board

USB3.1 Gen1 Combo Jack

CC/Vconn I2C_3VLP EC
MUX/CC HDA Audio Codec SPK
3

USB3.1x1, Gen1 Realtek RTS5448 Int. Speaker 3

USB3.1x1, Gen1 Synaptics CX11880

USB3 redriver DMIC
Int. Array Mic *2
Parade PS8713B
I2C
TouchPad
SPI

SPI ROM
8MB

LPC
G- Sensor x2
For C340-14 only

Int. KBD KBC

4 4

ENE KB9022
Hall Sensor x2
S540-14 used one

LED
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 2 of 41
A B C D E
 A B C D E

Voltage Rails BOM Structure Table

SIGNAL
Power Plane Description S0 S3 S5 STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
VIN Adapter power supply ON ON ON
BOM Structure Item BOM Structure Item
Full ON HIGH HIGH ON ON ON ON RAVEN7@ RAVEN7 CPU X76GL@ O2 Card Reader
B+ AC or battery power rail for power circuit. ON ON ON
RAVEN5@ RAVEN5 CPU X76RT@ Realtek Card Reader
+APU_CORE Core voltage for APU ON OFF OFF S3 (Suspend to RAM) HIGH HIGH ON ON OFF OFF
RAVEN3@ RAVEN3 CPU HDT@ For HDT Debug used
+APU_CORE_SOC Core voltage for APU ON OFF OFF
1 S4 (Suspend to Disk) LOW HIGH ON OFF OFF OFF X76DDR4H@ Onboard RAM HYNIX FP@ Finger Print Component 1
+RTC_APU RTC power ON ON ON
X76DDR4M@ Onboard RAM MICRON KBL@ KeyBoard Backlight
+3VALW 3.3V always on power rail ON ON ON S5 (Soft OFF) LOW LOW ON OFF OFF OFF
X76DDR4S@ Onboard RAM SAMSUNG @ Unpop
+3VS 3.3V switched power rail ON OFF OFF
X76RAM@ Onboard RAM couple cap SDP@ DDR SDP Component
+1.8VALW 1.8V always on power rail ON ON ON
+1.8VS 1.8V switched power rail ON OFF OFF CPU PCB X4EUMA@ EMC component for UMA DDP@ DDR DDP Component
ME@ ME part C340@ C340 SKU
+0.8VALW 0.95V always on power rail ON ON ON UC1 ZZZ
SA0000C7640 DA8001H5010 EMI pop componemt S540 SKU
+0.8VS 0.95V switched power rail ON OFF OFF S IC RYZEN7 YM3700C4T4MFG 2.2G BGA 1140 APU PCB 2GB LA-H091P REV1 M/B 3, A.2
EMI@ S540@
APU_R7@ @EMI@ EMI Unpop component G_SEN@ G-sensor Component
+1.2V_DDR 1.2V power rail for APU and DDR ON ON OFF
UC1 ESD pop component QHD panel component
+2.5V_MEM 2.5V power rail for DDR ON ON OFF SA0000CCR20 ZZZ 45@
ESD@ QHD@
S IC RYZEN5 YM3500C4T4MFG 2G BGA 1140 APU RO0000003HM ESD Unpop component Level shift Component
+0.6VS_VTT 0.6V switched power rail for DDR terminator ON OFF OFF APU_R5@ HDMI Logo
@ESD@ LS@
20V_PRTCT@ 20V protection circuit
+5VALW 5V always on power rail ON ON ON
X76_PA@ Pericom USB re-driver
+5VS 5V switched power rail ON OFF OFF
X76_PE@ Parade USB re-driver
EMC X4E X76_TI@ TI USB re-driver
ZZZ Pericom USB re-driver couple cap
X4EAF738L51
PA@
SMT EMC FOR EE AH091 EL452 Parade USB re-driver couple cap
PE@
SMBUS Control Table
X4EUMA@
TI@ TI USB re-driver couple cap
RF@ RF pop componemt
@RF@ RF Unpop component
2
SOURCE APU BATT KB9022 SODIMM WLAN G-sensor THM-sensor DDR X76 2

X V V X X X X
EC_SMB_CK1 KB9022 ZZZ
X7680638L51
EC_SMB_DA1 +3VALW Hynix 1G onboard RAM
+3VALW +3VALW X76DDR4H@

V X V X X X V
EC_SMB_CK2 KB9022 ZZZ
X7680638L52
EC_SMB_DA2 +3VS Micron 1G onboard RAM
+1.8VS +3VALW +3VS X76DDR4M@

X X X X X V X
EC_SMB_CK4 KB9022 ZZZ

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X7680638L53
EC_SMB_DA4 +3VS Samsung 1G onboard RAM
+3VS X76DDR4S@ GPP Port Table DisplayPort Table

Port Device Port Device

GPP0 CardReader (PCIe) 0 eDP
EC SM Bus1 address EC SM Bus2 address USB OC MAPPING GPP1 WLAN (PCIe) 1 HDMI
GPP2 3
Device Address HEX Device Address HEX OC# USB Port SSD x 2 (PCIe)
Smart Battery 0001 011x b 16H APU 1001 100X b 98H
GPP3 2
0 USB2_0_port1 USB3_0_port1 GPP4
Charger 0001 0010 b 12H G-SEN (M/B) 0001 1000 b 18H
1 USB2_0_port2 USB3_0_port2 GPP5
G-SEN (S/B) 0001 1001 b 19H SSD x 4 (PCIe)
3
Thermal sensor 1001 101xb 9AH
2 GPP6 3

3 GPP7

APU I2C Bus address USB3.0 Port Table USB2.0 Port Table
Port Device Address HEX

I2C 1 G-sensor (Reserve) Port Device Port Device

DDR so-DIMM 1010 001Xb A2H
I2C 2
Touch Panel (Wacom) 0X0A
0 Type C Right 0 Type C Right
Touch Pad (Synaptics) $2C 1 1
I2C 3
USB3.0 Left-1 USB3.0 Left-1
Touch Pad (Elan) 0X15 2 2
USB3.0 Left-2 USB3.0 Left-2
G-sensor 3 3 Camera
4 4 USB Hub
5 NGFF_BT
4-1 Touch Screen
4-2 Finger Print
4-3
4
4-4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NOTES LIST
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Thursday, December 20, 2018 Sheet 3 of 41
A B C D E
 A B C D E

Shut
Power Sequence Boot Down

VCIN1_AC_IN
VCIN1_AC_IN
EC Pin 110 Intput
1
+3VLP 1
+3VLP
EC_ON
EC Pin 112 Output EC_ON
+5VALW
+5VALW
AC Plug
+3VALW
+3VALW
3V/5VALW_PG
3V/5VALW_PG
+1.8VALW
+1.8VALW
+0.8VALW
+0.8VALW

ON/OFF#
EC Pin 114 Intput ON/OFF#
T1_Min : 10ms
EC_RSMRST#
EC Pin 100 Output EC_RSMRST#
T2 : 15ms~26ms
RTC_CLK
RTC_CLK
PBTN_OUT#
EC Pin 122 Output PBTN_OUT#
PM_SLP_S5#
2
EC Pin 123 Intput PM_SLP_S5# 2
T3 : 30us~64us
PM_SLP_S3#
EC Pin 6 Intput PM_SLP_S3#
SYSON
EC Pin 95 Output SYSON
+2.5V
+2.5V_MEM
+1.2V
+1.2V_DDR
SUSP#
EC Pin 116 Output

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SUSP#

0.8VS_PWR_EN 0.8VS_PWR_EN
EC Pin 98 Output
+5VS +5VS

+3VS +3VS

+1.8VS +1.8VS

+0.8VS +0.8VS

+0.6VS +0.6VS

VR_ON VR_ON
EC Pin 121 Output
3 3

+APU_CORE +APU_CORE

+APU_CORE_SOC +APU_CORE_SOC

VGATE VGATE
T5_Min : 1ms

PCH_PWROK PCH_PWROK
EC Pin 32 Output
APU_PWRGD APU_PWRGD

EC Pin 13 Intput PLT_RST# PLT_RST#

T8 : 15ms~17ms

PCIE_RST# PCIE_RST#

APU_RST# APU_RST#

CLK_PCIE CLK_PCIE
T9 : 12ms~14.6ms

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 4 of 41
A B C D E
 A B C D E

Main Func = CPU

1 1

UC1A @
UC1I @
MEMORY A
[12] DDR_A_MA[13..0]
DDR_A_DQ[63..0] [12] MEMORY B
DDR_A_MA0 [13] DDR_B_MA[13..0]
AF25 MA_ADD0
DDR_A_MA1 DDR_A_DQ0 DDR_B_MA0 DDR_B_DQ[63..0] [13]
AE23 MA_ADD1 MA_DATA0 J21 AG30 MB_ADD0
DDR_A_MA2 AD27 MA_ADD2 MA_DATA1 H21 DDR_A_DQ1 DDR_B_MA1 AC32 MB_ADD1 MB_DATA0 B21 DDR_B_DQ0
DDR_A_MA3 AE21 MA_ADD3 MA_DATA2 F23 DDR_A_DQ2 DDR_B_MA2 AC30 MB_ADD2 MB_DATA1 D21 DDR_B_DQ1
DDR_A_MA4 AC24 MA_ADD4 MA_DATA3 H23 DDR_A_DQ3 DDR_B_MA3 AB29 MB_ADD3 MB_DATA2 B23 DDR_B_DQ2
DDR_A_MA5 AC26 MA_ADD5 MA_DATA4 G20 DDR_A_DQ4 DDR_B_MA4 AB31 MB_ADD4 MB_DATA3 D23 DDR_B_DQ3
DDR_A_MA6 AD21 MA_ADD6 MA_DATA5 F20 DDR_A_DQ5 DDR_B_MA5 AA30 MB_ADD5 MB_DATA4 A20 DDR_B_DQ4
DDR_A_MA7 AC27 MA_ADD7 MA_DATA6 J22 DDR_A_DQ6 DDR_B_MA6 AA29 MB_ADD6 MB_DATA5 C20 DDR_B_DQ5
DDR_A_MA8 AD22 MA_ADD8 MA_DATA7 J23 DDR_A_DQ7 DDR_B_MA7 Y30 MB_ADD7 MB_DATA6 A22 DDR_B_DQ6
DDR_A_MA9 AC21 MA_ADD9 DDR_B_MA8 AA31 MB_ADD8 MB_DATA7 C22 DDR_B_DQ7
DDR_A_MA10 AF22 MA_ADD10 MA_DATA8 G25 DDR_A_DQ8 DDR_B_MA9 W29 MB_ADD9
DDR_A_MA11 AA24 MA_ADD11 MA_DATA9 F26 DDR_A_DQ9 DDR_B_MA10 AH29 MB_ADD10 MB_DATA8 D24 DDR_B_DQ8
DDR_A_MA12 AC23 MA_ADD12 MA_DATA10 L24 DDR_A_DQ10 DDR_B_MA11 Y32 MB_ADD11 MB_DATA9 A25 DDR_B_DQ9
DDR_A_MA13 AJ25 MA_ADD13_BANK2 MA_DATA11 L26 DDR_A_DQ11 DDR_B_MA12 W31 MB_ADD12 MB_DATA10 D27 DDR_B_DQ10
AG27 MA_WE_L_ADD14 MA_DATA12 L23 DDR_A_DQ12 DDR_B_MA13 AL30 MB_ADD13_BANK2 MB_DATA11 C27 DDR_B_DQ11
[12] DDR_A_WE# DDR_A_DQ13 DDR_B_DQ12
AG23 MA_CAS_L_ADD15 MA_DATA13 F25 AK30 MB_WE_L_ADD14 MB_DATA12 C23
[12] DDR_A_CAS# DDR_A_DQ14 [13] DDR_B_WE# DDR_B_DQ13
AG26 MA_RAS_L_ADD16 MA_DATA14 K25 AK32 MB_CAS_L_ADD15 MB_DATA13 B24
[12] DDR_A_RAS# DDR_A_DQ15 [13] DDR_B_CAS# DDR_B_DQ14
MA_DATA15 K27 AJ30 MB_RAS_L_ADD16 MB_DATA14 C26
[13] DDR_B_RAS# DDR_B_DQ15
MB_DATA15 B27
AF21 MA_BANK0 MA_DATA16 M25 DDR_A_DQ16
[12] DDR_A_BA0 DDR_A_DQ17 DDR_B_DQ16
AF27 MA_BANK1 MA_DATA17 M27 AH31 MB_BANK0 MB_DATA16 C30
[12] DDR_A_BA1 DDR_A_DQ18 [13] DDR_B_BA0 DDR_B_DQ17
MA_DATA18 P27 AG32 MB_BANK1 MB_DATA17 E29
DDR_A_BG0 DDR_A_DQ19 [13] DDR_B_BA1 DDR_B_DQ18
AA21 MA_BG0 MA_DATA19 R24 MB_DATA18 H29
[12] DDR_A_BG0 DDR_A_BG1 DDR_A_DQ20 DDR_B_BG0 DDR_B_DQ19
AA27 MA_BG1 MA_DATA20 L27 V31 MB_BG0 MB_DATA19 H31
[12] DDR_A_BG1 DDR_A_DQ21 [13] DDR_B_BG0 DDR_B_BG1 DDR_B_DQ20
MA_DATA21 M24 V29 MB_BG1 MB_DATA20 A28
DDR_A_ACT# DDR_A_DQ22 [13] DDR_B_BG1 DDR_B_DQ21
AA22 MA_ACT_L MA_DATA22 P24 MB_DATA21 D28
[12] DDR_A_ACT# DDR_A_DQ23 DDR_B_ACT# DDR_B_DQ22
MA_DATA23 P25 V30 MB_ACT_L MB_DATA22 F31
[12] DDR_A_DM[7..0] DDR_A_DM0 [13] DDR_B_ACT# DDR_B_DQ23
F21 MA_DM0 MB_DATA23 G30
DDR_A_DM1 DDR_A_DQ24 [13] DDR_B_DM[7..0] DDR_B_DM0
G27 MA_DM1 MA_DATA24 M22 C21 MB_DM0
DDR_A_DM2 N24 MA_DM2 MA_DATA25 N21 DDR_A_DQ25 DDR_B_DM1 C25 MB_DM1 MB_DATA24 J29 DDR_B_DQ24
DDR_A_DM3 N23 MA_DM3 MA_DATA26 T22 DDR_A_DQ26 DDR_B_DM2 E32 MB_DM2 MB_DATA25 J31 DDR_B_DQ25
2
DDR_A_DM4 AL24 MA_DM4 MA_DATA27 V21 DDR_A_DQ27 DDR_B_DM3 K30 MB_DM3 MB_DATA26 L29 DDR_B_DQ26 2
DDR_A_DM5 AN27 MA_DM5 MA_DATA28 L21 DDR_A_DQ28 DDR_B_DM4 AP30 MB_DM4 MB_DATA27 L31 DDR_B_DQ27
DDR_A_DM6 AW25 MA_DM6 MA_DATA29 M20 DDR_A_DQ29 DDR_B_DM5 AW31 MB_DM5 MB_DATA28 H30 DDR_B_DQ28
DDR_A_DM7 AT21 MA_DM7 MA_DATA30 R23 DDR_A_DQ30 DDR_B_DM6 BB26 MB_DM6 MB_DATA29 H32 DDR_B_DQ29
T27 RSVD_36 MA_DATA31 T21 DDR_A_DQ31 DDR_B_DM7 BD22 MB_DM7 MB_DATA30 L30 DDR_B_DQ30
N32 RSVD_21 MB_DATA31 L32 DDR_B_DQ31
F22 MA_DQS_H0 MA_DATA32 AL27 DDR_A_DQ32
[12] DDR_A_DQS0 DDR_A_DQ33 DDR_B_DQ32
G22 MA_DQS_L0 MA_DATA33 AL25 D22 MB_DQS_H0 MB_DATA32 AP29
[12] DDR_A_DQS0# DDR_A_DQ34 [13] DDR_B_DQS0 DDR_B_DQ33
H27 MA_DQS_H1 MA_DATA34 AP26 B22 MB_DQS_L0 MB_DATA33 AP32
[12] DDR_A_DQS1 DDR_A_DQ35 [13] DDR_B_DQS0# DDR_B_DQ34
H26 MA_DQS_L1 MA_DATA35 AR27 D25 MB_DQS_H1 MB_DATA34 AT29
[12] DDR_A_DQS1# DDR_A_DQ36 [13] DDR_B_DQS1 DDR_B_DQ35
N27 MA_DQS_H2 MA_DATA36 AK26 B25 MB_DQS_L1 MB_DATA35 AU32
[12] DDR_A_DQS2 DDR_A_DQ37 [13] DDR_B_DQS1# DDR_B_DQ36
N26 MA_DQS_L2 MA_DATA37 AK24 F29 MB_DQS_H2 MB_DATA36 AN30
[12] DDR_A_DQS2# DDR_A_DQ38 [13] DDR_B_DQS2 DDR_B_DQ37
R21 MA_DQS_H3 MA_DATA38 AM24 F30 MB_DQS_L2 MB_DATA37 AP31
[12] DDR_A_DQS3 DDR_A_DQ39 [13] DDR_B_DQS2# DDR_B_DQ38
P21 MA_DQS_L3 MA_DATA39 AP27 K31 MB_DQS_H3 MB_DATA38 AR30
[12] DDR_A_DQS3# [13] DDR_B_DQS3 DDR_B_DQ39
AM26 MA_DQS_H4 K29 MB_DQS_L3 MB_DATA39 AT31
[12] DDR_A_DQS4 DDR_A_DQ40 [13] DDR_B_DQS3#
AM27 MA_DQS_L4 MA_DATA40 AM23 AR29 MB_DQS_H4
[12] DDR_A_DQS4# DDR_A_DQ41 [13] DDR_B_DQS4 DDR_B_DQ40
AN24 MA_DQS_H5 MA_DATA41 AM21 AR31 MB_DQS_L4 MB_DATA40 AU29
[12] DDR_A_DQS5 DDR_A_DQ42 [13] DDR_B_DQS4# DDR_B_DQ41
AN25 MA_DQS_L5 MA_DATA42 AR25 AW30 MB_DQS_H5 MB_DATA41 AV30

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[12] DDR_A_DQS5# DDR_A_DQ43 [13] DDR_B_DQS5 DDR_B_DQ42
AU23 MA_DQS_H6 MA_DATA43 AU27 AW29 MB_DQS_L5 MB_DATA42 BB30
[12] DDR_A_DQS6 DDR_A_DQ44 [13] DDR_B_DQS5# DDR_B_DQ43
AT23 MA_DQS_L6 MA_DATA44 AL22 BC25 MB_DQS_H6 MB_DATA43 BA28
[12] DDR_A_DQS6# DDR_A_DQ45 [13] DDR_B_DQS6 DDR_B_DQ44
AV20 MA_DQS_H7 MA_DATA45 AL21 BA25 MB_DQS_L6 MB_DATA44 AU30
[12] DDR_A_DQS7 DDR_A_DQ46 [13] DDR_B_DQS6# DDR_B_DQ45
AW20 MA_DQS_L7 MA_DATA46 AP24 BC22 MB_DQS_H7 MB_DATA45 AU31
[12] DDR_A_DQS7# DDR_A_DQ47 [13] DDR_B_DQS7 DDR_B_DQ46
V24 RSVD_41 MA_DATA47 AP23 BA22 MB_DQS_L7 MB_DATA46 AY32
[13] DDR_B_DQS7# DDR_B_DQ47
V23 RSVD_40 N31 RSVD_20 MB_DATA47 AY29
MA_DATA48 AW26 DDR_A_DQ48 N29 RSVD_18
AD25 MA_CLK_H0 MA_DATA49 AV25 DDR_A_DQ49 MB_DATA48 BA27 DDR_B_DQ48
[12] DDR_A_CLK0 DDR_A_DQ50 DDR_B_DQ49
AD24 MA_CLK_L0 MA_DATA50 AV22 AC31 MB_CLK_H0 MB_DATA49 BC27
[12] DDR_A_CLK0# DDR_A_DQ51 [13] DDR_B_CLK0 DDR_B_DQ50
AE26 MA_CLK_H1 MA_DATA51 AW22 AD30 MB_CLK_L0 MB_DATA50 BA24
DDR_A_DQ52 [13] DDR_B_CLK0# DDR_B_DQ51
AE27 MA_CLK_L1 MA_DATA52 AU26 AD29 MB_CLK_H1 MB_DATA51 BC24
DDR_A_DQ53 [13] DDR_B_CLK1 DDR_B_DQ52
MA_DATA53 AV27 AD31 MB_CLK_L1 MB_DATA52 BD28
DDR_A_DQ54 [13] DDR_B_CLK1# DDR_B_DQ53
MA_DATA54 AW23 AE30 MB_CLK_H2 MB_DATA53 BB27
MA_DATA55 AT22 DDR_A_DQ55 AE32 MB_CLK_L2 MB_DATA54 BB25 DDR_B_DQ54
AF29 MB_CLK_H3 MB_DATA55 BD25 DDR_B_DQ55
MA_DATA56 AW21 DDR_A_DQ56 AF31 MB_CLK_L3
AG21 MA_CS_L0 MA_DATA57 AU21 DDR_A_DQ57 MB_DATA56 BC23 DDR_B_DQ56
[12] DDR_A_CS0# DDR_A_DQ58 DDR_B_DQ57
AJ27 MA_CS_L1 MA_DATA58 AP21 AJ31 MB0_CS_L0 MB_DATA57 BB22
DDR_A_DQ59 [13] DDR_B_CS0# DDR_B_DQ58
MA_DATA59 AN20 AM31 MB0_CS_L1 MB_DATA58 BC21
DDR_A_DQ60 [13] DDR_B_CS1# DDR_B_DQ59
3 MA_DATA60 AR22 AJ29 MB1_CS_L0 MB_DATA59 BD20 3
MA_DATA61 AN22 DDR_A_DQ61 AM29 MB1_CS_L1 MB_DATA60 BB23 DDR_B_DQ60
MA_DATA62 AT20 DDR_A_DQ62 MB_DATA61 BA23 DDR_B_DQ61
MA_DATA63 AR20 DDR_A_DQ63 MB_DATA62 BB21 DDR_B_DQ62
Y23 MA_CKE0 MB_DATA63 BA21 DDR_B_DQ63
[12] DDR_A_CKE0
Y26 MA_CKE1 RSVD_34 T24 U29 MB0_CKE0
[13] DDR_B_CKE0
RSVD_35 T25 T30 MB0_CKE1 RSVD_17 M31
[13] DDR_B_CKE1
RSVD_51 W25 V32 MB1_CKE0 RSVD_19 N30
RSVD_52 W27 U31 MB1_CKE1 RSVD_26 P31
AG24 MA_ODT0 RSVD_27 R26 RSVD_29 R32
[12] DDR_A_ODT0
AJ22 MA_ODT1 RSVD_28 R27 AL31 MB0_ODT0 RSVD_16 M30
[13] DDR_B_ODT0
RSVD_43 V27 AM32 MB0_ODT1 RSVD_15 M29
[13] DDR_B_ODT1
RSVD_42 V26 AL29 MB1_ODT0 RSVD_25 P30
AM30 MB1_ODT1 RSVD_24 P29
AA25 MA_ALERT_L
[12] DDR_A_ALERT# DDR_A_PAR
MA_PAROUT AF24 DDR_A_PAR [12] W30 MB_ALERT_L
DDR_A_EVENT# [13] DDR_B_ALERT# DDR_B_PAR
AE24 MA_EVENT_L MB_PAROUT AG31
DDR_B_EVENT# DDR_B_PAR [13]
Y24 MA_RESET_L AG29 MB_EVENT_L
[12] DDR_A_RST# [13] DDR_B_EVENT#
FP5 REV 0.90 T31 MB_RESET_L
PART 1 OF 13
[13] DDR_B_RST#
FP5 REV 0.90
FP5_BGA1140~D PART 9 OF 13
FP5_BGA1140~D

DDR_B_RST# 1 2 @ESD@

CC85
EVENT# pull high 100P_0402_50V8J

+1.2V
ESD
4 4
RC1 1 2 1K_0402_5% DDR_B_EVENT#

RC2 1 2 1K_0402_5% DDR_A_EVENT#

MD@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP5 DDR4 MEMORY I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Wednesday, December 19, 2018 Sheet 5 of 41
A B C D E
 A B C D E

Main Func = CPU

UC1B @
1 PCIE 1

P8 P_GFX_RXP0 P_GFX_TXP0 N1
P9 P_GFX_RXN0 P_GFX_TXN0 N3

N6 P_GFX_RXP1 P_GFX_TXP1 M2
N7 P_GFX_RXN1 P_GFX_TXN1 M4

M8 P_GFX_RXP2 P_GFX_TXP2 L2
M9 P_GFX_RXN2 P_GFX_TXN2 L4

L6 P_GFX_RXP3 P_GFX_TXP3 L1
L7 P_GFX_RXN3 P_GFX_TXN3 L3

K11 P_GFX_RXP4 P_GFX_TXP4 K2

J11 P_GFX_RXN4 P_GFX_TXN4 K4

H6 P_GFX_RXP5 P_GFX_TXP5 J2
H7 P_GFX_RXN5 P_GFX_TXN5 J4

G6 P_GFX_RXP6 P_GFX_TXP6 H1
F7 P_GFX_RXN6 P_GFX_TXN6 H3

G8 P_GFX_RXP7 P_GFX_TXP7 H2
2 2
F8 P_GFX_RXN7 P_GFX_TXN7 H4

PCIE_ARX_DTX_P0 N10 P_GPP_RXP0 P_GPP_TXP0 N2 PCIE_ATX_DRX_P0 CC9 1 2 0.1U_0201_10V6K

[22] PCIE_ARX_DTX_P0 PCIE_ATX_C_DRX_P0 [22]
CardReader PCIE_ARX_DTX_N0 N9 P_GPP_RXN0 P_GPP_TXN0 P3 PCIE_ATX_DRX_N0 CC10 1 2 0.1U_0201_10V6K CardReader
[22] PCIE_ARX_DTX_N0 PCIE_ATX_C_DRX_N0 [22]
PCIE_ARX_DTX_P1 L10 P_GPP_RXP1 P_GPP_TXP1 P4 PCIE_ATX_DRX_P1 CC11 1 2 0.1U_0201_10V6K
[17] PCIE_ARX_DTX_P1 PCIE_ATX_C_DRX_P1 [17]
WLAN PCIE_ARX_DTX_N1 L9 P_GPP_RXN1 P_GPP_TXN1 P2 PCIE_ATX_DRX_N1 CC12 1 2 0.1U_0201_10V6K WLAN
[17] PCIE_ARX_DTX_N1 PCIE_ATX_C_DRX_N1 [17]
PCIE_ARX_DTX_P2 L12 P_GPP_RXP2 P_GPP_TXP2 R3 PCIE_ATX_DRX_P2 CC13 1 2 0.22U_0402_6.3V6K PCIE_ATX_C_DRX_P2
[19] PCIE_ARX_DTX_P2 PCIE_ATX_C_DRX_P2 [19]
PCIE_ARX_DTX_N2 M11 R1 PCIE_ATX_DRX_N2 CC14 1 2 0.22U_0402_6.3V6K PCIE_ATX_C_DRX_N2

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P_GPP_RXN2 P_GPP_TXN2 PCIE_ATX_C_DRX_N2 [19]
[19] PCIE_ARX_DTX_N2
2nd_SSD
2nd_SSD PCIE_ARX_DTX_P3 P12 P_GPP_RXP3 P_GPP_TXP3 T4 PCIE_ATX_DRX_P3 CC15 1 2 0.22U_0402_6.3V6K PCIE_ATX_C_DRX_P3
[19] PCIE_ARX_DTX_P3 PCIE_ATX_C_DRX_P3 [19]
PCIE_ARX_DTX_N3 P11 P_GPP_RXN3 P_GPP_TXN3 T2 PCIE_ATX_DRX_N3 CC16 1 2 0.22U_0402_6.3V6K PCIE_ATX_C_DRX_N3
[19] PCIE_ARX_DTX_N3 PCIE_ATX_C_DRX_N3 [19]

PCIE_ARX_DTX_P4 V6 P_GPP_RXP4 P_GPP_TXP4 W2 PCIE_ATX_DRX_P4 CC1 1 2 0.22U_0402_6.3V6K PCIE_ATX_C_DRX_P4

[18] PCIE_ARX_DTX_P4 PCIE_ATX_C_DRX_P4 [18]
PCIE_ARX_DTX_N4 V7 P_GPP_RXN4 P_GPP_TXN4 W4 PCIE_ATX_DRX_N4 CC2 1 2 0.22U_0402_6.3V6K PCIE_ATX_C_DRX_N4
[18] PCIE_ARX_DTX_N4 PCIE_ATX_C_DRX_N4 [18]
PCIE_ARX_DTX_P5 T8 P_GPP_RXP5 P_GPP_TXP5 W3 PCIE_ATX_DRX_P5 CC3 1 2 0.22U_0402_6.3V6K PCIE_ATX_C_DRX_P5
[18] PCIE_ARX_DTX_P5 PCIE_ATX_C_DRX_P5 [18]
PCIE_ARX_DTX_N5 T9 P_GPP_RXN5 P_GPP_TXN5 V2 PCIE_ATX_DRX_N5 CC4 1 2 0.22U_0402_6.3V6K PCIE_ATX_C_DRX_N5
[18] PCIE_ARX_DTX_N5 PCIE_ATX_C_DRX_N5 [18]
Main_SSD Main_SSD
3 PCIE_ARX_DTX_P6 R6 P_GPP_RXP6/SATA_RXP0 P_GPP_TXP6/SATA_TXP0V1 PCIE_ATX_DRX_P6 CC5 1 2 0.22U_0402_6.3V6K PCIE_ATX_C_DRX_P6 3
[18] PCIE_ARX_DTX_P6 PCIE_ATX_C_DRX_P6 [18]
PCIE_ARX_DTX_N6 R7 P_GPP_RXN6/SATA_RXN0 P_GPP_TXN6/SATA_TXN0V3 PCIE_ATX_DRX_N6 CC6 1 2 0.22U_0402_6.3V6K PCIE_ATX_C_DRX_N6
[18] PCIE_ARX_DTX_N6 PCIE_ATX_C_DRX_N6 [18]
SATA_ARX_DTX_P1 R9 P_GPP_RXP7/SATA_RXP1 P_GPP_TXP7/SATA_TXP1U2 SATA_ATX_DRX_P1 CC7 1 2 0.22U_0402_6.3V6K SATA_ATX_C_DRX_P1
[18] SATA_ARX_DTX_P1 SATA_ATX_C_DRX_P1 [18]
NGFF_SATA SATA_ARX_DTX_N1 R10 P_GPP_RXN7/SATA_RXN1 P_GPP_TXN7/SATA_TXN1U4 SATA_ATX_DRX_N1 CC8 1 2 0.22U_0402_6.3V6K SATA_ATX_C_DRX_N1 NGFF_SATA
[18] SATA_ARX_DTX_N1 SATA_ATX_C_DRX_N1 [18]

FP5 REV 0.90

PART 2 OF 13
FP5_BGA1140~D

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP5 PCIE/UMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 6 of 41
A B C D E
 A B C D E

Main Func = CPU

DP0: eDP
DP1: HDMI
+1.8VS
DP2: N/A
DP3: N/A
QC1
UC1C @ 2 +3VS
Gate
DISPLAY/SVI2/JTAG/TEST
C8 DP0_TXP0 DP_BLON G15 ENBKL_R 1
[14] EDP_TXP0 Drain ENBKL [14,28]
[14] EDP_TXN0 A8 DP0_TXN0 DP_DIGON F15 ENVDD +LCDVDD_CONN PWR switch enable pin VIH=1.2V
INVTPWM_R ENVDD [14] ENBKL_R
DP_VARY_BL L14 3 INVTPWM RC4 1 2 4.7K_0402_5%
D8 Source ENBKL RC5 1 2 2.2K_0402_5%
1 [14] EDP_TXP1 DP0_TXP1 1
[14] EDP_TXN1 B8 DP0_TXN1 DP0_AUXP D9 EDP_AUXP [14] LBSS139WT1G_SC70-3
eDP DP0_AUXN B9 eDP
EDP_AUXN [14]
[14] EDP_TXP2 B6 DP0_TXP2 DP0_HPD C10
EDP_HPD [14]
[14] EDP_TXN2 C7 DP0_TXN2
DP1_AUXP G11 APU_DP1_CTRL_CLK [15]
C6 DP0_TXP3 DP1_AUXN F11 HDMI ENBKL_R RC6 1 2 100K_0402_5%
[14] EDP_TXP3 APU_DP1_CTRL_DAT [15]
[14] EDP_TXN3 D6 DP0_TXN3 DP1_HPD G13 ENVDD RC8 1 2 100K_0402_5%
APU_DP1_HPD [15] INVTPWM_R RC9 1 2 100K_0402_5%
E6 DP1_TXP0 DP2_AUXP J12 +1.8VS EDP_HPD RC10 1 2 100K_0402_5%
[15] APU_DP1_P0
[15] APU_DP1_N0 D5 DP1_TXN0 DP2_AUXN H12 U19
DP2_HPD K13 1 5
E1 NC VCC
[15] APU_DP1_P1 DP1_TXP1
C1 DP1_TXN1 DP3_AUXP J10 INVTPWM_R 2
[15] APU_DP1_N1 A
HDMI DP3_AUXN H10 4
Y INVTPWM [14]
[15] APU_DP1_P2 F3 DP1_TXP2 DP3_HPD K8 3
E4 GND
[15] APU_DP1_N2 DP1_TXN2
DP_STEREOSYNC K15 DP_STEREOSYNC 74AUP1G07GW_TSSOP5
[15] APU_DP1_P3 F4 DP1_TXP3

[15] APU_DP1_N3 F2 DP1_TXN3 RSVD_4 F14

RSVD_3 F12

RSVD_2 F10

+1.8VS

TEST4 AP14 APU_TEST4

T1
TEST5 AN14 APU_TEST5 APU_TEST14 RC11 1 @ 2 10K_0402_5%
T2
APU_TEST15 RC12 1 @ 2 10K_0402_5%
TEST6 F13 APU_TEST6 APU_TEST16 RC13 1 @ 2 10K_0402_5%
T3
APU_TEST17 RC14 1 @ 2 10K_0402_5%
TEST14 G18 APU_TEST14
T4
TEST15 H19 APU_TEST15
2 T5 +1.8VS
2
TEST16 F18 APU_TEST16
T6
TEST17 F19 APU_TEST17
T7
TEST31 W24 APU_TEST31 APU_TEST31 RC15 1 @ 2 1K_0402_5%
T8
RC16 1 @ 2 1K_0402_5%

TEST41 AR11 APU_TEST41

T9
APU_TDI AU2 TDI TEST470 AJ21 APU_TEST470
T10 +1.8VS
APU_TDO AU4 TDO TEST471 AK21 APU_TEST471
T11
APU_TCK AU1 TCK
APU_TMS AU3 TMS
APU_TRST# AV3 TRST_L DP_STEREOSYNC RC17 1 2 1K_0402_5%
APU_DBREQ# AW3 DBREQ_L RC18 1 @ 2 1K_0402_5%

APU_RST# AW4 V4 SMU_ZVDDP

Stereosync need to High to enable HDMI functionality,
RESET_L SMU_ZVDD

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APU_PWRGD AW2 PWROK
[38] APU_PWRGD
T12
[26,28] EC_SMB_CK2 H14 SIC CORETYPE AW11 CORETYPE T13
[26,28] EC_SMB_DA2 J14 SID T14
APU_ALERT# J15 ALERT_L
RC21 1 @ 2 0_0402_5% THERMTRIP# AP16 THERMTRIP_L VDDP_SENSE AN11 APU_VDDP_RUN_FB_H
[28] EC_THERMTRIP# APU_VDDP_RUN_FB_H [37] +0.8VS
[28] H_PROCHOT# L19 PROCHOT_L VDDCR_SOC_SENSEJ19 APU_VDDSOC_SEN [38]
VDDCR_SENSE K18 APU_VDDCR_SEN [38]
T15
F16 SVC0 SMU_ZVDDP RC22 1 2 196_0402_1%
[38] APU_SVC
H16 SVD0 VSS_SENSE_A J18 APU_VDD_RUN_FB_L
[38] APU_SVD APU_VDD_RUN_FB_L [38] +3VALW
J16 SVT0 FP5 REV 0.90 VSS_SENSE_B AM11 APU_VDDP_RUN_FB_L
[38] APU_SVT APU_VDDP_RUN_FB_L [37]
PART 3 OF 13
FP5_BGA1140~D
CORETYPE RC23 1 @ 2 1K_0402_5%

3 3
+3VS
+1.8VS HDT+ (debug + HDT@)
RC24 1 2 300_0402_5% APU_RST#
5

RC25 1 2 300_0402_5% APU_PWRGD UC22

1 +1.8VALW +1.8VALW
P

NC 4 APU_RST#
+3VS 2 Y
[28] APU_RST#_EC A
G

JHDT1
74AUP1G07GW_SC70-5 1 2 APU_TCK APU_TRST# RHDT1 1 @ 2 1K_0402_5%
3

RC31 1 2 1K_0201_5% APU_ALERT# @ 1 2 APU_TCK RHDT2 1 @ 2 1K_0402_5%

RC28 1 2 1K_0201_5% H_PROCHOT# 3 4 APU_TMS APU_TMS RHDT3 1 @ 2 1K_0402_5%
RC29 1 2 1K_0201_5% THERMTRIP# 3 4 APU_TDI RHDT4 1 @ 2 1K_0402_5%
5 6 APU_TDI APU_DBREQ# RHDT5 1 @ 2 1K_0402_5%
5 6
RC30 1 @ 2 220_0402_5% APU_PWRGD RC1112 @ 1 0_0402_5% 7 8 APU_TDO
7 8
APU_TRST# RHDT61 @ 2 33_0402_5% APU_TRST#_R 9 10 APU_PWRGD
9 10
RHDT71 @ 2 10K_0402_5% 11 12 APU_RST# @
11 12 APU_TDI CHDT1 1 2 0.01U_0402_16V7K
Reserve for sequence tuning RHDT81 @ 2 10K_0402_5% 13
13 14
14
@
RHDT91 @ 2 10K_0402_5% 15 16 APU_DBREQ# APU_DBREQ# CHDT2 1 2 0.01U_0402_16V7K
15 16
17 18 @
17 18 APU_TRST# CHDT3 1 2 0.01U_0402_16V7K
19 20
19 20

ESD SAMTE_ASP-136446-07-B
ME@

4 ESD@ CC17 1 2 100P_0402_50V8J H_PROCHOT# 4

ESD@ CC18 1 2 100P_0402_50V8J APU_PWRGD

ESD@ CC19 1 2 100P_0402_50V8J APU_RST#

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP5 DISP/MISC/HDT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Wednesday, December 19, 2018 Sheet 7 of 41
A B C D E
 A B C D E

Main Func = CPU

+1.8VALW

RC36 1 2 22K_0402_5%
RAM vender MEM_ID2 MEM_ID1 MEM_ID0
EC_RSMRST# [28]
Hynix 1 1 1
Micron 1 1 0
1
Samsung 1 0 1 1

RC108 1 2 33_0402_5% HDA_RST#

No onboard 0 0 0
[20] HDA_RST#_AUDIO HDA_BIT_CLK
RC67 1 EMI@ 2 33_0402_5%
[20] HDA_BITCLK_AUDIO HDA_SDOUT +3VALW
RC68 1 2 33_0402_5%
[20] HDA_SDOUT_AUDIO HDA_SYNC
RC69 1 2 33_0402_5% RC42
[20] HDA_SYNC_AUDIO
10K_0201_5%
NO_MD@
RC70 1
RC71 1
2 1K_0201_5%
2 1K_0201_5% EMI RC41

2
10K_0201_5%
UC1D @ NO_MD@ RC37 RC38 RC39
ACPI/AUDIO/I2C/GPIO/MISC 10K_0201_5% 10K_0201_5% 10K_0201_5%
RC43 X76RAM@ X76RAM@ X76RAM@
EGPIO41/SFI_S5_EGPIO41AW12 10K_0201_5%

1
AGPIO39/SFI_S5_AGPIO39AU12 NO_MD@
RC34 1 2 33_0402_5% APU_PCIE0_RST# BD5 PCIE_RST0_L/EGPIO26 MEM_ID0
APU_PCIE_RST#_R RC35 1 @ 2 33_0402_5% APU_PCIE1_RST# BB6 PCIE_RST1_L/EGPIO27 AR13
I2C0_SCL/SFI0_I2C_SCL/EGPIO151 MEM_ID1
T22 Internal Pull-down required by SW
EC_RSMRST# AT16 RSMRST_L AT13
I2C0_SDA/SFI0_I2C_SDA/EGPIO152 MEM_ID2
T21 Internal Pull-down required by SW

CC21 1 2 CC20 PBTN_OUT# AR15 PWR_BTN_L/AGPIO0 AN8

I2C1_SCL/SFI1_I2C_SCL/EGPIO149 I2C_1_SCL
[28] PBTN_OUT#
@ESD@ APU_FCH_PWRGD_R AV6 PWR_GOOD AN9
I2C1_SDA/SFI1_I2C_SDA/EGPIO150 I2C_1_SDA EC(G-Sensor)

2
150P_0402_50V8J

150P_0402_50V8J
CC23 1 2 100P_0402_50V8J EC_RSMRST# @ SYS_RESET# AP10 SYS_RESET_L/AGPIO1
APU_PCIE_WAKE# AV11 WAKE_L/AGPIO2 BC20
I2C2_SCL/EGPIO113/SCL0 I2C_2_SCL_R RC117 1 @ 2 0_0402_5% I2C_2_SCL RC42 RC41 RC43
2 1 I2C_2_SCL [13,14]
ESD@ I2C2_SDA/EGPIO114/SDA0BA20 I2C_2_SDA_R RC118 1 @ 2 0_0402_5% I2C_2_SDA DDR4/Touch Panel 10K_0201_5% 10K_0201_5% 10K_0201_5%
I2C_2_SDA [13,14]
CC24 1 2 100P_0201_25V8J SYS_RESET# PM_SLP_S3# AV13 SLP_S3_L X76RAM@ X76RAM@ X76RAM@
[28] PM_SLP_S3#
PM_SLP_S5# AT14 SLP_S5_L I2C3_SCL/AGPIO19/SCL1AM9 I2C_3_SCL TouchPad
[28,33,36] PM_SLP_S5#

1
I2C3_SDA/AGPIO20/SDA1AM10 I2C_3_SDA EC(G-Sensor)
AR8 S0A3_GPIO/AGPIO10
L16
MEM_ID
ESD Internal Pull-down required by SW
AT10
AN6
AC_PRES/AGPIO23
LLB_L/AGPIO12
PSA_I2C_SCL
PSA_I2C_SDA M16

3.3VALW Domain AGPIO3 AT15

+3VS
AW8 EGPIO42 3.3VALW Domain AGPIO4/SATAE_IFDET AW10
MODEL ID0 Detect

2
3.3VALW Domain AGPIO5/DEVSLP0 AP9 PCIE_DET
MEM_ID0 PCIE_DET [18] S540 0
3.3VALW Domain AGPIO6/DEVSLP1 AU10 RC112
3.3VS Domain SATA_ACT_L/AGPIO130AV15 10K_0201_5%
C340 1 C340@
+3VALW 3.3VALW Domain AGPIO9 AU7 MEM_ID1

1
3.3VALW Domain AGPIO40 AU6 MODEL_ID0
Internal Pull-down required by SW
2 3.3VS Domain AGPIO69 AW13 MODEL_ID0 2
3.3VS Domain AGPIO86 AW15 SENSOR_EC_INT#
SENSOR_EC_INT# [28]

2
RC45 1 2 10K_0201_5% PCIE_DET HDA_BIT_CLK AR2 AZ_BITCLK/TDM_BCLK_MIC
RC47 1 2 10K_0201_5% PBTN_OUT# HDA_SDIN0 AP7 AZ_SDIN0/CODEC_GPI RC115
[20] HDA_SDIN0
RC48 1 @ 2 10K_0402_5% APU_PCIE_WAKE# AP1 AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK INTRUDER_ALERT AU14 10K_0201_5%
check list discuss unconnected if no used AP4 AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK 3.3VS Domain SPKR/AGPIO91 AU16 HDA_SPKR S540@
HDA_SPKR [20]
HDA_RST# AP3 AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC 3.3VALW Domain BLINK/AGPIO11 AV8 MEM_ID2

1
RC109 1 2 2.2K_0402_5% I2C_1_SCL HDA_SYNC AR4
RC110 1 2 2.2K_0402_5% I2C_1_SDA HDA_SDOUT AR3
AZ_SYNC/TDM_FRM_MIC
AZ_SDOUT/TDM_FRM_PLAYBACK 3.3VS Domain
3.3VS Domain
GENINT1_L/AGPIO89 AW16
GENINT2_L/AGPIO90 BD15
TS_I2C_RESET#
TS_INT#
TS_I2C_RESET#
TS_INT# [14]
[14] MODEL ID
RC61 1 2 2.2K_0402_5% I2C_3_SCL AT2 SW_MCLK/TDM_BCLK_BT
RC62 1 2 2.2K_0402_5% I2C_3_SDA AT4 SW_DATA0/TDM_DOUT_BT
AR6 AGPIO7/FCH_ACP_I2S_SDIN_BT 3.3VS Domain FANIN0/AGPIO84 AR18 MODEL_ID1
AP6 AGPIO8/FCH_ACP_I2S_LRCLK_BT 3.3VS Domain FANOUT0/AGPIO85 AT18 TP_INT# +3VS
TP_INT# [27]
+3VS
FP5 REV 0.90
PART 4 OF 13
MODEL_ID1 Detect

2
FP5_BGA1140~D 0
RC56 1 2 2.2K_0402_5% I2C_2_SCL RC113
RC57 1 2 2.2K_0402_5% I2C_2_SDA 10K_0201_5%
1 @

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1
RC50 1 2 1K_0201_5% HDA_RST# +3VALW MODEL_ID1
RC53 1 @ 2 10K_0402_5% HDA_SDIN0
RC54 1 @ 2 10K_0402_5% HDA_BIT_CLK

2
+3VALW +3VALW RC116
1 10K_0201_5%
@ @

1
CC26

1
0.1U_0201_10V6K

CC93 @ 1 2 150P_0201_50V8G I2C_1_SCL

5 RC55
8.2K_0402_5%
2
Reserve
CC94 @ 1 2 150P_0201_50V8G I2C_1_SDA UC7 UC8

5
1 MC74VHC1G08DFT2G SC70 5P
P

NC 4 APU_FCH_PWRGD_R APU_PCIE_RST#_R 2

P
CC95 @ 1 2 150P_0402_50V8J I2C_2_SCL SYS_PWRGD_EC 2 Y B 4
[28] SYS_PWRGD_EC A Y APU_PCIE_RST# [17,18,22]
G

CC96 @ 1 2 150P_0402_50V8J I2C_2_SDA 1

A

G
74AUP1G07GW_SC70-5 +1.8VALW +3VALW
3

SA00007WE00 @

3
CC97 @ 1 2 150P_0402_50V8J I2C_3_SCL @ @ RC72
CC98 @ 1 2 150P_0402_50V8J I2C_3_SDA 10K_0402_5%

2
2
3 RC59 RC60 3
RC64 2 @ 1 0_0402_5% 10K_0201_5% 10K_0201_5%
RC73 1 @ 2 0_0402_5%

1
[9] APU_SPI_CLK_R
SYS_RESET#
+3VS

1
RC65 RC66
5

2K_0402_5% 2K_0402_5%
G

@ @

2
4 3 RC121 2 @ 1 0_0201_5% I2C_1_SCL
S

[28] I2C_1_SCL_R
D

RC122 2 @ 1 0_0201_5% I2C_1_SDA

Strap pin
2
G

QC2B
2N7002KDW_SOT363-6
RC123 2 1 0_0201_5% I2C_3_SCL
1 6 RC124 2 1 0_0201_5% I2C_3_SDA
S

[28] I2C_1_SDA_R
D

STRAP DEFINITION
QC2A
2N7002KDW_SOT363-6
1 : Use 48MHZ Crystal Clock and Generate both internal
and external clocks (Default)
+3VS SPI_CLK
0 : Use 100MHZ PCIE clock as reference clock
and generate internal clocks only
5
G

1 : Normal reset mode (Default)

4 3 RC125 2 @ 1 0_0201_5%
SYS_RST# 0 : short reset mode
S

[27] I2C_3_SCL_R
D

RC126 2 @ 1 0_0201_5%
2
G

QC3B
2N7002KDW_SOT363-6
4 RC127 2 1 0_0201_5% 4
1 6 RC128 2 1 0_0201_5%
S

[27] I2C_3_SDA_R
D

QC3A
2N7002KDW_SOT363-6

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP4 GPIO/AZ/MISC/STRAPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 8 of 41
A B C D E
 A B C D E

Main Func = CPU

48MHz CRYSTAL
UC1E @
CLK/LPC/EMMC/SD/SPI/eSPI/UART

1 1
CLKREQ_SSD2#
AV18 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
[19] CLKREQ_SSD2#
48M_X2_R RC74 1 EMI@ 2 33_0402_5% 48M_X2 CLKREQ_SSD1#
AN19 CLK_REQ1_L/AGPIO115
[18] CLKREQ_SSD1#
CLKREQ_SD# AP19 CLK_REQ2_L/AGPIO116
[22] CLKREQ_SD#
2 1 48M_X1_R RC76 1 EMI@ 2 33_0402_5% 48M_X1 CLKREQ_WLAN#AT19 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
[17] CLKREQ_WLAN#
RC75 1M_0402_5% AU19 CLK_REQ4_L/OSCIN/EGPIO132
Internal Pull-down required by SW
AW18 CLK_REQ5_L/EGPIO120
Internal Pull-down required by SW
APU_BT_OFF# AW19 CLK_REQ6_L/EGPIO121
[17] APU_BT_OFF#
2
2 1
1
EMI EGPIO70/SD_CLK BD13
BB14 LPCPD#
T17 Internal Pull-down required by SW

LPC_PD_L/SD_CMD/AGPIO21
CLK_PCIE_SSD2 AK1 GPP_CLK0P LAD0/SD_DATA0/EGPIO104BB12 LPC_AD0_R RC77 2 1 10_0402_5%
[19] CLK_PCIE_SSD2 LPC_AD0 [28]
2nd_SSD CLK_PCIE_SSD2# AK3 GPP_CLK0N LAD1/SD_DATA1/EGPIO105BC11 LPC_AD1_R RC78 2 1 10_0402_5%
[19] CLK_PCIE_SSD2# LPC_AD1 [28]
YC1 LAD2/SD_DATA2/EGPIO106BB15 LPC_AD2_R RC79 2 1 10_0402_5% LPC_AD2 [28]
48MHZ_8PF_7V48000010 CLK_PCIE_SSD1 AM2 GPP_CLK1P LAD3/SD_DATA3/EGPIO107BC15 LPC_AD3_R RC80 2 1 10_0402_5%
[18] CLK_PCIE_SSD1 LPC_AD3 [28]
Main_SSD CLK_PCIE_SSD1# AM4 GPP_CLK1N LPCCLK0/EGPIO74 BA15 LPC_CLK0 RC81 2 1 22_0402_5%
[18] CLK_PCIE_SSD1# LPC_CLK0_EC [28]
BC13
LPC_CLKRUN_L/AGPIO88 CLKRUN# CLKRUN# [28]
CLK_PCIE_SD AM1 GPP_CLK2P LPCCLK1/EGPIO75 BB13
[22] CLK_PCIE_SD Internal Pull-down required by SW
3 4 CardReader CLK_PCIE_SD# AM3 GPP_CLK2N SERIRQ/AGPIO87 BC12
3 4 [22] CLK_PCIE_SD# SERIRQ [28]
1 1 LFRAME_L/EGPIO109BA12 LPC_FRAME# [28]
CLK_PCIE_WLAN AL2 GPP_CLK3P
[17] CLK_PCIE_WLAN
CC27 CC28 WLAN CLK_PCIE_WLAN# AL4 GPP_CLK3N BD11
LPC_RST_L/SD_WP_L/AGPIO32 LPC_RST#_R RC82 2 1 33_0402_5%
[17] CLK_PCIE_WLAN# LPC_RST# [28]
4.7P_0402_50V8B 4.7P_0402_50V8B AGPIO68/SD_CD BA11 LPC_RST# RC83 2 @ 1 100K_0402_5%
2 2 AN2 BA13
GPP_CLK4P LPC_PME_L/SD_PWR_CTRL/AGPIO22 EC_SCI# [28]
AN4 GPP_CLK4N CC29 2 1 150P_0402_50V8J

AN3 GPP_CLK5P
AP2 GPP_CLK5N SPI_ROM_REQ/EGPIO67BC8
SPI_ROM_GNT/AGPIO76 BB8
AJ2 GPP_CLK6P
AJ4 GPP_CLK6N BB11
ESPI_RESET_L/KBRST_L/AGPIO129
+3VS
KB_RST# [28]
BC6
ESPI_ALERT_L/LDRQ0_L/EGPIO108
AJ3 48M_OSC

SPI_CLK/ESPI_CLK BB7 APU_SPI_CLK RC84 2 EMI@ 1 10_0402_1% KB_RST# RC85 2 @ 1 10K_0402_5%

32.768KHz CRYSTAL 48M_X1 BB3
SPI_DI/ESPI_DATA BA9
BB10
APU_SPI_MISO
APU_SPI_MOSI
APU_SPI_CLK_R [8]

32K_X1
X48M_X1 SPI_DO
SPI_WP_L/ESPI_DAT2BA10
SPI_HOLD_L/ESPI_DAT3BC10
APU_SPI_WP#
APU_SPI_HOLD#
EMI
SPI_CS1_L/EGPIO118BC9 APU_SPI_CS1#
2 1 32K_X2 48M_X2 BA5 X48M_X2 BA8
SPI_CS2_L/ESPI_CS_L/AGPIO30 Internal Pull-down required by SW
RC86 20M_0402_5% SPI_CS3_L/AGPIO31 BA6 Internal Pull-down required by SW
SPI_TPM_CS_L/AGPIO29BD8
2 2
YC2 AF8 RSVD_76
1 2 AF9 RSVD_77 UART0_RXD/EGPIO136BA16 UART_0_ARXD_DTXD
UART_0_ARXD_DTXD [17]
UART0_TXD/EGPIO138BB18 UART_0_ATXD_DRXD
32.768KHZ_9PF_X1A000141000200 BC17 UART_0_ATXD_DRXD [17]
UART0_RTS_L/UART2_RXD/EGPIO137 T18
BA18
UART0_CTS_L/UART2_TXD/EGPIO135 T19
1 1 RC87 2 @ 1 22 +-5% 0402 RTC_CLK AW14 RTCCLK UART0_INTR/AGPIO139BD18
[17] RTC_CLK_R T20
CC30 CC31

10P_0402_50V8J 10P_0402_50V8J 32K_X1 AY1 X32K_X1 EGPIO141/UART1_RXDBC18

2 2 EGPIO143/UART1_TXDBA17
BC16
EGPIO142/UART1_RTS_L/UART3_RXD SSD_RST#
BB19 SSD_RST# [18]
EGPIO140/UART1_CTS_L/UART3_TXD
32K_X2 AY4 X32K_X2 AGPIO144/UART1_INTRBB16 APU_WL_OFF#
APU_WL_OFF# [17]

FP5 REV 0.90

PART 5 OF 13
FP5_BGA1140~D

+3VS

Vinafix.com
RC88 2 1 10K_0201_5% CLKREQ_SSD2#
RC89 2 1 10K_0201_5% CLKREQ_SSD1#
RC90 2 1 10K_0201_5% CLKREQ_SD#
RC91 2 1 10K_0201_5% CLKREQ_WLAN#

UC1J @
USB

USB20_P0 AE7 USB_0_DP0 AD2

USBC0_A2/USB_0_TXP0/DP3_TXP2 USB3_ATX_DRX_P0
[25] USB20_P0 USB3_ATX_DRX_P0 [23]
3
USB3.1 Type-C USB20_N0 AE6 USB_0_DM0 AD4
USBC0_A3/USB_0_TXN0/DP3_TXN2 USB3_ATX_DRX_N0 3
[25] USB20_N0 USB3_ATX_DRX_N0 [23]
USB20_P1 AG10 USB_0_DP1 AC2
USBC0_B11/USB_0_RXP0/DP3_TXP3 USB3_ARX_DTX_P0 TYPEC Right
[22] USB20_P1 USB3_ARX_DTX_P0 [23]
USB3.1 Type-A port1 USB20_N1 AG9 USB_0_DM1 AC4
USBC0_B10/USB_0_RXN0/DP3_TXN3 USB3_ARX_DTX_N0
[22] USB20_N1 USB3_ARX_DTX_N0 [23]
USB20_P2 AF12 USB_0_DP2 USBC0_B2/DP3_TXP1AF4
[22] USB20_P2
USB3.1 Type-A port2 USB20_N2 AF11 USB_0_DM2 USBC0_B3/DP3_TXN1AF2
[22] USB20_N2
USB20_P3 AE10 USB_0_DP3 USBC0_A11/DP3_TXP0AE3
[14] USB20_P3
Camera USB20_N3 AE9 USB_0_DM3 USBC0_A10/DP3_TXN0AE1
[14] USB20_N3

USB2.0 Hub
[21] USB20_P4
USB20_P4
USB20_N4
AJ12
AJ11
USB_1_DP0
USB_1_DM0
USB_0_TXP1
USB_0_TXN1
AG3
AG1
USB3_ATX_DRX_P1
USB3_ATX_DRX_N1
USB3_ATX_DRX_P1 [22] 8MB SPI ROM
[21] USB20_N4 USB3_ATX_DRX_N1 [22] +1.8VALW
USB20_P5 USB3_ARX_DTX_P1
Type-A left port1 +1.8VALW
[17] USB20_P5 AD9 USB_1_DP1 USB_0_RXP1 AJ9 USB3_ARX_DTX_P1 [22]
NGFF_BT USB20_N5 AD8 USB_1_DM1 USB_0_RXN1 AJ8 USB3_ARX_DTX_N1 UC2
[17] USB20_N5 USB3_ARX_DTX_N1 [22]
RC92 2 @ 1 10K_0402_5% APU_SPI_MOSI APU_SPI_CS1# 1 8
AG4 USB3_ATX_DRX_P2 RC93 2 1 10K_0402_5% APU_SPI_MISO APU_SPI_MISO 2 CS# VCC 7 APU_SPI_HOLD#
USB_0_TXP2 USB3_ATX_DRX_P2 [22]
USB3_ATX_DRX_N2 APU_SPI_WP# APU_SPI_WP# DO(IO1) HOLD#(IO3) APU_SPI_CLK_R
USB_0_TXN2 AG2 USB3_ATX_DRX_N2 [22] RC94 2 1 10K_0402_5% 3 6 1
RC96 2 1 10K_0402_5% APU_SPI_HOLD# 4 WP#(IO2) CLK 5 APU_SPI_MOSI CC32
USB3_ARX_DTX_P2
Type-A left port2 APU_SPI_CS1# GND DI(IO0)
USB_0_RXP2 AG7 USB3_ARX_DTX_P2 [22] RC95 2 1 10K_0402_5% 0.1U_0201_10V6K
AM6 USBC_I2C_SCL USB_0_RXN2 AG6 USB3_ARX_DTX_N2 GD25LB64CSIGR SOP 8P @
USB3_ARX_DTX_N2 [22] 2
AM7 USBC_I2C_SDA AA2
USBC1_A2/USB_0_TXP3/DP2_TXP2
AA4
USBC1_A3/USB_0_TXN3/DP2_TXN2

Y1
USBC1_B11/USB_0_RXP3/DP2_TXP3
Y3
USBC1_B10/USB_0_RXN3/DP2_TXN3 RC97 2 @EMI@ 1 10_0402_5% APU_SPI_CLK

USBC1_B2/DP2_TXP1AC1 1
USBC1_B3/DP2_TXN1AC3 CC33
USB_OC0# AK10 USB_OC0_L/AGPIO16 10P_0402_50V8J
[22] USB_OC0#
USB_OC1# AK9 USB_OC1_L/AGPIO17 USBC1_A11/DP2_TXP0AB2 @EMI@
[22] USB_OC1# 2
AL9 USB_OC2_L/AGPIO18 USBC1_A10/DP2_TXN0AB4
AL8 USB_OC3_L/AGPIO24
Internal Pull-HIgh required by SW AW7
AT12
AGPIO14/USB_OC4_L
AGPIO13/USB_OC5_L
USB_1_TXP0
USB_1_TXN0
AH4
AH2 EMI
+3VALW USB_1_RXP0 AK7
USB_1_RXN0 AK6
FP5 REV 0.90
PART 10 OF 13
4 RC98 1 2 100K_0201_5% USB_OC0# FP5_BGA1140~D 4
RC99 1 2 100K_0201_5% USB_OC1#

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP5 SATA/CLK/USB/SPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 9 of 41
A B C D E
 A B C D E

Main Func = CPU

+1.2V

+APU_CORE

+APU_CORE_SOC
UC1F @
1
All BU(on bottom side under SOC) Across VDDIO & VSS split. TDC :10A POWER TDC: 35A
1

EDC: 13A M15 VDDCR_SOC_1 VDDCR_1 G7 EDC: 45A

M18 VDDCR_SOC_2 VDDCR_2 G10
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 M19 VDDCR_SOC_3 VDDCR_3 G12
22U_0603_6.3V6M
CC35

22U_0603_6.3V6M
CC36

22U_0603_6.3V6M
CC37

10U_0402_6.3V6M
CC38

10U_0402_6.3V6M
CC91

10U_0402_6.3V6M
CC52

10U_0402_6.3V6M
CC92

10U_0402_6.3V6M
CC39

10U_0402_6.3V6M
CC40

10U_0402_6.3V6M
CC41

10U_0402_6.3V6M
CC42

10U_0402_6.3V6M
CC87

10U_0402_6.3V6M
CC88

10U_0402_6.3V6M
CC89

10U_0402_6.3V6M
CC90

1U_0201_6.3V6M
CC43

1U_0201_6.3V6M
CC44

180P_0402_50V8J
CC45

180P_0402_50V8J
CC46

180P_0402_50V8J
CC47

.22U 6.3V K X5R 0402

CC48

.22U 6.3V K X5R 0402

CC49

.22U 6.3V K X5R 0402

CC50

.22U 6.3V K X5R 0402

CC51
N16 VDDCR_SOC_4 VDDCR_4 G14
N18 VDDCR_SOC_5 VDDCR_5 H8
N20 VDDCR_SOC_6 VDDCR_6 H11
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 P17 VDDCR_SOC_7 VDDCR_7 H15
@ @ @ @ @ @ P19 VDDCR_SOC_8 VDDCR_8 K7
R18 VDDCR_SOC_9 VDDCR_9 K12
R20 VDDCR_SOC_10 VDDCR_10 K14
T19 VDDCR_SOC_11 VDDCR_11 L8
U18 VDDCR_SOC_12 VDDCR_12 M7
U20 VDDCR_SOC_13 VDDCR_13 M10
V19 VDDCR_SOC_14 VDDCR_14 N14
W18 VDDCR_SOC_15 VDDCR_15 P7
+1.2V W20 VDDCR_SOC_16 VDDCR_16 P10
Y19 VDDCR_SOC_17 VDDCR_17 P13
VDDCR_18 P15
TDC :6A T32 VDDIO_MEM_S3_1 VDDCR_19 R8
V28 VDDIO_MEM_S3_2 VDDCR_20 R14
+0.8VS +0.8VALW W28 VDDIO_MEM_S3_3 VDDCR_21 R16
W32 VDDIO_MEM_S3_4 VDDCR_22 T7
+1.8VS Y22 T10
+VDDP_ALW Y25
VDDIO_MEM_S3_5
VDDIO_MEM_S3_6
VDDCR_23
VDDCR_24 T13
Y28 VDDIO_MEM_S3_7 VDDCR_25 T15
AA20 VDDIO_MEM_S3_8 VDDCR_26 T17
AA23 VDDIO_MEM_S3_9 VDDCR_27 U14
RC101 1 @ 2 0_0402_5% VDDIO_AUDIO AA26 VDDIO_MEM_S3_10 VDDCR_28 U16
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AA28 VDDIO_MEM_S3_11 VDDCR_29 V13
22U_0603_6.3V6M
CC53

22U_0603_6.3V6M
CC54

1U_0201_6.3V6M
CC55

1U_0201_6.3V6M
CC56

1U_0201_6.3V6M
CC57

1U_0201_6.3V6M
CC58

1U_0201_6.3V6M
CC59

1U_0201_6.3V6M
CC60

1U_0201_6.3V6M
CC61

1U_0201_6.3V6M
CC62

220P_0201_25V7K
CC63

22U_0603_6.3V6M
CC64

1U_0201_6.3V6M
CC65

1U_0201_6.3V6M
CC66

1U_0201_6.3V6M
CC67
1 1 1 1 1 AA32 VDDIO_MEM_S3_12 VDDCR_30 V15
CC68 CC69 CC83 CC84 CC86 AC20 VDDIO_MEM_S3_13 VDDCR_31 V17
AC22 VDDIO_MEM_S3_14 VDDCR_32 W7
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M
@ AC25 VDDIO_MEM_S3_15 VDDCR_33 W10
2 2 2 2 2 2 AC28 VDDIO_MEM_S3_16 VDDCR_34 W14 2
AD23 VDDIO_MEM_S3_17 VDDCR_35 W16
AD26 VDDIO_MEM_S3_18 VDDCR_36 Y8
AD28 VDDIO_MEM_S3_19 VDDCR_37 Y13
AD32 VDDIO_MEM_S3_20 VDDCR_38 Y15
AE20 VDDIO_MEM_S3_21 VDDCR_39 Y17
AE22 VDDIO_MEM_S3_22 VDDCR_40 AA7
AE25 AA10
BO BU AE28
VDDIO_MEM_S3_23
VDDIO_MEM_S3_24
VDDCR_41
VDDCR_42 AA14
AF23 VDDIO_MEM_S3_25 VDDCR_43 AA16
AF26 VDDIO_MEM_S3_26 VDDCR_44 AA18
AF28 VDDIO_MEM_S3_27 VDDCR_45 AB13
AF32 VDDIO_MEM_S3_28 VDDCR_46 AB15
+1.8VALW +1.8VS +3VALW +3VS

Vinafix.com
AG20 VDDIO_MEM_S3_29 VDDCR_47 AB17
AG22 VDDIO_MEM_S3_30 VDDCR_48 AB19
AG25 VDDIO_MEM_S3_31 VDDCR_49 AC14
AG28 VDDIO_MEM_S3_32 VDDCR_50 AC16
AJ20 VDDIO_MEM_S3_33 VDDCR_51 AC18
AJ23 VDDIO_MEM_S3_34 VDDCR_52 AD7
AJ26 VDDIO_MEM_S3_35 VDDCR_53 AD10
AJ28 VDDIO_MEM_S3_36 VDDCR_54 AD13
1 1 1 1 1 1 1 1 1 1 1 1 AJ32 VDDIO_MEM_S3_37 VDDCR_55 AD15
22U_0603_6.3V6M
CC70

1U_0201_6.3V6M
CC71

1U_0201_6.3V6M
CC72

22U_0603_6.3V6M
CC73

1U_0201_6.3V6M
C1

1U_0201_6.3V6M
CC74

22U_0603_6.3V6M
CC75

1U_0201_6.3V6M
CC76

1U_0201_6.3V6M
CC77

10U_0402_6.3V6M
CC78

1U_0201_6.3V6M
CC79

1U_0201_6.3V6M
CC80
AK28 VDDIO_MEM_S3_38 VDDCR_56 AD17
AL28 VDDIO_MEM_S3_39 VDDCR_57 AD19
@ @ +3VS AL32 VDDIO_MEM_S3_40 VDDCR_58 AE8
2 2 2 2 2 2 2 2 2 2 2 2 VDDCR_59 AE14
VDDIO_AUDIO TDC :0.2A AP12 VDDIO_AUDIO VDDCR_60 AE16
VDDCR_61 AE18
TDC :0.25A AL18 VDD_33_1 VDDCR_62 AF7
AM17 VDD_33_2 VDDCR_63 AF10
+1.8VS VDDCR_64 AF13
+1.8VALW TDC :2A AL20 VDD_18_1 VDDCR_65 AF15
AM19 VDD_18_2 VDDCR_66 AF17
+3VALW AF19
3
BO BU BO BU TDC :0.5A AL19 VDD_18_S5_1
VDDCR_67
VDDCR_68 AG14 3
+0.8VALW AM18 VDD_18_S5_2 VDDCR_69 AG16
VDDCR_70 AG18
TDC :0.25A AL17 VDD_33_S5_1 VDDCR_71 AH13
AM16 VDD_33_S5_2 VDDCR_72 AH15
VDDCR_73 AH17
TDC :1A AL14 VDDP_S5_1 VDDCR_74 AH19
AL15 AJ7
Note : Cap placemet need to close APU +0.8VS AM14
VDDP_S5_2
VDDP_S5_3
VDDCR_75
VDDCR_76 AJ10
VDDCR_77 AJ14
TDC :4A AL13 VDDP_1 VDDCR_78 AJ16
AM12 VDDP_2 VDDCR_79 AJ18
AM13 VDDP_3 VDDCR_80 AK13
AN12 VDDP_4 VDDCR_81 AK15
+RTC_APU AN13 VDDP_5 VDDCR_82 AK17
W>=15mils VDDCR_83 AK19
TDC :4.5uA AT11 VDDBT_RTC_G
+RTC_APU +RTCBATT
W>=15mils 1.5V FP5 REV 0.90
PART 6 OF 13
UC11 FP5_BGA1140~D
[28] EC_CLEAR_CMOS# RC106 1 @ 2 0_0402_5% RC107 1 2 10K_0402_5% 3
Vout 1
2 Vin
GND
0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

1U_0201_6.3V6M

@
1

1 1 AP2138N-1.5TRG1_SOT23-3 CC82
CC99 CLRP1 CC81
@ SHORT PADS
2

2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title
FP4 PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 10 of 41
A B C D E
 A B C D E

Main Func = CPU

UC1L @
UC1G @ UC1H @ UC1K @ RSVD
1 T11 AA9 1
GND GND GND/RSVD RSVD_32 RSVD_62
N12 VSS_316 VSS_62 K32 V8 VSS_124 VSS_186 AG8 AR5 VSS_248 VSS_310 BD16 RSVD_61 AA8
A3 VSS_1 VSS_63 L5 V11 VSS_125 VSS_187 AG11 AR7 VSS_249 VSS_311 BD19 AC7 RSVD_66 RSVD_65 AC6
A5 VSS_2 VSS_64 L13 V12 VSS_126 VSS_188 AG12 AR12 VSS_250 VSS_312 BD21
A7 VSS_3 VSS_65 L15 V14 VSS_127 VSS_189 AG13 AR14 VSS_251 VSS_313 BD23
A10 VSS_4 VSS_66 L18 V16 VSS_128 VSS_190 AG15 AR16 VSS_252 VSS_314 BD26 Y9 RSVD_55
A12 VSS_5 VSS_67 L20 V18 VSS_129 VSS_191 AG17 AR19 VSS_253 VSS_315 BD30 Y10 RSVD_56 RSVD_72 AD11
A14 VSS_6 VSS_68 L25 V20 VSS_130 VSS_192 AG19 AR21 VSS_254
A16 VSS_7 VSS_69 L28 V22 VSS_131 VSS_193 AH14 AR26 VSS_255 W11 RSVD_47 RSVD_67 AC9
A19 VSS_8 VSS_70 M1 V25 VSS_132 VSS_194 AH16 AR28 VSS_256 W12 RSVD_48 RSVD_63 AA11
A21 VSS_9 VSS_71 M5 W1 VSS_133 VSS_195 AH18 AR32 VSS_257
A23 VSS_10 VSS_72 M12 W5 VSS_134 VSS_196 AH20 AU5 VSS_258 V9 RSVD_38 RSVD_33 T12
A26 VSS_11 VSS_73 M21 W13 VSS_135 VSS_197 AJ1 AU8 VSS_259 V10 RSVD_39 RSVD_73 AD12
A30 VSS_12 VSS_74 M23 W15 VSS_136 VSS_198 AJ5 AU11 VSS_260
C3 VSS_13 VSS_75 M26 W17 VSS_137 VSS_199 AJ13 AU13 VSS_261 RSVD_53 Y6
C32 VSS_14 VSS_76 M28 W19 VSS_138 VSS_200 AJ15 AU15 VSS_262 RSVD_54 Y7
D16 VSS_15 VSS_77 M32 W23 VSS_139 VSS_201 AJ17 AU18 VSS_263
D18 VSS_16 VSS_78 N4 W26 VSS_140 VSS_202 AJ19 AU20 VSS_264 AA12 RSVD_64 RSVD_45 W8
D20 VSS_17 VSS_79 N5 Y5 VSS_141 VSS_203 AK5 AU22 VSS_265 AC10 RSVD_68 RSVD_46 W9
E7 VSS_18 VSS_80 N8 Y11 VSS_142 VSS_204 AK8 AU25 VSS_266 RSVD_1 B20
E8 VSS_19 VSS_81 N11 Y12 VSS_143 VSS_205 AK11 AU28 VSS_267 RSVD_5 G3
E10 VSS_20 VSS_82 N13 Y14 VSS_144 VSS_206 AK12 AV1 VSS_268 RSVD_7 J20 FP5 REV 0.90
E11 VSS_21 VSS_83 N15 Y16 VSS_145 VSS_207 AK14 AV5 VSS_269 RSVD_8 K3 PART 12 OF 13
E12 VSS_22 VSS_84 N17 Y18 VSS_146 VSS_208 AK16 AV7 VSS_270 RSVD_9 K6 FP5_BGA1140~D
2 2
E13 VSS_23 VSS_85 N19 Y20 VSS_147 VSS_209 AK18 AV10 VSS_271 RSVD_10 K20
E14 VSS_24 VSS_86 N22 AA1 VSS_148 VSS_210 AK20 AV12 VSS_272 RSVD_11 M3
E15 VSS_25 VSS_87 N25 AA5 VSS_149 VSS_211 AK22 AV14 VSS_273 RSVD_12 M6
E16 VSS_26 VSS_88 N28 AA13 VSS_150 VSS_212 AK25 AV16 VSS_274 RSVD_13 M13
E18 VSS_27 VSS_89 P1 AA15 VSS_151 VSS_213 AL1 AV19 VSS_275 RSVD_22 P6
E19 VSS_28 VSS_90 P5 AA17 VSS_152 VSS_214 AL5 AV21 VSS_276 RSVD_23 P22
E20 VSS_29 VSS_91 P14 AA19 VSS_153 VSS_215 AL7 AV23 VSS_277 RSVD_30 T3 UC1M @
E21 VSS_30 VSS_92 P16 AB14 VSS_154 VSS_216 AL10 AV26 VSS_278 RSVD_31 T6 CAMERAS
E22 VSS_31 VSS_93 P18 AB16 VSS_155 VSS_217 AL12 AV28 VSS_279 RSVD_37 T29
E23 VSS_32 VSS_94 P20 AB18 VSS_156 VSS_218 AL16 AV32 VSS_280 RSVD_44 W6 A18 CAM0_CSI2_CLOCKP CAM0_CLK B15
E25 VSS_33 VSS_95 P23 AB20 VSS_157 VSS_219 AL23 AW5 VSS_281 RSVD_49 W21 C18 CAM0_CSI2_CLOCKN
E26 VSS_34 VSS_96 P26 AC5 VSS_158 VSS_220 AL26 AW28 VSS_282 RSVD_50 W22 CAM0_I2C_SCL D15
E27 VSS_35 VSS_97 P28 AC8 VSS_159 VSS_221 AM5 AY6 VSS_283 RSVD_57 Y21 A15 CAM0_CSI2_DATAP0 CAM0_I2C_SDA C14
F5 VSS_36 VSS_98 P32 AC11 VSS_160 VSS_222 AM8 AY7 VSS_284 RSVD_58 Y27 C15 CAM0_CSI2_DATAN0
F28 R5 AC12 AM15 AY8 AA3 CAM0_SHUTDOWN B13

Vinafix.com
VSS_37 VSS_99 VSS_161 VSS_223 VSS_285 RSVD_59
G1 VSS_38 VSS_100 R11 AC13 VSS_162 VSS_224 AM20 AY10 VSS_286 RSVD_60 AA6 B16 CAM0_CSI2_DATAP1
G5 VSS_39 VSS_101 R12 AC15 VSS_163 VSS_225 AM22 AY11 VSS_287 RSVD_69 AC29 C16 CAM0_CSI2_DATAN1
G16 VSS_40 VSS_102 R13 AC17 VSS_164 VSS_226 AM25 AY12 VSS_288 RSVD_70 AD3
G19 VSS_41 VSS_103 R15 AC19 VSS_165 VSS_227 AM28 AY13 VSS_289 RSVD_71 AD6 C19 CAM0_CSI2_DATAP2
G21 VSS_42 VSS_104 R17 AD1 VSS_166 VSS_228 AN1 AY14 VSS_290 RSVD_74 AF3 B18 CAM0_CSI2_DATAN2
G23 VSS_43 VSS_105 R19 AD5 VSS_167 VSS_229 AN5 AY15 VSS_291 RSVD_75 AF6
G26 VSS_44 VSS_106 R22 AD14 VSS_168 VSS_230 AN7 AY16 VSS_292 RSVD_78 AF30 B17 CAM0_CSI2_DATAP3
G28 VSS_45 VSS_107 R25 AD16 VSS_169 VSS_231 AN10 AY18 VSS_293 RSVD_79 AJ6 D17 CAM0_CSI2_DATAN3
3 G32 VSS_46 VSS_108 R28 AD18 VSS_170 VSS_232 AN15 AY19 VSS_294 RSVD_80 AJ24 3
H5 VSS_47 VSS_109 R30 AD20 VSS_171 VSS_233 AN18 AY20 VSS_295 RSVD_81 AK23 D12 CAM1_CSI2_CLOCKP CAM1_CLK B10
H13 VSS_48 VSS_110 T1 AE5 VSS_172 VSS_234 AN21 AY21 VSS_296 RSVD_82 AK27 B12 CAM1_CSI2_CLOCKN
H18 VSS_49 VSS_111 T5 AE11 VSS_173 VSS_235 AN23 AY22 VSS_297 RSVD_83 AL3 CAM1_I2C_SCL A11
H20 VSS_50 VSS_112 T14 AE12 VSS_174 VSS_236 AN26 AY23 VSS_298 RSVD_87 AN29 C13 CAM1_CSI2_DATAP0 CAM1_I2C_SDA C11
H22 VSS_51 VSS_113 T16 AE13 VSS_175 VSS_237 AN28 AY25 VSS_299 RSVD_88 AN31 A13 CAM1_CSI2_DATAN0
H25 VSS_52 VSS_114 T18 AE15 VSS_176 VSS_238 AN32 AY26 VSS_300 CAM1_SHUTDOWN D11
H28 VSS_53 VSS_115 T20 AE17 VSS_177 VSS_239 AP5 AY27 VSS_301 B11 CAM1_CSI2_DATAP1
K1 VSS_54 VSS_116 T23 AE19 VSS_178 VSS_240 AP8 BB1 VSS_302 C12 CAM1_CSI2_DATAN1 CAM_PRIV_LED D13
K5 VSS_55 VSS_117 T26 AF1 VSS_179 VSS_241 AP13 BB20 VSS_303 CAM_IR_ILLU D10
K16 VSS_56 VSS_118 T28 AF5 VSS_180 VSS_242 AP15 BB32 VSS_304 RSVD_14 M14 J13 RSVD_6 FP5 REV 0.90
K19 VSS_57 VSS_119 U13 AF14 VSS_181 VSS_243 AP18 BD3 VSS_305 RSVD_84 AL6 PART 13 OF 13
K21 VSS_58 VSS_120 U15 AF16 VSS_182 VSS_244 AP20 BD7 VSS_306 RSVD_85 AL11 FP5_BGA1140~D
K22 VSS_59 VSS_121 U17 AF18 VSS_183 VSS_245 AP25 BD10 VSS_307 RSVD_86 AN16
K26 VSS_60 VSS_122 U19 AF20 VSS_184 VSS_246 AP28 BD12 VSS_308
K28 VSS_61 VSS_123 V5 AG5 VSS_185 VSS_247 AR1 BD14 VSS_309
FP5 REV 0.90 FP5 REV 0.90 FP5 REV 0.90
PART 7 OF 13 PART 8 OF 13 PART 11 OF 13
FP5_BGA1140~D FP5_BGA1140~D FP5_BGA1140~D

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP5 GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 11 of 41
A B C D E
 A B C D E

Memory Down
+0.6V_DDRA_VREFCA +0.6V_DDRA_VREFCA
+0.6VS
DDR_A_DQ[63..0] UD1 UD2
DDR_A_DQ[63..0] [5] RD3 1 MD@ 2 39_0402_5% DDR_A_MA0
DDR_A_DM[7..0] M1 G2 DDR_A_DQ14 M1 G2 DDR_A_DQ30 RD4 1 MD@ 2 39_0402_5% DDR_A_MA1
DDR_A_DM[7..0] [5] VREFCA DQL0 DDR_A_DQ12 VREFCA DQL0 DDR_A_DQ29 DDR_A_MA2
F7 F7 RD5 1 MD@ 2 39_0402_5%
DQL1 DQL1

.047U_0402_16V7K

.047U_0402_16V7K
1 H3 DDR_A_DQ11 1 H3 DDR_A_DQ27 RD6 1 MD@ 2 39_0402_5% DDR_A_MA3
CD2 P3 DQL2 H7 DDR_A_DQ9 CD1 DDR_A_MA0 P3 DQL2 H7 DDR_A_DQ25 RD7 1 MD@ 2 39_0402_5% DDR_A_MA4
[5] DDR_A_MA0 A0 DQL3 DDR_A_DQ10 DDR_A_MA1 A0 DQL3 DDR_A_DQ31 DDR_A_MA5
MD@ P7 H2 MD@ P7 H2 RD8 1 MD@ 2 39_0402_5%
[5] DDR_A_MA1 A1 DQL4 DDR_A_DQ13 DDR_A_MA2 A1 DQL4 DDR_A_DQ28 DDR_A_MA6
R3 H8 R3 H8 RD9 1 MD@ 2 39_0402_5%
+1.2V 2 [5] DDR_A_MA2 A2 DQL5 DDR_A_DQ15 2 DDR_A_MA3 A2 DQL5 DDR_A_DQ26 DDR_A_MA7
N7 J3 N7 J3 RD10 1 MD@ 2 39_0402_5%
1 [5] DDR_A_MA3 A3 DQL6 DDR_A_DQ8 DDR_A_MA4 A3 DQL6 DDR_A_DQ24 DDR_A_MA8 1
N3 J7 N3 J7 RD11 1 MD@ 2 39_0402_5%
[5] DDR_A_MA4 A4 DQL7 DDR_A_MA5 A4 DQL7 DDR_A_MA9
P8 P8 RD12 1 MD@ 2 39_0402_5%
[5] DDR_A_MA5 A5 A5
RD1 1 2 1K_0402_5% DDR_A_ALERT# P2 DDR_A_MA6 P2 RD13 1 MD@ 2 39_0402_5% DDR_A_MA10
[5] DDR_A_MA6 A6 DDR_A_DQ6 DDR_A_MA7 A6 DDR_A_DQ18 DDR_A_MA11
MD@ R8 A3 R8 A3 RD14 1 MD@ 2 39_0402_5%
[5] DDR_A_MA7 A7 DQU0 DDR_A_DQ4 DDR_A_MA8 A7 DQU0 DDR_A_DQ21 DDR_A_MA12
R2 B8 R2 B8 RD15 1 MD@ 2 39_0402_5%
+0.6VS [5] DDR_A_MA8 A8 DQU1 DDR_A_DQ3 DDR_A_MA9 A8 DQU1 DDR_A_DQ23 DDR_A_MA13
R7 C3 R7 C3 RD16 1 MD@ 2 39_0402_5%
[5] DDR_A_MA9 A9 DQU2 DDR_A_DQ5 DDR_A_MA10 A9 DQU2 DDR_A_DQ16
M3 C7 M3 C7
[5] DDR_A_MA10 A10/AP DQU3 DDR_A_DQ7 DDR_A_MA11 A10/AP DQU3 DDR_A_DQ19
T2 C2 T2 C2
DDR_A_PAR [5] DDR_A_MA11 A11 DQU4 DDR_A_DQ1 DDR_A_MA12 A11 DQU4 DDR_A_DQ20 DDR_A_WE#
RD2 1 2 39_0402_5% M7 C8 M7 C8 RD17 1 MD@ 2 39_0402_5%
[5] DDR_A_MA12 A12/BC DQU5 DDR_A_DQ2 DDR_A_MA13 A12/BC DQU5 DDR_A_DQ22 DDR_A_CAS#
MD@ T8 D3 T8 D3 RD18 1 MD@ 2 39_0402_5%
+1.2V [5] DDR_A_MA13 A13 DQU6 DDR_A_DQ0 DDR_A_WE# A13 DQU6 DDR_A_DQ17 DDR_A_RAS#
L2 D7 L2 D7 RD19 1 MD@ 2 39_0402_5%
[5] DDR_A_WE# A14/WE DQU7 A14/WE DQU7
N2 DDR_A_BA0 N2
[5] DDR_A_BA0 BA0 DDR_A_BA1 BA0 DDR_A_ODT0
N8 B3 N8 B3 RD20 1 MD@ 2 39_0402_5%
[5] DDR_A_BA1 BA1 VDD B9
+1.2V BA1 VDD B9
+1.2V RD21 1 MD@ 2 39_0402_5% DDR_A_CS0#
CD3 1 2 0.1U_0201_10V6K RD28 1 2 39_0402_5% DDR_A_CLK0 DDR_A_DM0 E2 VDD D1 DDR_A_DM2 E2 VDD D1 RD22 1 MD@ 2 39_0402_5% DDR_A_CKE0
MD@ MD@ DDR_A_DM1 E7 DMU/DBIU VDD G7 DDR_A_DM3 E7 DMU/DBIU VDD G7
DML/DBIL VDD J1 DML/DBIL VDD J1 RD23 1 MD@ 2 39_0402_5% DDR_A_ACT#
VDD J9 VDD J9 RD24 1 MD@ 2 39_0402_5% DDR_A_BA0
CD4 1 2 0.1U_0201_10V6K RD29 1 2 39_0402_5% DDR_A_CLK0# VDD L1 VDD L1 RD25 1 MD@ 2 39_0402_5% DDR_A_BA1
@ MD@ K7 VDD L9 DDR_A_CLK0 K7 VDD L9 RD26 1 MD@ 2 39_0402_5% DDR_A_BG0
[5] DDR_A_CLK0 CK_t VDD DDR_A_CLK0# CK_t VDD
K8 R1 K8 R1
[5] DDR_A_CLK0# CK_c VDD DDR_A_CKE0 CK_c VDD
K2 T9 K2 T9
[5] DDR_A_CKE0 CKE VDD CKE VDD RD27 1 DDP@ 2 39_0402_5% RD30 1 DDP@ 2 0_0201_5%
DDR_A_BG1 [5]
A1 A1 RD31 1 SDP@ 2 0_0201_5% DDR_A_BG1_R
VDDQ A9 VDDQ A9
VDDQ C1 VDDQ C1
VDDQ D9 VDDQ D9
+1.2V VDDQ F2 VDDQ F2
VDDQ F8 VDDQ F8
K3 VDDQ G1 DDR_A_ODT0 K3 VDDQ G1
[5] DDR_A_ODT0 ODT VDDQ DDR_A_CS0# ODT VDDQ
L7 G9 L7 G9
[5] DDR_A_CS0# CS VDDQ DDR_A_RAS# CS VDDQ
L8 J2 L8 J2
[5] DDR_A_RAS# RAS VDDQ DDR_A_CAS# RAS VDDQ
M8 J8 M8 J8
[5] DDR_A_CAS# CAS VDDQ CAS VDDQ
Memory Side
0.1U_0201_10V6K

B2 B2
VSS VSS
2

2 E1 E1
@ RD32 VSS E9 RD33 1 DDP@ 2 0_0201_5% VSS E9 RD34 1 DDP@ 2 0_0201_5%
CD5 1K_0402_1% VSS G8 VSS G8
MD@ +0.6V_DDRA_VREFCA A7 VSS K1 A7 VSS K1
1 [5] DDR_A_DQS0# DQSU_c VSS [5] DDR_A_DQS2# DQSU_c VSS
B7 K9 B7 K9
[5] DDR_A_DQS0 [5] DDR_A_DQS2
1

F3 DQSU_t VSS M9 DDR_A_BG1_R F3 DQSU_t VSS M9 DDR_A_BG1_R

[5] DDR_A_DQS1# DQSL_c VSS [5] DDR_A_DQS3# DQSL_c VSS
G3 N1 G3 N1
[5] DDR_A_DQS1 DQSL_t VSS [5] DDR_A_DQS3 DQSL_t VSS
T1 T1
P1 VSS DDR_A_RST# P1 VSS
[5] DDR_A_RST# RESET RESET
0.1U_0201_10V6K

2 2 RD35 1 2 240_0201_1% F9 RD36 1 2 240_0201_1% F9

ZQ ZQ
2

CD7 MD@ MD@

CD6 RD37 0.1U_0201_10V6K
2 MD@ 1K_0402_1% MD@ L3 A2 DDR_A_ACT# L3 A2 2
1 1 [5] DDR_A_ACT# ACT VSSQ DDR_A_BG0 ACT VSSQ
MD@ M2 A8 M2 A8
[5] DDR_A_BG0 BG0 VSSQ BG0 VSSQ
N9 C9 N9 C9
1

P9 TEN VSSQ D2 DDR_A_ALERT# P9 TEN VSSQ D2

[5] DDR_A_ALERT# ALERT VSSQ DDR_A_PAR ALERT VSSQ
T3 D8 T3 D8
[5] DDR_A_PAR PAR VSSQ PAR VSSQ
E3 E3
T7 VSSQ E8 T7 VSSQ E8
B1 NC VSSQ F1 B1 NC VSSQ F1
+2.5V R9 VPP VSSQ H1
+2.5V R9 VPP VSSQ H1
VPP VSSQ H9 VPP VSSQ H9
VREF traces should be at least 20mils wide 96-BALL VSSQ 96-BALL VSSQ
20mils spacing to other signals SDRAM DDR4 SDRAM DDR4
K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96
@ @

+0.6V_DDRA_VREFCA

UD3
+0.6V_DDRA_VREFCA

UD4
Vinafix.com +1.2V
DRAM DOWN DECOUPLING
+0.6VS

CD10

CD11

CD12

CD13

CD14

CD15

CD16

CD17

CD18

CD19

CD20

CD21

CD22

CD23

CD24

CD25

CD26

CD27

CD28

CD29

CD30

CD31

CD32
M1 G2 DDR_A_DQ43 M1 G2 DDR_A_DQ62 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VREFCA DQL0 F7 DDR_A_DQ44 VREFCA DQL0 F7 DDR_A_DQ60 MD@ MD@ @ @ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ @
DQL1 DQL1
.047U_0402_16V7K

.047U_0402_16V7K
CD9

1 H3 DDR_A_DQ47 1 H3 DDR_A_DQ59
DQL2 DQL2

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K
CD8 DDR_A_MA0 P3 H7 DDR_A_DQ45 DDR_A_MA0 P3 H7 DDR_A_DQ61 MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@
A0 DQL3 A0 DQL3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K
MD@ DDR_A_MA1 P7 H2 DDR_A_DQ46 DDR_A_MA1 P7 H2 DDR_A_DQ63
DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_DQ40 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_DQ57
2 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_DQ42 2 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_DQ58
DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_DQ41 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_DQ56
DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7
DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5
DDR_A_MA7 R8 A6 A3 DDR_A_DQ38 DDR_A_MA7 R8 A6 A3 DDR_A_DQ54
A7 DQU0 MD@ A7 DQU0
DDR_A_MA8 R2 B8 DDR_A_DQ36 DDR_A_MA8 R2 B8 DDR_A_DQ53
DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_DQ34 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_DQ55
DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_DQ37 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_DQ52
DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_DQ39 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_DQ51
3 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_DQ32 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_DQ49 3
DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_DQ35 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_DQ50
DDR_A_WE# L2 A13 DQU6 D7 DDR_A_DQ33 DDR_A_WE# L2 A13 DQU6 D7 DDR_A_DQ48
A14/WE DQU7 A14/WE DQU7
DDR_A_BA0 N2 DDR_A_BA0 N2
DDR_A_BA1 N8 BA0 B3 DDR_A_BA1 N8 BA0 B3 +1.2V +0.6VS
BA1 VDD B9
+1.2V BA1 VDD B9
+1.2V +0.6V_DDRA_VREFCA +1.2V
DDR_A_DM4 E2 VDD D1 DDR_A_DM6 E2 VDD D1
DDR_A_DM5 E7 DMU/DBIU VDD G7 DDR_A_DM7 E7 DMU/DBIU VDD G7 CD33 1 2 0.22U_0402_6.3V6K
DML/DBIL VDD J1 DML/DBIL VDD J1 MD@ CD34 1 2 0.1U_0201_10V6K
VDD J9 VDD J9 CD35 1 2 0.22U_0402_6.3V6K MD@
VDD L1 VDD L1 MD@ CD36 1 2 0.1U_0201_10V6K
DDR_A_CLK0 K7 VDD L9 DDR_A_CLK0 K7 VDD L9 CD37 1 2 0.22U_0402_6.3V6K MD@
DDR_A_CLK0# K8 CK_t VDD R1 DDR_A_CLK0# K8 CK_t VDD R1 MD@ CD38 1 2 0.1U_0201_10V6K
DDR_A_CKE0 K2 CK_c VDD T9 DDR_A_CKE0 K2 CK_c VDD T9 CD39 1 2 0.22U_0402_6.3V6K MD@
CKE VDD CKE VDD MD@ CD40 1 2 0.1U_0201_10V6K
CD41 1 2 0.22U_0402_6.3V6K MD@
A1 A1 MD@
VDDQ A9 VDDQ A9
VDDQ C1 VDDQ C1
VDDQ D9 VDDQ D9
VDDQ F2 VDDQ F2
VDDQ F8 VDDQ F8
DDR_A_ODT0 K3 VDDQ G1 DDR_A_ODT0 K3 VDDQ G1
DDR_A_CS0# L7 ODT VDDQ G9 DDR_A_CS0# L7 ODT VDDQ G9
DDR_A_RAS# L8 CS VDDQ J2 DDR_A_RAS# L8 CS VDDQ J2
DDR_A_CAS# M8 RAS VDDQ J8 DDR_A_CAS# M8 RAS VDDQ J8
CAS VDDQ CAS VDDQ
B2 B2
VSS E1 VSS E1 +2.5V +2.5V +2.5V +2.5V
VSS E9 RD38 1 DDP@ 2 0_0201_5% VSS E9 RD39 1 DDP@ 2 0_0201_5%
VSS G8 VSS G8
A7 VSS K1 A7 VSS K1
[5] DDR_A_DQS4# DQSU_c VSS [5] DDR_A_DQS6# DQSU_c VSS
B7 K9 B7 K9
[5] DDR_A_DQS4 DQSU_t VSS [5] DDR_A_DQS6 DQSU_t VSS

1U_0201_6.3V6M
CD42

1U_0201_6.3V6M
CD43

10U 6.3V M X5R 0402

CD44

1U_0201_6.3V6M
CD45

1U_0201_6.3V6M
CD46

10U 6.3V M X5R 0402

CD47

1U_0201_6.3V6M
CD48

1U_0201_6.3V6M
CD49

10U 6.3V M X5R 0402

CD50

1U_0201_6.3V6M
CD51

1U_0201_6.3V6M
CD52

10U 6.3V M X5R 0402

CD53
F3 M9 DDR_A_BG1_R F3 M9 DDR_A_BG1_R 1 1 1 1 1 1 1 1 1 1 1 1
[5] DDR_A_DQS5# DQSL_c VSS [5] DDR_A_DQS7# DQSL_c VSS
G3 N1 G3 N1
[5] DDR_A_DQS5 DQSL_t VSS [5] DDR_A_DQS7 DQSL_t VSS
T1 T1
DDR_A_RST# P1 VSS DDR_A_RST# P1 VSS MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@
RESET RESET 2 2 2 2 2 2 2 2 2 2 2 2
RD40 1 2 240_0201_1% F9 RD41 1 2 240_0201_1% F9
MD@ ZQ MD@ ZQ

DDR_A_ACT# L3 A2 DDR_A_ACT# L3 A2
ACT VSSQ ACT VSSQ
DDR_A_BG0 M2
N9 BG0 VSSQ
A8
C9
DDR_A_BG0 M2
N9 BG0 VSSQ
A8
C9
Closed to UD1 Closed to UD2 Closed to UD3 Closed to UD4
DDR_A_ALERT# P9 TEN VSSQ D2 DDR_A_ALERT# P9 TEN VSSQ D2
DDR_A_PAR T3 ALERT VSSQ D8 DDR_A_PAR T3 ALERT VSSQ D8
PAR VSSQ E3 PAR VSSQ E3
T7 VSSQ E8 T7 VSSQ E8
B1 NC VSSQ F1 B1 NC VSSQ F1
4 +2.5V R9 VPP VSSQ H1
+2.5V R9 VPP VSSQ H1 4
VPP VSSQ H9 VPP VSSQ H9
96-BALL VSSQ 96-BALL VSSQ
SDRAM DDR4 SDRAM DDR4
K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96
@ @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4_CHA Onboard
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 12 of 41
A B C D E
 A B C D E

Main Func = DIMM2

DDR_B_DQ[0..63]
JDIMM1A DDR_B_DQ[0..63] [5]
DDR_B_CLK0 137 REVERSE 8 DDR_B_DQ4 DDR_B_DM[0..7]
[5] DDR_B_CLK0 CK0(T) DQ0 DDR_B_DM[0..7] [5]
DDR_B_CLK0# 139 7 DDR_B_DQ0
[5] DDR_B_CLK0# DDR_B_CLK1 138 CK0#(C) DQ1 20 DDR_B_DQ2 DDR_B_MA[0..13]
[5] DDR_B_CLK1 CK1(T) DQ2 DDR_B_MA[0..13] [5]
DDR_B_CLK1# 140 21 DDR_B_DQ6
[5] DDR_B_CLK1# CK1#(C) DQ3 4 DDR_B_DQ1
DDR_B_CKE0 109 DQ4 3 DDR_B_DQ5
[5] DDR_B_CKE0 DDR_B_CKE1 CKE0 DQ5 DDR_B_DQ7
110 16
[5] DDR_B_CKE1 CKE1 DQ6 DDR_B_DQ3
17
1 DDR_B_CS0# 149 DQ7 13 DDR_B_DQS0 1
[5] DDR_B_CS0# DDR_B_CS1# S0# DQS0(T) DDR_B_DQS0# DDR_B_DQS0 [5] +1.2V +1.2V
157 11
[5] DDR_B_CS1# S1# DQS0#(C) DDR_B_DQS0# [5]
162
165 S2#/C0 28 DDR_B_DQ8 JDIMM1B
S3#/C1 DQ8 29 DDR_B_DQ9 REVERSE
DDR_B_ODT0 155 DQ9 41 DDR_B_DQ14 111 141
[5] DDR_B_ODT0 DDR_B_ODT1 161 ODT0 DQ10 42 DDR_B_DQ11 112 VDD1 VDD11 142
[5] DDR_B_ODT1 ODT1 DQ11 24 DDR_B_DQ12 117 VDD2 VDD12 147
DDR_B_BG0 115 DQ12 25 DDR_B_DQ13 118 VDD3 VDD13 148
[5] DDR_B_BG0 DDR_B_BG1 BG0 DQ13 DDR_B_DQ10 VDD4 VDD14
113 38 123 153
[5] DDR_B_BG1 DDR_B_BA0 BG1 DQ14 DDR_B_DQ15 +3VS VDD5 VDD15 +0.6VS
150 37 124 154
[5] DDR_B_BA0 DDR_B_BA1 145 BA0 DQ15 34 DDR_B_DQS1 129 VDD6 VDD16 159
[5] DDR_B_BA1 BA1 DQS1(T) DDR_B_DQS1# DDR_B_DQS1 [5] VDD7 VDD17
32 130 160
DDR_B_MA0 DQS1#(C) DDR_B_DQS1# [5] VDD8 VDD18
144 135 163
DDR_B_MA1 133 A0 50 DDR_B_DQ21 136 VDD9 VDD19 +2.5V
DDR_B_MA2 132 A1 DQ16 49 DDR_B_DQ16 +VREFB_CA VDD10
DDR_B_MA3 131 A2 DQ17 62 DDR_B_DQ23 255 258
DDR_B_MA4 128 A3 DQ18 63 DDR_B_DQ19 VDDSPD VTT
DDR_B_MA5 126 A4 DQ19 46 DDR_B_DQ17 164 257
DDR_B_MA6 127 A5 DQ20 45 DDR_B_DQ20 VREFCA VPP1 259
A6 DQ21 VPP2

1000P_0402_50V7K
CD81
DDR_B_MA7 122 58 DDR_B_DQ22 1
DDR_B_MA8 125 A7 DQ22 59 DDR_B_DQ18 1 99
DDR_B_MA9 121 A8 DQ23 55 DDR_B_DQS2 2 VSS VSS 102
DDR_B_MA10 A9 DQS2(T) DDR_B_DQS2# DDR_B_DQS2 [5] VSS VSS
146 53 5 103
DDR_B_MA11 A10_AP DQS2#(C) DDR_B_DQS2# [5] 2 VSS VSS
120 6 106
DDR_B_MA12 119 A11 70 DDR_B_DQ25 9 VSS VSS 107
DDR_B_MA13 158 A12 DQ24 71 DDR_B_DQ28 10 VSS VSS 167
DDR_B_WE# 151 A13 DQ25 83 DDR_B_DQ26 14 VSS VSS 168
[5] DDR_B_WE# DDR_B_CAS# 156 A14_WE# DQ26 84 DDR_B_DQ27 15 VSS VSS 171
[5] DDR_B_CAS# DDR_B_RAS# 152 A15_CAS# DQ27 66 DDR_B_DQ24 18 VSS VSS 172
[5] DDR_B_RAS# A16_RAS# DQ28 67 DDR_B_DQ29 19 VSS VSS 175
DDR_B_ACT# 114 DQ29 79 DDR_B_DQ30 22 VSS VSS 176
[5] DDR_B_ACT# ACT# DQ30 80 DDR_B_DQ31 23 VSS VSS 180
DDR_B_PAR 143 DQ31 76 DDR_B_DQS3 26 VSS VSS 181
[5] DDR_B_PAR DDR_B_ALERT# PARITY DQS3(T) DDR_B_DQS3# DDR_B_DQS3 [5] VSS VSS
116 74 27 184
[5] DDR_B_ALERT# DDR_B_EVENT# ALERT# DQS3#(C) DDR_B_DQS3# [5] VSS VSS
134 30 185
[5] DDR_B_EVENT# DDR_B_RST# 108 EVENT# 174 DDR_B_DQ36 31 VSS VSS 188
[5] DDR_B_RST# RESET# DQ32 173 DDR_B_DQ33 35 VSS VSS 189
2 2
DQ33 187 DDR_B_DQ35 36 VSS VSS 192
254 DQ34 186 DDR_B_DQ38 39 VSS VSS 193
[8,14] I2C_2_SDA SDA DQ35 VSS VSS
253 170 DDR_B_DQ37 40 196
[8,14] I2C_2_SCL SCL DQ36 VSS VSS
169 DDR_B_DQ32 43 197
166 DQ37 183 DDR_B_DQ34 44 VSS VSS 201
260 SA2 DQ38 182 DDR_B_DQ39 47 VSS VSS 202
256 SA1 DQ39 179 DDR_B_DQS4 48 VSS VSS 205
+3VS SA0 DQS4(T) DDR_B_DQS4 [5] VSS VSS
177 DDR_B_DQS4# 51 206
DQS4#(C) DDR_B_DQS4# [5] VSS VSS
52 209
92 195 DDR_B_DQ44 56 VSS VSS 210
91 CB0_NC DQ40 194 DDR_B_DQ45 57 VSS VSS 213
101 CB1_NC DQ41 207 DDR_B_DQ46 60 VSS VSS 214
105 CB2_NC DQ42 208 DDR_B_DQ43 61 VSS VSS 217
88 CB3_NC DQ43 191 DDR_B_DQ41 64 VSS VSS 218
87 CB4_NC DQ44 190 DDR_B_DQ40 65 VSS VSS 222

Vinafix.com
100 CB5_NC DQ45 203 DDR_B_DQ42 68 VSS VSS 223
104 CB6_NC DQ46 204 DDR_B_DQ47 69 VSS VSS 226
97 CB7_NC DQ47 200 DDR_B_DQS5 72 VSS VSS 227
DQS8(T) DQS5(T) DDR_B_DQS5# DDR_B_DQS5 [5] VSS VSS
95 198 73 230
DQS8#(C) DQS5#(C) DDR_B_DQS5# [5] VSS VSS
77 231
216 DDR_B_DQ49 78 VSS VSS 234
DDR_B_DM0 12 DQ48 215 DDR_B_DQ53 81 VSS VSS 235
DDR_B_DM1 33 DM0#/DBI0# DQ49 228 DDR_B_DQ54 82 VSS VSS 238
DDR_B_DM2 54 DM1#/DBI1# DQ50 229 DDR_B_DQ50 85 VSS VSS 239
DDR_B_DM3 75 DM2#/DBI2# DQ51 211 DDR_B_DQ48 86 VSS VSS 243
DDR_B_DM4 178 DM3#/DBI3# DQ52 212 DDR_B_DQ52 89 VSS VSS 244
DDR_B_DM5 199 DM4#/DBI4# DQ53 224 DDR_B_DQ55 90 VSS VSS 247
DDR_B_DM6 220 DM5#/DBI5# DQ54 225 DDR_B_DQ51 93 VSS VSS 248
DDR_B_DM7 241 DM6#/DBI6# DQ55 221 DDR_B_DQS6 94 VSS VSS 251
DDR_B_RST# DM7#/DBI7# DQS6(T) DDR_B_DQS6# DDR_B_DQS6 [5] VSS VSS
1 2 ESD@ 96 219 98 252
DM8#/DBI8# DQS6#(C) DDR_B_DQS6# [5] VSS VSS
CD69 262 261
100P_0402_50V8J GND GND
237 DDR_B_DQ57
DQ56 236 DDR_B_DQ60 LOTES_ADDR0206-P001A

3
ESD DQ57
DQ58
DQ59
249
250
232
DDR_B_DQ59
DDR_B_DQ62
DDR_B_DQ61
ME@
3
DQ60 233 DDR_B_DQ56
DQ61 245 DDR_B_DQ58
DQ62 246 DDR_B_DQ63
DQ63 242 DDR_B_DQS7
DQS7(T) DDR_B_DQS7# DDR_B_DQS7 [5]
240
DQS7#(C) DDR_B_DQS7# [5]

+1.2V LOTES_ADDR0206-P001A
ME@
+1.2V +1.2V
Layout Note: Layout Note:
Place near JDIMM1.257,259 Place near JDIMM1.258 DIMM Side
10U 6.3V M X5R 0402
CD54

10U 6.3V M X5R 0402

CD55

10U 6.3V M X5R 0402

CD56

10U 6.3V M X5R 0402

CD57

10U 6.3V M X5R 0402

CD58

10U 6.3V M X5R 0402

CD59

1 1 1 1 1 1 1
1

2
1U_0201_6.3V6M
CD60

1U_0201_6.3V6M
CD61

1U_0201_6.3V6M
CD62

1U_0201_6.3V6M
CD63

1U_0201_6.3V6M
CD64

1U_0201_6.3V6M
CD65

1U_0201_6.3V6M
CD66

1U_0201_6.3V6M
CD67

+ @ RD42
@ CD68 +VREFB_CA 1K_0402_1%
2

2 2 2 2 2 2 330U_D3_2.5VY_R6M +2.5V +0.6VS +3VS

@ @ 2

1
+VREFB_CA
10U 6.3V M X5R 0402
CD70

10U 6.3V M X5R 0402

CD71

1U_0201_6.3V6M
CD72

0.1U_0201_10V6K
CD73

1U_0201_6.3V6M
CD74

10U 6.3V M X5R 0402

CD75

10U 6.3V M X5R 0402

CD76

0.1U_0201_10V6K
CD77

2.2U_0402_6.3V6M
CD78

0.1U_0201_10V6K
CD79

0.1U_0201_10V6K
CD80
1 1 1 1 1 1
1 2 2 2 2

2
@ @ @
2

2 2 2 2 2 2 RD43
1 1 1 1 1K_0402_1%
+1.2V
RF reserve

1
10U 6.3V M X5R 0402
CD82

10U 6.3V M X5R 0402

CD83

10U 6.3V M X5R 0402

CD84

10U 6.3V M X5R 0402

CD85

0.1U_0201_10V6K
CD86

0.1U_0201_10V6K
CD87

0.1U_0201_10V6K
CD88

0.1U_0201_10V6K
CD89

4 1 1 1 1 1 1 1 1 4

RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@

2 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 So-DIMM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 13 of 41
A B C D E
 A B C D E

Camera
LCD Power Circuit +3VS

Consumption Test
+3VS_CMOS

+3VS
1 Consumption Test +LCDVDD_CONN R3 1 @ 2 0_0603_5% 1

W=60mils U5 W=20mils C5 C6
5 1 +LCDVDD R2 1 @ 2 0_0805_5% 1 1
IN OUT

0.1U_0201_10V6K

10U_0603_6.3V6M
2
W=60mils @
GND 1
4 3 C3 2 2
[7] ENVDD EN OC 4.7U_0402_6.3V6M
EM5203AJ-20 SOT23 5P 2
1

C4
1U_0201_6.3V6M
2

Consumption Test
B+ +LEDVDD
+LCDVDD_CONN
W=100mils
+3VS
R9 1 @ 2 0_0805_5% eDP PANEL Conn.
1
C7
U2 4.7U_0805_25V6-K JEDP1

5
U74AHC1G08G-AL5-R_SOT353-5 1
2 2 2 1
From PCH

P
[7,28] ENBKL B 2
4 DISPOFF# 3
1 Y 4 3
2 From EC [28] BKOFF# A W=60mils 4 2

G
5
[7] INVTPWM 5

2
@ DISPOFF# 6

3
6
2

R7 EDP_HPD 7
[7] EDP_HPD 7
R265 100K_0402_5% 8
100K_0402_5% @ 9 8
C8 1 2 0.1U_0201_10V K X5R EDP_AUXN_C 10 9
[7] EDP_AUXN

1
C9 1 2 0.1U_0201_10V K X5R EDP_AUXP_C 11 10
[7] EDP_AUXP
1

12 11
R1 1 @ 2 0_0402_5%
eDP C10 1 2 0.1U_0201_10V K X5R EDP_TXP0_C 13 12
[7] EDP_TXP0 13
C11 1 2 0.1U_0201_10V K X5R EDP_TXN0_C 14
[7] EDP_TXN0 14
15
C12 1 2 0.1U_0201_10V K X5R EDP_TXP1_C 16 15
[7] EDP_TXP1 16
C13 1 2 0.1U_0201_10V K X5R EDP_TXN1_C 17
[7] EDP_TXN1 17
18
C232 QHD@ 1 2 0.1U_0201_10V K X5R EDP_TXP2_C 19 18

Vinafix.com
[7] EDP_TXP2 19
C233 QHD@ 1 2 0.1U_0201_10V K X5R EDP_TXN2_C 20
[7] EDP_TXN2 20
21
C234 QHD@ 1 2 0.1U_0201_10V K X5R EDP_TXP3_C 22 21
[7] EDP_TXP3 22
C235 QHD@ 1 2 0.1U_0201_10V K X5R EDP_TXN3_C 23
[7] EDP_TXN3 23
24
[8] TS_I2C_RESET# 24
25
[8] TS_INT# HUB_USB20_N1_R 25
RTOUCH1 1 C340@ 2 0_0402_5% 26
[8,13] I2C_2_SDA HUB_USB20_P1_R 26
Touch Screen RTOUCH2 1 C340@ 2 0_0402_5% 27
[8,13] I2C_2_SCL 27
RTOUCH3 1 S540@ 2 0_0402_5% +3VS_TS 28
[21] HUB_USB20_N1
Touch Screen [21]
[28]
HUB_USB20_P1
TS_DISABLE#
RTOUCH4 1 S540@ 2 0_0402_5% 29
30
31
28
29
30
[9] USB20_N3 32 31
3 Camera [9] USB20_P3 +3VS_CMOS
33 32 3
+3VS [26,28] EC_SMB_DA4 33
+3VS_TS 34
[26,28] EC_SMB_CK4 34
Consumption Test G-Sensor [28] TAB_SW# 35
36 35 41
+3VALW 36 GND
+3VS 37 42
38 37 GND 43
[20] DMIC_CLK 38 GND
R264 1 @ 2 0_0603_5% DMIC [20] DMIC_DAT 39 44
40 39 GND 45
40 GND
W=20mils 1 1
0.1U_0201_10V6K
C230

10U_0603_6.3V6M
C231

CVILU_CVS3402M1RM-NH
ME@
TS@ @
2 2 DT6
USB20_P3 3 6 DMIC_DAT
I/O2 I/O4

2 5
GND VDD

DMIC_CLK 1 4 USB20_N3
I/O1 I/O3
L30ESDL5V0C6-4_SOT23-6
@ESD@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 14 of 41
A B C D E
 A B C D E

Near Pin20 Near Pin12 Near Pin40 Near Pin31 Near Pin19 +1.2V_HDMI
+1.2V +1.2V_HDMI

W = 40mils

0.01U_0402_16V7K
CLS1

0.01U_0402_16V7K
CLS2

0.1U_0201_10V6K
CLS3

0.1U_0201_10V6K
CLS4

0.1U_0201_10V6K
CLS5

0.1U_0201_10V6K
CLS6
RLS1 2 @ 1 0_0603_5%
1 1
2 2 2 2 2 2

1 1 1 1 1 1
LS@

LS@

LS@

LS@

LS@

LS@
+3VS

ULS1 LS@
Near Pin11 Near Pin37
19 11
20 VDDTA VDD33 37
31 VDDTX VDD33
VDDTX

0.01U_0402_16V7K
CLS7

0.1U_0201_10V6K
CLS8
12
40 VDDRX 30
Near ULS1 VDDRX OUT_D2p 29
HDMI_RD_TX_P2 [16] 2 2
OUT_D2n HDMI_RD_TX_N2 [16]
CLS9 LS@ 1 2 0.1U_0201_10V6K HDMI_TX_P2 1 27
[7] APU_DP1_P0 IN_D2p OUT_D1p HDMI_RD_TX_P1 [16] 1 1

LS@

LS@
CLS10 LS@ 1 2 0.1U_0201_10V6K HDMI_TX_N2 2 26
[7] APU_DP1_N0 IN_D2n OUT_D1n HDMI_RD_TX_N1 [16]
CLS11 LS@ 1 2 0.1U_0201_10V6K HDMI_TX_P1 4 25
To HDMI
[7] APU_DP1_P1 HDMI_TX_N1 IN_D1p OUT_D0p HDMI_RD_TX_P0 [16]
CLS12 LS@ 1 2 0.1U_0201_10V6K 5 24
[7] APU_DP1_N1 IN_D1n OUT_D0n HDMI_RD_TX_N0 [16]
From CPU CLS13 LS@ 1 2 0.1U_0201_10V6K HDMI_TX_P0 6 22
[7] APU_DP1_P2 HDMI_TX_N0 IN_D0p OUT_CKp HDMI_RD_CLKP [16]
CLS14 LS@ 1 2 0.1U_0201_10V6K 7 21
2 [7] APU_DP1_N2 IN_D0n OUT_CKn HDMI_RD_CLKN [16] 2

CLS15 LS@ 1 2 0.1U_0201_10V6K HDMI_CLKP 9 39

[7] APU_DP1_P3
CLS16 LS@ 1 2 0.1U_0201_10V6K HDMI_CLKN 10 IN_CKp SDA_SRC 38
APU_DP1_CTRL_DAT [7] From CPU
[7] APU_DP1_N3 IN_CKn SCL_SRC APU_DP1_CTRL_CLK [7]
33 HDMI_CTRL_DAT [16]
SDA_SNK 32
SCL_SNK HDMI_CTRL_CLK [16] To HDMI
+3VS
DDCBUF 14
RLS2 1 LS@ 2 4.7K_0402_5% 13 DDCBUF/SDA_CTL 3
EQ 17 DCIN_EN/SCL_CTL HPD_SRC 34 ISET
APU_DP1_HPD [7] To CPU
I2C_CTL_EN_LS 8 EQ/I2C_ADDR0 ISET 28
I2C_CTL_EN HPD_SNK HDMI_HPD [16]
From HDMI
RLS3 1 LS@ 2 4.3K_0402_1% 18
36 REXT

Vinafix.com
RLS4 1 @ 2 4.7K_0402_5% 23 PD# 15 +5V_Display
PRE 16 CFG / I2C_ADDR1 GND 35
PRE GND 41
EPAD
PS8407ATQFN40GTR2A1_TQFN40_5X5
HDMI_CTRL_DAT RLS18 1 2 2.2K_0402_5%

HDMI_CTRL_CLK RLS19 1 2 2.2K_0402_5%

3 3

+3VS +3VS +3VS +3VS +3VS

+3VS +3VS @RF@
HDMI_CTRL_DAT CLS17 1 2 10P_0402_50V8C
1

1
RLS5 RLS7 RLS9 RLS11 RLS14 @RF@
1

LS@ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% HDMI_CTRL_CLK CLS18 1 2 10P_0402_50V8C

RLS16 RLS17
4.7K_0402_5% 4.7K_0402_5% @RF@
2

2
@ @ DDCBUF EQ I2C_CTL_EN_LS PRE ISET APU_DP1_CTRL_DAT CLS19 1 2 10P_0402_50V8C
2

1
@RF@
APU_DP1_CTRL_DAT RLS6 RLS8 RLS10 RLS13 RLS15 APU_DP1_CTRL_CLK CLS20 1 2 10P_0402_50V8C
@ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5%
APU_DP1_CTRL_CLK
2

2
Reserve for SDV Verify
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Level shifter_PS8407A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 15 of 41
A B C D E
 A B C D E

HDMI
For HDMI
+5VS +5V_Display
1 1
UH1

3
W=40mils
OUT

EMI @
1
1
IN
2
1
CH3
0.1U_0201_10V K X5R
CH5 GND
RH1 1 EMI@ 2 6.8_0402_1%~D 0.1U_0201_10V K X5R 2
2 S IC AP2330W-7 SC59 3P PWR SW

HDMI_RD_CLKP HDMI_L_CLKP
[15] HDMI_RD_CLKP

HDMI_RD_CLKN HDMI_L_CLKN
[15] HDMI_RD_CLKN

RH2 1 EMI@ 2 6.8_0402_1%~D

RH3 1 EMI@ 2 6.8_0402_1%~D

JHDMI1
HDMI_HPD 19
HDMI_RD_TX_P2 HDMI_L_TX_P2 [15] HDMI_HPD HP_DET
[15] HDMI_RD_TX_P2 +5V_Display 18
17 +5V
HDMI_CTRL_DAT 16 DDC/CEC_GND
HDMI_RD_TX_N2 HDMI_L_TX_N2 [15] HDMI_CTRL_DAT HDMI_CTRL_CLK SDA
[15] HDMI_RD_TX_N2 15
[15] HDMI_CTRL_CLK SCL
14
13 Reserved
HDMI_L_CLKN 12 CEC 20
RH4 1 EMI@ 2 6.8_0402_1%~D 11 CK- GND 21
2 HDMI_L_CLKP 10 CK_shield GND 22 2
HDMI_L_TX_N0 9 CK+ GND 23
RH5 1 EMI@ 2 6.8_0402_1%~D 8 D0- GND
HDMI_L_TX_P0 7 D0_shield
HDMI_L_TX_N1 6 D0+
HDMI_RD_TX_P1 HDMI_L_TX_P1 5 D1-
[15] HDMI_RD_TX_P1 D1_shield
HDMI_L_TX_P1 4
HDMI_L_TX_N2 3 D1+
HDMI_RD_TX_N1 HDMI_L_TX_N1 2 D2-
[15] HDMI_RD_TX_N1 D2_shield
HDMI_L_TX_P2 1
D2+
ACON_HMR2E-AK120F
RH6 1 EMI@ 2 6.8_0402_1%~D ME@

Vinafix.com
RH7 1 EMI@ 2 6.8_0402_1%~D

HDMI_RD_TX_P0 HDMI_L_TX_P0
[15] HDMI_RD_TX_P0

HDMI_RD_TX_N0 HDMI_L_TX_N0
[15] HDMI_RD_TX_N0

EMI@
RH8 1 2 6.8_0402_1%~D

Near JHDMI1
3 3

DH1 @ESD@ DH2 @ESD@ DH3 @ESD@

HDMI_CTRL_CLK 9 10 1 1 HDMI_CTRL_CLK HDMI_L_TX_P1 9 10 1 1 HDMI_L_TX_P1 HDMI_L_TX_P2 9 10 1 1 HDMI_L_TX_P2

HDMI_CTRL_DAT 8 9 2 2 HDMI_CTRL_DAT HDMI_L_TX_N1 8 9 2 2 HDMI_L_TX_N1 HDMI_L_TX_N2 8 9 2 2 HDMI_L_TX_N2

+5V_Display 7 7 4 4 +5V_Display HDMI_L_CLKP 7 7 4 4 HDMI_L_CLKP HDMI_L_TX_P0 7 7 4 4 HDMI_L_TX_P0

HDMI_HPD 6 6 5 5 HDMI_HPD HDMI_L_CLKN 6 6 5 5 HDMI_L_CLKN HDMI_L_TX_N0 6 6 5 5 HDMI_L_TX_N0

3 3 3 3 3 3

8 8 8

L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD

ESD

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title
HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 16 of 41

A B C D E
 A B C D E

NGFF - WLAN / BT (E- KEY)

+3VS +3VS_WLAN

1 1
Consumption Test

RWL1 1 @ 2 0_0805_5%

4.7U_0402_6.3V6M
CWL1

0.1U_0201_10V K X5R
CWL2
1 1
@

2 2

+3VS_WLAN

JWLAN1
1 2
3 GND_1 3.3VAUX_2 4
[9] USB20_P5 USB_D+ 3.3VAUX_4
BT [9] USB20_N5 5 6
7 USB_D- LED1# 8
9 GND_7 PCM_CLK 10
2
11 SDIO_CLK PCM_SYNC 12
2

13 SDIO_CMD PCM_OUT 14
15 SDIO_DAT0 PCM_IN 16
17 SDIO_DAT1 LED2# 18
19 SDIO_DAT2 GND_18 20
21 SDIO_DAT3 UART_WAKE 22 UART_0_ARXD_R_DTXD RWL4 1 @ 2 0_0402_5%
23 SDIO_WAKE UART_TX UART_0_ARXD_DTXD [9]
SDIO_RST
24 UART_0_ATXD_R_DRXD RWL5 1 @ 2 0_0402_5%
UART_RX UART_0_ATXD_DRXD [9]
25 26
27 GND_33 UART_RTS 28
[6] PCIE_ATX_C_DRX_P1 PET_RX_P0 UART_CTS
29 30 RWL6 1 @ 2 0_0402_5%
[6] PCIE_ATX_C_DRX_N1 PET_RX_N0 CLink_RST EC_TX [28]
31 32 RWL7 1 @ 2 0_0402_5%
33 GND_39 CLink_DATA 34 EC_RX [28]
[6] PCIE_ARX_DTX_P1 PER_TX_P0 CLink_CLK
35 36

Vinafix.com
WLAN [6] PCIE_ARX_DTX_N1
37 PER_TX_N0 COEX3 38
39 GND_45 COEX2 40
[9] CLK_PCIE_WLAN REFCLK_P0 COEX1
41 42 SUSCLK_R RWL8 1 @ 2 0_0402_5%
[9] CLK_PCIE_WLAN# REFCLK_N0 SUSCLK(32KHz) WL_RST# RTC_CLK_R [9]
43 44 RWL9 1 @ 2 0_0402_5%
GND_51 PERST0# APU_PCIE_RST# [8,18,22]
[9] CLKREQ_WLAN# RWL2 1 @ 2 0_0402_5% CLKREQ_WLAN#_R 45 46 BT_DISABLE_R RWL101 @ 2 0_0402_5%
CLKREQ0# W_DISABLE2# WLAN_DISABLE_R APU_BT_OFF# [9]
47 48 RWL111 @ 2 0_0402_5%
PEWAKE0# W_DISABLE1# APU_WL_OFF# [9]
49 50
51 GND_57 I2C_DAT 52
53 RSVD/PCIE_RX_P1 I2C_CLK 54
3
55 RSVD/PCIE_RX_N1 I2C_IRQ 56
Note: The real behavior of BT_DISABLE_R are 3

57 GND_63 RSVD_64 58 BT_DISABLE_R = LOW, BT=OFF

RSVD/PCIE_TX_P1 RSVD_66

2
59
RSVD/PCIE_TX_N1 RSVD_68
60 BT_DISABLE_R = HIGH, BT=ON
61 62 RWL12
63 GND_69 RSVD_70 64 100K_0402_5%
65 RSVD_71 3.3VAUX_72 66
67 RSVD_73 3.3VAUX_74

1
GND_75 68
69 GND1
GND2
BELLW_80152-3221
ME@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN/BT Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 17 of 41
A B C D E
 A B C D E

NGFF for SSD co-lay SATA M.2 (M-KEY)

1 1

+3VS_SSD1

+3VS Consumption Test +3VS_SSD1

JSSD1
1 2
RSSD1 1 @ 2 0_0805_5% 3 GND 3P3VAUX 4
PCIE_ARX_DTX_N4 5 GND 3P3VAUX 6
[6] PCIE_ARX_DTX_N4 PERn3 NC

10U 6.3V M X5R 0402

CSSD1

0.1U_0201_10V6K
CSSD2

0.01U_0402_16V7K
CSSD3
PCIE_ARX_DTX_P4 7 8
[6] PCIE_ARX_DTX_P4 PERp3 NC
1 1 1 9 10
PCIE_ATX_C_DRX_N4 11 GND DAS/DSS# 12
[6] PCIE_ATX_C_DRX_N4 PCIE_ATX_C_DRX_P4 PETn3 3P3VAUX
13 14
[6] PCIE_ATX_C_DRX_P4 PETp3 3P3VAUX
15 16
2 2 2 GND 3P3VAUX
SSD@

SSD@

@
PCIE_ARX_DTX_N5 17 18
[6] PCIE_ARX_DTX_N5 PCIE_ARX_DTX_P5 PERn2 3P3VAUX
19 20
[6] PCIE_ARX_DTX_P5 PERp2 NC
21 22
PCIE_ATX_C_DRX_N5 23 GND NC 24
[6] PCIE_ATX_C_DRX_N5 PCIE_ATX_C_DRX_P5 PETn2 NC
25 26
[6] PCIE_ATX_C_DRX_P5 PETp2 NC
27 28
2
PCIE_ARX_DTX_N6 29 GND NC 30
2
[6] PCIE_ARX_DTX_N6 PCIE_ARX_DTX_P6 PERn1 NC
31 32
[6] PCIE_ARX_DTX_P6 PERp1 NC
33 34
PCIE_ATX_C_DRX_N6 35 GND NC 36
[6] PCIE_ATX_C_DRX_N6 PCIE_ATX_C_DRX_P6 PETn1 NC
37 38
[6] PCIE_ATX_C_DRX_P6 PETp1 DEVSLP
39 40
SATA_ARX_DTX_P1 41 GND NC 42
+3VS_SSD1 [6] SATA_ARX_DTX_P1 SATA_ARX_DTX_N1 PERn0/SATA-B+ NC
43 44
[6] SATA_ARX_DTX_N1 PERp0/SATA-B- NC
45 46
SATA_ATX_C_DRX_N1 47 GND NC 48
[6] SATA_ATX_C_DRX_N1 SATA_ATX_C_DRX_P1 PETn0/SATA-A- NC PLT_RST_SSD#
U3 49 50
[6] SATA_ATX_C_DRX_P1 PETp0/SATA-A+ PERST# PLT_RST_SSD# [19]
MC74VHC1G08DFT2G_SC70-5 51 52 CLKREQ_SSD1# [9]
@ CLK_PCIE_SSD1# 53 GND CLKREQ# 54
[9] CLK_PCIE_SSD1# REFCLKN PEWake#
5

CLK_PCIE_SSD1 55 56
[9] CLK_PCIE_SSD1 REFCLKP NC
1 57 58

Vinafix.com
P

[9] SSD_RST# IN1 GND NC

4 PLT_RST_SSD#
2 O
[8,17,22] APU_PCIE_RST# IN2
G

+3VS_SSD1
1
3

@ 59 60
RSSD3 PCIE_DET 61 NC SUSCLK(32kHz) 62
[8] PCIE_DET PEDET(NC-PCIE/GND-SATA) 3P3VAUX
100K_0402_5% 63 64
65 GND 3P3VAUX 66
PU at APU side
2

67 GND 3P3VAUX
3 3
RSSD2 1 @ 2 0_0402_5% GND 68
GND1 69
GND2
BELLW_80159-3221
ME@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2018/08/24 Deciphered Date 2018/05/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M.2 SSD/HDD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 18 of 41
A B C D E
 A B C D E

NGFF for 2nd_SSD (M-KEY)

1 1

+3VS Consumption Test +3VS_SSD2

+3VS_SSD2

RSSD4 1 @ 2 0_0805_5%
JSSD2

10U 6.3V M X5R 0402

CSSD7

0.1U_0201_10V6K
CSSD8

0.01U_0402_16V7K
CSSD9
1 2
3 GND 3P3VAUX 4
1 1 1 GND 3P3VAUX
5 6
7 PERn3 NC 8
9 PERp3 NC 10
2 2 2 GND DAS/DSS#

SSD@

SSD@

@
11 12
13 PETn3 3P3VAUX 14
15 PETp3 3P3VAUX 16
17 GND 3P3VAUX 18
19 PERn2 3P3VAUX 20
21 PERp2 NC 22
23 GND NC 24
25 PETn2 NC 26
2
27 PETp2 NC 28
2

PCIE_ARX_DTX_N3 29 GND NC 30
[6] PCIE_ARX_DTX_N3 PCIE_ARX_DTX_P3 PERn1 NC
31 32
[6] PCIE_ARX_DTX_P3 PERp1 NC
33 34
PCIE_ATX_C_DRX_N3 35 GND NC 36
[6] PCIE_ATX_C_DRX_N3 PCIE_ATX_C_DRX_P3 PETn1 NC
37 38
[6] PCIE_ATX_C_DRX_P3 PETp1 DEVSLP
39 40
PCIE_ARX_DTX_N2 41 GND NC 42
[6] PCIE_ARX_DTX_N2 PCIE_ARX_DTX_P2 PERn0/SATA-B+ NC
43 44
[6] PCIE_ARX_DTX_P2 PERp0/SATA-B- NC
45 46
PCIE_ATX_C_DRX_N2 47 GND NC 48
[6] PCIE_ATX_C_DRX_N2 PCIE_ATX_C_DRX_P2 PETn0/SATA-A- NC PLT_RST_SSD#
49 50
[6] PCIE_ATX_C_DRX_P2 PETp0/SATA-A+ PERST# PLT_RST_SSD# [18]
51 52 CLKREQ_SSD2# [9]
CLK_PCIE_SSD2# 53 GND CLKREQ# 54
[9] CLK_PCIE_SSD2# CLK_PCIE_SSD2 REFCLKN PEWake#
55 56

Vinafix.com
[9] CLK_PCIE_SSD2 REFCLKP NC
57 58
GND NC

+3VS_SSD2

59 60
61 NC SUSCLK(32kHz) 62
63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
65 GND 3P3VAUX 66
3 3
67 GND 3P3VAUX
GND 68
GND1 69
GND2
BELLW_80159-3221
ME@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2018/08/24 Deciphered Date 2018/05/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M.2 2nd SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 19 of 41
A B C D E
 A B C D E

+5VALW CA38 1 2 1U_0201_6.3V6M

+5VDDA_CODEC Speaker
RA66 1 2 0_0402_5%
CX11880 +1.8VDD_CODEC
RA67 1 @ 2 0_0402_5%
EMI wide 40MIL

CA31

CA30
1U_0201_6.3V6M

1U_0201_6.3V6M
GNDA SPEAK 4 ohm : 40MIL

CA54

CA53
JSPK1

2.2U_0402_6.3V6M

0.1U_0201_10V K X5R
+IOVDD_CODEC +5VDDA_CODEC SPEAK 8 ohm : 20MIL
1 1 6
5 G2
1 1 G1
+1.8VDD_CODEC SPK_L1- RA16 1 @ 2 0_0603_5% SPK_L1-_CONN 4
SPK_L2+ RA17 1 @ 2 0_0603_5% SPK_L2+_CONN 3 4

0.47U_0402_25V6K
2 2 SPK_R1- RA18 1 @ 2 0_0603_5% SPK_R1-_CONN 2 3
1 2 2 2
SPK_R2+ RA19 1 @ 2 0_0603_5% SPK_R2+_CONN 1
1 1 1

CA42

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
CVILU_CI4404M1HRT-NH
2 +1.8VS

39

38

18

29

13

16

37

28

27
ME@

9
UA1 1 1 1 1

EMI@ CA19

EMI@ CA20

EMI@ CA21

EMI@ CA22
Place near Pin18

LDO_V12

HDA_VDDIO

DVDD_IO

VDD18

CP_AVDD18

AVDD5

PVDD5_L

PVDD5_R

LDO_AVDD

VREFP

VREF_DAC

1
2 2 2 2
RA39
HDA_RST#_AUDIO 5.11K_0402_1%
[8] HDA_RST#_AUDIO
[8] HDA_BITCLK_AUDIO 2

2
RESET#
@EMI@ @EMI@ CX11880-11Z 32 MICBIASB ESD protection needs to be placed near connector side
CA29 22P_0402_50V8J RA36 2 1 33_0402_5% 40 MICBIASB
41 HDA_BUS_BCLK 35 PLUG_IN_R RA1 1 2 39.2K_0402_1% PLUG_IN
[8] HDA_SYNC_AUDIO
[8]
[8]
HDA_SDIN0
HDA_SDOUT_AUDIO
RA35 1 2 33_0402_5% HDA_SDIN0_AUDIO 42
1
HDA_BUS_SYNC
HDA_BUS_SDI
HDA_BUS_SDO
JSENSE
RA61 1 2 20K_0402_1% ESD
34 Port_B_R +5VS
RA56 1 2 100K_0402_5% 7 PORT_B_R 33 Port_B_L
+3VS SPKR_MUTE#/SPDIF/GPIO1 PORT_B_L @ESD@ DA1
RA34 1 @ 2 0_0402_5% PDB 11 SPK_R1-_CONN 6 3 SPK_L2+_CONN
[28] EC_MUTE# Bi-directional EAPD I/O4 I/O2
31 EXT_MIC_RING2
PC_BEEP 36 PORTD_B_MIC 30 EXT_MIC_SLEEVE
PCBEEP PORTD_A_MIC
6 5 2
MUSIC_REQ/SPDIF/GPIO0 26 HGNDB VDD GND
EMI@ HGNDB 25 HGNDA
LA1 1 2 BLM15PX221SN1D_2P DMIC_CLK_R 10 HGNDA
[14] DMIC_CLK PORTC_DMIC_CLK1/GPIO2
DMIC_DAT 8 SPK_R2+_CONN 4 1 SPK_L1-_CONN
[14] DMIC_DAT PORTC_DMIC_DATA1/GPIO3 I/O3 I/O1
24 HP_OUTR
PORTA_R
+1.8VDD_CODEC RA32 1 2 10K_0402_5% 4
5 HSCL/TEST1 PORTA_L
23 HP_OUTL Headphone AZC099-04S.R7G_SOT23-6
HSDA/TEST2

12 21
14 LEFT+ CP_VNEG 22
LEFT- CP_VPOS

CA33

CA34
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
2 2

CA32
15 20

2.2U_0402_6.3V6M
RIGHT- CP_FLY_N

EP_GND
17 19 1 1 1
RIGHT+ CP_FLY_P

CX11880-11Z_QFN42_5X5 2 2 2

43
@
2 1 CA52 2 @ 1 RA40 SPK_R2+

@
220P_0402_50V7K 10_0402_5% EMI
2 1 CA51 2 @ 1 RA42 SPK_R1-
220P_0402_50V7K 10_0402_5%
@ EXT_MIC_SLEEVE RA62 1 2 100_0402_5% CA55 1 2 1U_0402_10V6K EMI@ LA2 1 2 BLM15BD121SN1D_2P HGNDB
2 1 CA45 2 @ 1 RA44 SPK_L1-
Speaker W=40mils EXT_MIC_RING2 RA63 1 2 100_0402_5% CA56 1 2 1U_0402_10V6K EMI@ LA3 1 2 BLM15BD121SN1D_2P HGNDA
220P_0402_50V7K 10_0402_5%
W=40mils HP_OUTL EMI@ RA22 1 2 47_0402_5% HPOUT_L
@ HP_OUTR EMI@ RA23 1 2 47_0402_5% HPOUT_R

Vinafix.com
2 1 CA46 2 @ 1 RA43 SPK_L2+
220P_0402_50V7K 10_0402_5% EMI@ LA4 1 2 BLM15BD121SN1D_2P RA64 1 2 100_0402_5% CA57 1 2 2.2U_0402_6.3V6M Port_B_R
EMI@ LA5 1 2 BLM15BD121SN1D_2P RA65 1 2 100_0402_5% CA58 1 2 2.2U_0402_6.3V6M Port_B_L
Reserved Snubber Networks

470P_0402_50V7K

470P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
1

1
Place near Codec Pins

RA59
3K_0402_5%

3K_0402_5%
RA60
1 1

2
2
CA25

CA26
10K_0402_5%

10K_0402_5%
RA24

RA25

CA50

CA24
@ @

1
1
2 2

1
MICBIASB EMI@ EMI@ EMI@ EMI@

+5VS --> +5VDDA_CODEC +3VS --> +IOVDD_CODEC RF request GNDA GNDA GNDA GNDA GNDA GNDA

@RF@

3
+5VS
wide 40MIL +5VDDA_CODEC
+3VS +IOVDD_CODEC
HDA_RST#_AUDIO CA59 1

@RF@
2 2.2P_0402_50V8C
3
RA9 1 @ 2 0_0603_5% RA10 1 @ 2 0_0603_5% HDA_SYNC_AUDIO CA60 1 2 2.2P_0402_50V8C

@RF@
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

HDA_SDIN0 CA61 1 2 2.2P_0402_50V8C

1U_0201_6.3V6M

1 1 1 1 1 1
CA39

CA40

CA37

CA12

CA28 CA13 @RF@

HDA_SDOUT_AUDIO CA62 1 2 2.2P_0402_50V8C
2 2 2 2 2 2 Combo Jack (Normal Open)
HGNDA / HGNDB , W=60mils
JHP1
HGNDA 3 RING2_L
HPOUT_L RA28 1 @ 2 0_0402_5% HPOUT_L1 1 HPOUT_L_2
Place near Pin13,16,29 Place near Pin9,18
5 HP_PLUG#
PLUG_IN 6 GND
HPOUT_R RA29 1 @ 2 0_0402_5% HPOUT_R1 2 HPOUT_R_2
HGNDB 4 SLEEVE_L
7 GND

CA65

CA66

CA63

CA64

CA67
YUQIU_PJ784-F07M1BE-A

L03ESDL5V0CC3-2_SOT23-3
DA3

L03ESDL5V0CC3-2_SOT23-3
DA4
2 2 ME@
+1.8VS --> +1.8VDD_CODEC

1
2

2
1 1

@ESD@

@ESD@

2200P_0402_25V7K

2200P_0402_25V7K

.047U 16V K X7R

RA57 1 @ 2 0_0402_5%
+1.8VS +1.8VDD_CODEC

100P_0402_50V8J

100P_0402_50V8J
PC Beep

@ESD@

ESD@

ESD@

ESD@

@ESD@
RA31 1 @ 2 0_0402_5% RA14 1 @ 2 0_0402_5%
0.1U_0201_10V K X5R

1
1 1 1 2 1 2 PC_BEEP RA15 1 @ 2 0_0402_5%
[28] BEEP#
CA41

CA43
1U_0201_6.3V6M

RA12 4.7K_0402_5% CA15 0.1U_0201_10V K X5R

[8] HDA_SPKR 1 2 1 2
RA4 4.7K_0402_5% CA44 0.1U_0201_10V K X5R RA58 1 @ 2 0_0402_5%
4
2 2 4

GND GNDA
Place near Pin38

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_CX11880
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 20 of 41
A B C D E
 A B C D E

USB20 HUB
1 1

+3VS_HUB
+3VS +3VALW +3VS_HUB
UHUB1
RHUB1 2 @ 1 0_0603_5% 5 1
AVDD DM0 USB20_N4 [9]
Close to P14 Close to P28 9 2 SOC
AVDD DP0 USB20_P4 [9]
RHUB2 2 1 0_0603_5% 14
@ 21 AVDD 3
DVDD DM1 HUB_USB20_N1 [14]
27 4 Touch Screen
V5 DP1 HUB_USB20_P1 [14]

1U_0201_6.3V6M
CHUB1

0.1U_0201_10V6K
CHUB2

1U_0201_6.3V6M
CHUB3

0.1U_0201_10V6K
CHUB4

0.1U_0201_10V6K
CHUB5

0.1U_0201_10V6K
CHUB6

10U_0402_6.3V6M
CHUB7

0.1U_0201_10V6K
CHUB11
1 1 1 1 1 1 1 1 28
V33 6
DM2 HUB_USB20_N2 [27]
7 Finger print
DP2 HUB_USB20_P2 [27]
18
2 2 2 2 2 2 2 2 26 TEST/SCL 12
SDA DM3 13
HUB_RESET# 17 DP3
RESET# 15
HUB_X1 10 DM4 16
HUB_X2 11 X1 DP4
X2 25
2 Close to P9 Close to P5 Close to P21 OVCUR1#/SMC 2
HUB_RSELF 22 24
23 PSELF OVCUR2#/SMD 20
PGANG OVCUR3# 19
OVCUR4#

1
29 8 RREF
GND RREF

1
RHUB8
100K_0402_5% GL850G-OHY50_QFN28_5X5 RHUB9 Pin 18 TEST:
0 : Switch mode.
680_0402_1%

2
1 : Chip will be put in test mode.
RHUB5 1 2 10K_0402_5% HUB_RSELF
+3VS_HUB NC : Normal hub operation.

2
RHUB6 1 2 1K_0402_5% HUB_RESET#

Vinafix.com
Y1
1

1 12MHZ_12PF_7V12000011
@
CHUB8 RHUB7 HUB_X1 1 3HUB_X2
1U_0201_6.3V6M 47K_0402_5% 1 3
2 1 GND GND 1
CHUB9
2

33P_0402_50V8J CHUB10
2 4 33P_0402_50V8J
2 2
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB20 Hub
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 21 of 41
A B C D E
 A B C D E

USB3.0_Port (AUO_Port) USB Charge switch

+VL +5VALW_CHG +5VALW

IO CONN
+3VL +5VALW_CHG
1 1

1
R280 1 2 0_0805_5%
+5VALW_USB1

10K_0402_5%
R110
+3VALW

1
1 2 3 1

D
2 @

10U_0603_6.3V6M
C52
R108 1 Q2 1 JIO1
10K_0402_5% C51 R111 @ 1
U7 10U 6.3V M X5R 0402 @ 0_0603_5% USB3_ARX_DTX_P1 2 1
80mil

G
[9] USB3_ARX_DTX_P1

2
1 12 @ USB3_ARX_DTX_N1 3 2
[9] USB3_ARX_DTX_N1

2
9 IN OUT 10 USB20_P1_C 2 ME2301DC-G_SOT23-3 2 USB3_ATX_DRX_P1 4 3
[28] USB_CHG_STATUS# STATUS# DP_IN [9] USB3_ATX_DRX_P1 4
R112 2 @ 1 0_0402_5% USB_OC0#_R 13 11 USB20_N1_C USB3_ATX_DRX_N1 5
[9] USB_OC0# FAULT# DM_IN [9] USB3_ATX_DRX_N1 5
4 2 USB20_N1 [9] 6
[28] USB_CHG_ILIM_SEL ILIM_SEL DM_OUT +VL USB20_N1_R 6
5 3 USB20_P1 [9] 7
[28] USB_CHG_EN EN DP_OUT USB20_P1_R 7
6 15 R113 1 2 2.7M_0402_1% 8
[28] USB_CHG_CTL1 CTL1 ILIM_LO 8
7 16 R114 1 2 24.9K_0402_1% 9
[28] USB_CHG_CTL2 CTL2 ILIM_HI USB3_ARX_DTX_P2 9
8 14 R115 1 @ 2 100K_0402_5% [9] USB3_ARX_DTX_P2 10
[28] USB_CHG_CTL3 CTL3 GND USB3_ARX_DTX_N2 10
17 [9] USB3_ARX_DTX_N2 11
T-PAD USB3_ATX_DRX_P2 12 11
[9] USB3_ATX_DRX_P2 12

0.1U_0201_10V K X5R
C53
SN1702001RTER_WQFN16_3X3 1 USB3_ATX_DRX_N2 13
[9] USB3_ATX_DRX_N2 13
1

2N7002KW_SOT323-3
10K_0402_5%
R117

14

1
D
USB20_N2_R 15 14
R118 1 @ 2 0_0402_5% EC_ON_R 2 15
10U_0603_6.3V6M
C48

10U_0603_6.3V6M
C49

0.1U_0201_10V K X5R
C50
1 1 1 [28,29,34,36] 3V/5VALW_PG @ USB20_P2_R 16
G 2 16
17

0.1U_0201_10V K X5R
C54
+5VALW_USB1 17
18
Q3
2

@ 1 @ S 19 18

3
2 2 2 20 19
21 20
@ 21
2 +5VALW_USB2 22
23 22
24 23
25 24
26 25
+3VS 26
27
APU_PCIE_RST# 28 27
[8,17,18] APU_PCIE_RST# 28
PCIE_ATX_C_DRX_P0 29
[6] PCIE_ATX_C_DRX_P0 29
PCIE_ATX_C_DRX_N0 30
[6] PCIE_ATX_C_DRX_N0 30
PCIE_ARX_DTX_P0 31
[6] PCIE_ARX_DTX_P0 31
PCIE_ARX_DTX_N0 32
[6] PCIE_ARX_DTX_N0 32
33
+5VALW CLK_PCIE_SD 34 33
[9] CLK_PCIE_SD 34
CLK_PCIE_SD# 35
[9] CLK_PCIE_SD# 35
CLKREQ_SD# 36
[9] CLKREQ_SD# 36
2 [28] NOVO# NOVO# 37 2
ON/OFF# 38 37
[28,29] ON/OFF# 38
22U_0603_6.3V6M
C55

22U_0603_6.3V6M
C56

22U_0603_6.3V6M
C57

10U 6.3V M X5R 0402

C58

10U 6.3V M X5R 0402

C59

47U_0805_6.3V6M
C60

22U_0603_6.3V6M
C61

22U_0603_6.3V6M
C62

22U_0603_6.3V6M
C63

22U_0603_6.3V6M
C64
1 1 1 1 1 1 1 1 1 1 +VL 39

@ @ @ @ @ @ @ @ @ @
EMI [28]
[28]
PWR_LED#
PWR_BATT_LOW#
PWR_LED#
PWR_BATT_LOW#
40
41
42
39
40
41 43
2 2 2 2 2 2 2 2 2 2 USB20_P1_C R119 1 @ 2 0_0402_5% USB20_P1_R 42 GND 44
GND
ACES_50501-04201-001
USB20_N1_C R120 1 @ 2 0_0402_5% USB20_N1_R ME@

For USB Charger to improve +5VALWP power ripple

Vinafix.com
ON/OFF#

NOVO#

2
AZ5125-02S.R7G_SOT23-3
D2
ESD

@ESD@

1
3 3

USB3.0_Port (Non AUO_Port)

+5VALW
+5VALW_USB2
2A/Active Low
W=80mils
5
U9
1
W=80mils EMI
IN OUT USB20_P2 R125 1 @ 2 0_0402_5% USB20_P2_R
[9] USB20_P2
2
GND
USB_EN# 4 3 R122 1 @ 2 0_0402_5% USB20_N2 R126 1 @ 2 0_0402_5% USB20_N2_R
[28] USB_EN# EN(EN#) OC# USB_OC1# [9] [9] USB20_N2
0.1U_0201_10V K X5R
C66

1 G524B2T11U_SOT23-5

USB port cap on Sub/B

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 Type-A / IO Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 22 of 41
A B C D E
 A B C D E

Type-C USB3.1_Port TI @ UT4 TI@ RT48 TI@ RT26 TI@ RT22 TI@ RT50 TI@ RT51 TI@
SN65LVPE512RGER 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

PA@ UT4 PA@ RT25 PA@

PS8713BTQFN24GTR2-A2 4.7K_0402_5%

1 UT4 PE@ RT49 PE@ RT24 PE@ RT28 PE@ 1

PE@ PI3EQX7502AIZDEX TQFN24 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%

+3VALW +3VALW ZZZ X76_PA@

USB3.0 re-driver_PARADE
X7680638L54

ZZZ X76_PE@

0.01U_0402_16V7K

0.1U_0201_10V K X5R
USB3.0 re-driver_PERICOM

CT31

CT32
X7680638L55
1 1
ZZZ X76_TI@
USB3.0 re-driver_TI
UT4 @ X7680638L56
1 2 2
VDD 13
VDD
P3_A_EQ1 4
P3_A_DE0 3 NC 15 P3_B_EQ1
P3_A_EQ0 2 DE_A NC 16 P3_B_DE0
2
P3_A_DE1 6 EQ_A DE_B 17 P3_B_EQ0
2
To CPU NC EQ_B 18 P3_B_DE1
NC To Mux
CT29 1 2 0.33U_0402_10V6K USB3_ARX_C_RD_DTX_P0 12 19
[9] USB3_ARX_DTX_P0 USB3_ARX_C_RD_DTX_N0 11 TXB+ RXB+ USB3_ARX_RD_DTX_P0 [24]
CT30 1 2 0.33U_0402_10V6K 20
[9] USB3_ARX_DTX_N0 TXB- RXB- USB3_ARX_RD_DTX_N0 [24]

[9] USB3_ATX_DRX_P0 CT27 1 2 0.22U_0402_6.3V6K USB3_ATX_C_RD_DRX_P0 9 22

RXA+ TXA+ USB3_ATX_RD_DRX_P0 [24]
[9] USB3_ATX_DRX_N0 CT28 1 2 0.22U_0402_6.3V6K USB3_ATX_C_RD_DRX_N0 8 23
RXA- TXA- USB3_ATX_RD_DRX_N0 [24]

5 PD#_1
10 RXD_EN 7
21 EN_A# NC 14 TEST3
EN_B# NC

4.99K_0402_1%

4.7K_0402_5%
25 24 I2C_EN1

Vinafix.com
GPAD NC

1
RT46

RT47
PI3EQX7502AIZDEX_TQFN24_4X4
@ @

USB3 Re-driver

2
3 3

+3VALW +3VALW +3VALW

+3VALW +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

1
1

1
RT29 RT45 RT30
RT56 RT55 RT52 RT53 RT23 RT25 RT27 RT54 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% @ @ @

2
@ @ @ @ @ @ @ @
2

2
P3_B_EQ0 P3_B_EQ1 P3_B_DE0 P3_B_DE1 P3_A_EQ0 P3_A_EQ1 P3_A_DE0 P3_A_DE1 TEST3 PD#_1 I2C_EN1
1

1
RT49 RT50 RT51 RT22 RT24 RT26 RT28 RT48
4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
@ @ @ @ @ @ @ @
2

2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Type-C USB3.1 Re-driver
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 23 of 41
A B C D E
 A B C D E

TYPE-C - CC+MUX (RTS5448-GR)

+5VALW +VCON_IN_5448 +5VALW +5V_IN_5448

RT1 1 @ 2 0_0603_5% RT2 1 @ 2 0_0603_5%

+5V_IN_5448

1 CC1_5448_CONN CC2_5448_CONN 1

+VCON_IN_5448 +LDO_3V3_5448
1 1

1
CT5 CT6
CT3 CT4 10U_0402_6.3V6M 0.1U_0201_10V K X5R
220P_0402_50V8J 220P_0402_50V8J 1 1

2
CT2 CT1 2 2
0.1U_0201_10V K X5R 4.7U_0402_6.3V6M
2 2

13

19

20
UT1
USB3_MRX_DTX_P2 CT23 1 2 0.33U_0402_10V6K USB3_MRX_C_DTX_P2 1

VCON_IN

5V_IN

LDO_3V3
[25] USB3_MRX_DTX_P2 USB3_MRX_DTX_N1 USB3_MRX_C_DTX_N1 C_RX2_1N/2P CC2_5448_CONN
CT24 1 2 0.33U_0402_10V6K 2 14 CC2_5448_CONN [25]
[25] USB3_MRX_DTX_N1 USB3_MRX_DTX_P1 USB3_MRX_C_DTX_P1 C_RX1_1P/2N CC2 VBUS_EN_5448
CT25 1 2 0.33U_0402_10V6K 3 15 VBUS_EN_5448 [25]
[25] USB3_MRX_DTX_P1 USB3_ARX_RD_DTX_N0 USB3_ARX_C_MTX_N0 C_RX1_1N/2P VBUS_EN OCP_DET_5448_R
CT19 1 2 0.33U_0402_10V6K 4 16
[23] USB3_ARX_RD_DTX_N0 USB3_ARX_RD_DTX_P0 USB3_ARX_C_MTX_P0 SSRX_1P/2N OCP_DET VMON_5448
CT20 1 2 0.33U_0402_10V6K 5 17
[23] USB3_ARX_RD_DTX_P0 USB3_ATX_RD_DRX_N0 USB3_ATX_C_MRX_N0 SSRX_1N/2P INPUT VMON
CT18 1 2 0.22U_0402_6.3V6K 6 18 RT3 1 2 6.2K_0402_1%
[23] USB3_ATX_RD_DRX_N0 USB3_ATX_RD_DRX_P0 USB3_ATX_C_MRX_P0 SSTX_1P/2N REXT
CT17 1 2 0.22U_0402_6.3V6K 7
[23] USB3_ATX_RD_DRX_P0 USB3_MTX_C_DRX_N1 USB3_MTX_DRX_N1 SSTX_1N/2P
CT7 1 2 0.1U_0201_10V6K 8
[25] USB3_MTX_C_DRX_N1 USB3_MTX_C_DRX_P1 USB3_MTX_DRX_P1 C_TX1_1P/2N TYPEC_LIMIT_CTL1
CT8 1 2 0.1U_0201_10V6K 9 21 TYPEC_LIMIT_CTL1 [28]
[25] USB3_MTX_C_DRX_P1 USB3_MTX_C_DRX_P2 USB3_MTX_DRX_P2 C_TX1_1N/2P RP_SEL_M1 TYPEC_LIMIT_CTL2
CT9 1 2 0.1U_0201_10V6K 10 22 TYPEC_LIMIT_CTL2 [28]
[25] USB3_MTX_C_DRX_P2 USB3_MTX_C_DRX_N2 USB3_MTX_DRX_N2 C_TX2_1N/2P RP_SEL_M0 DIR_SET
CT10 1 2 0.1U_0201_10V6K 11 23
[25] USB3_MTX_C_DRX_N2 CC1_5448_CONN C_TX2_1P/2N NC USB3_MRX_C_DTX_N2
12 24 1 2 USB3_MRX_DTX_N2 [25]
[25] CC1_5448_CONN CC1 C_RX2_1P/2N 25 CT26 0.33U_0402_10V6K
GND

DIR_SET
USB3_MRX_DTX_P2 RT18 1 2 220K_0402_5% RTS5448-GR QFN 24P TYPE-C
USB3_MRX_DTX_N1 RT19 1 2 220K_0402_5%

2
USB3_MRX_DTX_P1 RT20 1 2 220K_0402_5%
USB3_MRX_DTX_N2 RT21 1 2 220K_0402_5% RT17
10K_0402_5%

2 2

MUX MISC.

1
+LDO_3V3_5448 +LDO_3V3_5448
2

Vinafix.com
RT12 RT13
10K_0402_5% 10K_0402_5%
1

TYPEC_LIMIT_CTL1 TYPEC_LIMIT_CTL2
1

RT4 @ RT5 @
10K_0402_5% 10K_0402_5%
2

Rp Configuration

3 3

+VBUS_5448 +5V_IN_5448 +5V_IN_5448

1

1
RT6 RT7 RT8
200K_0402_1% 4.7K_0402_5% @ 4.7K_0402_5%
2

VMON_5448 VBUS_EN_5448 OCP_DET_5448 1 @ 2 OCP_DET_5448_R

OCP_DET_5448_R [25]
RT16 0_0603_5%
1
1

RT9 RT11 @
10K_0402_1% RT10 10K_0402_5%
10K_0402_5%
2
2

For C_VBUS For C_VBUS

(Power Switch Enable Pin) (Power Switch OCP Pin)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Type-C_RTS5448
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 24 of 41
A B C D E
 A B C D E

ESD COMPONENTS Over Current Protection Pin: +VBUS_5448 +VBUS_5448_R

JT1 @
If Over Current Occurred - From High to Low.
1 2
1 2

20V_PRTCT@
10U_0603_25V6M
CT22
1
+VBUS_5448

10U_0603_25V6M
CT21

150U_B2_6.3VM_R35M
CT33
DT1 +5VALW 1 JUMP_43X79 1
USB3_MRX_DTX_P1 9 10 1 1 USB3_MRX_DTX_P1 +
1 UT3 1
USB3_MRX_DTX_N1 8 9 2 2 USB3_MRX_DTX_N1 @
2 B1 C2 2 2
7 4
USB3_MTX_C_DRX_N2 7 4 USB3_MTX_C_DRX_N2 C1 VINT VBUS D1
1 VINT VBUS
UT2 CT12 B2 D2
6 5
USB3_MTX_C_DRX_P2 6 5 USB3_MTX_C_DRX_P2 5 1 10U_0603_25V6M VINT VBUS
IN OUT @
3 3 OCP_DET_5448_R 3 2 A3
[24] OCP_DET_5448_R VBUS_EN_5448 FLAG +VBUS_5448 ILIM
4 2 A2
8 [24] VBUS_EN_5448 EN(#EN) GND FAULT B3
G517G1TO1U_TSOT23-5 A1 GND C3
L05ESDL5V0NA-4 SLP2510P8 ESD EN GND D3
GND

1
ESD@ 1

1
CT11 NX5P3090UK_WLCSP12 RT15
10U_0402_6.3V6M RT14 20V_PRTCT@ 16K_0402_1%
10K_0402_5% 20V_PRTCT@
DT2 2 20V_PRTCT@
9 10 1

2
USB3_MTX_C_DRX_P1 1 USB3_MTX_C_DRX_P1

2
USB3_MTX_C_DRX_N1 8 9 2 2 USB3_MTX_C_DRX_N1

USB3_MRX_DTX_N2 7 7 4 4 USB3_MRX_DTX_N2
20 Volts Protection Circuit
2
USB3_MRX_DTX_P2 6 6 5 5 USB3_MRX_DTX_P2
2

3 3

L05ESDL5V0NA-4 SLP2510P8 ESD

ESD@ +VBUS_5448_R +VBUS_5448_R

JUSBC1
A1 B12
GND GND
USB3_MTX_C_DRX_P1 A2 B11 USB3_MRX_DTX_P1
[24] USB3_MTX_C_DRX_P1 USB3_MTX_C_DRX_N1 SSTXP1 SSRXP1 USB3_MRX_DTX_N1 USB3_MRX_DTX_P1 [24]
A3 B10

Vinafix.com
[24] USB3_MTX_C_DRX_N1 SSTXN1 SSRXN1 USB3_MRX_DTX_N1 [24]
CT13 1 2 0.47U_0402_25V6K A4 B9 CT14 1 2 0.47U_0402_25V6K
DT4 VBUS VBUS
USB20_P0_R 3 6 CC1_5448_CONN CC1_5448_CONN A5 B8
I/O2 I/O4 [24] CC1_5448_CONN CC1 SBU2
USB20_P0_R A6 B7 USB20_N0_R
USB20_N0_R A7 DP1 DN2 B6 USB20_P0_R
2 5 DN1 DP2
GND VDD A8 B5 CC2_5448_CONN
3 CC2_5448_CONN [24] 3
SBU1 CC2
CT15 1 2 0.47U_0402_25V6K A9 B4 CT16 1 2 0.47U_0402_25V6K
CC2_5448_CONN 1 4 USB20_N0_R VBUS VBUS
I/O1 I/O3 USB3_MRX_DTX_N2 A10 B3 USB3_MTX_C_DRX_N2
[24] USB3_MRX_DTX_N2 SSRXN2 SSTXN2 USB3_MTX_C_DRX_N2 [24]
AZC099-04S.R7G_SOT23-6 USB3_MRX_DTX_P2 A11 B2 USB3_MTX_C_DRX_P2
[24] USB3_MRX_DTX_P2 SSRXP2 SSTXP2 USB3_MTX_C_DRX_P2 [24]
ESD@
A12 B1
GND GND

3
1 4 DT5
2 GND GND 5 L30ESD24VC3-2_SOT23-3
3 GND GND 6 ESD@
GND GND

1
LT1 EMI@

ESD
USB20_P0 2 1 USB20_P0_R DEREN_560Q10-002H
[9] USB20_P0 2 1 ME@

USB20_N0 3 4 USB20_N0_R
[9] USB20_N0 3 4
DLM0NSN900HY2D_4P

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Type-C_RTS5448_CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Wednesday, December 19, 2018 Sheet 25 of 41
A B C D E
 A B C D E

G-Sensor LID
Hall -Sensor for S540 Hall -Sensor for C340
+3VS Consumption Test +3VS_GS +3VALW
1 +3VALW 1
UGS1 UHS2
RGS1 1 @ 2 0_0603_5% +3VS_GS 7 3 UHS1 APX8132AI-TRG_SOT23-3
10 VDD VDDIO 11 APX8132AI-TRG_SOT23-3
CSB PS
0.1U_0201_10V6K
CG1

LID_SW# 3 2

GND
VOUT VDD
2

0.1U_0201_10V6K
CG2
5 4 LID_SW# 3 2

GND
INT1 NC [28] LID_SW# VOUT VDD

2
6 2 1
INT2 1 CHS3 C340@ CHS4
2 1
1

1
G_SEN@ 2 SDO 9 CHS1 S540@ CHS2 10P_0402_50V8J 0.1U_0201_10V6K
[14,28] EC_SMB_DA4

1
12 SDx GND 8 @ 10P_0402_50V8J 0.1U_0201_10V6K C340@ C340@
[14,28] EC_SMB_CK4 SCx GNDIO 1 2
S540@ S540@
BMA253_LGA12 1 2
G_SEN@

SMB Address: 0X18

FAN Conn Thermistor

2 2

+5VS
Thermal Decided Thermal Decided Thermal Decided
Consumption Test
+EC_VCCA +EC_VCCA +EC_VCCA

RF1 1 @ 2 0_0603_5%

1
16.5K_0402_1%
RTS1

16.5K_0402_1%
RTS2

16.5K_0402_1%
RTS3
1 1
6.8P_0402_50V8C
CF3

CF1
@RF@ 10U 6.3V M X5R 0402
2 2 JFAN1

2
6

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5 G2
+5VS_FAN1 4 G1 CUST_TEMP1 CUST_TEMP2 CUST_TEMP3
4 [28] CUST_TEMP1 [28] CUST_TEMP2 [28] CUST_TEMP3
3
[28] EC_FAN_SPEED1 3
[28] EC_FAN_PWM1 2
2

1
1
1 RTS4 RTS5 RTS6
CVILU_CI4404M1HRT-NH 100K +-1% 0402 B25/50 4250K 100K +-1% 0402 B25/50 4250K 100K +-1% 0402 B25/50 4250K
ME@
Close to APU Close to DDR Close to Charger

2
+5VS
Consumption Test

RF2 1 @ 2 0_0603_5%
1 1 ECAGND ECAGND ECAGND
6.8P_0402_50V8C
CF4

CF2
@RF@ 10U 6.3V M X5R 0402
2 2 JFAN2
6
5 G2
+5VS_FAN2 4 G1
3
3 4 3
[28] EC_FAN_SPEED2 3
[28] EC_FAN_PWM2 2
1 2
1
CVILU_CI4404M1HRT-NH +3VS
ME@

1
CTH1
0.1U_0201_10V6K
2 BOTT DDR
EC_FAN_SPEED1 EC_FAN_PWM1 EC_FAN_SPEED2 EC_FAN_PWM2

BOTTOM CHARGER REMOTE1+ Close UTH1 UTH1

+3VS

1 1 1 1
CF5 CF6 CF7 CF8 1
QTH1
1

1
6.8P_0402_50V8C 6.8P_0402_50V8C 6.8P_0402_50V8C 6.8P_0402_50V8C C CTH3 1 10 EC_SMB_CK2
VCC SCL EC_SMB_CK2 [7,28]
MMBT3904WH_SOT323-3 2 2200P_0402_25V7K CTH4
2 @RF@ 2 @RF@ 2 @RF@ 2 @RF@ EC_SMB_DA2 RTH2
B @ 2200P_0402_25V7K REMOTE1+ 2 9 @
EC_SMB_DA2 [7,28] 10K_0402_5%
2

E 2 DP1 SDA
3

REMOTE1- REMOTE1- 3 8

2
DN1 ALERT#
REMOTE2+ REMOTE2+ 4 7 THM_ALERT#
BOTTOM APU DP2 THERM#
1 REMOTE2- 5 6
DN2 GND
1

C CTH5
QTH2 2 2200P_0402_25V7K CTH6
B @ 2200P_0402_25V7K F75303M_MSOP10
MMBT3904WH_SOT323-3
2

E 2
SA000046C00
3

REMOTE2-

REMOTE1,2 (+/-) :
Trace width/space:10/10 mil Address 1001_101xb
4 Trace length:<8" 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title
G sensor/LID/FAN/Thermistor
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 26 of 41
A B C D E
 A B C D E

Touch Pad +3VS

RTP1 1
Consumption

@
Test

2 0_0402_5%
Keyboard Backlight
+3VS

1U_0201_6.3V6M
CTP1
1
4.7K_0402_5%
RTP2
2

1
1K_0402_5%
RTP3

1K_0402_5%
RTP4
@

2
1 1
JTP1

2
+TP_VCC 8 +5VALW
7 8 10
[8] I2C_3_SCL_R 7 G2 +5VS +5VS_KBL
6 9
[8] I2C_3_SDA_R 6 G1
5
5 For C340_S540

1
4
3 4 RKBL1 QKBL1
2 3 10K_0402_5%
[8] TP_INT# JKBL1
1 2 3 1 4 6

D
[28] TP_DISABLE# 1 4 GND
3 5

2
ACES_51522-00801-001 ME2301DC-G_SOT23-3 KBL_ID_R 2 3 GND
1 1 2

CTP2
150P_0402_50V8J

150P_0402_50V8J
CTP3

10U 6.3V M X5R 0402

CKBL1

0.1U_0201_10V K X5R
CKBL2
ME@ 1

G
1 1

2
1

2
DTP1 [28] KB_BL_PWM RKBL2 1 2 30K_0402_1% CVILU_CF31041D0R4-10-NH
2 2 PSOT24C_SOT23-3 @
2 2 ME@
1

1
RNOKBL6 CKBL3

1
@ESD@ 10K_0402_5% 0.01U_0402_16V7K
NOKBL@ 2

ESD

2
+3VALW

1
RKBL4
100K_0402_5%

2
RKBL51 2 330_0402_1%
[28] KBL_ID

Finger Printer

1
2 2
RKBL3
10K_0402_5%
@

2
JFP1
1
2 1
3 2
4 3
5 4
6 5 9
[21] HUB_USB20_P2 6 G1
7 10

Vinafix.com
[21] HUB_USB20_N2 +FP_VCC 7 G2
+3VS RFP1 1 @ 2 0_0402_5% 8
8

Keyboard Conn
+3VALW RFP2 1 @ 2 0_0402_5%
ACES_51522-00801-001
0.1U_0201_10V K X5R
CFP1

ME@

Consumption Test
3

ESD@

JKB1
1

DFP1
L03ESDL5V0CC3-2_SOT23-3 RKB1 1 @ 2 0_0402_5% PWR_CAPS_LED 32
+5VALW 32
RKB2 1 2 470_0402_5% CAPS_LED#_R 31
[28] CAPS_LED# 31
KSO15 30
30

0.1U_0201_10V K X5R
CKB1
1 KSO10 29
ESD 29

ESD@
KSO11 28 34
KSO14 27 28 GND 33
KSO13 26 27 GND
2 KSO12 25 26
3
KSO3 24 25 3
KSO6 23 24
KSO8 22 23
KSO7 21 22
KSO4 20 21
KSO2 19 20
KSI[0..7] KSI0 18 19
KSI[0..7] [28] 18
KSO1 17
KSO[0..15] KSO5 16 17
KSO[0..15] [28] 16

LED
KSI3 15
KSI2 14 15
KSO0 13 14
KSI5 12 13
KSI4 11 12
KSO9 10 11
KSI6 9 10
KSI7 8 9
RS1 KSI1 7 8
412_0402_1% White 6 7
LED1 5 6
BATT_CHG_LED# 1 @ 2 BATT_CHG_LED#_R 2 4 5
[28] BATT_CHG_LED# 4
3
1 RS2 1 @ 2 0_0402_5% 2 3
C340_14 BATT_LOW_LED# BATT_LOW_LED#_R
+VL [28] KB_MUTLI_KEY 2
[28] BATT_LOW_LED# 1 @ 2 3 1
1
RS3 JXT_FP257H-032S10M
523_0402_1% Amber
ME@
HT-210UD5-BP5_AMBER-WHITE
C340@

White
RS1 RS1 LED2
C340@ S540@ BATT_CHG_LED#_R 2
330_0402_1% 604_0402_1%
1
S540_14 BATT_LOW_LED#_R 3
4
RS3 RS3 4
C340@ S540@
330_0402_1% 523_0402_1% Amber
HT-210UD5-BP5_AMBER-WHITE
S540@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title
KBD/FP/TP/LED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 27 of 41
A B C D E
 A B C D E

Embedded Controller
+3VALW_EC +3VL
L1
+3VL Consumption Test +3VALW_EC +3VL BLM15AX601SN1D_0402_2P
1 2 KB_MUTLI_KEY R79 1 2 10K_0402_5%
+EC_VCCA
1
R53 1 @ 2 0_0603_5% C67 +5VALW
0.1U_0201_10V6K
1 2
1 1 1 1 C238 @ 1 2 USB_EN# R54 1 2 10K_0402_5%
1 1

0.1U_0201_10V6K
C65

0.1U_0201_10V6K
C237

1000P_0402_50V7K
C68

1000P_0402_50V7K
C69
100P_0402_50V8J L2
BLM15AX601SN1D_0402_2P
2 +3VALW
2 2 @ 2 @ 2
ECAGND
+EC_VCCA TAB_SW# R277 1 2 100K_0402_5%

LID_SW# R55 1 @ 2 100K_0402_5%

EC_PCIE_WAKE# R57 1 2 10K_0402_5%

111
125
22
33
96

67
9
UEC1
ESD @ESD@

VCC_LPC
VCC
VCC
VCC

VCC

AVCC
VCC0
C71 2 1 0.1U_0201_10V6K

1 21
[27] KB_MUTLI_KEY GATEA20/GPIO00 EC_VCCST_PG/GPIO0F KBL_ID [27]
2 23
EMI [9]
[9]
[9]
KB_RST#
SERIRQ
LPC_FRAME#
3
4
5
KBRST#/GPIO01
SERIRQ
LPC_FRAME# PWM Output
BEEP#/GPIO10
EC_FAN_PWM/GPIO12
AC_OFF/GPIO13
26
27
BEEP# [20]
EC_FAN_PWM2
EC_FAN_PWM1
[26]
[26]
VCIN1_BATT_TEMP C72 1 2 100P_0402_50V8J
[9] LPC_AD3 LPC_AD3 VCIN1_AC_IN
@EMI@ @EMI@ 7 C74 1 2 100P_0402_50V8J
[9] LPC_AD2 LPC_AD2
C73 2 1 22P_0402_50V8J R58 2 1 10_0402_5% 8 63
[9] LPC_AD1 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 VCIN1_BATT_TEMP [32,33]
10 LPC & MISC 64 R59 1 @ 2 4.7K_0402_5%
[9] LPC_AD0 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 EN_5VALW [34]
65
ADP_I/AD2/GPIO3A ADP_I [33]
12 AD Input 66
[9] LPC_CLK0_EC LPC_RST# CLK_PCI_EC AD_BID/AD3/GPIO3B CUST_TEMP3 [26]
13 75
[9] LPC_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 TS_DISABLE# [14]
+3VALW_EC R60 2 @ 1 47K_0402_5% 37 76
EC_RST# AD5/GPIO43 CUST_TEMP2 [26]
20
[9] EC_SCI# EC_SCI#/GPIO0E
2 CLKRUN# 38
[9] CLKRUN# CLKRUN#/GPIO1D
C70 68
DA0/GPIO3C NOVO# [22] 3V/5VALW_PG_R
0.1U_0201_10V6K DA Output EN_DFAN1/DA1/GPIO3D 70 R61 1 @ 2 0_0402_5%
1 TP_DISABLE# [27] 3V/5VALW_PG [22,29,34,36]
KSI0 55 71
KSI1 56 KSI0/GPIO30 DA2/GPIO3E 72
KSI1/GPIO31 DA3/GPIO3F USB_EN# [22]
KSI2 57
KSI3 58 KSI2/GPIO32 83 I2C_1_SCL_R ESD@
KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A I2C_1_SDA_R I2C_1_SCL_R [8]
2 KSI4 59 84 C75 1 2 0.1U_0201_10V K X5R 2
KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B EC_SMB_CK4 I2C_1_SDA_R [8]
KSI5 60 85
KSI5/GPIO35 PSCLK2/GPIO4C EC_SMB_DA4 EC_SMB_CK4 [14,26]
KSI6 61 PS2 Interface 86

[27] KSO[0..15]
KSO[0..15]
KSI7
KSO0
KSO1
62
39
40
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
PSDAT2/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
87
88
EC_SMB_DA4
USB_CHG_ILIM_SEL
TAB_SW# [14]
[14,26]
[22] ESD +3VS
KSI[0..7] KSO2 41 KSO1/GPIO21
[27] KSI[0..7] KSO2/GPIO22
KSO3 42 97
KSO3/GPIO23 ENKBL/GPXIOA00 0.8VS_PWR_EN ENBKL [7,14] EC_SMB_CK4
KSO4 43 98 R82 1 G_SEN@2 1K_0402_5%
KSO4/GPIO24 WOL_EN/GPXIOA01 1.8VS_PWR_EN 0.8VS_PWR_EN [29] EC_SMB_DA4
KSO5 44 99 R83 1 G_SEN@2 1K_0402_5%
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109
1.8VS_PWR_EN [29] I2C_1_SCL_R R275 1 @ 2 1K_0402_5%
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH1 [32] I2C_1_SDA_R R276 1 @ 2 1K_0402_5%
KSO8 47 KSO7/GPIO27
KSO8/GPIO28 SPI Device Interface
KSO9 48 119 C254 @ 1 2 150P_0402_50V8J
KSO10 49 KSO9/GPIO29 MISO/GPIO5B 120 C255 @ 1 2 150P_0402_50V8J
KSO11 50 KSO10/GPIO2A MOSI/GPIO5C 126

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KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
KSO12 51 128
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A
KSO14 53 KSO13/GPIO2D
+3VL KSO15 54 KSO14/GPIO2E 73
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 CUST_TEMP1 [26]
81 74
KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 SENSOR_EC_INT# [8]
82 89
EC_SMB_DA1 KSO17/GPIO49 GPIO50 EC_MUTE# [20]
R62 1 2 2.2K_0402_5% 90
R63 1 2 2.2K_0402_5% EC_SMB_CK1
[32,33] EC_SMB_CK1
EC_SMB_CK1
EC_SMB_DA1
77
78 EC_SMB_CLK1/GPIO44 GPIO
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
91
92
93
BATT_CHG_LED#
CAPS_LED#
PWR_LED#
[27]
[22]
[27]
ESD
[32,33] EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# [27]
79 95 @ESD@
[7,26] EC_SMB_CK2 EC_SMB_DA2 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 SYSON [35,36] KB_RST#
80 121 C76 1 2 0.1U_0201_10V6K
+3VS [7,26] EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 VR_ON [37,38]
127
DPWROK_EC/GPIO59 APU_RST#_EC [7]
SM Bus ESD@
LPC_RST# C77 1 2 100P_0402_50V8J
R64 2 1 10K_0402_5% EC_FAN_SPEED1 6 100
EC_FAN_SPEED2 [8] PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 3V/5VALW_PG_R EC_RSMRST# [8]
R80 2 1 10K_0402_5% 14 101 ESD@
EC_SMB_CK2 [22] USB_CHG_CTL1 GPIO07 GPXIOA04 SYS_PWRGD_EC
R273 1 2 1K_0402_5% 15 102 C78 1 2 100P_0402_50V8J
EC_SMB_DA2 [10] EC_CLEAR_CMOS# GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 VCOUT1_PROCHOT#
R274 1 2 1K_0402_5% 16 103
[22] USB_CHG_CTL3 GPIO0A VCOUT1_PROCHOT#/GPXIOA06
17 104 ESD@
[22] USB_CHG_EN GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 VCOUT0_MAIN_PWR_ON [34] EC_RSMRST#
18 105 C79 1 2 100P_0402_50V8J
+3VL [22] USB_CHG_CTL2 GPIO0C BKOFF#/GPXIOA08 BKOFF# [14]
19 GPIO GPO 106
3 [22] USB_CHG_STATUS# AC_PRESENT/GPIO0D GPXIOA09 TYPEC_LIMIT_CTL1 [24] 3
25 107 ESD@
[27] KB_BL_PWM EC_FAN_SPEED2 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 EC_PCIE_WAKE# TYPEC_LIMIT_CTL2 [24]
28 108 SYSON C80 1 2 0.1U_0201_10V6K
[26] EC_FAN_SPEED2 EC_FAN_SPEED1 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11
R65 1 2 100K_0402_5% NOVO# 29
[26] EC_FAN_SPEED1 FANFB1/GPIO15
R66 1 2 100K_0402_5% ON/OFF# 30 @ESD@
[17] EC_TX EC_TX/GPIO16
31 110 ON/OFF# C81 1 2 100P_0402_50V8J
[17] EC_RX SYS_PWRGD_EC EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 VCIN1_AC_IN [33]
32 112
1.8VS_PWR_EN [8] SYS_PWRGD_EC PWR_BATT_LOW# PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON [34]
R67 1 @ 2 100K_0402_5% 34 114 @ESD@
[22] PWR_BATT_LOW# EC_THERMTRIP# SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 ON/OFF# [22,29] LID_SW#
R68 1 2 100K_0402_5% SUSP# 36 GPI 115 C82 2 1 100P_0402_50V8J
[7] EC_THERMTRIP# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# [26]
R69 1 2 100K_0402_5% SYSON 116
0.8VS_PWR_EN SUSP#/GPXIOD05 SUSP# [29,35]
R70 1 @ 2 100K_0402_5% 117
GPXIOD06 118
122 PECI/GPXIOD07
[8] PBTN_OUT# PBTN_OUT#/GPIO5D +VCC_IO2
123 124 R71 1 @ 2 0_0402_5% +3VALW_EC
[8,33,36] PM_SLP_S5# PM_SLP_S4#/GPIO5E V18R/VCC_IO2
AGND
GND
GND
GND
GND
GND

4.7U_0402_6.3V6M
1
C84
KB9022QD_LQFP128_14X14
11
24
35
94
113

69

2
20mil

ECAGND
VCOUT1_PROCHOT# R270 1 @ 2 0_0402_5%

R271 1 @ 2 0_0402_5%
[33,38] PROCHOT# H_PROCHOT# [7]

1
@
C239
100P_0402_50V8J
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC_ENE_KB9022
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 28 of 41
A B C D E
 A B C D E

DC to DC Discharge Circuit 1

For +1.8VALW Discharge For +0.6VS Discharge

+5VALW +5VS
+VL J2
2 1
2 1 +5VALW +1.8VALW +5VALW +0.6VS

10U_0402_6.3V6M
C90

0.1U_0201_10V K X5R
C91
JUMP_43X79 1 1
+5VALW to +5VS
0.1U_0201_10V K X5R
C88

10U_0402_6.3V6M
C89

1 1 @

1
@
@ U10 2 2 R74 R75
2 2 1 14 +5VALW_5VS @ @ 22_0603_1% @ R77 @ R78
VIN1 VOUT1 100K_0402_1%
2 13 100K_0402_5% 470_0402_5%
VIN1 VOUT1

1 2
3 12 C93 1 2 2200P_0402_25V7K
ON1 CT1

6
4 11 D D
VBIAS GND +3VS 1.8VALW_PWR_EN# 2 SUSP 2 Q7
5 10 C94 1 2 1000P_0402_50V7K G G 2N7002K_SOT23-3
[28,35] SUSP# ON2 CT2

1
+3VALW J3 @ S @
6 9 +3VALW_3VS 2 1 S D

3
VIN2 VOUT2 2 1

3
7 8 D Q5A SUSP# 2 Q8
VIN2 VOUT2

10U_0402_6.3V6M
C97

0.1U_0201_10V K X5R
C98
JUMP_43X79 1 1 5 2N7002KDW_SOT363-6 G 2N7002K_SOT23-3
[22,28,34,36] 3V/5VALW_PG
0.1U_0201_10V K X5R
C95

10U_0402_6.3V6M
C96

1 1 15 @ G S @
GPAD @

3
EM5209VF_DFN14_3X2 @ S

4
@ 2 2 Q5B
2 2 2N7002KDW_SOT363-6

+3VALW to +3VS

2 2

+0.8VALW
+5VALW Max:4.0A +0.8VS
J6
2 1
2 1

10U_0402_6.3V6M
C243

0.1U_0201_10V K X5R
C248
JUMP_43X79 1 1
+0.8VALW to +0.8VS
0.1U_0201_10V K X5R
C246

10U_0402_6.3V6M
C240

1 1 @
@
@ U20 2 2
2 2 1 14 +0.8VALW_0.8VS
2 VIN1
VIN1
VOUT1
VOUT1
13 CPU WLAN SSD2 SSD1 FAN

Vinafix.com
3 12 C245 1 2 1000P_0402_50V7K
[28] 0.8VS_PWR_EN ON1 CT1
4 11 H1 H2 H3 H6 H7 H16 H17 H9 H10 H11 H12 H8 H13 H14
VBIAS GND +1.8VS HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
5 10 C244 1 2 1000P_0402_50V7K
+1.8VALW [28] 1.8VS_PWR_EN ON2 CT2 J5
6 9 +1.8VALW_1.8VS 2 1

1
7 VIN2 VOUT2 8 2 1
VIN2 VOUT2
10U_0402_6.3V6M
C242

0.1U_0201_10V K X5R
C249
JUMP_43X79 1 1
0.1U_0201_10V K X5R
C247

10U_0402_6.3V6M
C241

1 1 15 @
GPAD H_2P9 H_2P9 H_2P9 H_3P2 H_3P2 H_3P3 H_3P3 H_2P5 H_2P5N H_2P5 H_3P7 H_2P8 H_2P5X2P8N H_2P5X2P8
EM5209VF_DFN14_3X2 @
@ 2 2
2 2
Max:2.0A
+1.8VALW to +1.8VS DDR Shielding Clip LASER BARCODE ON/OFF# SHORT PADS
3 Larger CODE1 @ CODE2 @ @
3

CLIP10 CLIP11 JP2 2 1 ON/OFF#

ON/OFF# [22,28]
HOLEA HOLEA
SHORT PADS

+1.8VS
RF reserve @ @

1
BARCODE_8X8 BARCODE_12X4
@
JP3 2 1 ON/OFF#

Smaller
10U 6.3V M X5R 0402
C250

10U 6.3V M X5R 0402

C251

10U 6.3V M X5R 0402

C252

10U 6.3V M X5R 0402

C253

1 1 1 1 CODE3 @ CODE4 @ SHORT PADS

CLIP1 CLIP2 CLIP3 CLIP4 CLIP5 CLIP6 CLIP7 CLIP8 CLIP12

RF@ RF@ RF@ RF@ HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
2 2 2 2

@ @ @ @ @ @ @ @ @ BARCODE_20X4 BARCODE_10X10

1
FD1 FD2 FD3 FD4

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 29 of 41
A B C D E
 A B C D E

1 1

2 2

Vinafix.com

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 30 of 41
A B C D E
 A B C D E

1 1

ACES_50278-00401-001
6
G2 5
G1 4 EMI@ PL101
4 3
3 2 PF101
5A_Z80_0805_2P
1 2
+19V_VIN
2 1 7A_32VDC_0437007.WRML
1 +19V_APDIN
APDIN 1 2
JDCIN1
CONN@ EMI@ PL102

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
1 2
5A_Z80_0805_2P

1
EMI@ PC101

EMI@ PC102

EMI@ PC103

EMI@ PC104
2

2
2 2

Vinafix.com

2
+CHGRTC
@ PR107
45.3K_0603_1% PR108
0_0603_5%

1
1 2
PD101 +3VL
S SCH DIO BAS40CW SOT-323
3 2 +RTCBATT_R 3
+RTCBATT 1
3

4 4

Security Classification Compal Secret Data

Issued Date 2018/05/04 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- DCIN / Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2018 Sheet 31 of 41
A B C D E
 A B C D E

1 1

VMB2 +8.4V_VMB EMI@ PL201

Conn@ PF201 1 2
JBAT1 F1206HB12V024TM 12A 24V UL FAST 5A_Z80_0805_2P
1 1 2
1 +12.6V_BATT+
2
2 3 EC_SMCA EMI@ PL202
3 4 EC_SMDA 1 2
4 5 5A_Z80_0805_2P
5 6
6 +RTCBATT_R

1
7
7

1
100_0402_1%

100_0402_1%
8
8 9 PC201 EMI@ PC202 EMI@
G1 10 1000P_0402_50V7K 0.01U_0402_25V7K

2
G2

PR201

PR202
11

2
G3 12
G4

ACES_60757-00802-001 +EC_VCCA
2 EC_SMB_CK1 [28,33] 2

16.5K_0402_1%
EC_SMB_DA1 [28,33]

1
PR206
PR203 1 2 200K_0402_1% +3VL
PR204 1 2 200K_0402_1% +3VALW
@

2
PR205 1 2 10K_0402_5%
VCIN1_BATT_TEMP [28,33] [28] VCIN0_PH1

1
PH201
100K +-1% 0402 B25/50 4250K

Vinafix.com

2
3 3
ECAGND

PH201 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C

4 4

Security Classification Compal Secret Data

Issued Date 2018/05/04 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2018 Sheet 32 of 41
A B C D E
 A B C D E

Module model information

ISL95520A_Hybrid_Boost_V2.mdd

Protection for reverse input

Vgs = 20V
Vds = 60V
1 1
Id = 250mA

1
D
2 PQ707
G 2N7002KW_SOT323-3

3
max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W B+
Rds(on) = 15.8mohm max CSR rating: 1W
1 2 1 2
Vgs = 20V VCSIP-VCSIN spec < 81mV
PR738 PR737 Vds = 30V
1M_0402_1% 3M_0402_5% ID = 10.5A (Ta=70C)
PQ740
EMB04N03H_EDFN5X6-8-5 +19V_P1
1 PQ712 PR703
Need check the SOA for inrush AON7506_DFN3X3-8-5 +19V_P2 +19VB_CHG
2 0.01_1206_1%
PJ101 @
5 3 1
2 1 4 1 2
+19V_VIN 1 2

PC765 @EMI@

EMI@
3 5

2200P_0402_25V7K
2 3 JUMP_43X79

10U_0603_25V6M

10U_0603_25V6M

0.1U_0402_25V7K
1

1
CSIN_CHG_R

PC760

PC762
CSIP_CHG_R
4

PC705
2

2
1
2_0402_5%
1

PR740
0_0402_5%
PR772
1
392K_0402_1%
PR729

2
ASGATE_CHG_R @ PC11279

2
PC747 1 2
2

PC11280 PQ705

4.02K_0402_1%

4.02K_0402_1%
2 1 2 2
2 1 0.1U_0402_25V6 AON7506_DFN3X3-8-5
@ 1
0.1U_0402_25V6

1
0.1U_0402_25V6 2
@ 5 3

PR745
PR729 and PR732 are ACDET set t i ng base on your proj ect to set.

PC750 0.22U_0603_25V7K
100_0402_1%

4
PR762

PR763
1 2 +12.6V_BATT+ Rds(on) = 32mohm max
Vgs = 20V
Vds = 30V
1

2200P_0402_50V7K

CMSRC_CHG
48.7K_0402_1%

ID = 8A (Ta=70C) @ PC779
1
PR732

PC715

1
Vinafix.com
ASGATE_CHG 1 2
2

BGATE_CHG
2

OPCN_CHG 2
0.1U_0402_25V7K

CSIN_CHG
CSIP_CHG

OPCP_CHG

VBAT_CHG
0x3CH <BIT9> PSYS current gain
Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 10mΩ and Rs2 = 10 m
Ω Rds(on) = 32mohm max
1 VDD_CHG

BIT0 = 1.14uA/W Vgs = 20V

BIT1 = 0.285uA/W Vds = 30V

5
=========================================================
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ PU703
ID = 8A (Ta=70C) PQ704
100K_0402_1%

support Turbo boost : 2200P Support max charge 3.5A

32

31

30

29

28

27

26

25
BIT0 = 2.28uA/W no support Turbo boost : 0.1u S IC ISL88739AHRZ-T QFN 32P CHARGER
BIT1 = 0.57uA/W AON7408L_DFN8-5 Power loss: 0.245W
PR741

7X7X3

CSIP

ASGATE

QPCP

VBAT

BGATE
CSIN

CMSRC

OPCN
PC721 4 CSR rating: 1W
PR771 @ 0_0603_5% 0.47U_0603_25V7K
Isat: 6.5A VCSPP-VCSON spec < 81mV
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R 1 2 DCR: 28mohm
2

ACIN BOOT
Ipsys = KPSYS  x  T
( VAD P x IAD P + VBA T x IBA ) PL700 PR765
R_Psys = 1.2V / Ipsys 2 23 UG_CHG 0.01_1206_1%

3
2
1
[28] VCIN1_AC_IN ACOK UGATE
KPSYS = 1.14uA/W @ 4.7UH_5.5A_20%_7X7X3_M +12.6V_BATT+
20_0402_5%
1
158K_0402_1%

PR769 1 3 22 LX_CHG 1 2 +17.4V_BATT_CHG 1 4

adapter wattage = 45W [28,32] EC_SMB_DA1 SDA PHASE
PR731

Battery wattage = 40Wh @

PR770 1 20_0402_5% LG_CHG

4.7_1206_5%
4 21 2 3
Ipsys = 1.14 x (45+40) = 96.9uA [28,32] EC_SMB_CK1 SCL LGATE

RF@ PR766
3 @ 3
R_Psys = 1.2V / 96.9uA = 12.3K-ohm. 20_0402_5%

5
PR777 1 5 20 VDDP_CHG
[28,38] PROCHOT#
2

===================================== PROCHOT# VDDP

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
PQ706

1
adapter wattage = 65W 2 1K_0402_1%AMON_ISL95520 6 VDD_CHG

PC775

PC776

PC761
PR780 1 19 1 2 AON7506_DFN3X3-8-5
Battery wattage = 40Wh [28] ADP_I AMON VDD

2
Ipsys = 1.14 x (65+40) = 119.7uA 7 18 PR760 4.7_0402_5%

2
BMON DCIN

1
R_Psys = 1.2V / 96.9uA = 10K-ohm. 4

BATGONE
Close to EC. 8 17 PC768 PC769
PSYS NTC

1
1U_0402_16V6K 1U_0402_16V6K
CCLIM

2
ACLIM
COMP
PROG
AGND

CSON

CSOP
FSET PR757 PC767 RF@

1
10K_0402_1%

100K_0402_1% 680P_0402_50V7K

3
2
1

2
1

1
PR727

PC748
PD703
0.1U_0402_25V6
33

10

11

12

13

14

15

16
**Design Notes** Follow adapter and PR743 10_1206_5% 3
+19V_VIN
2

@ 1 2 1
For 45W/65W /90W system, 2S/3S/4S battery battery wattage in

3
Close to 2 PQ710
Vsys current source. BA
2

Maximum Charging current 3.5A

2
EC.
FSET_CHG

PC757
1U_0603_25V6K
Base on CPU Core VR design. VF = 0.38V
Maximum Battery discharge power 55W The resistor is pop on CPU VR schematic. S SCH DIO BAS40CW SOT-323
LMUN5113T1G_SOT323-3
1

#Register Setting 2

1
PR778
1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function
2. Disable turbo when AC only
10K_0402_1% A31 connect to BA
VDD=5V VDD_CHG Other team connect to bat t c onn
#Circuit Design
2

1
1. ACLIM and CCLIM are devider voltage control.

1
CCLIM_CHG PQ711
2. Use 7X7 choke and 3X3 H/L side MOSFET
200K_0402_1%

LTC015EUBFS8TL_UMT3F
1

Charge current 3A ACLIM_CHG

[8,28,36] PM_SLP_S5#
PR749

PR750 2
Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W) PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R
200K_0402_1%

BA
Power density : 0.61 (23X16)
#Protect function COMP_CHG PR742 2_0402_5%
2

1
100_0402_1%

1. ACOVP : VCC voltage > 24V

3
@ PR779 Fs=729KHZ ~ +/- 15% PC708
2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default). BA
1

0_0402_5%

76.8K_0402_1% 0.1U_0402_25V6

2
3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).
PR755
PR754

1 2
150K_0402_1%
1

560P_0402_50V7K

4. CHGOCP : based on charge current setting CSON_CHG 1 2 CSON_CHG_R

1
PR753

5. BATOVP : 4.6V/Cell
PC751

@ PQ741 @ PR776 0_0402_5% @

4 4
2

6. BATLOWV : No.
1

D
76.8K_0402_1%

2
1

7. TSHUT : 150C VCIN1_AC_IN

2
0.033U_0402_25V7K

PR752
2

G 348K_0402_1% VCIN1_BATT_TEMP [28,32]

1
PR751

PC752

S
3

L2N7002WT1G_SC70-3 BATGONE(BATT_TEMP) For A31 only.

2

logic high: above 2.4V Turn off Charger IC on battery only.

2

Hybrid boost power mode logic low: under 0.8V Depend on customer design for
Cell = 2s system power consumption.
(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 20mΩ and Rs2 = 10mΩ).
CC_LIM = VccLIM / 64 x Rs2
=============================================================
Security Classification Compal Secret Data Compal Electronics, Inc.
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ ). Issued Date 2018/05/04 2018/05/25 Title
CC_LIM = VccLIM / 32 x Rs2
Deciphered Date
PWR_CHARGER
============================================================= Battery current limimed by CCLIm ~ 3.89A.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AC_LIM = Vac_LIM / 32 x Rs1 Adapter current limimed by ACLIm ~ 4.33A. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
(PR779 and PQ741 are for change ACLIm when AC in) MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2018 Sheet 33 of 41
A B C D E
 A B C D E

B+
1 1
EMI@ PL401

2200P_0402_50V7K
1 2 +19VB_3V

10U_0603_25V6M
@EMI@ PC403

EMI@ PC404
0.1U_0402_25V6
5A_Z80_0805_2P

10U_0603_25V6M

1
1

PC405
PC11274

2
2
PU401 @ PR401 PC401
@ 0_0402_5% 0.1U_0402_25V7K

1
SY8386BRHC_QFN16_2P5X2P5
BST_3V 1 2 BST_3V_R 1 2 Use 7x7x3 size when the layout space is enough.

IN3

IN2

IN1

BS
PL402
LX_3V 5 17
LX EP 1.5UH_6A_20%_5X5X3_M
+3VALWP
LX_3V 1 4
+3VL LX2
16
6 2 3
GND

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
4.7_1206_5%
15

1
PR405
RF@
LX1

PC407

PC408

PC409

PC410
7
PG 14

2
PR406 GND1
100K_0402_5%

3V_SN2
2 8
EN2 LDO
13 +3VLP

680P_0402_50V7K
[22,28,29,36] 3V/5VALW_PG

TEST
OUT
PC411

EN1

1
FF

PC412
RF@
4.7U_0603_6.3V6M

2
ENLDO_3V5V

10

11

12

2
2 2
PC402 PR403
1000P_0402_50V7K 1K_0402_1%
5V_3V_EN 3V_FB 1 2 3V_FB_1 1 2

@ PJ401
1 2
+3VALWP 1 2 +3VALW
JUMP_43X118
Module model information
SY8286C_V3_single.mdd @ PJP402
SY8286C_V3_dual.mdd

Vinafix.com
JUMP_43X39
1 2
keep short pad, +3VLP 1 2 +3VL
2 Cell battery : Cin=10uF*2pcs snubber is for EMI only.
3 Cell ~ 4 Cell battery : Cin=10uF*1pcs
B+ +19VB_5V
@ PR408 PC418
EMI@ PL403 PU402 IC SY8288CRAC QFN 20P PWM 0_0402_5% 0.1U_0402_25V7K
1 2 +19VB_5V BST_5V1 2 BST_5V_R 1 2
5A_Z80_0805_2P
5

1
IN

IN

IN

IN

BS
PL404
2200P_0402_50V7K

LX_5V 6
0.1U_0402_25V6

20
LX LX 2.2UH_7.8A_20%_7X7X3_M
LX_5V
10U_0603_25V6M

10U_0603_25V6M

7 19 1 2 +5VALWP
GND LX
1

1
PC414

PC415

EMI@ PC416

@EMI@ PC417

8 18
GND GND PC419

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
3 3
2

1
9 17 VCC_5V 1 2
PG VCC

4.7_1206_5%
PR409

PC420

PC421

PC422

PC423

PC424

PC425
PR402
499K_0402_1% 10 16

RF@

2
1 2 ENLDO_3V5V NC NC 2.2U_0402_6.3V6M
B+
OUT

LDO
EN2

EN1

21 @
FF

GND
1

2
1

PR404 +3VL
11

12

13

14

15

150K_0402_1% PC429
+5VLP

15V_SN
1U_0201_6.3V6M
4.7U_0603_6.3V6M
2

680P_0402_50V7K
5V LDO 150mA~300mA
100K_0402_5%
2

1
1

3V/5VALW_PG
PC427
PR2258

PC426
RF@
ENLDO_3V5V
2

@ PR2260

2
0_0402_5% Vout is 4.998V~5.202V
2

5V_3V_EN 1 2 5V_EN

PR2261 TDC=6A Iocp=10A

100K_0402_5%

PC413 PR407
1

0_0402_5% 1000P_0402_50V7K 1K_0402_1%

@ PR2259

1 2 5V_FB 1 2 5V_FB_1 1 2
[28] EN_5VALW
4.7U_0402_6.3V6M

2
1

@ PC11290

PR410 Fsw : 600K Hz

2.2K_0402_5% @ PJ403
1 2
2

1 2
[28] EC_ON EN1 and EN2 dont't be floating. +5VALWP 1 2 +5VALW
EN :H>0.8V ; L<0.4V JUMP_43X118
1 2
4 [28] VCOUT0_MAIN_PWR_ON @ PR411 @ PJP404 4
0_0402_5% JUMP_43X39
1 2
+5VLP 1 2 +VL
5V_3V_EN
1M_0402_1%

4.7U_0402_6.3V6M
1

Compal Secret Data Compal Electronics, Inc.

1

Security Classification
PR412

PC428

Issued Date 2018/05/04 Deciphered Date 2018/05/25 Title

+3VALW/+5VALW
2
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2018 Sheet 34 of 41
A B C D E
 A B C D E

Module model information

1 RT8207P_single_V3.mdd For Single layer 1

RT8207P_dual_V3.mdd For Dual layer

Pin19 need pull separate from +1.35VP.

If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
you can change from +1.35VP to +1.35VS. TDC 0.7A
B+ EMI@ PL501
Peak Current 1A
1 2 +12.6VB_DDR PR501
5A_Z80_0805_2P 2.2_0603_5%

2200P_0402_50V7K
BST_DDR_R BST_DDR

0.1U_0402_25V6
1 2

10U_0603_25V6M

10U_0603_25V6M
+1.2VP
1

1
PC503

PC504
PC501

PC502
UG_DDR +0.6VSP
2

2
@EMI@

EMI@

10U_0603_6.3V6M

10U_0603_6.3V6M
LX_DDR

1
PC505

PC506

PC507
16

17

18

19

20
0.1U_0402_25V7K

2
2 PU501 2

2
PQ501

PHASE

UGATE

BOOT

VLDOIN

VTT
21
AON7408L_DFN8-5 PAD
4 LG_DDR 15 1
LGATE VTTGND

PL502 14 2
1UH_11A_20%_7X7X3_M PR502 PGND VTTSNS

1
2
3
12.7K_0402_1%
1 4 1 2 CS_DDR 13 3
+1.2VP PC508 CS RT8207PGQW_WQFN20_3X3 GND

Vinafix.com
1

2 3 1U_0402_10V6K

5
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1 2 12 4 VTTREF_DDR
RF@ PR503 30MA_30V_0.5UA_0.4V_SOD323-2 PD501 VDDP VTTREF
1

1
PC509

PC510

PC511

PC512

PC513

PC514

4.7_1206_5% PR504 2 1
5.1_0603_5% 11 5
+1.2VP
1 2

VDD VDDQ

1
1 2 VDD_DDR

PGOOD
+5VALW
2

4 PC515
+5VALW PR505

TON
1
RF@ PC517 0.033U_0402_16V7K

FB
S5

S3

2
680P_0402_50V7K PQ502 PC516 1 2
2

1U_0402_10V6K 2.2_0603_5%

10

6
1
2
3

EN_0.675VSP
EN_DDR
AON7506_DFN3X3-8-5

FB_DDR
TON_DDR
PR506
1 2 +1.2VP
PR507 470K_0402_1%
3 +12.6VB_DDR1 2 3
6.04K_0402_1%

1
@ PR508
0_0402_5%
Choke: 7x7x3 [28,36] SYSON
1 2 PR509
Rdc=6.7mohm(Typ), 7.4mohm(Max) 10K_0402_1%

2
1
Mode Level +0.675VSP VTTREF_1.35V @ PC518
Switching Frequency:540kHz 0.1U_0402_10V7K
S5 L off off Ipeak=8A

2
S3 L off on Iocp~9.6A
S0 H on on OVP: 113%~120% @ PR510
VFB=0.75V, Vout=1.3545V 0_0402_5%
Note: S3 - sleep ; S5 - power off 1 2 @ PJ501
[28,29] SUSP# +1.2VP 1 2 +1.2V
1 2
JUMP_43X118

1
@ PC519
0.1U_0402_10V7K

2
PJ503 @
1 2
+0.6VSP 1 2 +0.6VS
JUMP_43X39

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date Deciphered Date 2018/05/25 Title
2018/05/04
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.2VP/0.6VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2018 Sheet 35 of 41
A B C D E
 A B C D E

+3VALW @ PR2102
0_0402_5%
+1.8VSP_ON 1 2
3V/5VALW_PG [22,28,29,34]

0.1U_0402_16V7K
PC2101

1
PR2101

1
1 100K_0402_5% PR2103 1
1M_0402_5%
@
Note:Iload(max)=2.5A

2
[37] 1.8VALW_PG PU2101

2
9
1 PGND 8
FB SGND
2 7
@ PJ801 PG EN PL2101
+3VALW 1 2 3 6 LX_1.8V 1 2
1 2 IN LX 1UH_2.8A_30%_4X4X2_F +1.8VALWP

68P_0402_50V8J
4 5
JUMP_43X79 PGND NC

1
4.7_0603_5%

1
PR2104

PC2104
2

1
22U_0603_6.3V6M

22U_0603_6.3V6M
PR2105
SY8003ADFC_DFN8_2X2 Rup

PC2105

PC2106
20K_0402_1%

RF@

2
22U_0603_6.3V6M

2
FB_1.8V

PC2102

1
1

680P_0402_50V7K
FB=0.6V

RF@ PC2103
Note:Iload(max)=3A PR2106
10K_0402_1%
Rdown @
PJ802

2
+1.8VALWP 1 2 +1.8VALW
1 2

2
JUMP_43X79
2 2

Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)

+3VALW +5VALW

Vinafix.com
1

1 PC2006
1

1U_0402_6.3V6K
JUMP_43X79 @
2

PJ803
2

Vout=0.8V* (1+Rup/Rdown)
2

PU2002
1

PC2008 G9661MF11U_SO8
4.7U_0603_6.3V6K 4 5
3 3 VPP NC 6 3
+2.5VP
2

PR2223 1 @ 2 0_0402_5% 2 VIN VO 7

GND

[28,35] SYSON VEN ADJ

3.4K_0402_1%

0.01U_0402_25V7K
1 8
@ POK GND

1
PR2003 1 2 0_0402_5%
[8,28,33] PM_SLP_S5#

PR2004

PC2005

22U_0603_6.3V6M
9

Rup

2
1

1
0.1U_0402_25V6

2
PC2001

PC2010
PR2008
47K_0402_5% PJ804 @
2

2
1 2
+2.5VP +2.5V
2

1 2

1.6K_0402_1%
JUMP_43X79

PR2002
Rdown

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/05/04 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VALW/+2.5V_G9661
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G241P
Date: Monday, December 17, 2018 Sheet 36 of 41
A B C D E
 A B C D E

Module model information

SY8286_V2_single.mdd
SY8286_V2_dual.mdd

1 1

+19VB_1V
keep short pad,
snubber is for EMI only.
EMI@ PL601
5A_Z80_0805_2P
+19VB_1V
B+ 1 2 @ PR606
10U_0603_25V6M

PC603
0.1U_0402_25V6

0_0603_5%
2200P_0402_50V7K

2 0.1U_0402_25V7K 2
1

BST_1V BST_1V_R
EMI@ PC604

@EMI@ PC605

1 2 1 2
PC606
2

PU601 RF@ PR605 RF@ PC602

4.7_1206_5% 680P_0402_50V7K

1
SY8386RHC_QFN16_2P5X2P5 1 2 SNUB_1V 1 2

IN3

IN2

IN1

BS
+3VALW
Use 7x7x3 size when the layout space is enough.
LX_1V 5 17
LX EP
1

Confirm HW side
PR611
PL602 +0.8VALWP

Vinafix.com
@ 100K_0402_5% 16 LX_1V 1 2
6 LX2
GND

330P_0402_50V7K

PC11282@RF@
1UH_6.6A_20%_5X5X3_M

10P_0402_25V8J
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
2

10_0402_1%
15
LX1

1
PC608

PC609

PC610

PC611

PC612
PR2221

PC11225

PC11226
7
PG 14

2
GND1

2
8 13 LDO_3V
TEST VCC

1
11K_0402_1%
R1

1
@ PR619

PR608
ILMT

BYP PC613 PR612 1 2

EN

FB

VR_ON [28,38]
2.2U_0402_6.3V6M 1K_0402_1% 0_0402_5%

2
FB=0.6V
9

10

11

12

2
Vout=0.6V* (1+R1/R2) @ PR2222
+3VALW =0.6*(1+(6.8/20)) 1 2 1 3
APU_VDDP_RUN_FB_H [7]

1
0_0402_5%
Vout=0.8V PR610 PQ601
3 @ PR603 R2 20K_0402_1% LSK3541G1ET2L_VMT3 3
ILMT_1V

0_0402_5%
@ PR621

2
1 2 EN_1V PC614
[36] 1.8VALW_PG 1 2
1U_0402_6.3V6K APU_VDDP_RUN_FB_L [7]
2

0_0402_5%
1

@ PC601
PR601 0.1U_0402_25V6
1M_0402_1% +3VALW
2
2

FB_1V
@ PR607
0_0402_5%
2

@ PJ601
1

JUMP_43X118
EN :H>0.8V ; L<0.4V @ PR609 1 2
+0.8VALWP 1 2 +0.8VALW
0_0402_5%
EN pin don't floating
2

If have pull down resistor at HW side,

please delete PR601.

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high.

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/05/04 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.0VALW_SY8286RAC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2018 Sheet 37 of 41
A B C D E
 A B C D E

[7] APU_VDDCR_SEN APU_B+ B+

[7] APU_VDD_RUN_FB_L
+APU_CORE
@ PC11235
0.1U_0402_25V6
2 1
APU_B+ EMI@ PL2104
1 2
5A_Z80_0805_2P

1
10_0402_5%

10_0402_5%
2
@ PR2233 @ PR2231

PR2234

PR2229

0.1U_0402_25V6

10U_0603_25V6M

10U_0603_25V6M
0_0402_5%

2200P_0402_50V7K
@EMI@ PC11262

@EMI@ PC11248
0_0402_5%
UG1_CPU 1 1 1 1

PC11239

PC11230

33U_D1_25VM_R6M

33U_D1_25VM_R6M

33U_25V_NC_6.3X4.5
1

1
+ + + + EMI@ PL2105

PC11278

PC11277

PC11266

PC11265
33U_25V_NC_6.3X4.5
2

2
1 2

1
5A_Z80_0805_2P

2
PR2225 PC11243 PQ1004 2 2 2 2
2.2_0603_5% 0.22U_0603_25V7K
AON6962_DFN5X6D-8-7

2
1 BST1_CPU1 2 BST1_CPU_R
1 2 1

G1

D1
PL2103 @C340@
@C340@
0.24UH_22A_+-20%_ 7X7X3_M @S540@ S540@
LX1_CPU 7 1 4
@ PC11237 D2/S1
+APU_CORE
ISEN1P_CPU_R

4.7_1206_5%
PR2240 RF@
0.1U_0402_25V6 2 3
LL(Rdroop)=0.7m 2 1

G2

S2

S2

S2

1
6

3
1 2 1 2
PR2251 PR2237 LG1_CPU
68K_0402_1% 10K_0402_1% PR2243 PC11256

1 2
2 1 2 1 SNB_APU1 1.1K_0603_1% 0.47U_0402_25V6K
APU_CORE

680P_0402_50V7K
RF@ PC11234
TDC 35A(1H1L)

0.1U_0402_25V6

0.1U_0402_25V6
Peak current 45A

2
1

1
PC11261

PC11249
PC11253
2 1 1 2 OCP current > 55A

2
68P_0402_50V8J PC11228
220P_0402_50V8J @ @ @ PR2238
1.1K_0402_1%
FSW=400kHz
VREF_APU
APU_CORE_SEN_H_R
ISEN1P_CPU 1 2 DCR 1.19mohm +/-5%
TYP MAX
RGND_RT3662
PR1062
1_0402_1%
H/S Rds(on) :6.8mohm , 8.6mohm
PC11238 ISEN1N_CPU 1 2 ISEN1N_CPU_R L/S Rds(on) :2.0mohm , 2.5mohm
0.1U_0402_25V6
9/26
1 2 +3VS Modify for stardust test result PR1063
34K_0402_1%

2 1 1.1K_0402_1%
2

PR2232 100K_0402_5% ISEN2P_CPU 1 2

0_0402_5%

0_0402_5%
@ PR2245

@ PR2248
PR2250
1

COMP_CPU
ISEN1N_CPU

ISEN1P_CPU

ISEN2P_CPU

FB_CPU

BST2_CPU

UG2_CPU
261K_0402_1%
3.92K_0402_1%

66.5K_0402_1%
2

+3VS
PR2247

PR2244

PR2226

UG2_CPU

2
APU_B+
PU2102

10
1

1
@ PR2246 RT3662ACGQW_WQFN40_5X5
SET_APU 4.7K_0402_1%

ISEN1N

VSEN

RGND

PGOOD
ISEN1P

ISEN2P

FB

COMP

BOOT2

UGATE2

0.1U_0402_25V6
10U_0603_25V6M

10U_0603_25V6M
1

2200P_0402_50V7K
PC11245

PC11263
TSEN_APU_R TSEN_APU

PC11246

PC11240
2 1 2 41 PC11241
0.22U_0603_25V7K 2
GND

1
PR2242 11 BST2_CPU1 2 BST2_CPU_R1 2 PQ1002
[28,33] PROCHOT# VRHOT_L LX2_CPU

@EMI@

@EMI@
60.4K_0402_1% Near APU MOS 40
PHASE2 AON6962_DFN5X6D-8-7

2
TSEN_APU 12 PR2235 2.2_0603_5%

2
2 1 TSEN 39 LG2_CPU

G1

D1
2 1 1 2 SET_APU 13 LGATE2
PH1003 SET1 38 BST1_CPU
100K_0402_1%_B25/50 4250K PC11254 PR2241 IMON_APU 14 BOOT1 LX2_CPU 7
0.47U_0402_6.3V6K 3.9_0402_1% IMON 37 UG1_CPU D2/S1
TSEN_NB_R 1 2 TSEN_NB 15 UGATE1 PL2102
VREF_APU VREF_PINSET
PR2227 36 LX1_CPU 0.24UH_22A_+-20%_ 7X7X3_M

G2

S2

S2

S2
60.4K_0402_1% IMON_NB 16 PHASE1 1 4
Near CORE_NB MOS IMON_NB PR2228 @
LG1_CPU
24K_0402_1%

35
6.65K_0402_1%

33.2K_0402_1%

+APU_CORE

3
LGATE1
2

VCC_CPU 0_0603_5%

RF@ PR2249
4.7_1206_5%
2 1 +5VALW 2 1 17 ISEN2P_CPU_R 2 3
VCC PVCC_CPU LG2_CPU
PR2230

PR2253

PR2239

PR2224 34 1 2 +5VALW
PVCC

1
PH1006 4.7_0603_5% 18
100K_0402_1%_B25/50 4250K PWROK 33 LG1_NB
[7] APU_PWRGD @ PR2252 LGATE_NB
1 2 SVC_RT3662 19 1 2 1 2
[7] APU_SVC
1

2 1 SVC 32 LX1_NB 2 1 PR2236

1

0_0402_5% 20 PHASE_NB 1.1K_0603_1% PC11244

SVD_RT3662

1 2
SVD

ISENN_NB
@ PC11242

ISENP_NB

COMP_NB
31 UG1_NB SNB_APU2

BOOT_NB
PC11269 PC11270 0.47U_0402_25V6K

TSEN_NB
@ PR1035
1

1
1

UGATE_NB
0_0402_5%

0_0402_5%

680P_0402_50V7K
RF@ PC11267
2.2U_0402_10V6M 1 2 2.2U_0402_10V6M
0_0402_5%

@ PR1037

@ PR1038

FB_NB
@ PR1036

VDDIO
4.7K_0402_1% @ PR1039

SVT

VIN
10P_0402_50V8J 0_0402_5%

EN
2

2
[7] APU_SVD 1 2
2

2
2

21

22

23

24

25

26

27

28

29

30
+1.8VS @ PC11250
1 2 @ PR1040
APU_SVD and APU_SVC RC filter put CPU side.

FB_NB

COMP_NB
ISENA1N_NB

ISENA1P_NB
TSEN_NB

BST1_NB
1.1K_0402_1%
APU_SVT RC filter put controller side. 10P_0402_50V8J @ PR1041 ISEN2P_CPU 1 2
0_0402_5%
[7] APU_SVT 1 2 SVT_RT3662

Vinafix.com
@ PR1043 PR1064
+1.8VS @ PC11260 0_0402_5% 1_0402_1%
+1.8VS EN_RT3662 ISEN1N_CPU ISEN2N_CPU_R
10P_0402_50V8J 1 2 1 2
1 2 VR_ON [28,37]
2 1 APU_B+
2 1 PR1044 PR1065

0.1U_0402_25V6
1

1K_0402_5%
1

4.7_0603_5% 1.1K_0402_1%
1K_0402_5%

@PR2256

1
ISEN1P_CPU
@PR2254

PC11233
PC11255 1 2
1U_0402_6.3V6K

0.1U_0402_25V6
2
2.2_0402_5%

2
1

PC11258
@
2
2

PR1042

2
1
1

220_0402_1%
1

220_0402_1%

@ PR2257
@ PR2255

3 +1.8VS 3
2
2

LL_NB(Rdroop)=2.1m 2 1 2 1

VREF_APU 1 2 Near APU CHOKE PR1045 PR1046

PR1047 PC11236@ 10K_0402_1% 60.4K_0402_1%
10.7K_0402_1% 330P_0402_50V7K
2 1 1 2 2 1 B+
1 2 2 1 1 2 IMON_APU
PR1048 PR1049 PC11251 PC11229
15.8K_0402_1% PH1004 1.65K_0402_1% 220P_0402_50V8J 68P_0402_50V8J
100K_0402_1%_B25/50 4250K

10U_0603_25V6M

10U_0603_25V6M
RGND_RT3662

UG1_NB

PC11231

PC11232
1

1
1 2 9/26
PR1053 Near CORE_NB CHOKE Modify for stardust test result
16.5K_0402_1% @ PC11259 PR1057 PC11252 PQ1003

2
0.1U_0402_25V6 2.2_0603_5% 0.22U_0603_25V7K
AON6962_DFN5X6D-8-7

2
1 2 2 1 1 2 IMON_NB 2 1 BST1_NB
1 2 BST1_NB1_R
1 2
PR1055

G1

D1
PR1056
9.76K_0402_1% PH1005 PL2106
13.3K_0402_1%
100K_0402_1%_B25/50 4250K 0.24UH_22A_+-20%_ 7X7X3_M
LX1_NB 7 1 4
D2/S1 +APU_CORE_SOC
2

1
10_0402_5%
1

@ PR1051 ISENA1P_NB_R 2
PR1050

1
@ PR1054 0_0402_5%

RF@ PR1059
4.7_1206_5%
PR1058

G2

S2

S2

S2
0_0402_5% 931_0402_1%
1 2 1 2
APU_CORE_NB
1

3
2

@ PC11264 PC11257 TDC 19A(1H1L)

2
0.1U_0402_25V6 LG1_NB 0.47U_0402_25V6K
2 1 SNB_APU_NB Peak current 13A

1
OCP current > 16A

680P_0402_50V7K
RF@ PC11268
2
[7] APU_VDDSOC_SEN FSW=400kHz
+APU_CORE_SOC

DCR 1.19mohm +/-5%

PR1060
931_0402_1% TYP MAX
ISENA1P_NB 1 2 H/S Rds(on) :6.8mohm , 8.6mohm
L/S Rds(on) :2.0mohm , 2.5mohm

ISENA1N_NB
4 4

0.1U_0402_25V6
1

PC11247
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/05/04 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RT3662ACGQW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2018 Sheet 38 of 41
A B C D E
 4
3
2
1

A
A

2
1
+
+APU_CORE
PC9083
220U_D7_2VM_R4.5M

2
1
+
PC11276
PC9084 10U_0402_6.3V6M
330U_D1_2VY_R9M 2 1

+
PC11275

2
1
10U_0402_6.3V6M
2 1
PC9085
330U_B2_2.5VM_R9M

2
1
PC9057 PC9029
PC9087 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
330U_B2_2.5VM_R9M

near CPU
PC1238 PC9056 PC9030
+APU_CORE

0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1

PC1239 PC9031
0.22U_0402_10V6K 22U_0603_6.3V6M

B
B

2
1
+
2 1
PC9086
220U_D7_2VM_R4.5M PC9058
22U_0603_6.3V6M
2 1

PC9059 PC9033 PC9005

CPU back side 22U_0603_6.3V6M 22U_0603_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1

PC9060 PC9034 PC9006

22U_0603_6.3V6M 22U_0603_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1

PC9062 PC9007
+APU_CORE

22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1

22uF*23
220uF*1
330uF*3
PC1244 PC9063 PC9008
0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1

APU_CORE
PC1245 PC9009
0.22U_0402_10V6K 22U_0603_6.3V6M

Issued Date
2 1
2 1
PC9010

Security Classification
PC1254 22U_0603_6.3V6M
180P_0402_50V8J 2 1

C
C

2 PC9088
1
+

2018/05/04
220U_D2 SX_2VY_R9M PC9011
PC1246 22U_0603_6.3V6M
0.22U_0402_10V6K 2 1
2 1 2 1
2
1
+

PC9012
near CPU
PC9089 PC1255 PC1247 22U_0603_6.3V6M
330U_D1_2VY_R9M 180P_0402_50V8J 0.22U_0402_10V6K 2 1
2 1
PC9013
Vinafix.com
+APU_CORE_SOC

PC1248 22U_0603_6.3V6M
0.22U_0402_10V6K 2 1
2 1
PC9014
PC1249 22U_0603_6.3V6M
0.22U_0402_10V6K 2 1
2 1

Compal Secret Data

PC9015

Deciphered Date
PC1250 22U_0603_6.3V6M
220uF*2

0.22U_0402_10V6K 2 1
2 1
PC9016
PC1251 22U_0603_6.3V6M
0.22U_0402_10V6K 2 1
2 1
APU_CORENB

PC9017
22uF*17+10uF*3

PC1252 22U_0603_6.3V6M

D
D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
0.22U_0402_10V6K 2 1
2 1
2018/05/25

PC9018
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

PC1253 22U_0603_6.3V6M
0.22U_0402_10V6K 2 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
+APU_CORE_SOC

2 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

PC9019
22U_0603_6.3V6M
2 1

PC9020
22U_0603_6.3V6M
2 1
Title

Date:

PC9039
22U_0603_6.3V6M
Custom

2 1

PC11285
22U_0603_6.3V6M
2 1

PC11289
Size Document Number

22U_0603_6.3V6M
2 1

PC11287
22U_0603_6.3V6M
Monday, December 17, 2018

2 1

PC11283
22U_0603_6.3V6M
E
E

2 1
LA-H091P
Sheet

PC11288
22U_0603_6.3V6M
2 1
39
+APU_CORE Cap

PC11284
22U_0603_6.3V6M
Compal Electronics, Inc.

of

2 1

PC11286
41

22U_0603_6.3V6M
2 1
Rev
1.0
4
3
2
1
 A B C D E

EE PIR List for SIV phase

NO DATE PAGE MODIFICATION LIST PURPOSE
1 18/08/08 13 Re-connect DDR_B_CS0# to Pin149 and DDR_B_CS1# to Pin157. Fix DDR SO-DIMM can't recognized issue

2 18/08/29 20 Swap SPK signal L/R for SPK module For audio request
1 1
3 18/08/29 21 Change 12MHz cap from 20pF to 33pF For crystal EA result fine tuning

4 18/08/29 9 Change 48MHz cap from 6.8pF to 4.7pF For crystal EA result fine tuning

5 18/08/29 26 Add thermal sensor circuit For thermal request\

6 18/08/29 25 Combine Type-C CC signal into DT4 For ESD request

7 18/08/29 29 Change 0.8VS/1.8VS solution from single to dual load switch For EA fine tune

8 18/08/29 20 Reserve 4pcs 2.2pF cap. on audio HDA bus (RST#,SYNC,SDIN,SDOUT) For RF request

9 18/08/29 7 Change RC17 to mount and RC18 to un-mount on DP_STEREOSYNC For HDMI HW enable

10 18/09/13 27 Change RTP3,RTP4 from 10K to 1K , CTP2,CTP3 to 150pF For EA fine tune

2
EE PIR List for SIT phase 2

NO DATE PAGE MODIFICATION LIST PURPOSE

1 18/10/29 28 Swap EC FAN1 PWM/SPEED & FAN2 PWM/SPEED trace For Thermal request

2 18/10/29 26 RF reqiured Reserve FAN PWM/Speed couple cap : CF3~CF8 For RF request

Vinafix.com
3 18/10/29 20 Supplier required modify AVDD5 power domain, +5VS to +5VALW Follow Supplier suggestion

4 18/10/29 20 ESD reqiured reserve HGNDA/HDNDB couple cap : CA63~CA66 For ESD EA test request

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/24 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H091P
Date: Monday, December 17, 2018 Sheet 40 of 41
A B C D E
 A B C D E

Version change list (P.I.R. List) Page 1 of 1 for

PWR
Item Reason for change PG# Modify List Date Phase

1 Based on AMD SDLE test P38 Change PR1046 to 54.9k ohm 2018/08/23 For SIV
1 1

2 Based on AMD SDLE test P38 Change PR1053 to 21.5k ohm 2018/08/23 For SIV

3 Based on AMD SDLE test P38 Change PR1055 to 4.87k ohm 2018/08/23 For SIV

4 Based on AMD SDLE test P38 Change PR1056 to 28.7k ohm 2018/08/23 For SIV

5 Based on AMD SDLE test P38 Change PR2226 to 261k ohm 2018/08/23 For SIV

2 2

Vinafix.com

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/05/04 Deciphered Date 2018/05/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-XXXXP
Date: Monday, December 17, 2018 Sheet 41 of 41
A B C D E