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  • T490 T590 DRIFT NM-B901 v1.0

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    Mosh Piter
    17 views125 pages
    This document is a 125 page logic schematic for a T490/T590 laptop computer. It contains detailed schematics and diagrams for the various components and subsystems of the laptop including the CPU, memory, display, audio, power delivery, and other internal components. The document contains a title page with security classification and proprietary markings.

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    This document is a 125 page logic schematic for a T490/T590 laptop computer. It contains detailed schematics and diagrams for the various components and subsystems of the laptop including the CPU, memory, display, audio, power delivery, and other internal components. The document contains a title page with security classification and proprietary markings.

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    © All Rights Reserved
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    17 views125 pages

    T490 T590 DRIFT NM-B901 v1.0

    Uploaded by

    Mosh Piter
    This document is a 125 page logic schematic for a T490/T590 laptop computer. It contains detailed schematics and diagrams for the various components and subsystems of the laptop including the CPU, memory, display, audio, power delivery, and other internal components. The document contains a title page with security classification and proprietary markings.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    of 125

    5 4 3 2 1

    T490/T590 Logic Schematics


    DRIFT
    VER 1.0
    D D

    1.TITLE PAGE 36.DDR4 SUB CHANNEL-B SODIMM_2 Dec.4 2018


    2.BLOCK DIAGRAM 37.N17S-G1(1/7) PEG I/F
    3.CPU (1/16): DDI/TYPE-C 38.N17S-G1(2/7) VRAM I/F
    BASE LOGIC 1 : Lightsaber-3 Pass-1 VER 0.25 Jul/10/2017
    4.CPU (2/16): DDR (1/2) 39.BLANK BASE LOGIC 2 : Finn-1 SIT VER 2.01 Jun/28/2017
    5.CPU (3/16): DDR (2/2) 40.N17S-G1(3/7) DIGITA / XTAL
    6.CPU (4/16): MISC/JTAG 41.N17S-G1(4/7) STRAP / GPIO
    7.CPU (5/16): ESPI/SPI/SMBUS/C-LINK 42.N17S-G1(5/7) POWER
    8.CPU (6/16): LPSS/ISH 43.N17S-G1(6/7) POWER 2 71.BLANK 99.SCREW HOLES
    9.CPU (7/16): AUDIO/SDXC 44.N17S-G1(7/7) GND 72.Smart Card Reader 100.DC-IN
    10.CPU (8/16): PCIE/USB/SATA 45.VRAM CHANNEL-A 73.GBE JACKSONVILLE 101.BATTERY INPUT
    11.CPU (9/16): CSI-2/EMMC/CNVI 46.BLANK 74.GBE LAN SWITCH 102.BATTERY CHARGER(BQ25700A)
    C
    12.CPU (10/16): CLOCK SIGNALS 47.BLANK 75.LAN_B CONNECTOR 103.DC/DC VCC5M (NB690) C

    13.CPU (11/16): SYSTEM PM 48.BLANK 76.MEDIA CARD CONTROLLER 104.DC/DC VCC5M_PD (NB693)
    14.CPU (12/16): CPU POWER (1/2) 49.BLANK 77.MEDIA CONNECTOR 105.DC/DC VCC3M (TPS51393)
    15.CPU (13/16): CPU POWER (2/2) 50.BLANK 78.AUDIO ALC3287 106.BLANK
    16.CPU (14/16): PCH POWER 51.LCD INTERFACE 79.AUDIO CONNECTOR 107.DC/DC VCC1R8_SUS (MP1603L)
    17.CPU (15/16): GND 52.LID/CAMERA/MIC/TOUCH INTERFACE 80.AUDIO JACK SENSE 108.DC/DC IMVP8 (MP2949AGQKT)
    18.CPU (16/16): CFG/RESERVED 53.BLANK 81.AUDIO EXT MIC I/F 109.DC/DC VCCCPUCORE (MP86901C)
    19.XDP CONNECTOR 54.HDMI CONNECTOR 82.AUDIO SPEAKER 110.DC/DC VCCGFXCORE_I (MP86901
    20.RTC BATTERY 55.ALPINE RIDGE (1/2) 83.AUDIO BEEP 111.DC/DC VCCSA (MP86901A)
    21.SPI FLASH 56.ALPINE RIDGE (2/2) 84.AUDIO DEBUG 112.DC/DC VCC1R2A(NB687)
    22.BLANK 57.BLANK 85.MEC1663(1/3) 113.DC/DC VCC1R05_SUS(NB693)
    23.BLANK 58.BLANK 86.MEC1663(2/3) 114.DC/DC VCC1R0VIDEO(BD9B304)
    B 24.BLANK 59.TUNDERBOLT PD 87.MEC1663(3/3) 115.DC/DC VCCGFXCORE_D (NCP8127 B

    25.BLANK 60.THUNDERBOLT DEMUX 88.KEYBOARD/TRACK POINT 116.DC/DC VCC1R35VIDEO(NB693)


    26.BLANK 61.USB TYPE-C SWITCH 89.TOUCH PAD/NFC/FPR 117.DC/DC VCC1R8VIDEO(BD9B304)
    27.BLANK 62.DOCKING CONNECTOR 90.FAN CONNECTOR 118.LOAD SW VIDEO
    28.BLANK 63.TYPE-C CONNECTOR 91.APS G-SENSOR 119.BLANK
    29.BLANK 64.M.2 SOCKET 3 MODULE I/F 92.BLANK 120.LOAD SW VCCST & VCCSTG
    30.BLANK 65.BLANK 93.SMBUS SWITCH 121.LOAD SW PCH SUS
    31.BLANK 66.M.2 TYPE 1216 MODULE 94.THINK ENGINE-3 (1/2) 122.BLANK
    32.BLANK 67.M.2 SOCKET 2 MODULE I/F 95.THINK ENGINE-3 (2/2) 123.LOAD SW LAN
    33.DDR4 SUB CHANNEL-A MD_1 68.DDI DEMULTIPLEXER 96.BLANK 124.LOAD SW B
    34.DDR4 SUB CHANNEL-A MD_2 69.USB TYPE-A CONNECTOR 97.BLANK 125.LOAD SW WLAN
    35.DDR4 SUB CHANNEL-B SODIMM_1 70.USB TYPE-A CONN 98.DISCRETE TPM 2.0
    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 TITLE PAGE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 1 of 125

    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    Drift/Ironhide Block Diagram


    LCD CONN DDR4 / 1.2V Project Code: FT490/FT590
    eDP 14" 15" EDPx4
    CPU Channel A DDR4
    51
    DDR4 2400MHz SUB VRAM 8Gb 2018 April ' 20
    MD 45
    Intel 33,34

    GDDR5
    D D
    DDI1 X4 Antenna
    Whiskey Lake U Channel B DDR4 Antenna
    DDR4 2400MHz SUB
    SODIMM
    35,36
    Platform (M.2 WLAN Card) NVIDIA
    HDMI
    DP++ DEMUX DDI2 x4 BGA1528 9560PD2WGPLQ_146P
    HDMI Conn 54 PS8337BQFN On board 1216 N17S-G1 (M.2 WWAN Card)
    K4G80325FB-HC03_BGA170
    68 15W Bluetooth
    I2C XDP CPU XDP 66 37~44 67
    19

    DP
    Type-A M.2 Card Port 13~16 Type-B M.2 Card
    I2C
    I2C NFC (X4)
    USB-C SW 89
    Type-C Conn 63 USB3.0 CH2 Micro SIM
    PS8747BQFN
    Card Slot
    61 SM Bus 67 Port 1
    (X1) Multi-Media
    Controller SD
    CNVi
    Realtek
    Card Slot
    USB3.1 Gen1 Port 7 77
    USB3.0 CH4 USB x 12 ports 10 RTS5232S-GR
    CONN 69 USB2.0 CH4 (X1) 76

    USB3.1 Gen1 USB3.0 CH3


    Port 9~12
    AOU (USB1) 70 USB2.0 CH3 (X4)
    C M.2 Slot C
    10 PCI Express x 13 ports
    USB2.0 USB2.0 CH1
    SSD
    Smart Cart 72 Port 8 Port 5,6 64
    HDA (X1) (X2)
    USB2.0 DDI1 X4
    USB2.0 CH2
    Type-C Port 63
    SPI Flash ALPINE RIDGE_LP
    SBU SW Side Dock
    USB2.0 USB2.0 CH5 SPI 32MB ALC3287 Intel GbE PHY TS3DS10224 (CS18)
    Side Dock Port 62 RTC Battery 20 (SPI0) HDA CODEC JACKSONVILLE JHL6240_BGA337 62
    55.56 60
    3,4,5,6,7,8,9,10,11,12 MX25L25673GM2I-08G ALC3287-CG_MQFN48_6X6 78 I219
    WGI219LM-QREF-A0_QFN48_6X6
    USB2.0 13,14,15,16,17,18 21
    USB2.0 CH6 Stereo 73
    Touch Panel 51
    Speaker
    SPI PD Conntroller
    USB2.0 82 SM Bus
    USB2.0 CH7 TI TPS65988
    M.2 WWAN Slot 67 I2C
    LPC Bus 33MHz SN1701012RJTR
    TPM 2.0 SPI Flash TBT
    USB2.0 USB2.0 CH8
    Microphone External Internal LAN SW 8MB SPI
    IR Camera 52
    FAN 90 ST33HTPH2E32AHB4 Headphone Mic Mic PI3L720ZHE W25Q80DVSSIG_SO8
    _VQFN32_5X5 PI3L720ZHE+CX_TQFN42_9X3P5
    79 81 52 74 55 59
    USB2.0 98
    USB2.0 CH9 G-Sensor
    Fingerprint 89 BMA255_LGA12_2X2
    91
    I2C
    B B
    I2C
    Thermal Sensor Embedded Lenovo
    PECI 3.0 Controller ASIC
    SMB-MB/SB THINK ENGINE-3 Audio 80
    MEC1663 Combo Jack MAGNETICS
    MEC1663-WC_WFBGA144 BD4179MWV_UQFN56_7X7
    LED for ThinkPad Logos RJ45
    85,86,87 94,95 TABLE: Chip Capacitor Tolerance
    75
    USB2.0
    Port 9 SM Bus Tolerance Code
    TABLE: Chip Part Dimension
    Sub Board +/-0.25pF C
    +/-0.5pF D
    Size [mm] mm Size Code Inch Size Code
    LID Fingerprint Keyboard Power Button Different with Windu-2 +/-5% J
    Reader ClickPad 0.40 x 0.20 0402 01005 +/-10% K
    52 89 89 88 51 External Connector/Socket 0.60 x 0.30 0603 0201 +/-20% M
    1.00 x 0.50 1005 0402 +80/-20% Z
    Internal Connector/Socket 1.60 x 0.80 1608 0603
    2.00 x 1.25 2125 0805
    2016 0806
    Sub-Board Internal Switch 2.00
    2.50
    3.20
    x
    x
    x
    1.60
    2.00
    1.60
    2520
    3216
    1008
    1206
    TABLE: Chip Capacitor Thermal Characteristics

    Board to Board 3.20 x 2.50 3225 1210


    Code
    4.50 x 1.60 4516 1806
    FFC 4.50 x 2.50 4525 1810
    MAGNETICS 4532 1812 -55 to 150degC +/-30ppm/degC NPO
    LID 4.50 x 3.20 -55 to 125degC +/-30ppm/degC C0G
    A
    RJ45 5025 2010 A
    5.00 x 2.50
    sub-B Sub-B 6.40 x 3.20
    6432 2512
    -55 to 125degC +/-15% X7R
    -55 to 105degC +/-22% X6S
    -55 to 85degC +/-15% X5R
    FPC FFC LOGIC
    USB3.1 Gen1 Power Button Title
    AOU (USB1) Security Classification LC Future Center Secret Data
    Sub-B Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLOCK DIAGRAM
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 2 of 125
    5 4 3 2 1
    5 4 3 2 1

    TABLE : Functional Strap


    GPP_E19/DDPB_CTRLDATA/CNV_BT_IF_SELECT (Display Port B Detected)
    HIGH Port B is detected LOGIC
    LOW Port B is not detected (Default)

    TABLE : Functional Strap


    GPP_E21/DDPC_CTRLDATA (Display Port C Detected)
    HIGH Port C is detected LOGIC
    LOW Port C is not detected (Default)

    D D
    TABLE : Functional Strap
    GPP_E23/DDPD_CTRLDATA (Display Port D Detected)
    HIGH Port D is detected
    LOW Port D is not detected (Default) LOGIC

    VCC3_SUS VCCIO VCC3_SUS

    1/20W_20K_5%_0201
    1/20W_2.2K_5%_0201

    1/20W_24.9_1%_0201
    2

    1
    R0301

    R0307

    @ R0311
    ?

    2
    UCPU1A

    DDIP1_0N AL5 AG4 EDP_TXN0


    <55> DDIP1_0N DDI1_TXN_0 EDP_TXN_0 EDP_TXN0 <51>
    DDIP1_0P AL6 AG3 EDP_TXP0
    <55> DDIP1_0P DDI1_TXP_0 EDP_TXP_0 EDP_TXP0 <51>
    DDIP1_1N AJ5 AG2 EDP_TXN1
    <55> DDIP1_1N DDI1_TXN_1 EDP_TXN_1 EDP_TXN1 <51>
    C DDIP1_1P AJ6 AG1 EDP_TXP1 C
    <55> DDIP1_1P DDI1_TXP_1 EDP_TXP_1 EDP_TXP1 <51>
    DDIP1_2N AF6 AJ4 EDP_TXN2
    <55> DDIP1_2N DDI1_TXN_2 EDP_TXN_2 EDP_TXN2 <51>
    DDIP1_2P AF5 AJ3 EDP_TXP2
    <55> DDIP1_2P DDI1_TXP_2 EDP_TXP_2 EDP_TXP2 <51>
    DDIP1_3N AE5 AJ2 EDP_TXN3
    <55> DDIP1_3N DDI1_TXN_3 EDP_TXN_3 EDP_TXN3 <51>
    DDIP1_3P AE6 AJ1 EDP_TXP3
    <55> DDIP1_3P DDI1_TXP_3 EDP_TXP_3 EDP_TXP3 <51>
    DDIP2_0N AC4
    <68> DDIP2_0N AC3 DDI2_TXN_0
    AH4
    DDIP2_0P EDP_AUXN
    <68> DDIP2_0P DDI2_TXP_0 EDP_AUX_N EDP_AUXN <51>
    DDIP2_1N AC1 AH3 EDP_AUXP
    <68> DDIP2_1N DDI2_TXN_1 EDP_AUX_P EDP_AUXP <51>
    DDIP2_1P AC2
    <68> DDIP2_1P AE4 DDI2_TXP_1
    AM7
    DDIP2_2N
    <68> DDIP2_2N DDI2_TXN_2 DISP_UTILS
    DDIP2_2P AE3
    <68> DDIP2_2P DDI2_TXP_2
    AC7
    DDIP2_3N AE1 DDIP1_AUXN
    <68> DDIP2_3N DDI2_TXN_3 DDI1_AUX_N
    AC6 DDIP1_AUXN <55>
    DDIP2_3P AE2 DDIP1_AUXP
    <68> DDIP2_3P DDI2_TXP_3 DDI1_AUX_P
    AD4 DDIP1_AUXP <55>
    DDIP2_AUXN
    DDI2_AUX_N
    AD3 DDIP2_AUXN <68>
    DDIP2_AUXP
    DDI2_AUX_P
    AG7 DDIP2_AUXP <68>
    DDI3_AUX_N
    AG6
    DDI3_AUX_P

    CN6 DDIP1_HPD
    GPP_E13/DDPB_HPD0/DISP_MISC0
    CM6 DDIP1_HPD <55>
    DDIP2_HPD
    GPP_E14/DDPC_HPD1/DISP_MISC1
    CP7 DDIP2_HPD <68>
    GPP_E15/DPPD_HPD2/DISP_MISC2
    CP6 -WWAN_PERST <67>
    GPP_E16/DPPE_HPD3/DISP_MISC3
    CM7
    GPP_E17/EDP_HPD/DISP_MISC4 EDP_HPD <51>
    CK11
    EDP_BKLTEN
    CG11 VGA_BLON <85>
    PANEL_POWER_ON_CPU
    EDP_VDDEN
    CH11
    EDP_BKLTCTL PANEL_BKLT_CTRL_CPU <51>

    1/20W_100K_5%_0201

    1/20W_100K_5%_0201

    1/20W_100K_5%_0201
    1/20W_100K_5%_0201

    1/20W_100K_5%_0201
    2

    2
    2

    2
    EDP_COMP AM6
    DISP_RCOMP

    R0303

    R0305

    R0306
    @ R0304

    R0302
    CC8
    GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#
    GPP_E19 CC9
    GPP_E19/DPPB_CTRLDATA

    1
    1

    1
    CH4
    <68> DDIP2_CTRLCLK CH3 GPP_E20/DPPC_CTRLCLK
    B <68> DDIP2_CTRLDATA GPP_E21/DPPC_CTRLDATA B

    CP4
    <37> -GPU_RST CN4 GPP_E22/DPPD_CTRLCLK
    <41,117> 1R8VIDEO_AON_ON GPP_E23/DPPD_CTRLDATA
    CR26
    GPP_H16/DDPF_CTRLCLK
    GPP_H17 CP26 PANEL_POWER_ON_CPU D0301 2 1 RB520CM-30T2R_VMN2M2
    GPP_H17/DDPF_CTRLDATA PANEL_POWER_ON <95>
    1/20W_20K_5%_0201
    1/20W_1M_1%_0201
    1/20W_1M_1%_0201

    WHISKEYLAKE-U_BGA1528
    1
    1
    1

    1 of 20 LCD_SELF_TEST_ON D0302 2 1 RB520CM-30T2R_VMN2M2


    CPU@
    <51,87> LCD_SELF_TEST_ON
    @ R0312
    R0308
    R0309

    1/20W_100K_5%_0201
    2
    2
    2
    2

    R0310
    1
    CPU Config

    UCPU1 UCPU1 UCPU1

    A A

    WHL_i7 WHL_i5 WHL_i3


    SA00009GY10 SA00009GZ10 SA00009H010 PCB
    i7_NV@ i5_NV@ i3_NV@
    ZZZ
    UCPU1 UCPU1

    Security Classification LC Future Center Secret Data Title


    PCB NM-B901 NS-B901/B902/B903/B904/B906 Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (1/16): DDI/TYPE-C
    WHL_i7 WHL_i5
    DAZ1AC00100
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    SA00009D110
    Vinafix.com SA00009QQ00 PCB@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    i7_V@ i5_V@ DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 3 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    <33> M_A_DQ[63:0] ?

    UCPU1B
    V32 -M_A_DDRCLK0_1200M
    DDR0_CKN_0/DDR0_CKN_0 -M_A_DDRCLK0_1200M <33,34>
    V31 M_A_DDRCLK0_1200M
    DDR0_CKP_0/DDR0_CKP_0 M_A_DDRCLK0_1200M <33,34>
    M_A_DQ4 A26 T32
    DDR0_DQ_0/DDR0_DQ_0 DDR0_CKN_1/DDR0_CKN_1
    M_A_DQ0 D26 T31
    DDR0_DQ_1/DDR0_DQ_1 DDR0_CKP_1/DDR0_CKP_1
    M_A_DQ1 D28
    DDR0_DQ_2/DDR0_DQ_2
    M_A_DQ7 C28 U36 M_A_CKE0
    DDR0_DQ_3/DDR0_DQ_3 DDR0_CKE_0/DDR0_CKE_0 M_A_CKE0 <33,34>
    M_A_DQ6 B26 U37
    DDR0_DQ_4/DDR0_DQ_4 DDR0_CKE_1/DDR0_CKE_1
    M_A_DQ2 C26 U34
    DDR0_DQ_5/DDR0_DQ_5 DDR0_CKE_2/NC
    M_A_DQ3 B28 U35
    DDR0_DQ_6/DDR0_DQ_6 DDR0_CKE_3/NC
    M_A_DQ5 A28
    DDR0_DQ_7/DDR0_DQ_7
    M_A_DQ12 B30 AE32 -M_A_CS0
    DDR0_DQ_8/DDR0_DQ_8 DDR0_CS#_0/DDR0_CS#_0 -M_A_CS0 <33,34>
    M_A_DQ14 D30 AF32
    DDR0_DQ_9/DDR0_DQ_9 DDR0_CS#_1/DDR0_CS#_1
    M_A_DQ11 B33 AE31 M_A_ODT0
    DDR0_DQ_10/DDR0_DQ_10DDR0_ODT_0/DDR0_ODT_0 M_A_ODT0 <33,34>
    M_A_DQ9 D32 AF31
    DDR0_DQ_11/DDR0_DQ_11 NC/DDR0_ODT_1
    M_A_DQ10 A30
    DDR0_DQ_12/DDR0_DQ_12
    M_A_DQ8 C30 AC37 M_A_A0
    DDR0_DQ_13/DDR0_DQ_13 DDR0_CAB_9/DDR0_MA_0 AC36
    M_A_DQ15 B32 M_A_A1
    DDR0_DQ_14/DDR0_DQ_14 DDR0_CAB_8/DDR0_MA_1
    M_A_DQ13 C32 AC34 M_A_A2
    DDR0_DQ_15/DDR0_DQ_15 DDR0_CAB_5/DDR0_MA_2
    M_A_DQ20 H37 AC35 M_A_A3
    DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_MA_3
    M_A_DQ16 H34 AA35 M_A_A4
    DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_MA_4
    M_A_DQ17 K34 AB35 M_A_A5
    DDR0_DQ_18/DDR0_DQ_34 DDR0_CAA_0/DDR0_MA_5
    C M_A_DQ23 K35 AA37 M_A_A6 C
    DDR0_DQ_19/DDR0_DQ_35 DDR0_CAA_2/DDR0_MA_6
    M_A_DQ22 H36 AA36 M_A_A7
    H35 DDR0_DQ_20/DDR0_DQ_36 DDR0_CAA_4/DDR0_MA_7
    AB34 M_A_A[16:0] <33,34>
    M_A_DQ18 M_A_A8
    DDR0_DQ_21/DDR0_DQ_37 DDR0_CAA_3/DDR0_MA_8
    M_A_DQ19 K36 W36 M_A_A9
    DDR0_DQ_22/DDR0_DQ_38 DDR0_CAA_1/DDR0_MA_9
    M_A_DQ21 K37 Y31 M_A_A10
    DDR0_DQ_23/DDR0_DQ_39 DDR0_CAB_7/DDR0_MA_10
    M_A_DQ28 N36 W34 M_A_A11
    DDR0_DQ_24/DDR0_DQ_40DDR0_CAA_7/DDR0_MA_11
    M_A_DQ24 N34 AA34 M_A_A12
    DDR0_DQ_25/DDR0_DQ_41 DDR0_CAA_6/DDR0_MA_12
    M_A_DQ25 R37 AC32 M_A_A13
    DDR0_DQ_26/DDR0_DQ_42 DDR0_CAB_0/DDR0_MA_13
    M_A_DQ31 R34
    DDR0_DQ_27/DDR0_DQ_43
    M_A_DQ26 N37 AC31 M_A_A14
    N35 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_2/DDR0_MA_14 -M_A_DQS[7:0] <33>
    M_A_DQ30 AB32 M_A_A15
    DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_1/DDR0_MA_15
    M_A_DQ27 R36 Y32 M_A_A16
    DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_3/DDR0_MA_16
    M_A_DQ29 R35
    AN35 DDR0_DQ_31/DDR0_DQ_47 W32 M_A_DQS[7:0] <33>
    M_A_DQ32 M_A_BS0
    DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_4/DDR0_BA_0 M_A_BS0 <33,34>
    M_A_DQ38 AN34 AB31 M_A_BS1
    DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_6/DDR0_BA_1
    V34 M_A_BS1 <33,34>
    M_A_DQ33 AR35 M_A_BG0
    AR34 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAA_5/DDR0_BG_0 M_A_BG0 <33,34>
    M_A_DQ39
    DDR0_DQ_35/DDR1_DQ_3
    M_A_DQ36 AN37 V35 -M_A_ACT
    DDR0_DQ_36/DDR1_DQ_4 DDR0_CAA_8/DDR0_ACT# -M_A_ACT <33,34>
    M_A_DQ34 AN36 W35 M_A_BG1
    DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_9/DDR0_BG_1 M_A_BG1 <33>
    M_A_DQ37 AR36
    AR37 DDR0_DQ_38/DDR1_DQ_6
    M_A_DQ35 C27 -M_A_DQS0
    DDR0_DQ_39/DDR1_DQ_7
    DDR0_DQSN_0/DDR0_DQSN_0
    M_A_DQ46 AU35 D27 M_A_DQS0
    AU34 DDR0_DQSP_0/DDR0_DQSP_0
    DDR0_DQ_40/DDR1_DQ_8
    M_A_DQ44 D31 -M_A_DQS1
    DDR0_DQ_41/DDR1_DQ_9
    DDR0_DQSN_1/DDR0_DQSN_1
    M_A_DQ45 AW35 C31 M_A_DQS1
    DDR0_DQ_42/DDR1_DQ_10
    DDR0_DQSP_1/DDR0_DQSP_1
    M_A_DQ41 AW34 J35 -M_A_DQS2
    DDR0_DQSN_2/DDR0_DQSN_4
    DDR0_DQ_43/DDR1_DQ_11
    M_A_DQ40 AU37 J34 M_A_DQS2
    DDR0_DQ_44/DDR1_DQ_12
    DDR0_DQSP_2/DDR0_DQSP_4
    M_A_DQ42 AU36 P34 -M_A_DQS3
    DDR0_DQ_45/DDR1_DQ_13
    DDR0_DQSN_3/DDR0_DQSN_5
    M_A_DQ47 AW36 P35 M_A_DQS3
    DDR0_DQ_46/DDR1_DQ_14
    DDR0_DQSP_3/DDR0_DQSP_5
    M_A_DQ43 AW37 AP35 -M_A_DQS4
    DDR0_DQSN_4/DDR1_DQSN_0
    DDR0_DQ_47/DDR1_DQ_15
    M_A_DQ48 BA35 AP34 M_A_DQS4
    DDR0_DQSP_4/DDR1_DQSP_0
    DDR0_DQ_48/DDR1_DQ_32
    M_A_DQ50 BA34 AV34 -M_A_DQS5
    DDR0_DQ_49/DDR1_DQ_33
    DDR0_DQSN_5/DDR1_DQSN_1
    M_A_DQ51 BC35 AV35 M_A_DQS5
    DDR0_DQ_50/DDR1_DQ_34
    DDR0_DQSP_5/DDR1_DQSP_1
    M_A_DQ55 BC34 BB35 -M_A_DQS6
    DDR0_DQ_51/DDR1_DQ_35
    DDR0_DQSN_6/DDR1_DQSN_4
    M_A_DQ54 BA37 BB34 M_A_DQS6
    DDR0_DQSP_6/DDR1_DQSP_4
    DDR0_DQ_52/DDR1_DQ_36
    M_A_DQ52 BA36 BF34 -M_A_DQS7
    DDR0_DQ_53/DDR1_DQ_37
    DDR0_DQSN_7/DDR1_DQSN_5
    M_A_DQ53 BC36 BF35 M_A_DQS7
    DDR0_DQ_54/DDR1_DQ_38
    DDR0_DQSP_7/DDR1_DQSP_5
    M_A_DQ49 BC37
    BE35 DDR0_DQ_55/DDR1_DQ_39
    M_A_DQ62 W37 -M_A_ALERT
    DDR0_DQ_56/DDR1_DQ_40 NC/DDR0_ALERT# W31 -M_A_ALERT <33,34>
    M_A_DQ56 BE34 M_A_PARITY
    B BG35 DDR0_DQ_57/DDR1_DQ_41 NC/DDR0_PAR M_A_PARITY <33,34> B
    M_A_DQ57 F36
    BG34 DDR0_DQ_58/DDR1_DQ_42 DDR_VREF_CA D35 M_A_VREF_CA_CPU <34>
    M_A_DQ61
    DDR0_DQ_59/DDR1_DQ_43 DDR0_VREF_DQ_0
    M_A_DQ58 BE37 D37
    DDR0_DQ_60/DDR1_DQ_44 DDR0_VREF_DQ_1
    M_A_DQ60 BE36 E36
    BG36 DDR0_DQ_61/DDR1_DQ_45 DDR1_VREF_DQ C35 M_B_VREF_CA_CPU <35>
    M_A_DQ59 DDR_PG_CTRL
    DDR0_DQ_62/DDR1_DQ_46 DDR_VTT_CNTL
    M_A_DQ63 BG37
    DDR0_DQ_63/DDR1_DQ_47

    WHISKEYLAKE-U_BGA1528
    2 of 20
    CPU@ VCC3M

    2
    R0402
    1/20W_100K_5%_0201

    1
    VCC1R2A DDR_VTT_PG_CTRL
    DDR_VTT_PG_CTRL <112>

    1
    Q0401
    2 DTC015TMT2L NPN VMT3

    3
    2
    R0401
    @ 1/20W_10K_5%_0201

    A 1 A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (2/16): DDR (1/2)
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 4 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    <35> M_B_DQ[63:0] ?

    UCPU1C

    M_B_DQ0 J22 AF28 -M_B_DDRCLK0_1200M


    DDR1_CKN_0/DDR1_CKN_0
    DDR1_DQ_0/DDR0_DQ_16 -M_B_DDRCLK0_1200M <35>
    M_B_DQ1 H25 AF29 M_B_DDRCLK0_1200M
    DDR1_CKP_0/DDR1_CKP_0
    DDR1_DQ_1/DDR0_DQ_17 M_B_DDRCLK0_1200M <35>
    M_B_DQ2 G22 AE28 -M_B_DDRCLK1_1200M
    DDR1_DQ_2/DDR0_DQ_18
    DDR1_CKN_1/DDR1_CKN_1 -M_B_DDRCLK1_1200M <35>
    M_B_DQ3 H22 AE29 M_B_DDRCLK1_1200M
    DDR1_CKP_1/DDR1_CKP_1
    DDR1_DQ_3/DDR0_DQ_19 M_B_DDRCLK1_1200M <35>
    M_B_DQ4 F25
    DDR1_DQ_4/DDR0_DQ_20
    M_B_DQ5 J25 T28 M_B_CKE0
    DDR1_CKE_0/DDR1_CKE_0
    DDR1_DQ_5/DDR0_DQ_21 M_B_CKE0 <35>
    M_B_DQ6 G25 T29 M_B_CKE1
    DDR1_CKE_1/DDR1_CKE_1
    DDR1_DQ_6/DDR0_DQ_22 M_B_CKE1 <35>
    M_B_DQ7 F22 V28
    DDR1_DQ_7/DDR0_DQ_23 DDR1_CKE_2/NC
    M_B_DQ8 D22 V29
    DDR1_DQ_8/DDR0_DQ_24 DDR1_CKE_3/NC
    M_B_DQ9 C22
    DDR1_DQ_9/DDR0_DQ_25
    M_B_DQ10 C24 AL37 -M_B_CS0
    D24 DDR1_DQ_10/DDR0_DQ_26
    DDR1_CS#_0/DDR1_CS#_0 -M_B_CS0 <35>
    M_B_DQ11 AL35 -M_B_CS1
    DDR1_DQ_11/DDR0_DQ_27
    DDR1_CS#_1/DDR1_CS#_1 -M_B_CS1 <35>
    M_B_DQ12 A22 AL36 M_B_ODT0
    DDR1_ODT_0/DDR1_ODT_0
    DDR1_DQ_12/DDR0_DQ_28
    AL34 M_B_ODT0 <35>
    M_B_DQ13 B22 M_B_ODT1
    DDR1_DQ_13/DDR0_DQ_29 NC/DDR1_ODT_1 M_B_ODT1 <35>
    M_B_DQ14 A24 AG36 M_B_A0
    DDR1_DQ_14/DDR0_DQ_30DDR1_CAB_9/DDR1_MA_0 M_B_A[16:0] <35>
    M_B_DQ15 B24 AG35 M_B_A1
    DDR1_DQ_15/DDR0_DQ_31DDR1_CAB_8/DDR1_MA_1
    M_B_DQ16 G31 AF34 M_B_A2
    DDR1_DQ_16/DDR0_DQ_48DDR1_CAB_5/DDR1_MA_2
    C M_B_DQ17 G32 AG37 M_B_A3 C
    DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_MA_3
    M_B_DQ18 H29 AE35 M_B_A4
    DDR1_DQ_18/DDR0_DQ_50 NC/DDR1_MA_4
    M_B_DQ19 H28 AF35 M_B_A5
    DDR1_DQ_19/DDR0_DQ_51DDR1_CAA_0/DDR1_MA_5
    M_B_DQ20 G28 AE37 M_B_A6
    DDR1_DQ_20/DDR0_DQ_52DDR1_CAA_2/DDR1_MA_6
    M_B_DQ21 G29 AC29 M_B_A7
    DDR1_DQ_21/DDR0_DQ_53DDR1_CAA_4/DDR1_MA_7
    M_B_DQ22 H31 AE36 M_B_A8
    DDR1_DQ_22/DDR0_DQ_54DDR1_CAA_3/DDR1_MA_8 AB29
    M_B_DQ23 H32 M_B_A9
    DDR1_DQ_23/DDR0_DQ_55DDR1_CAA_1/DDR1_MA_9
    M_B_DQ24 L31 AG34 M_B_A10
    DDR1_DQ_24/DDR0_DQ_56
    DDR1_CAB_7/DDR1_MA_10
    M_B_DQ25 L32 AC28 M_B_A11
    DDR1_CAA_7/DDR1_MA_11
    DDR1_DQ_25/DDR0_DQ_57
    M_B_DQ26 N29 AB28 M_B_A12
    DDR1_CAA_6/DDR1_MA_12
    DDR1_DQ_26/DDR0_DQ_58
    M_B_DQ27 N28 AK35 M_B_A13
    DDR1_CAB_0/DDR1_MA_13
    DDR1_DQ_27/DDR0_DQ_59
    M_B_DQ28 L28
    DDR1_DQ_28/DDR0_DQ_60
    M_B_DQ29 L29 AJ35 M_B_A14
    DDR1_DQ_29/DDR0_DQ_61
    DDR1_CAB_2/DDR1_MA_14
    M_B_DQ30 N31 AK34 M_B_A15
    DDR1_DQ_30/DDR0_DQ_62
    DDR1_CAB_1/DDR1_MA_15
    M_B_DQ31 N32 AJ34 M_B_A16
    DDR1_DQ_31/DDR0_DQ_63
    DDR1_CAB_3/DDR1_MA_16
    M_B_DQ32 AJ29
    DDR1_DQ_32/DDR1_DQ_16
    M_B_DQ33 AJ30 AJ37 M_B_BS0
    AM32 DDR1_DQ_33/DDR1_DQ_17DDR1_CAB_4/DDR1_BA_0 AJ36 M_B_BS0 <35>
    M_B_DQ34 M_B_BS1
    AM31 DDR1_DQ_34/DDR1_DQ_18DDR1_CAB_6/DDR1_BA_1 M_B_BS1 <35>
    M_B_DQ35 W29 M_B_BG0
    AM30
    DDR1_DQ_35/DDR1_DQ_19DDR1_CAA_5/DDR1_BG_0 M_B_BG0 <35>
    M_B_DQ36
    DDR1_DQ_36/DDR1_DQ_20
    M_B_DQ37 AM29 Y28 M_B_BG1
    DDR1_DQ_37/DDR1_DQ_21DDR1_CAA_9/DDR1_BG_1
    W28 M_B_BG1 <35>
    M_B_DQ38 AJ31 -M_B_ACT
    AJ32 DDR1_DQ_38/DDR1_DQ_22DDR1_CAA_8/DDR1_ACT# -M_B_ACT <35>
    M_B_DQ39
    DDR1_DQ_39/DDR1_DQ_23
    M_B_DQ40 AR31 H24 -M_B_DQS0
    AR32 DDR1_DQSN_0/DDR0_DQSN_2
    DDR1_DQ_40/DDR1_DQ_24
    G24 -M_B_DQS[7:0] <35>
    M_B_DQ41 M_B_DQS0
    DDR1_DQSP_0/DDR0_DQSP_2
    DDR1_DQ_41/DDR1_DQ_25 M_B_DQS[7:0] <35>
    M_B_DQ42 AV30 C23 -M_B_DQS1
    DDR1_DQSN_1/DDR0_DQSN_3
    DDR1_DQ_42/DDR1_DQ_26
    M_B_DQ43 AV29 D23 M_B_DQS1
    DDR1_DQ_43/DDR1_DQ_27
    DDR1_DQSP_1/DDR0_DQSP_3
    M_B_DQ44 AR30 G30 -M_B_DQS2
    DDR1_DQ_44/DDR1_DQ_28
    DDR1_DQSN_2/DDR0_DQSN_6
    M_B_DQ45 AR29 H30 M_B_DQS2
    DDR1_DQSP_2/DDR0_DQSP_6
    DDR1_DQ_45/DDR1_DQ_29
    M_B_DQ46 AV32 L30 -M_B_DQS3
    DDR1_DQ_46/DDR1_DQ_30
    DDR1_DQSN_3/DDR0_DQSN_7
    M_B_DQ47 AV31 N30 M_B_DQS3 VCC1R2A
    BA32 DDR1_DQSP_3/DDR0_DQSP_7
    DDR1_DQ_47/DDR1_DQ_31
    M_B_DQ48 AL31 -M_B_DQS4
    DDR1_DQ_48/DDR1_DQ_48
    DDR1_DQSN_4/DDR1_DQSN_2
    M_B_DQ49 BA31 AL30 M_B_DQS4
    DDR1_DQSP_4/DDR1_DQSP_2
    DDR1_DQ_49/DDR1_DQ_49
    M_B_DQ50 BD31 AU31 -M_B_DQS5
    DDR1_DQSN_5/DDR1_DQSN_3

    1
    DDR1_DQ_50/DDR1_DQ_50
    M_B_DQ51 BD32 AU30 M_B_DQS5
    DDR1_DQ_51/DDR1_DQ_51
    DDR1_DQSP_5/DDR1_DQSP_3
    M_B_DQ52 BA30 BC31 -M_B_DQS6 R0504
    DDR1_DQ_52/DDR1_DQ_52
    DDR1_DQSN_6/DDR1_DQSN_6
    M_B_DQ53 BA29 BC30 M_B_DQS6 1/20W_470_5%_0201
    DDR1_DQSP_6/DDR1_DQSP_6
    DDR1_DQ_53/DDR1_DQ_53
    M_B_DQ54 BD29 BH31 -M_B_DQS7
    DDR1_DQSN_7/DDR1_DQSN_7
    DDR1_DQ_54/DDR1_DQ_54
    M_B_DQ55 BD30 BH30 M_B_DQS7

    2
    B DDR1_DQSP_7/DDR1_DQSP_7
    DDR1_DQ_55/DDR1_DQ_55 B
    M_B_DQ56 BG31
    DDR1_DQ_56/DDR1_DQ_56
    M_B_DQ57 BG32 Y29 -M_B_ALERT
    DDR1_DQ_57/DDR1_DQ_57 NC/DDR1_ALERT# -M_B_ALERT <35>
    M_B_DQ58 BK32 AE34 M_B_PARITY
    BK31 DDR1_DQ_58/DDR1_DQ_58 NC/DDR1_PAR BU31 M_B_PARITY <35>
    M_B_DQ59 -DRAMRST
    BG29 DDR1_DQ_59/DDR1_DQ_59 DRAM_RESET# -DRAMRST <33,35>
    M_B_DQ60
    DDR1_DQ_60/DDR1_DQ_60 1 2 1/20W_121_1%_0201
    M_B_DQ61 BG30 BN28 DDR_RCOMP0 R0501 2
    DDR1_DQ_61/DDR1_DQ_61 DDR_COMP_0
    M_B_DQ62 BK30 BN27 DDR_RCOMP1 R0502 1 2 1/20W_80.6_1%_0201 C0501 EMC_NS@
    DDR1_DQ_62/DDR1_DQ_62 DDR_COMP_1 R0503 1 2 1/20W_100_1%_0201 0.1U_6.3V_K_X5R_0201
    M_B_DQ63 BK29 BN29 DDR_RCOMP2
    DDR1_DQ_63/DDR1_DQ_63 DDR_COMP_2
    WHISKEYLAKE-U_BGA1528 1
    3 of 20
    CPU@

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (3/16): DDR (2/2)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 5 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    VCCSTG VCCST VCCST

    C C

    2
    2
    R0603 R0605 R0604
    1/20W_1K_5%_0201 1/20W_1K_5%_0201 1/20W_1K_5%_0201

    1
    1

    UCPU1D

    -CATERR AA4 T6 PROC_TCK DCI@ R0611 1 2 1/20W_0_5%_0201 XDP_TCK0


    CATERR# PROC_TCK XDP_TCK0 <19>
    PECI AR1 U6 PROC_TDI DCI@ R0612 1 2 1/20W_0_5%_0201 XDP_TDI
    <86> PECI PECI PROC_TDI
    DCI@ R0613 1 2 1/20W_0_5%_0201 XDP_TDI <19>
    -PROCHOT R0601 2 1 1/20W_499_1%_0201 -PROCHOT_CPU Y4 Y5 PROC_TDO XDP_TDO
    <86,87,102,108> -PROCHOT PROCHOT# PROC_TDO
    DCI@ R0614 1 2 1/20W_0_5%_0201 XDP_TMS
    XDP_TDO <19>
    -THRMTRIP BJ1 T5 PROC_TMS
    THRMTRIP# PROC_TMS XDP_TMS <19>
    AB6 PROC_TRST DCI@ R0615 1 2 1/20W_0_5%_0201 -XDP_TRST
    PROC_TRST# -XDP_TRST <19>
    U1
    BPM#_0
    U2 W6 PCH_TCK_R @ R0616 1 2 1/20W_0_5%_0201
    BPM#_1 PCH_TCK PCH_TCK <19>
    U3 U5
    BPM#_2 PCH_TDI
    U4 W5
    BPM#_3 PCH_TDO
    P5
    PCH_TMS
    Y6
    PCH_TRST#
    P6
    PCH_JTAGX
    CE9 W2 -XDP_PREQ
    GPP_E3/CPU_GP0PROC_PREQ# -XDP_PREQ <19>
    R0602 1 2 1/20W_0_5%_0201 -WWAN_DISABLE_R CN3 W1 -XDP_PRDY
    <67> -WWAN_DISABLE GPP_E7/CPU_GP1PROC_PRDY# -XDP_PRDY <19>
    CB34

    2
    GPP_B3/CPU_GP2
    CC35
    <55> -TBT_PLUG_EVENT GPP_B4/CPU_GP3
    R0606 1 2 1/20W_49.9_1%_0201 PROC_POPIRCOMP BP27 R0610
    PROC_POPIRCOMP
    R0607 1 2 1/20W_49.9_1%_0201 PCH_OPIRCOMP BW25 1/20W_51_5%_0201
    PCH_OPIRCOMP
    R0608 1 @ 2 1/20W_49.9_1%_0201 OPCE_RCOMP L5

    1
    RSVD35
    R0609 1 @ 2 1/20W_49.9_1%_0201 OPC_RCOMP N5
    RSVD36

    4 of 20
    WHISKEYLAKE-U_BGA1528
    CPU@
    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (4/16): MISC/JTAG
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 6 of 125
    5 4 3 2 1
    5 4 3 2 1

    TABLE : Functional Strap TABLE : Functional Strap TABLE : Functional Strap


    SPI0_MOSI (Reserved) SPI0_IO2 (Reserved) SPI0_IO3 (Reserved)
    External pull-up is required. Recommend 100 kohm External pull-up is required. Recommend 100 kohm External pull-up is required. Recommend 100 kohm
    if pulled up to 3.3V or 75 kohm if pulled up to 1.8V if pulled up to 3.3V or 75 kohm if pulled up to 1.8V if pulled up to 3.3V or 75 kohm if pulled up to 1.8V

    TABLE : Functional Strap


    GPP_C5/SML0ALERT # (eSPI or LPC)
    HIGH eSPI (for EC)
    LOW LPC (for EC) (Default) LOGIC
    D D
    TABLE : Functional Strap
    GPP_C2/SMBALERT# (TLS Confidentiality)
    HIGH Enable ME Crypto TLS with Confidentiality LOGIC
    LOW Disable ME Crypto TLS (Default)

    VCC3_SUS

    VCC3B
    VCC3B
    VCC3_SUS_SPI

    SPI_IO2 R0721 1 2 1/20W_100K_5%_0201

    1
    1

    1/20W_499_1%_0201
    SPI_IO3

    1/20W_1K_5%_0201

    1/20W_499_1%_0201
    R0722 1 2 1/20W_100K_5%_0201 R0703

    1/20W_4.7K_5%_0201
    1/20W_4.7K_5%_0201
    R0704 1/20W_8.2K_5%_0201

    2
    2
    2

    2
    SPI_MOSI_IO0 R0723 1 2 1/20W_100K_5%_0201 1/20W_8.2K_5%_0201

    R0709

    R0708
    R0710
    R0711

    R0707

    2
    2
    ?

    1
    1
    1

    1
    UCPU1E
    C R0712 1 20_0201_SP R0712 R0712 CH37 C
    <21,98> SPI_CLK CF37 SPI0_CLK
    CK14
    R0713 1 20_0201_SP R0713 R0713 SMB_CLK
    <21,98> SPI_MISO_IO1 CF36 SPI0_MISO GPP_C0/SMBCLK
    CH15 SMB_CLK <93>
    R0714 1 20_0201_SP R0714 R0714 SMB_DATA
    <21,98> SPI_MOSI_IO0 CF34 SPI0_MOSI GPP_C1/SMBDATA
    CJ15 SMB_DATA <93>
    R0715 1 20_0201_SP R0715 R0715 GPP_C2
    <21> SPI_IO2 CG34 SPI0_IO2 GPP_C2/SMBALERT#
    R0716 1 20_0201_SP R0716 R0716
    <21> SPI_IO3 CG36 SPI0_IO3
    CH14 SML0_CLK
    <21> -SPI_CS0 CG35 SPI0_CS0# GPP_C3/SML0CLK
    CF15 SML0_CLK <73>
    SML0_DATA
    CH34 SPI0_CS1# GPP_C4/SML0DATA
    CG15 SML0_DATA <73>
    GPP_C5
    <98> -SPI_CS2 SPI0_CS2# GPP_C5/SML0ALERT#
    CN15 EC_SCL2
    GPP_C6/SML1CLK
    CM15 EC_SCL2 <86>
    EC_SDA2
    CF20 GPP_C7/SML1DATA
    CC34 EC_SDA2 <86>
    PCHHOT
    GPP_D1/SPI1_CLK/BK1/SBK1 GPP_B23/SML1ALERT#/PCHHOT#
    CG22
    CF22 GPP_D2/SPI1_MISO_IO1/BK2/SBK2 LPC_AD[3:0] <85,93>
    GPP_D3/SPI1_MOSI_IO0/BK3/SBK3
    CG23
    GPP_D21/SPI1_IO2
    CH23 CA29 LPC_AD0
    <89> -NFC_DTCT CG20 GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0
    BY29 LPC_AD1
    GPP_D0/SPI1_CS0#/BK0/SBK0 GPP_A2/LAD1/ESPI_IO1
    BY27 LPC_AD2
    GPP_A3/LAD2/ESPI_IO2
    BV27 LPC_AD3
    GPP_A4/LAD3/ESPI_IO3
    CA28
    CH7 GPP_A5/LFRAME#/ESPI_CS#
    CA27 -LPC_FRAME <85,93>
    CH8 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET# -SUS_STAT <85,93>
    CL_DATA
    CH9 BV32 LPCCLK_0 EMC@ R0702 1 2 1/20W_22_1%_0201
    CL_RST# GPP_A9/CLKOUT_LPC0/ESPI_CLK
    BV30 LPCCLK_EC_24M <85>
    LPCCLK_1 R0701 1 @ 2 1/20W_0_5%_0201
    GPP_A10/CLKOUT_LPC1
    BY30 LPCCLK_DEBUG_24M <93>
    BV29 GPP_A8/CLKRUN# -CLKRUN <85,93>
    <85> -KBRC BV28 GPP_A0/RCIN#/TIME_SYNC1
    <85,93> IRQSER GPP_A6/SERIRQ
    WHISKEYLAKE-U_BGA1528 5 of 20
    CPU@

    1
    1 1
    R0718 EMC_NS@ RF_NS@
    @ 1/20W_20K_5%_0201 C0701 C0702
    22P_25V_J_NPO_0201 22P_25V_J_NPO_0201
    2

    2 2
    0.1U_6.3V_K_X5R_0201

    2
    EMC_HC@ C0703

    @ R0705
    1/20W_1K_5%_0201
    2
    1

    B B
    VCC3_SUS

    DCI Use

    2
    VCC3_SUS @ R0719
    1/20W_1K_5%_0201

    1
    @ GPP_C5
    PCHHOT R0717 1 2 1/20W_4.7K_5%_0201

    1
    @ R0720
    1/20W_20K_5%_0201

    2
    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (5/16): ESPI/SPI/SMBUS/C-LINK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 7 of 125

    5 4 3 2 1
    5 4 3 2 1

    TABLE : Functional Strap


    GPP_B14/SPKR (Top Swap Override)
    HIGH Enable "Top Swap" Mode
    LOW Disable "Top Swap" Mode (Default) LOGIC

    TABLE : Functional Strap


    GPP_B18/GSPI0_MOSI (No Reboot)
    HIGH Enable "No Reboot" Mode
    LOW Disable "No Reboot" Mode (Default) LOGIC
    VCC3_SUS VCC3_SUS VCC3_SUS
    D TABLE : Functional Strap D

    GPP_B22/GSPI1_MOSI (Boot BIOS Strap Bit BBS)


    HIGH LPC

    1
    LOW SPI (Default) LOGIC R0814 R0807 R0809
    1/20W_100K_5%_0201 @ 1/20W_1K_5%_0201 @ 1/20W_20K_5%_0201

    TABLE : Functional Strap

    2
    GPP_B23/SML1ALERT#/PCHHOT# (Intel DCI-OOB) VCC3_SUS GPP_D12 GPP_B18 GPP_B22

    HIGH Enable Intel DCI-OOB

    1
    1
    LOW Disable Intel DCI-OOB (Default) LOGIC R0810
    R0808 @ 1/20W_20K_5%_0201

    21/20W_10K_5%_0201

    21/20W_10K_5%_0201

    2 1/20W_1K_5%_0201
    @ 1/20W_20K_5%_0201
    TABLE : Functional Strap

    2
    2
    GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI (Reserved)
    External pull-up is required. Recommend 100 kohm

    1/20W_10K_5%_0201
    if pulled up to 3.3V or 75 kohm if pulled up to 1.8V

    R0806
    TABLE : Functional Strap @
    GPP_F6/CNV_RGI_DT (M.2 CNV Mode Select)

    R08021
    1

    R08031

    R08041
    A weak external Pull-Up is required.
    HIGH Integrated CNVi disable. LOGIC
    TABLE : -DISCRETE_PRESENCE
    LOW Integrated CNVi Enable.

    GPP_B17
    ?
    Model R0811
    C
    UCPU1F
    SWG ASM C

    CC27
    <89> NFC_DLREQ GPP_B15/GSPI0_CS0#
    -TPM_IRQ CC32
    <98> -TPM_IRQ
    CE28 GPP_A7/PIRQA#/GSPI0_CS1#
    CN22 -DISCRETE_PRESENCE SWG@ R0811 1 2 1/20W_0_5%_0201 UMA NO ASM
    GPP_B16/GSPI0_CLK GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
    CE27 CR22
    GPP_B17/GSPI0_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK -RFID_LOW_POWER <89>
    GPP_B18 CE29 CM22
    GPP_B18/GSPI0_MOSI GPP_D11/ISH_SPI_MISO/GSPI2_MISO
    CP22 GPP_D12
    GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
    CA31
    CA32 GPP_B19/GSPI1_CS0#
    CK22 DGFX_VRAM_ID0 @ R0812 1 2 1/20W_0_5%_0201 TABLE : DGFX_VRAM_ID
    <67> -WWAN_PEWAKE GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN# GPP_D5/ISH_I2C0_SDA
    SWG@ R0813 1 2 1/20W_0_5%_0201
    CC29 CH20 DGFX_VRAM_ID1
    CC30
    GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL DFX_VRAM_ID[1..0]
    GPP_B21/GSPI1_MISO
    GPP_B22 CA30 CH22
    GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA
    CJ22
    CK20 GPP_D8/ISH_I2C1_SCL 00B 1GB
    <66> BRI_RSP_CNVI GPP_F5/CNV_BRI_RSP
    CG19 CJ27
    <66> RGI_DT_CNVI GPP_F6/CNV_RGI_DT GPP_H10/I2C5_SDA/ISH_I2C2_SDA WWAN_CFG2 <67>
    CJ20 CJ29 LOGIC
    <66> BRI_DT_CNVI
    CH19 GPP_F4/CNV_BRI_DT GPP_H11/I2C5_SCL/ISH_I2C2_SCL WWAN_CFG3 <67> 01B 2GB
    <66> RGI_RSP_CNVI GPP_F7/CNV_RGI_RSP
    CM24
    GPP_D13/ISH_UART0_RXD -FULL_CARD_POWER_OFF <67>
    CN23
    CR12
    GPP_D14/ISH_UART0_TXD
    CM23 10B 4GB
    <51> EPRIVACY_ON GPP_C20/UART2_RXD GPP_D15/ISH_UART0_RTS#/GSPI2_CS1# -RFID_CARD_READ <89>
    CP12 CR24
    <55> TBT_FORCE_PWR GPP_C21/UART2_TXD GPP_D16/ISH_UART0_CTS#/SML0BALERT# -RFID_COIL_ACTIVE <89>
    CN12
    <85> -EC_SCI
    CM12 GPP_C22/UART2_RTS#
    CG12 11B N/A
    <85> -EC_WAKE GPP_C23/UART2_CTS# GPP_C12/UART1_RXD/ISH_UART1_RXD
    CH12
    GPP_C13/UART1_TXD/ISH_UART1_TXD
    CM11 CF12
    <89> I2C0_DATA CN11 GPP_C16/I2C0_SDA GPP_C14/UART1_RTS#/ISH_UART1_RTS#
    CG14
    <89> I2C0_CLK GPP_C17/I2C0_SCL GPP_C15/UART1_CTS#/ISH_UART1_CTS#
    CK12 BW35
    <52> -IR_CAM_DTCT GPP_C18/I2C1_SDA GPP_A18/ISH_GP0
    BW34
    CJ12
    <51> Size CTL GPP_C19/I2C1_SCL GPP_A19/ISH_GP1
    CA37
    GPP_A20/ISH_GP2
    CF27 CA36
    GPP_H4/I2C2_SDA GPP_A21/ISH_GP3
    CF29 CA35
    GPP_H5/I2C2_SCL GPP_A22/ISH_GP4
    CA34
    GPP_A23/ISH_GP5
    -MIC_HW_EN CH27 BW37
    GPP_H6/I2C3_SDA GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#
    CH28
    <52> -INT_MIC_DTCT GPP_H7/I2C3_SCL
    CJ30
    <67> WWAN_CFG0 GPP_H8/I2C4_SDA
    CJ31
    B <67> WWAN_CFG1 GPP_H9/I2C4_SCL B

    WHISKEYLAKE-U_BGA1528 6 of 20
    CPU@
    2
    2

    R0801 R0805
    1/20W_0_5%_0201
    1/20W_100K_5%_0201
    1
    1

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (6/16): LPSS/ISH
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 8 of 125

    5 4 3 2 1
    5 4 3 2 1

    TABLE : Functional Strap


    HDA_SDO/I2S0_TXD
    Flash Descriptor Security Override
    HIGH Disable Flash Descriptor Security (Override)
    LOW Enable Flash Descriptor Security (Default) LOGIC

    D D

    VCC3_SUS

    PLACE ON BOTTOM SIDE

    1 2 R 1 2
    R0904 1/20W_1K_5%_0201 R0908 1/10W_0_5%_0603
    @
    VCC3_SUS VCC3_SUS
    TP0901 TP0902
    Test_Point_20MIL Test_Point_20MIL
    1 1

    @ @

    2
    R0903
    TEST PAD
    @ 1/20W_1K_5%_0201 BOTTOM SIDE
    DO NOT MOVE AFTER FIX ?

    1
    UCPU1G
    R0901 1 2 1/20W_33_5%_0201 HDA_SYNC_CPU BN34 CH36
    <78> HDA_SYNC HDA_SYNC/I2S0_SFRM GPP_G0/SD_CMD
    EMC@ R0907 1 2 1/20W_33_5%_0201 HDA_BCLK_CPU BN37 CL35
    <78> HDA_BCLK HDA_BCLK/I2S0_SCLK GPP_G1/SD3_DATA0
    R0902 1 2 1/20W_33_5%_0201 HDA_SDO_CPU BN36 CL36
    <78> HDA_SDO BN35 HDA_SDO/I2S0_TXD GPP_G2/SD3_DATA1
    CM35
    C C
    <78> HDA_SDIN0 BL36 HDA_SDI0/I2S0_RXD GPP_G3/SD3_DATA2
    CN35
    HDA_SDI1/I2S1_RXD/SNDW1_DATA GPP_G4/SD_DATA3 TBT_RTD3_PWR_EN <55>
    2 2 BL35 CH35
    CK23 HDA_RST#/I2S1_SCLK/SNDW1_CLK GPP_G5/SD_CD#
    CK36 TBT_FORCE_USB_PWR <55>
    EMC@ EMC@
    GPP_D23/I2S_MCLK GPP_G6/SD_CLK -TBT_PERST <55>
    C0902 C0901 CK34
    GPP_G7/SD_WP -TBT_PCIE_WAKE <55>
    22P_25V_J_NPO_0201 22P_25V_J_NPO_0201 BL37
    1 1 I2S1_SFRM/SNDW2_CLK
    BL34
    I2S1_TXD/SNDW2_DATA -WWAN_ANTENNA <67>

    -CNV_RF_RESET CJ32
    <66> -CNV_RF_RESET GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#

    3
    R0905 1 @ 21/20W_0_5%_0201 NFC_ACTIVE_R CH32
    <89> NFC_ACTIVE CH29 GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
    CNV_CLKREQ Q0901
    <66> CNV_CLKREQ CH30 GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ
    LSK3541G1ET2L_VMT3
    GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO
    BW36 WWAN_ANT_SW 1
    GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

    2
    D_S_CONTROL CP24 BY31
    CN24 GPP_D19/DMIC_CLK0/SNDW4_CLK GPP_A16/SD_1P8_SEL -SC_DTCT <72>
    N_Y_CONTROL
    GPP_D20/DMIC_DATA0/SNDW4_DATA
    CK33
    SD_1P8_RCOMP
    CK25 CM34 SD_RCOMP R0906 1 2 1/20W_200_1%_0201
    <68> DDI_PRIORITY1 CJ25 GPP_D17/DMIC_CLK1/SNDW3_CLK SD_3P3_RCOMP
    GPP_D18/DMIC_DATA1/SNDW3_DATA
    PCH_SPKR CF35
    <83> PCH_SPKR GPP_B14/SPKR
    R0913
    WHISKEYLAKE-U_BGA1528 7 of 20
    1 2 CPU@
    <87> TOP_SWAP_EN

    0_0201_SP

    VCC3_SUS
    VCC3_SUS
    H:OOO
    H:DRIFT/IRONHIDE L:N19M-Q1
    L:JAZZ/SIDEWIPE
    1/20W_10K_5%_0201

    1/20W_100K_5%_0201
    2

    2
    R0909

    @ R0911

    B B
    1

    D_S_CONTROL N_Y_CONTROL
    1/20W_100K_5%_0201
    1/20W_100K_5%_0201

    2
    2

    X76@ R0910
    @ R0912

    1
    1

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (7/16): AUDIO/SDXC
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 9 of 125

    5 4 3 2 1
    5 4 3 2 1

    Flexible I/O Configuration


    PCIe Port Assignment USB 2.0 Port Assignment USB 3.0 Port Assignment SATA Port Assignment
    WHL Lake PCH-LP Premium - U CS19 T14/T15/P53s
    PCIE 1 Media Card Controller USB2_1 Smart Card USB3_1 SATA 0
    PCI HSIO Descriptor PCI
    PCIE 2 USB2_2 Type-C Port C USB3_2 Type-C Port C SATA 1A HSIO Port High Speed Signals Device
    Device Function Configuration for PCIe Device Function
    PCIE 3 USB2_3 Type-A Port (AOU) USB3_3 Type-A Port (AOU) SATA 1B
    Port 1 USB3 1 / PCIE 1 0h PCIE 1 Media Card Controller
    PCIE 4 USB2_4 Type-A Port (DCI) USB3_4 Type-A Port (Std.A) SATA 2 SATA SSD X2 4x1
    Port 2 USB3 2 / PCIE 2 1h USB3 2 Type-C Port (Gen1)
    PCIE 5 (x2) Alpine Ridge-DP USB2_5 TBT Type-C Port USB3_5 X4 1Ch LaneReversal
    Port 3 USB3 3 / PCIE 3 2h USB3 3 Type-A Port (AOU) Disabled
    PCIE 7 WWAN USB2_6 Touch Panel USB3_6 X2
    Port 4 USB3 4 / PCIE 4 3h USB3 4 Type-A Port (Gen1)
    PCIE 8 GbE WGI219 USB2_7 WWAN Card
    Port 5 USB3 5 / PCIE 5 4h PCIE 5*4 L0 Alpine Ridge - DP
    PCIE 9 (x4) Nvdia GPU USB2_8 RGB / IR Hybrid Camera X2 4x1
    Port 6 USB3 6 / PCIE 6 5h PCIE 5*4 L1 Alpine Ridge - DP
    D PCIE 13 (x4) NVMe SSD USB2_9 Fingerprint Reader X4 1Ch LaneReversal D
    Port 7 PCIE 7 (GbE) 6h WWAN Fibocom L850 Disabled
    USB2_10 (Reserved for Bluetooth) X2
    Port 8 PCIE 8 (GbE) 7h GbE WGI 219
    Port 9 PCIE 9 (GbE) 0h PCIE 9 x4 L0 NV N17S-G1 / G3
    X2 4x1
    Port 10 PCIE 10 1h PCIE 9 x4 L1 NV N17S-G1 / G3 LaneReversal
    X4 1Dh
    Port 11 PCIE 11 / SATA 0 2h PCIE 9 x4 L2 NV N17S-G1 / G3 Disabled
    X2
    Port 12 PCIE 12 / SATA 1A 3h PCIE 9 x4 L3 NV N17S-G1 / G3
    Port 13 PCIE 13 (GbE) 4h PCIE 13 x4 L3 Storage Lane 3
    X2 4x1
    Port 14 PCIE 14 (GbE) 5h PCIE 13 x4 L2 Storage Lane 2 LaneReversal
    X4 1Dh
    Port 15 PCIE 15 / SATA 1B 6h PCIE 13 x4 L1 Storage Lane 1 Enabled
    X2
    Port 16 PCIE 16 / SATA 2 7h PCIE 13 x4 L0 / SATA2 Storage Lane 0 / SATA

    VCC3_SUS

    1/20W_10K_5%_0201

    1/20W_10K_5%_0201
    1

    1
    R1001

    R1002
    C C

    2
    ?

    UCPU1H
    BW9 CB5
    <55> PCIE5_L0_RXN BW8 PCIE5_RXN/USB31_5_RXN PCIE1_RXN/USB31_1_RXN
    CB6 PCIE1_RXN <76>
    <55> PCIE5_L0_RXP BW4 PCIE5_RXP/USB31_5_RXP PCIE1_RXP/USB31_1_RXP
    CA4 PCIE1_RXP <76>
    <55> PCIE5_L0_TXN BW3 PCIE5_TXN/USB31_5_TXN PCIE1_TXN/USB31_1_TXN
    CA3 PCIE1_TXN <76>
    <55> PCIE5_L0_TXP PCIE5_TXP/USB31_5_TXP PCIE1_TXP/USB31_1_TXP PCIE1_TXP <76>
    BU6 BY8
    <55> PCIE5_L1_RXN BU5 PCIE6_RXN/USB31_6_RXN PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN
    BY9 USB3P2_RXN <61>
    <55> PCIE5_L1_RXP BU4 PCIE6_RXP/USB31_6_RXP PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP
    CA2 USB3P2_RXP <61>
    <55> PCIE5_L1_TXN BU3 PCIE6_TXN/USB31_6_TXN PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN
    CA1 USB3P2_TXN <61>
    <55> PCIE5_L1_TXP PCIE6_TXP/USB31_6_TXP PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP USB3P2_TXP <61>
    BT7 BY7
    <67> PCIE7_RXN BT6 PCIE7_RXN PCIE3_RXN/USB31_3_RXN BY6 USB3P3_RXN <70>
    <67> PCIE7_RXP BU2 PCIE7_RXP PCIE3_RXP/USB31_3_RXP
    BY4 USB3P3_RXP <70>
    <67> PCIE7_TXN BU1 PCIE7_TXN PCIE3_TXN/USB31_3_TXN BY3 USB3P3_TXN <70>
    <67> PCIE7_TXP PCIE7_TXP PCIE3_TXP/USB31_3_TXP USB3P3_TXP <70>
    BU9 BW6
    <73> PCIE8_RXN BU8 PCIE8_RXN PCIE4_RXN/USB31_4_RXN
    BW5 USB3P4_RXN <69>
    <73> PCIE8_RXP BT4 PCIE8_RXP PCIE4_RXP/USB31_4_RXP
    BW2 USB3P4_RXP <69>
    <73> PCIE8_TXN BT3 PCIE8_TXN PCIE4_TXN/USB31_4_TXN
    BW1 USB3P4_TXN <69>
    <73> PCIE8_TXP PCIE8_TXP PCIE4_TXP/USB31_4_TXP USB3P4_TXP <69>
    BP5 CE3
    <37> PCIE9_L0_RXN BP6 PCIE9_RXN USB2_1N
    CE4 USBP1- <72>
    <37> PCIE9_L0_RXP SWG@ C1000 1 2 0.22U_6.3V_K_X5R_0201 BR2 PCIE9_RXP USB2_1P USBP1+ <72>
    PCIE9_L0_TXN_C
    <37> PCIE9_L0_TXN BR1 PCIE9_TXN
    CE1
    SWG@ C1001 1 2 0.22U_6.3V_K_X5R_0201 PCIE9_L0_TXP_C
    <37> PCIE9_L0_TXP PCIE9_TXP USB2_2N USBC_USB2N <63>
    CE2
    USB2_2P USBC_USB2P <63>
    BN6
    <37> PCIE9_L1_RXN BN5 PCIE10_RXN
    CG3
    <37> PCIE9_L1_RXP BR4 PCIE10_RXP USB2_3N
    CG4 USBP3- <70>
    SWG@ C1002 1 2 0.22U_6.3V_K_X5R_0201 PCIE9_L1_TXN_C
    <37> PCIE9_L1_TXN BR3 PCIE10_TXN USB2_3P USBP3+ <70>
    SWG@ C1003 1 2 0.22U_6.3V_K_X5R_0201 PCIE9_L1_TXP_C
    B <37> PCIE9_L1_TXP PCIE10_TXP
    CD3 B
    USB2_4N USBP4- <69>
    BN10 CD4
    <37> PCIE9_L2_RXN BN8
    PCIE11_RXN/SATA0_RXN USB2_4P USBP4+ <69>
    <37> PCIE9_L2_RXP BN4 PCIE11_RXP/SATA0_RXP
    CG5
    SWG@ C1004 1 2 0.22U_6.3V_K_X5R_0201 PCIE9_L2_TXN_C
    <37> PCIE9_L2_TXN BN3 PCIE11_TXN/SATA0_TXN USB2_5N TBT_USB5N <62>
    SWG@ C1005 1 2 0.22U_6.3V_K_X5R_0201 PCIE9_L2_TXP_C CG6
    <37> PCIE9_L2_TXP PCIE11_TXP/SATA0_TXP USB2_5P TBT_USB5P <62>
    BL6 CC1
    <37> PCIE9_L3_RXN BL5 PCIE12_RXN/SATA1A_RXN USB2_6N
    CC2 USBP6- <51>
    <37> PCIE9_L3_RXP BN2
    PCIE12_RXP/SATA1A_RXP USB2_6P USBP6+ <51>
    SWG@ C1006 1 2 0.22U_6.3V_K_X5R_0201 PCIE9_L3_TXN_C
    <37> PCIE9_L3_TXN 1 2 0.22U_6.3V_K_X5R_0201 BN1 PCIE12_TXN/SATA1A_TXN
    CG8
    SWG@ C1007 PCIE9_L3_TXP_C
    <37> PCIE9_L3_TXP PCIE12_TXP/SATA1A_TXP USB2_7N
    CG9 USBP7- <67>
    USB2_7P USBP7+ <67>
    BK6
    <64> PCIE13_L3_RXN BK5 PCIE13_RXN
    CB8
    <64> PCIE13_L3_RXP BM4 PCIE13_RXP USB2_8N
    CB9 USBP8- <52>
    <64> PCIE13_L3_TXN BM3 PCIE13_TXN USB2_8P USBP8+ <52>
    <64> PCIE13_L3_TXP PCIE13_TXP
    CH5
    BJ6 USB2_9N
    CH6 USBP9- <89> VCC3_SUS
    <64> PCIE13_L2_RXN BJ5 PCIE14_RXN USB2_9P USBP9+ <89>
    <64> PCIE13_L2_RXP PCIE14_RXP
    BL2 CC3
    <64> PCIE13_L2_TXN PCIE14_TXN USB2_10N
    BL1 CC4
    <64> PCIE13_L2_TXP PCIE14_TXP USB2_10P

    1/20W_10K_5%_0201
    BG5 CC5 USB2_COMP R1003 1 2 1/20W_113_1%_0201
    <64> PCIE13_L1_RXN PCIE15_RXN/SATA1B_RXN USB2_COMP

    2
    BG6 CE8 USB2_ID R1004 1 2 1/20W_0_5%_0201
    <64> PCIE13_L1_RXP BL4 PCIE15_RXP/SATA1B_RXP USB2_ID

    R1006
    CC6 USB2_VBU R1005 1 2 1/20W_1K_5%_0201
    <64> PCIE13_L1_TXN PCIE15_TXN/SATA1B_TXN USB2_VBUSSENSE
    BL3
    <64> PCIE13_L1_TXP PCIE15_TXP/SATA1B_TXP
    CK6
    GPP_E9/USB2_OC0#/GP_BSSB_CLK
    BE5 CK5 NFC_INT
    <64> PCIE13_L0_SATA1_RXN

    1
    BE6 PCIE16_RXN/SATA2_RXN GPP_E10/USB2_OC1#/GP_BSSB_DI CK8 NFC_INT <89>
    <64> PCIE13_L0_SATA1_RXP PCIE16_RXP/SATA2_RXP GPP_E11/USB2_OC2# -USB_PORT4_OC2 <69>
    BJ4 CK9
    <64> PCIE13_L0_SATA1_TXN PCIE16_TXN/SATA2_TXN GPP_E12/USB2_OC3# -USB_PORT3_OC3 <70>
    BJ3
    <64> PCIE13_L0_SATA1_TXP PCIE16_TXP/SATA2_TXP
    CP8
    GPP_E4/DEVSLP0
    CR8 NFC_ON
    R1007 1 2 1/20W_100_1%_0201 GPP_E5/DEVSLP1 NFC_ON <89>
    PCIE_RCOMP_N CE6 PCIE_RCOMP_N GPP_E6/DEVSLP2
    CM8
    PCIE_RCOMP_P CE5 SATA1_DEVSLP <64>
    PCIE_RCOMP_P
    CN8
    CR28 GPP_E0/SATAXPCIE0/SATAGP0
    CM10
    GPP_H12/M2_SKT2/CFG_0 GPP_E1/SATAXPCIE1/SATAGP1 BDC_ON <66>
    CP28 CP10
    CN28 GPP_H13/M2_SKT2/CFG_1 GPP_E2/SATAXPCIE2/SATAGP2 -SATA_DTCT <64>

    1/20W_10K_5%_0201
    GPP_H14/M2_SKT2/CFG_2
    CM28 CN7
    GPP_H15/M2_SKT2/CFG_3 GPP_E8/SATALED#/SPI1_CS1#

    2
    A A
    AR3

    R1008
    RSVD37
    WHISKEYLAKE-U_BGA1528
    8 of 20
    CPU@

    1
    Security Classification LC Future Center Secret Data Title
    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (8/16): PCIE/USB/SATA
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 10 of 125
    5 4 3 2 1
    5 4 3 2 1

    TABLE : Functional Strap VCC3M VCC3_SUS VCC3_SUS

    GPP_H21 (XTAL Frequency Select)

    1/20W_100K_5%_0201

    1/20W_4.7K_5%_0201

    1/20W_10K_5%_0201
    HIGH 24.0MHz LOGIC

    2
    R1118

    R1113

    R1115
    LOW 38.4MHz (Default) @

    TABLE : Functional Strap

    1
    GPP_H23 (eSPI Flash Sharing Mode) GPD7 XTAL_FREQ_SELECT GPP_H23
    HIGH Master Attached Flash Sharing (MAFS) enabled
    D LOW Master Attached Flash Sharing (MAFS) disabled (Default) LOGIC D

    1/20W_10K_5%_0201

    1/20W_10K_5%_0201
    2

    2
    R1114

    R1116
    @

    1
    @

    TABLE : Functional Strap


    GPD7 (Reserved)
    VCC3_SUS
    External pull-up is required. Recommend 100 kohm.

    1/20W_4.7K_5%_0201
    2
    R1120
    @

    1
    CML_ME_DET
    UCPU1I
    <66> CNV_WR_D0N CNV_WR_D0N CR30
    <66> CNV_WR_D0P CNV_WR_D0N
    CNV_WR_D0P CP30 CN27
    CNV_WR_D0P GPP_H18/CPU_C10_GATE# -CPU_C10_GATE <15,95,120>
    <66> CNV_WR_D1N

    1/20W_10K_5%_0201
    CNV_WR_D1N CM30 CM27
    CNV_WR_D1N GPP_H19/TIMESYNC_0

    2
    <66> CNV_WR_D1P CNV_WR_D1P CN30
    CNV_WR_D1P

    R1121
    CF25 XTAL_FREQ_SELECT
    <66> CNV_WT_D0N GPP_H21 / XTAL_FREQ_SELECT
    CNV_WT_D0N CN32 CN26 @
    <66> CNV_WT_D0P CNV_WT_D0N GPP_H22
    CNV_WT_D0P CM32 CM26 GPP_H23
    CNV_WT_D0P GPP_H23
    C CK17 C

    1
    <66> CNV_WT_D1N GPP_F10
    CNV_WT_D1N CP33
    <66> CNV_WT_D1P CNV_WT_D1N
    CNV_WT_D1P CN33
    CNV_WT_D1P
    BV35 GPD7
    <66> CNV_WR_CLKN GPD7
    CNV_WR_CLKN CN31 CN20
    <66> CNV_WR_CLKP CNV_WR_CLKN GPP_F3 DGFX_PWRGD <37>
    CNV_WR_CLKP CP31
    CNV_WR_CLKP
    CG25
    <66> CNV_WT_CLKN GPP_D4/IMGCLKOUT0/BK4/SBK4
    CNV_WT_CLKN CP34 CH25
    <66> CNV_WT_CLKP CNV_WT_CLKN GPP_H20/IMGCLKOUT_1
    CNV_WT_CLKP CN34
    CNV_WT_CLKP
    CR20 PLANARID1
    GPP_F12/EMMC_DATA0
    CNV_WT_RCOMP CP32 CM20 PLANARID2
    CNV_WT_RCOMP_0 GPP_F13/EMMC_DATA1
    CR32 CN19 PLANARID3
    CNV_WT_RCOMP_1 GPP_F14/EMMC_DATA2
    CP20 CM19 MEMORYID0
    GPP_F0/CNV_PA_BLANKING GPP_F15/EMMC_DATA3
    -WWAN_RESET CK19 CN18 MEMORYID1
    <67> -WWAN_RESET CG17 GPP_F1 GPP_F16/EMMC_DATA4
    CR18
    -GPU_EVENT MEMORYID2
    <41> -GPU_EVENT GPP_F2 GPP_F17/EMMC_DATA5
    CP18 MEMORYID3
    GPP_F18/EMMC_DATA6
    CML_ME_DET CR14 CM18 MEMORYID4
    GPP_C8/UART0_RXD GPP_F19/EMMC_DATA7
    CP14
    GPP_C9/UART0_TXD
    CN14 CM16
    GPP_C10/UART0_RTS# GPP_F20/EMMC_RCLK
    CM14 CP16
    GPP_C11/UART0_CTS# GPP_F21/EMMC_CLK
    CR16 -INTRUDER_PCH <13>
    PLANARID0
    GPP_F11/EMMC_CMD
    GC6_FB_EN CJ17 CN16
    <41,116> GC6_FB_EN CH17 GPP_F8/CNV_MFUART2_RXD GPP_F22/EMMC_RESET#
    GPP_F9/CNV_MFUART2_TXD
    CK15 EMMC_RCOMP R1119 1 2 1/20W_200_1%_0201
    EMMC_RCOMP
    A4WP_PRESENT CF17
    GPP_F23/A4WP_PRESENT

    1/20W_100K_5%_0201
    1/20W_10K_5%_0201
    1/20W_150_1%_0201

    2
    2

    2
    WHISKEYLAKE-U_BGA1528
    SWG@ R1111

    9 of 20
    R1101

    R1117
    CPU@
    1
    1

    B B

    TABLE: MEMORYID
    U3301, U3302, U3303, U3304 Capacity
    MEMORYID[4:0] Vendor
    Part Number Component Qty Channel-0 Channel-1 At least MEMORYID0 PLANARID3
    04h (00100b) MT40A512M16LY-075:E 8Gbit SDP 4pcs 4GB SO-DIMM 4GB MEMORYID1 PLANARID2
    Micron MEMORYID2 PLANARID1
    05h (00101b) MT40A1G16KNR-075:E 16Gbit DDP 4pcs 8GB SO-DIMM 8GB MEMORYID3 PLANARID0
    MEMORYID4
    08h (01000b) K4A8G165WC-BCTD 8Gbit SDP 4pcs 4GB SO-DIMM 4GB

    1/20W_0_5%_0201
    1/20W_0_5%_0201

    1/20W_0_5%_0201
    1/20W_0_5%_0201
    1/20W_0_5%_0201
    1/20W_0_5%_0201

    1/20W_0_5%_0201
    1/20W_0_5%_0201

    1/20W_0_5%_0201
    2
    2
    2
    2

    2
    09h (01001b) Samsung K4AAG165WB-MCTD 16Gbit DDP 4pcs 8GB SO-DIMM 8GB

    2
    2

    2
    2
    X76@ R1110
    X76@ R1109
    X76@ R1107
    X76@ R1106

    X76@ R1108

    R1104
    R1103

    R1105
    R1102
    0Ah (01010b) K4ABG165WA-MCTD 32Gbit DDP 4pcs 16GB SO-DIMM 16GB

    @
    @ @ @
    0Ch (01100b) H5AN8G6NCJR-VKC 8Gbit SDP 4pcs 4GB SO-DIMM 4GB

    1
    1
    1
    1

    1
    SK hynix

    1
    1

    1
    1
    0Dh (01101b) H5ANAG6NAMR-UHC 16Gbit DDP 4pcs 8GB SO-DIMM 8GB

    TABLE: PLANARID

    PLANARID[3:0] PHASE
    A A
    0h (0000b) PRE-EVT
    0h (0000b) EVT
    1h (0001b) FVT
    2h (0010b) SIT
    Fh (1111b) SVT
    Security Classification LC Future Center Secret Data Title
    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (9/16): CSI-2/EMMC/CNVI
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 11 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    VCC3B
    2

    R1250
    1/20W_10K_5%_0201
    1

    -CLKREQ_PCIE9

    Co-Lay
    L1201 EMC_NS@
    XTAL24_IN 2 1 XTAL24_IN_R
    2 1

    XTAL24_OUT 3 4 XTAL24_OUT_R_R
    3 4
    C C
    EXC24CH900U_4P

    ?
    R1201 / R1202

    XTAL24_IN_R
    UCPU1J

    1
    AW2 AU1
    <76> -PCIE1_CLK_100M CLKOUT_PCIE_N_0 CLKOUT_ITPXDP_N
    AY3 AU2 R1205
    <76> PCIE1_CLK_100M CLKOUT_PCIE_P_0 CLKOUT_ITPXDP_P
    CF32 1/20W_200K_1%_0201
    <76> -CLKREQ_PCIE1 GPP_B5/SRCCLKREQ0#
    BT32
    GPD8/SUSCLK SUSCLK_32K <66,85> Y1201
    BC1
    <55> -PCIE5_CLK_100M

    2
    CLKOUT_PCIE_N_1

    2
    BC2 CK3 XTAL24_IN R1201 1 20_0201_SP R1206 1/20W_0_5%_0201 24MHZ_12PF_8Y24000034
    <55> PCIE5_CLK_100M CLKOUT_PCIE_P_1 XTAL_IN
    R1202 1 20_0201_SP 1 3
    CE32 CK2 XTAL24_OUT XTAL24_OUT_R_R 1 2 XTAL24_OUT_R
    <55> -CLKREQ_PCIE5 GPP_B6/SRCCLKREQ1# XTAL_OUT
    BD3 CJ1 CLK_BIASREF
    <64> -PCIE13_CLK_100M

    4
    CLKOUT_PCIE_N_2 CLK_BIASREF
    BC3 CM3 CNV_REFCLK_R R1207 1 20_0201_SP
    <64> PCIE13_CLK_100M CLKOUT_PCIE_P_2 CLKIN_XTAL CNV_REFCLK <66>
    CF30
    <64> -CLKREQ_PCIE13 GPP_B7/SRCCLKREQ2#
    1 2 8.2P_50V_C_COG_0201
    BN31 RTCX1 C1201
    RTCX1
    BH3 BN32 RTCX2
    <67> -PCIE7_CLK_100M CLKOUT_PCIE_N_3 RTCX2
    BH4
    <67> PCIE7_CLK_100M CLKOUT_PCIE_P_3

    1/20W_10M_5%_0201
    CE31 BR37 1 1
    <67> -CLKREQ_PCIE7 GPP_B8/SRCCLKREQ3# SRTCRST# -SRTCRST <20>

    2
    2
    BR34 C1202 C1203
    RTCRST# -RTCRST <17,20>

    R1203
    BA1 Y1202 15P_0201_25V8-J 15P_0201_25V8-J
    <73> -PCIE8_CLK_100M CLKOUT_PCIE_N_4

    1/20W_10K_5%_0201

    1/20W_60.4_1%_0201
    BA2

    6.8PC_25VC_C_NPOC_0201
    <73> PCIE8_CLK_100M CLKOUT_PCIE_P_4 32.768KHZ_9PF_9H03280012
    CE30 2 2
    <73> -CLKREQ_PCIE8 2

    1
    GPP_B9/SRCCLKREQ4#

    2
    2

    @ C1205

    1
    R1204
    R1208
    BE1
    <37> -PCIE9_CLK_100M CLKOUT_PCIE_N_5
    BE2
    <37> PCIE9_CLK_100M CLKOUT_PCIE_P_5 1 C1204 1 2 8.2P_50V_C_COG_0201
    CF31
    <37> -CLKREQ_PCIE9 GPP_B10/SRCCLKREQ5#

    1
    1
    10 of 20
    WHISKEYLAKE-U_BGA1528
    CPU@

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (10/16): CLOCK SIGNALS
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 12 of 125
    5 4 3 2 1
    5 4 3 2 1

    TABLE of U1301
    Vendor P/N LCFC P/N
    ON NL17SZ17XV5T2G SA00005OU00
    TOSHIBA TC7SG17FE SA00005T00J
    TI SN74LVC1G17DRLR SA00005MG00

    VCC3M

    D D

    U1301
    5 1
    Vcc NC
    R1301 1 2 1/20W_33_5%_0201 U1301
    <37,64,67,73,85,93,94> -PLTRST_FAR
    2 -PLTRST
    IN A

    R1302 1 2 1/20W_33_5%_0201 4 3
    <55,76,98> -PLTRST_NEAR OUT GND

    NL17SZ17XV5T2G_SON-5

    2 2 2
    C1304 EMC@ C1301 C1302
    0.1U_6.3V_K_X5R_0201 100P_25V_J_NPO_0201 100P_25V_J_NPO_0201
    1 1 1

    VCC3M VCC3M
    RTCVCC VCC3M

    1/20W_1M_1%_0201

    1/20W_10K_5%_0201
    1

    2
    C C

    R1303

    @ R1304
    1/20W_4.7K_5%_0201

    2
    2
    R1307,R1308,R1309,R1310,R1311,R1312 ?

    R1305
    EVT FVT SIT SVT R1306

    1
    Resistor V 1/20W_1K_5%_0201
    R-short
    UCPU1K

    1
    1
    BJ35 BJ37
    CN10 GPP_B13/PLTRST# GPP_B12/SLP_S0#
    BU36 -PCH_SLP_S0 <17,108,120>
    <17,19> -XDP_DBR BR36 SYS_RESET# GPD4/SLP_S3#
    BU27 -PCH_SLP_S3 <17,55,86,94,95>
    <19,94> -RSMRST RSMRST# GPD5/SLP_S4#
    BT29 -PCH_SLP_S4 <17,86,94,112>
    AR2 GPD10/SLP_S5# -PCH_SLP_S5 <17,94>
    TP1301Test_Point_20MIL 1 CPU_PWRGD
    PROCPWRGD
    VCCST_PWRGD BJ2 BU29
    VCCST_PWRGOOD SLP_SUS#
    BT31 -PCH_SLP_SUS <86,95>
    R1307 1 2 0_0201_SP CR10 SLP_LAN#
    BT30 -PCH_SLP_LAN <94>
    BPWRG_R
    <86,89,93,95> BPWRG R1308 1 2 0_0201_SP BP31 SYS_PWROK GPD9/SLP_WLAN#
    BU37 -PCH_SLP_WLAN <86>
    CPUCORE_PWRGD_R
    <108> CPUCORE_PWRGD BP30 PCH_PWROK GPD6/SLP_A# -PCH_SLP_M <17,94>
    MPWRG R1309 1 2 0_0201_SP MPWRG_R
    <94,95> MPWRG DSW_PWROK
    BU28
    GPD3/PWRBTN# -PWRSW_EC <64,86>
    -SUSWARN BV34 BU35
    GPP_A13/SUSWARN#/SUSPWRDACK GPD1/ACPRESENT AC_PRESENT <86>
    R1310 1 2 0_0201_SP -SUSWARN_N BY32 BV36
    GPP_A15/SUSACK# GPD0/BATLOW# -BATLOW <55,87>
    BU30
    <55,67,76,94> -PCIE_WAKE BU32 WAKE#
    BR35 -INTRUDER
    <73> -LANWAKE BU34 GPD2/LAN_WAKE# INTRUDER#
    <73> LANPHYPC GPD11/LANPHYPC
    CC37 GPP_B11
    GPP_B11/EXT_PWR_GATE#
    CC36

    0.1U_6.3V_K_X5R_0201
    GPP_B2/VRALERT# 1

    EMC_HC@ C1303
    1 0.1U_6.3V_K_X5R_0201
    EMC_HC@ C1305

    BT27 INPUT3VSEL
    INPUT3VSEL
    2
    2
    WHISKEYLAKE-U_BGA1528
    11 of 20
    CPU@
    R1311
    1 2 -INTRUDER_PCH_R -INTRUDER_R
    <11> -INTRUDER_PCH

    4
    B B
    0_0201_SP
    R1312
    S1301
    SPVR310200_4P 1 2

    @
    R1317 1 2 1/20W_10K_5%_0201 CPUCORE_PWRGD 0_0201_SP
    @
    R1318 1 2 1/20W_10K_5%_0201 MPWRG D5:SCS00007M00(RB520CM)

    3
    @
    R1319 1 2 1/20W_10K_5%_0201 BPWRG

    VCC3_SUS VCCST
    VCC3_SUS VCC3_SUS

    Check list Suggest


    2
    2

    1/20W_100K_5%_0201
    1/20W_4.7K_5%_0201

    2
    2
    R1313 R1314

    R1320
    R1315
    1/20W_10K_5%_0201 1/20W_1K_5%_0201
    @
    1
    1

    TABLE : Functional Strap

    1
    1
    INPUT3VSEL (3.0V Select) Q1302 Q1301 1 2 VCCST_PWRGD INPUT3VSEL
    HIGH 3.3V supply is 3.0V +/- 5% R1321 GPP_B11
    1/20W_62_5%_0201
    LOW 3.3V supply is 3.3V +/- 5% LOGIC

    1/20W_4.7K_5%_0201
    2
    3
    3

    R1316
    Q1302 Q1301
    TABLE : Functional Strap CPUCORE_ON 1 LSK3541G1ET2L_VMT3 1 LSK3541G1ET2L_VMT3
    <94,108> CPUCORE_ON
    2
    2

    1
    INTRUDER# (SPI Voltage Configuration)
    A A
    HIGH SPI Voltage is 1.8V (Default)

    LOW SPI Voltage is 3.3V

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (11/16): SYSTEM PM
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    C
    Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 13 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCCCPUCORE VCCCPUCORE
    VccGT PDG LCFC
    47uF_0805 4 HW:0/PWR:0
    22uF_0603 15 HW:0/PWR:24

    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402
    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402
    10uF_0402 15 HW:5/PWR:10
    2 2 2 2 2 2 2 2 2 @2 @2 @2 @2 @2
    C1401
    1uF_0402/0201 11 HW:0/PWR:10

    C1402

    C1403

    C1405

    C1406

    C1408

    C1413

    C1414
    C1404

    C1407

    C1409

    C1410

    C1411

    C1412
    D D
    1 1 1 1 1 1 1 1 1 1 1 1 1 1
    VccCORE PDG PDG
    47uF_0805 18 HW:0/PWR:0
    22uF_0603 9 HW:0/PWR:24
    10uF_0402 22 HW:0/PWR:10
    1uF_0402/0201 42 HW:9/PWR:10

    VCCCPUCORE VCCGFXCORE_I VCCGFXCORE_I


    ?

    VCCCPUCORE
    VCCCPUCORE
    UCPU1M
    C ? C
    A5 D15
    VCCGT8 VCCGT58
    A6 D17
    VCCGT9 VCCGT59
    A8 D18
    VCCGT10 VCCGT60
    A11 D20 UCPU1L
    VCCGT1 VCCGT61
    A12 E4 AN9 AW24
    VCCGT2 VCCGT64 VCCCORE5 VCCCORE35
    A14 F5 AN10 AW25
    VCCGT3 VCCGT69 VCCCORE1 VCCCORE36
    A15 F6 AN24 AW26
    VCCGT4 VCCGT70 VCCCORE2 VCCCORE37
    A17 F7 AN26 AW27
    VCCGT5 VCCGT71 VCCCORE3 VCCCORE38
    A18 F8 AN27 AY24
    VCCGT6 VCCGT72 VCCCORE4 VCCCORE44
    A20 F11 AP2 AY26
    VCCGT7 VCCGT65 VCCCORE6 VCCCORE45
    AA9 F14 AP9 BA5
    VCCCORE75 VCCGT66 VCCCORE9 VCCCORE48
    AB2 F17 AP24 BA7
    VCCCORE76 VCCGT67 VCCCORE7 VCCCORE49
    AB8 F20 AP26 BA8
    VCCCORE77 VCCGT68 VCCCORE8 VCCCORE50
    AB9 G11 AR5 BA25
    VCCCORE78 VCCGT73 VCCCORE13 VCCCORE46
    AB10 G12 AR6 BA27
    VCCCORE79 VCCGT74 VCCCORE14 VCCCORE47
    AC8 G14 AR7 BB2 VCCST
    VCCCORE80 VCCGT75 VCCCORE15 VCCCORE51
    AD9 G15 AR8 BB26
    VCCCORE81 VCCGT76 VCCCORE16 VCCCORE52
    AE8 G17 AR10 BC5
    VCCCORE82 VCCGT77 VCCCORE10 VCCCORE56
    AE9 G18 AR25 BC6
    VCCCORE83 VCCGT78 VCCCORE11 VCCCORE57
    AE10 G20 AR27 BC7
    VCCCORE84 VCCGT79 VCCCORE12 VCCCORE58
    AF2 H5 AT9 BC9
    VCCCORE85 VCCGT87 VCCCORE19 VCCCORE59
    AF8 H6 AT24 BC10
    VCCCORE86 VCCGT88 VCCCORE17 VCCCORE53
    AF10 H7 AT26 BC26
    VCCCORE87 VCCGT89 VCCCORE18 VCCCORE54
    AG8 H8 AU5 BC27 VCCCPUCORE
    VCCCORE88 VCCGT90 VCCCORE24 VCCCORE55
    AG9 H11 AU6 BD5
    VCCGT80

    1
    VCCCORE89 VCCCORE63

    1
    VCCCORE25

    1
    AH9 H12 AU7 BD8
    VCCCORE90 VCCGT81 VCCCORE26 VCCCORE64
    AJ8 H14 AU8 BD10 @
    VCCCORE91 VCCGT82 VCCCORE27 VCCCORE60
    AJ10 H15 AU9 BD25 R1403 R1404 R1405
    VCCCORE92 VCCGT83 VCCCORE28 VCCCORE61
    AK2 H17 AU24 BD27
    VCCCORE93 VCCGT84 VCCCORE20 VCCCORE62
    AK9 H18 AU25 BE9

    2
    VCCGT85

    2
    VCCCORE94

    2
    VCCCORE21 VCCCORE69

    1
    AL8 H20 AU26 BE24
    VCCCORE95 VCCGT86 VCCCORE22 VCCCORE65

    1/20W_56_5%_0201
    AL9 J7

    1/20W_100_5%_0201
    AU27 BE25

    1/20W_100_5%_0201
    VCCGT95
    R1406
    VCCCORE96 J8 VCCCORE23 VCCCORE66
    AL10 AV2 BE26 1/20W_100_1%_0201
    VCCCORE97 VCCGT96 VCCCORE30 VCCCORE67
    AM8 J11 AV5 BE27
    VCCCORE98 VCCGT91 VCCCORE32 VCCCORE68
    B3 J14 AV7 BF2
    VCCGT39 VCCGT92

    2
    B4 J17 VCCCORE33 VCCCORE70
    AV10 BF9
    VCCGT40 VCCGT93 VCCCORE29 VCCCORE73
    B6 J20 AV27 BF24
    VCCGT41 VCCGT94 VCCCORE31 VCCCORE71
    B8 K2 AW5 BF26
    VCCGT42 VCCGT98 VCCCORE39 VCCCORE72
    B B11 K11 AW6 BG27 B
    VCCGT35 VCCGT97 VCCCORE40 VCCCORE74
    B14 L7 AW7
    VCCGT36 VCCGT100 VCCCORE41
    B17 L8 AW8 AN6 VCC_SENSE
    VCCGT37 VCCGT101 VCCCORE42 VCC_SENSE VCC_SENSE <108>
    B20 L10 AW9 AN5 VSS_SENSE
    VCCGT38 VCCGT99 VCCCORE43 VSS_SENSE VSS_SENSE <108>
    C2 M9 AW10
    VCCGT49 VCCGT102 VCCCORE34
    C3 N7 AA3 R1407 1 2 1/20W_220_5%_0201 -SVID_ALERT
    VCCGT51 VCCGT104 VIDALERT# -SVID_ALERT <108>
    C6 N8 BB9
    VCCGT52 VCCGT105 RSVD3
    C7 N9 BC24 AA1 SVID_CLK
    VCCGT53 VCCGT106 RSVD4 VIDSCK SVID_CLK <108>
    C8 N10 AY9
    VCCGT54 VCCGT103 RSVD1
    C11 P2 BB24 AA2 SVID_DATA
    VCCGT43 VCCGT107 RSVD2 VIDSOUT SVID_DATA <108>
    C12 P8
    VCCGT44 VCCGT108

    1
    C14 R9 Y3 VCCSTG
    VCCGT45 VCCGT109 RSVD5
    C15 T8 R1408
    VCCGT46 VCCGT111
    C17 T9 VCCGFXCORE_I BG3 1/20W_100_1%_0201
    VCCGT47 VCCGT112 VCCSTG1
    C18 T10 VCCCPUCORE
    VCCGT48 VCCGT110
    C20 U8
    VCCGT50 VCCGT114

    2
    1

    D4 U10
    VCCGT62 VCCGT113 12 of 20
    D7 V2 WHISKEYLAKE-U_BGA1528
    VCCGT63 VCCCORE100
    D11 V9 R1409
    VCCGT55 VCCGT116 CPU@
    D12 W8 1/20W_100_1%_0201
    VCCGT56 VCCGT117
    D14 W9
    VCCGT57 VCCGT118
    2

    Y10 Y8
    VCCCORE99 VCCCORE101
    E3 VCCGT_SENSE
    VCCGT_SENSE VCCGT_SENSE <108>
    D2 VSSGT_SENSE
    VSSGT_SENSE VSSGT_SENSE <108>
    13 of 20
    1

    WHISKEYLAKE-U_BGA1528
    CPU@
    R1410
    1/20W_100_1%_0201
    2

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (12/16): CPU POWER (1/2)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 14 of 125

    5 4 3 2 1
    5 4 3 2 1

    VccSA PDG LCFC


    VCCIO VCCIO VCCSA VCCSA VCCSA VCCST
    VCCSTG 47uF_0805 2 HW:0/PWR:0
    22uF_0805 0 HW:0/PWR:8
    10uF_0402 13 HW:6/PWR:7
    1uF_0402 0 HW:6/PWR:7

    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    10U_6.3V_M_X5R_0402

    22U_6.3V_M_X5R_0603
    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402
    1U_6.3V_M_X5R_0201

    1U_6.3V_M_X5R_0201
    1U_6.3V_M_X5R_0201
    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    2 2 2 2 @2 @2 @2 @2 @2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

    @ C1504
    C1501

    C1502

    C1514

    @ C1526

    @ C1527
    C1508

    C1516

    C1518

    C1529

    C1530

    C1531
    C1509
    C1507
    C1505

    C1512
    C1503

    C1511
    C1506

    C1510

    C1528

    C1532
    D 2 2 2 2 2 2 VDDQ PDG LCFC D

    C1520

    C1521
    C1519

    C1525
    C1524
    C1523
    C1522
    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 @1 1 1 @1 @1 1 1 1 47uF_0805 0 HW:0/PWR:0
    1 1 1 1 1 1
    22uF_0805 1 HW:4/PWR:6
    10uF_0402 9 HW:9/PWR:0
    1uF_0402 4 HW:0/PWR:0

    VccIO PDG LCFC


    47uF_0805 0 HW:0/PWR:0
    22uF_0805 0 HW:0/PWR:4
    VCC1R2A
    10uF_0402 6 HW:0/PWR:0
    VCCSFR_OC 1uF_0402 4 HW:3/PWR:0

    VccPLL PDG LCFC


    1uF_0402 1 HW:2/PWR:0
    0.1uF_0201 1 HW:0/PWR:0
    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402

    1U_6.3V_K_X5R_0402
    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402

    2 2 2 2 2 2 2 2 2 2 2 2 2 2 VccPLL_OC PDG LCFC


    C1538

    C1540

    C1546
    C1536

    C1537

    C1539

    C1541

    C1544
    C1543

    C1545
    C1542

    1uF_0402 1 HW:1/PWR:0
    C1535
    C1533

    C1534

    1 1 1 1 1 1 1 1 1 1 1 1 1 1

    C C

    VCCIO

    VCC1R2A ?

    UCPU1N
    AK24
    VCCIO1
    AD36 AK26
    VDDQ1 VCCIO2
    AH32 AL24
    VDDQ2 VCCIO3
    R1501 AH36 AL25
    VDDQ3 VCCIO4
    EVT FVT SIT SVT AM36 AL26
    VDDQ4 VCCIO5
    Resistor V AN32 AL27
    VDDQ5 VCCIO6
    R-short AW32 AM25
    VDDQ6 VCCIO7
    AY36 AM27
    VDDQ7 VCCIO8
    BE32 BH24
    VDDQ8 VCCIO9
    BH36 BH25
    VCCSFR_OC VCCST R32 VDDQ9 VCCIO10
    BH26
    VCC3M VCC1R2A VCCSFR_OC VCCSTG Y36 VDDQ10
    VDDQ11
    VCCIO11
    VCCIO12
    BH27
    BJ24 VCCSA
    VCCIO13
    BJ26
    R1501 VCCIO14
    BP16
    VCCIO15
    1 2 BC28 BP18
    RSVD1 VCCIO16
    BP11 BG8
    0_1%_0603_LE VCCST1 VCCSA2
    1

    BP2 BG10
    VCCST2 VCCSA1
    @ R1506 BH9
    VCCSA3
    1/16W_10K_1%_0402 BJ8
    VCCSA5
    BG1 BJ9 VCCIO VCCSA
    VCCSTG1 VCCSA6
    BG2 BJ10
    2

    VCCSTG2 VCCSA4
    A2 A1 BK8
    VIN1 VOUT1 VCCSA9
    BL27 BK25
    VCCPLL_OC1 VCCSA7
    B2 B1 BM26 BK27
    VIN2 VOUT2 VCCPLL_OC2 VCCSA8
    BL8
    VCCSA13

    1
    C2 C1 BR11 BL9
    CT PG VCCPLL1 VCCSA14
    BT11 BL10 R1502 R1503
    VCCPLL2 VCCSA10
    B @ D1501 1 2 RB521CM-30T2R_VMN2M-2 ON D2 D1 BL24 1/20W_100_1%_0201 1/20W_100_1%_0201 B
    <94,112,120> A_ON ON GND VCCSA11
    BL26
    VCCSA12
    @ U1501 BM24

    2
    VCCSA15
    @ D1502 1 2 RB521CM-30T2R_VMN2M-2 TPS22971YZPT_DSBGA8 BN25
    <11,95,120> -CPU_C10_GATE VCCSA16
    BP28 VCCIO_SENSE
    VCCIO_SENSE
    BP29 VSSIO_SENSE
    VSSIO_SENSE
    BE7 VSSSA_SENSE
    VSSSA_SENSE
    BG7 VSSSA_SENSE <108>
    VCCSA_SENSE
    VCCSA_SENSE VCCSA_SENSE <108>
    1 1
    @ C1547 14 of 20
    @ C1548

    1
    0.1UC_6.3VC_KC_X7RC_0402 WHISKEYLAKE-U_BGA1528
    10U_6.3V_M_X5R_0402
    CPU@ R1504 R1505
    2 2 1/20W_100_1%_0201 1/20W_100_1%_0201

    2
    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (13/16): CPU POWER (2/2)
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 15 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC3M
    VCC3M_PCH
    R1601
    VCCDPHY_1P24 VCCDSW_1P05 VCC1R05_SUS_PRIM VCC1R8_SUS_PRIM VCC3_SUS_PRIM RTCVCC VCC3M_PCH VCCRTCEXT
    1 2

    0.1U_6.3V_K_X5R_0201
    0.1U_6.3V_K_X5R_0201
    VCC3_SUS VCC3_SUS_PRIM 2 2
    0_1%_0603_LE

    C1605
    1U_6.3V_K_X5R_0402
    C1604
    R1602
    4.7U_6.3V_M_X5R_0402 1 1 1 2 1 1 2 1 2 1

    C1601

    C1602

    C1603

    C1606
    1U_6.3V_K_X5R_0402

    C1609

    C1616
    1U_6.3V_K_X5R_0402
    C1607

    C1617

    C1608
    1U_6.3V_K_X5R_0402
    1 2

    47UC_6.3VC_MC_X5RC_0805C_H1.25

    47UC_6.3VC_MC_X5RC_0805C_H1.25

    47UC_6.3VC_MC_X5RC_0805C_H1.25

    47UC_6.3VC_MC_X5RC_0805C_H1.25
    1 1 C1612
    0_1%_0603_LE 0.1U_6.3V_K_X5R_0201
    VCC1R8_SUS VCC1R8_SUS_PRIM 2 2 2 1 2 2 1 2 1 2
    R1603
    1 2
    D D
    VCC1R05_SUS VCC1R05_SUS_PRIM
    0_1%_0603_LE
    R1604 Near pin CP25
    1 2

    0_1%_0603_LE

    R1601,R1602,R1603,R1604
    EVT FVT SIT SVT
    Resistor V
    R-short

    VCC1R05_SUS VCC1R05_SUS_XTAL

    L1601 1 2MMZ0603AFY560VT_2P

    @ VCC1R05_SUS_PRIM VCC3_SUS_PRIM
    22UC_4VC_MC_X5RC_0402
    22UC_4VC_MC_X5RC_0402

    R1606
    2 2 2
    C1611
    1U_6.3V_K_X5R_0402

    1 2 UCPU1P ?
    @C1619
    @C1618

    VCC1R05_SUS_PRIM RTCVCC VCCRTCEXT


    BP20
    0_1%_0603_LE 1 1 1 BW16 VCCPRIM_1P051
    CB16
    VCCPRIM_1P059 VCCPRIM_3P33
    BW18
    VCCPRIM_1P0510
    VCC1R8_SUS_PRIM BW19
    VCCPRIM_1P0511
    BY16
    VCCPRIM_1P0512
    C CA14 BR23 C
    VCCPRIM_1P0514 VCCRTC
    CC15 BY20
    VCCPRIM_1P81 VCCPRIM_1P0513
    VCC3_SUS_PRIM CD15 BP24
    VCCPRIM_1P84 DCPRTC
    CD16
    VCCPRIM_1P85
    CP17
    VCCPRIM_1P88
    VCC1R05_SUS VCC1R05_SUS_AMP BR20
    VCCPRIM_1P053
    CB22
    VCCPRIM_3P34
    CB23 BT12
    VCCPRIM_3P35 VCCAPLL_1P053
    L1602 1 2MMZ0603AFY560VT_2P CC22
    VCCPRIM_3P36
    CC23 BP14
    VCCPRIM_3P37 VCCA_BCLK_1P05
    47U_6.3V_M_X5R_0603

    @ CD22 VCC1R05_SUS_XTAL
    VCCPRIM_3P38
    VCC1R05_SUS CD23 BR14
    R1607 VCCPRIM_3P39 VCCAPLL_1P051
    1 2 CP29
    VCCPRIM_3P310
    @ C1613

    C1614
    1U_6.3V_K_X5R_0402

    1 2 BU12
    VCCA_SRC_1P05
    BU15
    VCCPRIM_CORE1
    BU22 CP5
    0_1%_0603_LE 2 1 BV15 VCCPRIM_CORE2 VCCA_XTAL_1P05
    VCCPRIM_CORE3
    BV16 BY24 VCCLDOSRAM_1P24 1 TP1601
    VCCPRIM_CORE4 VCCDPHY_1P242 Test_Point_12MIL
    BV18 CA24
    VCCPRIM_CORE5 VCCDPHY_1P244
    BV19
    VCCPRIM_CORE6
    2 BV20 BY23 VCC3M_PCH VCC1R05_SUS_PRIM
    VCCPRIM_CORE7 VCCDPHY_1P241
    C1615
    1U_6.3V_K_X5R_0402

    BV22 CA23
    VCCPRIM_CORE8 VCCDPHY_1P243
    BW20 CP25 VCCDPHY_1P24
    VCCPRIM_CORE9 VCCDPHY_EC_1P24
    BW22
    1 VCCPRIM_CORE10
    CA12 BT23
    VCCPRIM_CORE11 VCCDSW_3P32
    CA16
    VCCPRIM_CORE12
    CA18 BR12
    VCCPRIM_CORE13 VCCA_19P2_1P05
    CA19
    VCCPRIM_CORE14
    CA20 VCC1R8_SUS_PRIM VCC3_SUS_PRIM
    VCCPRIM_CORE15
    CB12
    VCCPRIM_CORE16
    VCC1R05_SUS_PRIM CB14
    VCCPRIM_CORE17
    CB15 CC18
    VCCPRIM_CORE18 VCCPRIM_1P82
    VCCDSW_1P05 BT24 CC19
    VCCDSW_1P05 VCCPRIM_1P83
    VCC1R05_SUS_AMP CD18
    VCCPRIM_1P86
    BU14 CD19
    VCCAPLL_1P054 VCCPRIM_1P87
    CP23
    VCCPRIM_1P89
    BV12
    VCCPRIM_MPHY_1P051
    BW12 BW23
    B VCCPRIM_MPHY_1P053 VCCPRIM_3P32 B
    BW14
    VCCPRIM_MPHY_1P054
    BY12
    VCCPRIM_MPHY_1P055
    BY14
    VCCPRIM_MPHY_1P056
    BV2 BP23
    VCCAMPHYPLL_1P05 VCCPRIM_3P31
    VCC3_SUS_PRIM VCC3M_PCH BR15 CB36
    VCCAPLL_1P052 GPP_B0/CORE_VID0
    VCC1R05_SUS_PRIM CB35
    GPP_B1/CORE_VID1
    CC12
    VCCDUSB_1P05
    BR24
    VCCDSW_3P31
    BT20
    VCCHDA
    BV23
    VCCSPI
    BT18
    VCCPRIM_1P054
    BT19
    BU18 VCCPRIM_1P055
    VCCPRIM_1P057
    BU19
    VCCPRIM_1P058
    BT22
    VCCPRIM_1P056
    BP22
    VCCPRIM_1P052
    BV14
    VCCPRIM_MPHY_1P052

    16 of 20
    WHISKEYLAKE-U_BGA1528
    CPU@

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (1/16): DDI/TYPE-C
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 16 of 125
    5 4 3 2 1
    5 4 3 2 1

    APS/PETS Interface
    J1701
    VCC3_SUS VCC3M FCI_10051922-1810ELF

    18 20
    NC1 PEG2
    17 19
    NC2 PEG1
    16
    NC3
    15
    <13,108,120> -PCH_SLP_S0 14 SLP_S0#
    GND1
    D 13 D
    <13,19> -XDP_DBR 12 SYS_RESET#
    GND2
    11
    <51,62,93,94> -PWRSWITCH 10 PWRBTN#
    GND3
    9
    <12,20> -RTCRST 8 RTCRST#
    GND4
    7
    +V3.3DS
    6
    <13,94> -PCH_SLP_M 5 SLP_A#
    <13,86,94,112> -PCH_SLP_S4 4 SLP_S4#
    <13,94> -PCH_SLP_S5 3 SLP_S5#
    VccDSW3_3
    2
    <13,55,86,94,95> -PCH_SLP_S3 1 SLP_S3#
    VccSus3_3

    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201
    1 1 @

    EMC_HC@ C1701

    EMC_HC@ C1702
    2 2
    ?
    ?

    ?
    UCPU1R
    UCPU1T
    1 CR34 CR34 BL7
    VSS_1 VSS_73 N6 CF23 UCPU1S
    @ TP1702 BT5 AE25 VSS_290 VSS_362
    VSS_2 VSS_74 B37 V4
    Test_Point_20MIL BY5 BM33 VSS_291 VSS_363 BT35 BY25
    VSS_3 VSS_75 CB3 BE30 VSS_145 VSS_217
    CP35 CM5 VSS_292 VSS_364 D6 J18
    VSS_4 VSS_76 P10 CF28 VSS_146 VSS_218
    CM37 AE27 VSS_293 VSS_365 AL32 AU32
    VSS_5 VSS_77 B5 W10 VSS_147 VSS_219
    CK37 BM35 VSS_294 VSS_366 BT36 BY28
    AW1 VSS_6 VSS_78
    CM9 CB33 BE31 VSS_148 VSS_220
    VSS_295 VSS_367 D8 J21
    CM1 VSS_7 VSS_79 P3 CF3 VSS_149 VSS_221
    AE30 VSS_296 VSS_368 AL7 AV25
    BD6 VSS_8 VSS_80 B7 W27 VSS_150 VSS_222
    BM36 VSS_297 VSS_369 D9 BY33
    VSS_9 VSS_81 CB4 CF4 VSS_151 VSS_223
    AY4 CN13 VSS_298 VSS_370 AM10 J24
    VSS_10 VSS_82 P33 W30 VSS_152 VSS_224
    B34 AE7 VSS_299 VSS_371 BU11 AV28
    VSS_11 VSS_83 B9 BF3 VSS_153 VSS_225
    E35 BM9 VSS_300 VSS_372 E23 BY35
    VSS_12 VSS_84 CB7 CG33 VSS_154 VSS_226
    A4 CN17 VSS_301 VSS_373 AM28 J33
    VSS_13 VSS_85 P36 W7 VSS_155 VSS_227
    AE24 AF27 VSS_302 VSS_374 E27 AV3
    C VSS_14 VSS_86 BA10 BF33 VSS_156 VSS_228 C
    AE26 BN30 VSS_303 VSS_375 AM33 BY36
    VSS_15 VSS_87 CC11 CG7 VSS_157 VSS_229
    AF25 CN21 VSS_304 VSS_376 BU23 J36
    VSS_16 VSS_88 P4 BF36 VSS_158 VSS_230
    AG24 AF3 VSS_305 VSS_377 E29 AV33
    AG26 VSS_17 VSS_89 BA28 Y26 VSS_159 VSS_231
    BN7 VSS_306 VSS_378 AM35 J6
    VSS_18 VSS_90 P7 BF4 VSS_160 VSS_232
    AH24 CN25 VSS_307 VSS_379 BU24 AV36
    VSS_19 VSS_91 BA3 CH31 VSS_161 VSS_233
    AH25 AF30 VSS_308 VSS_380 E31 C1 C1 1
    VSS_20 VSS_92 CC20 Y27 VSS_162 VSS_234
    B2 CN29 VSS_309 VSS_381 BU25 K21
    VSS_21 VSS_93 R27 BG25 VSS_163 VSS_235
    B36 AF33 VSS_310 VSS_382 E33 AV4 @ TP1706
    VSS_22 VSS_94 BB3 Y30 VSS_164 VSS_236
    C36 BP15 VSS_311 VSS_383 AN25 C21 Test_Point_20MIL
    VSS_23 VSS_95 CC25 BG28 VSS_165 VSS_237
    C37 AF36 VSS_312 VSS_384 BU7 K22
    1 VSS_24 VSS_96 R28 CJ11 VSS_166 VSS_238
    CN1 CN1 AF4 VSS_313 VSS_385 E9 AV6
    VSS_25 VSS_97 BB33 Y33 VSS_167 VSS_239
    @ TP1708 CN2 CN5 VSS_314 VSS_386 AN28 C25
    VSS_26 VSS_98 CC28 CJ14 VSS_168 VSS_240
    Test_Point_20MIL CN37 AF7 VSS_315 VSS_387 BV11 K24
    VSS_27 VSS_99 R29 Y35 VSS_169 VSS_241
    CP2 BP25 VSS_316 VSS_388 F12 AV8
    D1 VSS_28 VSS_100
    CN9 BB36 BH28 VSS_170 VSS_242
    1 D1 VSS_317 VSS_389 AN29 C29
    1 VSS_29 VSS_101
    AG10 CC31 CJ19 VSS_171 VSS_243
    @ TP1705 A32 A32 VSS_318 VSS_390 F15 K25
    VSS_30 VSS_102 R30 Y7 VSS_172 VSS_244
    Test_Point_20MIL @ TP1703 F33 BP3 VSS_319 VSS_391 AN30 AW28
    VSS_31 VSS_103 1 BB4 BH29 VSS_173 VSS_245
    Test_Point_20MIL A3 CP1 CP1 VSS_320 VSS_392 F18 C33
    VSS_32 VSS_104 CC7 CJ23 VSS_174 VSS_246
    BJ7 BP32 @ TP1707 VSS_321 VSS_393 AN31 K27
    VSS_33 VSS_105 R31 BH32 VSS_175 VSS_247
    CJ36 CP11 Test_Point_20MIL VSS_322 VSS_394 BV3 AW29
    VSS_34 VSS_106 BC25 CJ28 VSS_176 VSS_248
    1 A36 A36 AH27 VSS_323 VSS_395 F2 C4
    VSS_35 VSS_107 CD11 BH33 VSS_177 VSS_249
    @ TP1704 BK10 BP33 VSS_324 VSS_396 AN7 K28
    VSS_36 VSS_108 T27 CJ33 VSS_178 VSS_250
    Test_Point_20MIL CJ4 CP13 VSS_325 VSS_397 BV31 AW3
    VSS_37 VSS_109 CD12 BH35 VSS_179 VSS_251
    AB27 AH28 VSS_326 VSS_398 F21 C9
    VSS_38 VSS_110 T30 CJ35 VSS_180 VSS_252
    BK2 BP4 VSS_327 VSS_399 AN8 K29
    VSS_39 VSS_111
    CP15 BC29 BP19 VSS_181 VSS_253
    CK1 VSS_328 VSS_400 BV33 AW30
    VSS_40 VSS_112
    AH29 CD14 BR16 VSS_182 VSS_254
    AB3 VSS_329 VSS_401 F24 CA11
    VSS_41 VSS_113 T33 BY18 VSS_183 VSS_255
    BK28 BP7 VSS_330 VSS_402 BV4 K3
    VSS_42 VSS_114 T35 BY19 VSS_184 VSS_256
    AB30 CP19 VSS_331 VSS_403 F3 AW31
    VSS_43 VSS_115 BC32 CC16 VSS_185 VSS_257
    BK3 AH30 VSS_332 VSS_404 AP3 CA15
    VSS_44 VSS_116 CD24 BU16 VSS_186 VSS_258
    CK4 CP21 VSS_333 VSS_405 BW11 K30
    VSS_45 VSS_117 T36 CC14 VSS_187 VSS_259
    AB33 AH31 VSS_334 VSS_406 F4 AY33
    VSS_46 VSS_118 CD25 BR22 VSS_188 VSS_260
    BK33 BR19 VSS_335 VSS_407 AP33 CA22
    VSS_47 VSS_119 T7 BU20 VSS_189 VSS_261
    CK7 CP27 VSS_336 VSS_408 BW15 K31
    VSS_48 VSS_120 BC8 CD20 VSS_190 VSS_262
    AB36 AH33 VSS_337 VSS_409 G21 AY35
    VSS_49 VSS_121 CE33 BT14 VSS_191 VSS_263
    BK4 BR25 VSS_338 VSS_410 AP36 K32
    VSS_50 VSS_122
    AH35 U26 BP12 VSS_192 VSS_264
    CL2 VSS_339 VSS_411 G27 B12
    VSS_51 VSS_123 BD28 CB24 VSS_193 VSS_265
    AB4 CP37 VSS_340 VSS_412 AP4 K4
    B VSS_52 VSS_124 CE35 CC24 VSS_194 VSS_266 B
    BK7 AJ25 VSS_341 VSS_413 G33 B15
    VSS_53 VSS_125 U7 J5 VSS_195 VSS_267
    CM13 BT15 VSS_342 VSS_414 AR28 CA25
    VSS_54 VSS_126 BD33 U24 VSS_196 VSS_268
    AB7 AJ28 VSS_343 VSS_415 G35 K9
    VSS_55 VSS_127 CE36 BD7 VSS_197 VSS_269
    BL25 BT16 VSS_344 VSS_416 G36 B18
    VSS_56 VSS_128 V26 AR4 VSS_198 VSS_270
    CM17 CP9 VSS_345 VSS_417 AT33 CB11
    VSS_57 VSS_129 BD35 AU4 VSS_199 VSS_271
    AC10 AJ7 VSS_346 VSS_418 BW24 L27
    VSS_58 VSS_130 CE7 AW4 G9 VSS_200 VSS_272
    BL28 CR2 VSS_347 VSS_419 B21
    VSS_59 VSS_131 V27 BA6 VSS_201 VSS_273
    CM21 AK3 VSS_348 VSS_420 AT35 L33
    VSS_60 VSS_132 1 BD36 BC4 VSS_202 VSS_274
    AC27 CR36 CR36 VSS_349 VSS_421 H21 B23
    VSS_61 VSS_133 @ TP1701 CF11 BE4 VSS_203 VSS_275
    BL29 AK33 VSS_350 VSS_422 AT36 L35
    VSS_62 VSS_134
    Test_Point_20MIL V3 BE8 VSS_204 VSS_276
    CM25 D21 VSS_351 VSS_423 BW7 B25
    VSS_63 VSS_135 BE10 BA4 VSS_205 VSS_277
    AC30 AK36 VSS_352 VSS_424 H27 CB18
    VSS_64 VSS_136 CF14 BD4 VSS_206 VSS_278
    BL30 BT25 V30 VSS_353 VSS_425 AT4 L36
    VSS_65 VSS_137 BG4 VSS_207 VSS_279
    CM29 D25 BE28 VSS_354 VSS_426 BY11 B27
    VSS_66 VSS_138 CJ2 VSS_208 VSS_280
    BL31 AK4 VSS_355 VSS_427 AU10 CB19
    VSS_67 VSS_139 CF19 CJ3 BY15 VSS_209 VSS_281
    CM31 BT28 VSS_356 VSS_428 L6
    VSS_68 VSS_140 V33 AM5 H9 VSS_210 VSS_282
    AD33 AL28 VSS_357 VSS_429 B29
    VSS_69 VSS_141 BE29 CM4 VSS_211 VSS_283
    BL32 BT33 VSS_358 VSS_430 AU28 CB2
    VSS_70 VSS_142 CF2 AC5 VSS_212 VSS_284
    CM33 D5 VSS_359 VSS_431 BY22 N25
    VSS_71 VSS_143 V36 AG5 VSS_213 VSS_285
    AD35 AL29 VSS_360 VSS_432 J12 B31
    VSS_72 VSS_144 BE3 CR6 VSS_214 VSS_286
    VSS_361 VSS_433 AU29 CB20
    VSS_215 VSS_287
    J15 N27
    VSS_216 VSS_288
    CB25
    17 of 20 19 of 20 VSS_289
    WHISKEYLAKE-U_BGA1528 WHISKEYLAKE-U_BGA1528
    CPU@ CPU@ 18 of 20
    WHISKEYLAKE-U_BGA1528
    CPU@

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (15/16): GND
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    Vinafix.com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 17 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    R1803,R1806 ?
    EVT FVT SIT SVT
    Resistor V
    R-short
    UCPU1Q

    T4 F37
    CFG_0 RSVD_TP5
    F34
    RSVD_TP4
    R4
    R1803 CFG_1
    T3 CP36 ?
    CFG_2 IST_TRIG
    1 2 CFG3_R R3 CN36
    <19> CFG3 CFG_3 RSVD_TP3
    CFG4 J4
    CFG_4
    M4
    0_0201_SP J3 CFG_5
    BJ36 UCPU1O
    CFG_6 RSVD72
    M3 BJ34 K12
    CFG_7 RSVD73 RSVD46
    R2 K14 AA24
    CFG_8 RSVD47 RSVD38
    K15 AA26

    1/20W_1K_5%_0201

    1/20W_1K_5%_0201
    CFG9 N2 BK34
    CFG_9 TP1 RSVD48 RSVD39

    1/20W_1K_5%_0201
    R1 BR18 K17 AB25
    CFG_10 TP3 RSVD49 RSVD40

    1
    1

    1
    N1 K18 AC24
    CFG_11 RSVD50 RSVD41

    R1804
    @ R1801

    @ R1802
    J2 K20 AC25
    CFG_12 RSVD51 RSVD42
    L2 L25 AC26
    CFG_13 RSVD52 RSVD43
    J1 BT9 M24 AD24
    CFG_14 RSVD74 RSVD53 RSVD44
    L1 BT8 M26 AD26

    2
    2

    2
    CFG_15 RSVD75 RSVD54 RSVD45
    P24
    RSVD55
    L3 BP8 P26 V25
    CFG_16 RSVD76 RSVD56 RSVD64
    N3 BP9 R24 T25
    CFG_18 RSVD77 RSVD57 RSVD65
    R25
    L4 RSVD58
    CFG_17 CR4 R26
    N4 RSVD29 RSVD59
    CFG_19
    CP3 W25
    RSVD26 RSVD60
    C R1805 1 2 1/20W_49.9_1%_0201 CGF_RCOMP AB5 CR3 V24 C
    CFG_RCOMP RSVD27 RSVD61
    ITP_PMODE_R W4 Y25
    ITP_PMODE RSVD62
    Y24
    RSVD63
    CG2
    R1806 RSVD25
    CG1
    RSVD24
    1 2 AU3
    <19> ITP_PMODE RSVD78
    AT3
    RSVD79
    0_0201_SP
    15 of 20
    H4 WHISKEYLAKE-U_BGA1528
    RSVD34
    H3 AN1 CPU@
    RSVD33 RSVD8
    AN2
    RSVD9
    BV24
    RSVD22
    BV25 AN4
    RSVD23 RSVD11
    AN3
    RSVD10
    AL2
    RSVD80
    AL1
    RSVD81

    G3
    RSVD69 AL4
    G4 RSVD82
    RSVD70 AL3
    RSVD83

    BK36 BP34
    RSVD17 TP2
    BK35 BP36
    RSVD16 VSS_392
    BP35
    TP5
    W3
    RSVD35
    AM4 C34
    RSVD7 RSVD68
    AM3 A34
    RSVD71 RSVD_TP1
    B35
    RSVD67
    TP1801
    CR35 RSVD84 1 Test_Point_20MIL
    RSVD84
    A35
    RSVD1
    D34 AH26
    RSVD30 RSVD66 AJ27
    B RSVD85 B
    G2
    RSVD32
    G1
    RSVD31
    E1 SKTOCC R1807 1 21/20W_0_5%_0201
    SKTOCC#

    20 of 20
    WHISKEYLAKE-U_BGA1528
    CPU@

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 CPU (16/16): CFG/RESERVED
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 18 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    VCCSTG VCCSTG VCC1R05_SUS VCC3B VCCSTG VCC1R05_SUS

    1/20W_1K_5%_0201

    1/20W_51_5%_0201
    1/20W_51_5%_0201

    1/20W_51_5%_0201

    1/20W_1.5K_5%_0201
    2

    2
    2

    2
    2

    @ R1901

    R1902

    R1903
    @ R1907

    @ R1906
    @ C1901
    0.1U_6.3V_K_X5R_0201
    1

    1
    1

    1
    JXDP1 @
    TABLE
    XDP_TCK0 26
    <6> XDP_TCK0 26
    25 28
    25 GND2
    PCH_TCK @ R1904 1 2 1/20W_0_5%_0201 XDP_TCK1 24 27 Logic Ref Des Merged DCI 2.0
    <6> PCH_TCK 24 GND1
    XDP_TMS 23
    <6> XDP_TMS 23
    XDP_TDI 22
    <6> XDP_TDI -XDP_TRST 22
    21
    <6> -XDP_TRST 21
    XDP_TDO 20 Page 6 R0610 ASM NO_ASM
    <6> XDP_TDO 20
    19
    19
    -XDP_DBR 18
    <13,17> -XDP_DBR 18
    C ITP_PMODE 17 Page 18 R1892 ASM NO_ASM C
    <18> ITP_PMODE 17
    16
    16
    15
    15
    14 JXDP1 ASM NO_ASM
    14
    13
    13
    12 C1901 ASM NO_ASM
    12
    11
    11
    -RSMRST @ R1905 1 2 1/20W_1K_5%_0201 R1905 10 R1903 ASM ASM
    <13,94> -RSMRST 10
    9
    9
    8 Page 19 R1902 ASM ASM
    <18> CFG3 8
    7
    7
    6 R1901 ASM NO_ASM
    6

    1/20W_51_5%_0201

    1/20W_51_5%_0201
    5
    5

    2
    4 R1905 ASM NO_ASM
    4

    @ R1909

    @ R1908
    3
    3
    -XDP_PRDY 2
    <6> -XDP_PRDY 2
    -XDP_PREQ 1 R1801 ASM NO_ASM
    <6> -XDP_PREQ 1
    1

    1
    MOLEX_52435-2671

    LOGIC

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 XDP CONNECTOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 19 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    VCC3SW
    RTCVCC

    2
    2
    D2001
    RB520CM-30T2R_VMN2M2 @ C2001

    1
    1U_6.3V_M_X5R_0201
    1
    C C

    D2003
    D2003 2 1

    RB520CM-30T2R_VMN2M2

    2
    R2001
    1/20W_1K_5%_0201

    1
    @
    JRTC1
    1 R2001
    1
    2 1 2 -RTCRST
    2 -RTCRST <12,17>
    3 R2002 1/20W_20K_5%_0201
    GND1
    4
    GND2

    2
    HIGHS_WS33020-S0351-HF C2002
    1U_6.3V_K_X5R_0402

    2
    JCMOS
    1
    SHORT PADS
    @

    1
    B B

    1 2 -SRTCRST
    -SRTCRST <12>
    R2003 1/20W_20K_5%_0201

    2
    C2003
    1U_6.3V_K_X5R_0402

    2
    JME
    1
    SHORT PADS
    @

    1
    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 RTC BATTERY
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    Vinafix.com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 20 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    VCC3_SUS
    VCC3_SUS_SPI

    2
    D2101
    RB520CM-30T2R_VMN2M2

    1
    VCC3_SUS_SPI

    C
    32MB (256Mb) 200MIL SOIC8 C
    2 MACRONIX MX25L25673GM2I-08G
    C2101
    MACRONIX MX25L25673GM2I-10G
    0.1U_6.3V_K_X5R_0201
    1
    32MB (256Mb) 8x6mm WSON8 (Optional)
    2
    WINBOND W25Q256JVEIQ
    C2102
    0.1U_6.3V_K_X5R_0201
    1

    U2101
    -SPI_CS0 R2101 1 2 1/20W_0_5%_0201 -SPI_CS0_R 1 8
    <7> -SPI_CS0 /CS VCC
    SPI_MISO_IO1 R2102 1 2 1/20W_51_5%_0201 SPI_MISO_IO1_0_R 2 7 SPI_IO3_0_R R2103 1 2 1/20W_51_5%_0201 SPI_IO3
    <7,98> SPI_MISO_IO1 DO(IO1) /HOLD(IO3) SPI_IO3 <7>
    SPI_IO2 R2104 2 1 1/20W_51_5%_0201 SPI_IO2_0_R 3 6 SPI_CLK_0_R R2105 2 1 1/20W_51_5%_0201 SPI_CLK
    <7> SPI_IO2 /WP(IO2) CLK SPI_CLK <7,98>
    4 5 SPI_MOSI_IO0_0_R R2106 2 1 1/20W_51_5%_0201 SPI_MOSI_IO0
    GND DI(IO0) SPI_MOSI_IO0 <7,98>

    W25Q256JVEIQ_WSON8_8X6

    Use SA00008WZ00 Footprint (WSON8)


    But PN is SA00008J400

    TABLE

    SF100 PIN HEADER INTERFACE (TOP VIEW)

    B 1 VCC D12.1 GND GND 2 B


    3 CS# R322.2 R681.2 CLK 4
    5 MISO R694.2 R674.2 MOSI 6
    7 (KEY) N/A N/A (RESET) 8

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 SPI FLASH
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 21 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    Drift/Ironhide
    Vinafix.com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date: Tuesday, December 18, 2018 Sheet 22 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Vinafix.com Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
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    Date: Tuesday, December 18, 2018 Sheet 23 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    Drift/Ironhide
    Vinafix.com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date: Tuesday, December 18, 2018 Sheet 24 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    BLANK
    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    Drift/Ironhide
    Vinafix.com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date: Tuesday, December 18, 2018 Sheet 25 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    Drift/Ironhide
    Vinafix.com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date: Tuesday, December 18, 2018 Sheet 26 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    Drift/Ironhide
    Vinafix.com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date: Tuesday, December 18, 2018 Sheet 27 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 28 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Vinafix.com Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 29 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    BLANK C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 30 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    Drift/Ironhide
    Vinafix.com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date: Tuesday, December 18, 2018 Sheet 31 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 32 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC2R5A M_A_VREF_CA

    0.047UC_6.3VC_KC_X5RC_0201

    0.047UC_6.3VC_KC_X5RC_0201
    0.047UC_6.3VC_KC_X5RC_0201

    0.047UC_6.3VC_KC_X5RC_0201
    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402
    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201
    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201
    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201
    <4> M_A_DQ[63:0]
    2 2 2 2 2 2 2 2 2 2 2 2 2 2

    C3304

    C3308
    C3303

    C3305

    C3306

    C3307

    C3309

    C3312

    C3313
    C3301

    C3302

    C3310

    C3314
    C3311
    <4> -M_A_DQS[7:0]

    <4> M_A_DQS[7:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1

    <4,34> M_A_A[16:0]

    D D

    VCC2R5A VCC2R5A VCC2R5A VCC2R5A

    100P_25V_J_NPO_0201

    100P_25V_J_NPO_0201

    100P_25V_J_NPO_0201
    47P_25V_J_NPO_0201

    47P_25V_J_NPO_0201

    100P_25V_J_NPO_0201
    47P_25V_J_NPO_0201
    47P_25V_J_NPO_0201
    1 1 1 1 1 1 1 1

    RF@ C3316

    RF@ C3318

    RF@ C3321
    RF@ C3317

    RF@ C3322
    RF@ C3315

    RF@ C3325
    RF@ C3319
    2 2 2 2 2 2 2 2
    M_A_VREF_CA M_A_VREF_CA M_A_VREF_CA M_A_VREF_CA

    VCC1R2A VCC1R2A VCC1R2A VCC1R2A VCC1R2A VCC1R2A VCC1R2A VCC1R2A

    U3301 U3302 U3303 U3304

    M_A_DQ15 D7 B1 M_A_DQ31 D7 B1 M_A_DQ47 D7 B1 M_A_DQ63 D7 B1


    DQU7 VPP_B1 DQU7 VPP_B1 DQU7 VPP_B1 DQU7 VPP_B1
    D3 R9 D3 R9 D3 R9

    100P_25V_J_NPO_0201
    100P_25V_J_NPO_0201

    100P_25V_J_NPO_0201

    100P_25V_J_NPO_0201
    R9

    47P_25V_J_NPO_0201
    M_A_DQ14 M_A_DQ30 D3 M_A_DQ46 M_A_DQ62 DQU6 VPP_R9
    DQU6 VPP_R9 DQU6 VPP_R9 DQU6 VPP_R9

    47P_25V_J_NPO_0201

    47P_25V_J_NPO_0201
    C8 C8

    47P_25V_J_NPO_0201
    M_A_DQ13 C8 M_A_DQ29 C8 M_A_DQ45 M_A_DQ61
    DQU5 DQU5 DQU5 DQU5
    M_A_DQ12 C2 M1 1 1 M_A_DQ28 C2 M1 1 1 M_A_DQ44 C2 M1 1 M_A_DQ60 C2 M1 1 1
    DQU4 VREFCA DQU4 VREFCA DQU4 VREFCA 1 DQU4 VREFCA

    RF@ C3326

    RF@ C3323
    C7

    RF@ C3324

    RF@ C3329
    RF@ C3320

    RF@ C3327

    RF@ C3330
    C7 C7

    RF@ C3328
    M_A_DQ11 M_A_DQ27 C7 M_A_DQ43 M_A_DQ59 DQU3
    DQU3 DQU3 DQU3 C3 B3
    M_A_DQ10 C3 B3 M_A_DQ26 C3 B3 M_A_DQ42 C3 B3 M_A_DQ58
    DQU2 VDD_B3 DQU2 VDD_B3 DQU2 VDD_B3 DQU2 VDD_B3
    M_A_DQ9 B8 B9 M_A_DQ25 B8 B9 M_A_DQ41 B8 B9 M_A_DQ57 B8 B9
    DQU1 VDD_B9 2 2 DQU1 VDD_B9 2 2 DQU1 VDD_B9 2 2 DQU1 VDD_B9 2 2
    M_A_DQ8 A3 D1 M_A_DQ24 A3 D1 M_A_DQ40 A3 D1 M_A_DQ56 A3 D1
    DQU0 VDD_D1 DQU0 VDD_D1 DQU0 VDD_D1 DQU0 VDD_D1
    G7 G7 G7 G7
    VDD_G7 VDD_G7 VDD_G7 VDD_G7
    M_A_DQS1 B7 J1 M_A_DQS3 B7 J1 M_A_DQS5 B7 J1 M_A_DQS7 B7 J1
    DQSU_T VDD_J1 DQSU_T VDD_J1 DQSU_T VDD_J1 DQSU_T VDD_J1
    -M_A_DQS1 A7 J9 -M_A_DQS3 A7 J9 -M_A_DQS5 A7 J9 -M_A_DQS7 A7 J9
    DQSU_C VDD_J9 DQSU_C VDD_J9 DQSU_C VDD_J9 DQSU_C VDD_J9
    L1 L1 L1 L1
    VDD_L1 VDD_L1 VDD_L1 VDD_L1
    E2 L9 E2 L9 E2 L9 E2 L9
    DMU_n/DBIU_n VDD_L9 DMU_n/DBIU_n VDD_L9 DMU_n/DBIU_n VDD_L9 DMU_n/DBIU_n VDD_L9
    R1 R1 R1 R1
    VDD_R1 VDD_R1 VDD_R1 VDD_R1
    T9 T9 T9 T9
    VDD_T9 VDD_T9 VDD_T9 VDD_T9

    M_A_DQ7 J7 A1 M_A_DQ23 J7 A1 M_A_DQ39 J7 A1 M_A_DQ55 J7 A1


    DQL7 VDDQ_A1 DQL7 VDDQ_A1 DQL7 VDDQ_A1 DQL7 VDDQ_A1
    M_A_DQ6 J3 A9 M_A_DQ22 J3 A9 M_A_DQ38 J3 A9 M_A_DQ54 J3 A9
    DQL6 VDDQ_A9 DQL6 VDDQ_A9 DQL6 VDDQ_A9 DQL6 VDDQ_A9
    M_A_DQ5 H8 C1 M_A_DQ21 H8 C1 M_A_DQ37 H8 C1 M_A_DQ53 H8 C1
    DQL5 VDDQ_C1 DQL5 VDDQ_C1 DQL5 VDDQ_C1 DQL5 VDDQ_C1
    M_A_DQ4 H2 D9 M_A_DQ20 H2 D9 M_A_DQ36 H2 D9 M_A_DQ52 H2 D9
    DQL4 VDDQ_D9 DQL4 VDDQ_D9 DQL4 VDDQ_D9 DQL4 VDDQ_D9
    M_A_DQ3 H7 F2 M_A_DQ19 H7 F2 M_A_DQ35 H7 F2 M_A_DQ51 H7 F2
    DQL3 VDDQ_F2 DQL3 VDDQ_F2 DQL3 VDDQ_F2 DQL3 VDDQ_F2
    M_A_DQ2 H3 F8 M_A_DQ18 H3 F8 M_A_DQ34 H3 F8 M_A_DQ50 H3 F8
    DQL2 VDDQ_F8 DQL2 VDDQ_F8 DQL2 VDDQ_F8 DQL2 VDDQ_F8
    M_A_DQ1 F7 G1 M_A_DQ17 F7 G1 M_A_DQ33 F7 G1 M_A_DQ49 F7 G1
    DQL1 VDDQ_G1 DQL1 VDDQ_G1 DQL1 VDDQ_G1 DQL1 VDDQ_G1
    M_A_DQ0 G2 G9 M_A_DQ16 G2 G9 M_A_DQ32 G2 G9 M_A_DQ48 G2 G9
    DQL0 VDDQ_G9 DQL0 VDDQ_G9 DQL0 VDDQ_G9 DQL0 VDDQ_G9
    J2 J2 J2 J2
    C VDDQ_J2 VDDQ_J2 VDDQ_J2 VDDQ_J2 C
    M_A_DQS0 G3 J8 M_A_DQS2 G3 J8 M_A_DQS4 G3 J8 M_A_DQS6 G3 J8
    DQSL_t VDDQ_J8 DQSL_t VDDQ_J8 DQSL_t VDDQ_J8 DQSL_t VDDQ_J8
    -M_A_DQS0 F3 -M_A_DQS2 F3 -M_A_DQS4 F3 -M_A_DQS6 F3
    DQSL_c DQSL_c DQSL_c DQSL_c
    E7 A2 E7 A2 E7 A2 E7 A2
    DML_n/DBIL_n VSSQ_A2 DML_n/DBIL_n VSSQ_A2 DML_n/DBIL_n VSSQ_A2 DML_n/DBIL_n VSSQ_A2
    A8 A8 A8 A8
    VSSQ_A8 VSSQ_A8 VSSQ_A8 VSSQ_A8
    C9 C9 C9 C9
    VSSQ_C9 VSSQ_C9 VSSQ_C9 VSSQ_C9
    D2 D2 D2 D2
    VSSQ_D2 VSSQ_D2 VSSQ_D2 VSSQ_D2
    M_A_DDRCLK0_1200M K7 D8 M_A_DDRCLK0_1200M K7 D8 M_A_DDRCLK0_1200M K7 D8 M_A_DDRCLK0_1200M K7 D8
    CK_t VSSQ_D8 CK_t VSSQ_D8 CK_t VSSQ_D8 CK_t VSSQ_D8
    -M_A_DDRCLK0_1200M K8 E3 -M_A_DDRCLK0_1200M K8 E3 -M_A_DDRCLK0_1200M K8 E3 -M_A_DDRCLK0_1200M K8 E3
    CK_c VSSQ_E3 CK_c VSSQ_E3 CK_c VSSQ_E3 CK_c VSSQ_E3
    E8 E8 E8 E8
    VSSQ_E8 VSSQ_E8 VSSQ_E8 VSSQ_E8
    M_A_CKE0 K2 F1 M_A_CKE0 K2 F1 M_A_CKE0 K2 F1 M_A_CKE0 K2 F1
    <4,34> M_A_CKE0 CKE VSSQ_F1 CKE VSSQ_F1 CKE VSSQ_F1 CKE VSSQ_F1
    H1 H1 H1 H1
    VSSQ_H1 VSSQ_H1 VSSQ_H1 VSSQ_H1
    -M_A_CS0 L7 H9 -M_A_CS0 L7 H9 -M_A_CS0 L7 H9 -M_A_CS0 L7 H9
    <4,34> -M_A_CS0 CS_n VSSQ_H9 CS_n VSSQ_H9 CS_n VSSQ_H9 CS_n VSSQ_H9

    M_A_ODT0 K3 B2 M_A_ODT0 K3 B2 M_A_ODT0 K3 B2 M_A_ODT0 K3 B2


    <4,34> M_A_ODT0 ODT VSS_B2 ODT VSS_B2 ODT VSS_B2 ODT VSS_B2
    E1 E1 E1 E1
    VSS_E1 VSS_E1 VSS_E1 VSS_E1
    -M_A_ACT L3 G8 -M_A_ACT L3 G8 -M_A_ACT L3 G8 -M_A_ACT L3 G8
    <4,34> -M_A_ACT ACT_n VSS_G8 ACT_n VSS_G8 ACT_n VSS_G8 ACT_n VSS_G8
    K1 K1 K1 K1
    VSS_K1 VSS_K1 VSS_K1 VSS_K1
    M_A_BG1_R M9 K9 M_A_BG1_R M9 K9 M_A_BG1_R M9 K9 M_A_BG1_R M9 K9
    VSS_M9 VSS_K9 VSS_M9 VSS_K9 VSS_M9 VSS_K9 VSS_M9 VSS_K9
    M_A_BG0 M2 N1 M_A_BG0 M2 N1 M_A_BG0 M2 N1 M_A_BG0 M2 N1
    <4,34> M_A_BG0 BG0 VSS_N1 BG0 VSS_N1 BG0 VSS_N1 BG0 VSS_N1
    T1 T1 T1 T1
    VSS_T1 VSS_T1 VSS_T1 VSS_T1
    M_A_BS1 N8 M_A_BS1 N8 M_A_BS1 N8 M_A_BS1 N8
    <4,34> M_A_BS1 BA1 BA1 BA1 BA1 T7
    M_A_BS0 N2 T7 M_A_BS0 N2 T7 M_A_BS0 N2 T7 M_A_BS0 N2
    <4,34> M_A_BS0 BA0 NC BA0 NC BA0 NC BA0 NC

    M_A_A16 L8 M_A_A16 L8 M_A_A16 L8 M_A_A16 L8


    RAS_n RAS_n RAS_n RAS_n
    M_A_A15 M8 M_A_A15 M8 M_A_A15 M8 M_A_A15 M8
    CAS_n CAS_n CAS_n CAS_n
    M_A_A14 L2 M_A_A14 L2 M_A_A14 L2 M_A_A14 L2
    WE_n/A14 WE_n/A14 WE_n/A14 WE_n/A14

    M_A_A13 T8 M_A_A13 T8 M_A_A13 T8 M_A_A13 T8


    A13 A13 A13 A13
    M_A_A12 M7 M_A_A12 M7 M_A_A12 M7 M_A_A12 M7
    A12/BC_n A12/BC_n A12/BC_n A12/BC_n
    M_A_A11 T2 M_A_A11 T2 M_A_A11 T2 M_A_A11 T2
    A11 A11 A11 A11 P1
    M_A_A10 M3 P1 M_A_A10 M3 P1 M_A_A10 M3 P1 M_A_A10 M3
    A10/AP RESET_n -DRAMRST A10/AP RESET_n -DRAMRST A10/AP RESET_n -DRAMRST A10/AP RESET_n -DRAMRST
    M_A_A9 R7 R7 M_A_A9 R7 M_A_A9 R7
    A9 M_A_A9 A9 A9 A9
    M_A_A8 R2 T3 R2 T3 R2 T3 M_A_PARITY R2 T3 M_A_PARITY
    A8 PAR M_A_PARITY M_A_A8 A8 PAR M_A_PARITY M_A_A8 A8 PAR M_A_A8 A8 PAR
    M_A_A7 R8 R8 M_A_A7 R8 M_A_A7 R8
    A7 M_A_A7 A7 A7 A7
    M_A_A6 P2 P9 -M_A_ALERT P2 P9 P2 P9 P2 P9
    A6 ALERT_n M_A_A6 A6 ALERT_n -M_A_ALERT M_A_A6 A6 ALERT_n -M_A_ALERT M_A_A6 A6 ALERT_n -M_A_ALERT
    M_A_A5 P8 P8 P8 M_A_A5 P8
    A5 M_A_A5 A5
    M_A_A5 A5 A5
    M_A_A4 N3 E9 R3303 N3 E9 N3 E9 N3 E9
    A4 VSS_E9 M_A_A4 A4 VSS_E9 R3306 M_A_A4 A4 VSS_E9 R3309 M_A_A4 A4 VSS_E9 R3312
    M_A_A3 N7 N7 N7 N7
    A3 M_A_A3 A3 M_A_A3 A3 M_A_A3 A3
    M_A_A2 R3 F9 R3 F9 R3 F9 R3 F9
    A2 ZQ R3302 M_A_A2 ZQ R3305 M_A_A2 A2 ZQ R3308 M_A_A2 A2 ZQ R3311
    P7 A2 P7 P7
    M_A_A1 A1 M_A_A1 P7 M_A_A1 A1 M_A_A1 A1
    P3 N9 A1 N9 P3 N9 P3 N9
    M_A_A0 A0 TEN M_A_A0 P3 M_A_A0 A0 TEN M_A_A0 A0 TEN
    A0 TEN

    1/20W_243_1%_0201
    1/20W_243_1%_0201

    1/20W_243_1%_0201

    1/20W_0_5%_0201
    1/20W_0_5%_0201

    1/20W_0_5%_0201

    1/20W_0_5%_0201
    1/20W_243_1%_0201
    2

    2
    2

    2
    2

    2
    2

    2
    2

    2
    2

    K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96

    X76@ R3312
    X76@ R3303

    R3311
    R3305

    X76@ R3306

    X76@ R3309
    X76@ X76@

    R3308
    R3302

    X76@ X76@
    R3301 X76@ R3304 X76@ R3307 X76@ R3310 X76@
    1/20W_0_5%_0201 1/20W_0_5%_0201 1/20W_0_5%_0201 1/20W_0_5%_0201
    1

    1
    1

    1
    1

    1
    1

    1
    1

    1
    1

    B B

    TABLE:
    M_A_DDRCLK0_1200M
    <4,34> M_A_DDRCLK0_1200M SDP DDP Original Footprint : K4A8G165WB-BCPB_FBGA_96P
    2 Temp Footprint : Samsung_memorydown_4G-XX
    @ C3331 R3301 ASM NA
    3300P_25V_K_X7R_0201
    1 R3304 ASM NA
    Supplier Capacity Supplier's P/N Package Size Die Configuration VSS_E9 BG1 / VSS Ch. A Ch. B
    -M_A_DDRCLK0_1200M R3307 ASM NA
    <4,34> -M_A_DDRCLK0_1200M 8Gb 1 Rank x
    R3310 ASM NA 8Gbit MT40A512M16LY-075:E 7.5 x 13.5 mm SDP (512Mx16) (512Mx16) 0_5% VSS 4GB SODIMM

    X76@ R3313 NA ASM Micron


    M_A_BG1 1 2 M_A_BG1_R
    16Gb 1 Rank x
    <4> M_A_BG1 M_A_BG1_R <34> 16Gbit MT40A1G16KNR-075:E 7.5 x 13.5 mm DDP (1Gx16) (1Gx16) 243_1% BG1 8GB SODIMM
    R3313
    1/20W_0_5%_0201 R3418 NA ASM
    8Gb 1 Rank x
    8Gbit K4A8G165WC-BCTD 7.5 x 13.3 mm SDP (512Mx16) (512Mx16) 0_5% VSS 4GB SODIMM
    R3303 0_5% 243_1% 16Gb 1 Rank x
    <5,35> -DRAMRST -DRAMRST Samsung 16Gbit K4AAG165WB-MCTD 7.5 x 13.3 mm DDP (1Gx16) 243_1% BG1 8GB SODIMM
    (1Gx16)
    R3306 0_5% 243_1%
    32Gb 1 Rank x
    R3309 0_5% 243_1% 32Gbit K4ABG165WA-MCTD 10.5 x 13.3 mm DDP (2Gx16) 243_1% BG1 16GB SODIMM
    <4,34> M_A_PARITY M_A_PARITY (2Gx16)
    R3312 0_5% 243_1% 8Gb 1 Rank x
    8Gbit H5AN8G6NCJR-VKC 7.5 x 13.0 mm SDP (512Mx16) (512Mx16) 0_5% VSS 4GB SODIMM
    -M_A_ALERT SK hynix
    <4,34> -M_A_ALERT 16Gb 1 Rank x
    DRAM Configuration: X76@ 16Gbit H5ANAG6NAMR-UHC 7.5 x 13.0 mm DDP (1Gx16) (1Gx16) 243_1% BG1 8GB SODIMM

    ON BOARD MEMORY
    ZZZ ZZZ ZZZ ZZZ ZZZ ZZZ ZZZ
    A A

    K4A8G165WC-BCTD MT40A512M16LY-075:E H5AN8G6NCJR-VKC K4AAG165WB-MCTD MT40A1G16KNR-075:E H5ANAG6NAMR-UHC K4ABG165WA-MCTD


    X7645Q01007 X7645Q01009 X7645Q01008 X7645Q01003 X7645Q01004 X7645Q0100A X7645Q0100F
    4GS@ 4GM@ 4GH@ 8GS@ 8GM@ 8GH@ 16GS@

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 LPDDR4 SUB CHANNEL-A
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 33 of 125

    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    VCC0R6B

    <4,33> M_A_A[16:0]
    D D
    VCC1R2A
    M_A_A16 R3401 1 2 1/20W_36_1%_0201

    M_A_A15 R3402 1 2 1/20W_36_1%_0201

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    M_A_A14 R3403 1 2 1/20W_36_1%_0201
    2 2 2 2 2 2 2 2
    M_A_A13 R3404 1 2 1/20W_36_1%_0201

    EMC@C3401

    C3408
    C3407
    C3406
    C3405
    C3404
    C3403
    C3402
    M_A_A12 R3405 1 2 1/20W_36_1%_0201
    1 1 1 1 1 1 1 1
    M_A_A11 R3406 1 2 1/20W_36_1%_0201

    M_A_A10 R3407 1 2 1/20W_36_1%_0201

    M_A_A9 R3408 1 2 1/20W_36_1%_0201

    M_A_A8 R3409 1 2 1/20W_36_1%_0201

    M_A_A7 R3410 1 2 1/20W_36_1%_0201

    M_A_A6 R3411 1 2 1/20W_36_1%_0201

    M_A_A5 R3412 1 2 1/20W_36_1%_0201 VCC1R2A

    M_A_A4 R3413 1 2 1/20W_36_1%_0201

    M_A_A3 R3414 1 2 1/20W_36_1%_0201

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    M_A_A2 R3415 1 2 1/20W_36_1%_0201
    2 2 2 2 2 2 2 2
    M_A_A1 R3416 1 2 1/20W_36_1%_0201

    EMC@C3409

    C3416
    C3415
    C3414
    C3413
    C3412
    C3411
    C3410
    M_A_A0 R3417 1 2 1/20W_36_1%_0201
    1 1 1 1 1 1 1 1
    M_A_BG1_R R3418 1 X76@ 2 1/20W_36_1%_0201
    <33> M_A_BG1_R
    M_A_BG0 R3419 1 2 1/20W_36_1%_0201
    <4,33> M_A_BG0
    M_A_BS1 R3420 1 2 1/20W_36_1%_0201
    <4,33> M_A_BS1
    M_A_BS0 R3421 1 2 1/20W_36_1%_0201
    <4,33> M_A_BS0
    -M_A_ACT R3422 1 2 1/20W_36_1%_0201
    <4,33> -M_A_ACT
    M_A_PARITY R3423 1 2 1/20W_36_1%_0201
    <4,33> M_A_PARITY
    -M_A_CS0 R3424 1 2 1/20W_36_1%_0201
    <4,33> -M_A_CS0
    VCC1R2A
    C M_A_ODT0 R3425 1 2 1/20W_36_1%_0201 C
    <4,33> M_A_ODT0
    M_A_CKE0 R3426 1 2 1/20W_36_1%_0201
    <4,33> M_A_CKE0

    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402
    2 2 2 2 2 2 2 2

    C3417

    C3424
    C3423
    C3422
    C3421
    C3420
    C3419
    C3418
    1 1 1 1 1 1 1 1
    M_A_DDRCLK0_1200M R3427 1 2 1/20W_36_1%_0201
    <4,33> M_A_DDRCLK0_1200M

    -M_A_DDRCLK0_1200M R3428 1 2 1/20W_36_1%_0201


    <4,33> -M_A_DDRCLK0_1200M

    VCC1R2A

    -M_A_ALERT R3429 1 2 1/20W_49.9_1%_0201


    <4,33> -M_A_ALERT

    B B
    M_A_VREF_CA
    VCC1R2A
    VCC0R6B VCC0R6B

    2
    R3430

    0.1U_6.3V_K_X5R_0201
    10U_6.3V_M_X5R_0402

    0.1U_6.3V_K_X5R_0201
    10U_6.3V_M_X5R_0402

    0.1U_6.3V_K_X5R_0201
    0.1U_6.3V_K_X5R_0201

    1/20W_1.82K_1%_0201
    0.1U_6.3V_K_X5R_0201
    0.1U_6.3V_K_X5R_0201
    0.1U_6.3V_K_X5R_0201
    0.1U_6.3V_K_X5R_0201

    2 2 2 2 2 2 2 2 2 2

    1
    EMC@ C3434
    C3433
    C3432
    C3431
    C3426

    C3430
    C3425

    C3429
    C3428
    C3427

    1 2
    <4> M_A_VREF_CA_CPU
    1 1 1 1 1 1 1 1 1 1 R3431

    2
    1/20W_2.74_1%_0201
    2 R3432
    C3435 1/20W_1.82K_1%_0201
    0.022UC_6.3VC_KC_X5RC_0201

    1
    1

    2 BIKINI
    R3433
    1/20W_24.9_1%_0201

    1
    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 LPDDR4 SUB CHANNEL-A
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 34 of 125

    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    <5> M_B_DQ[63:0]

    <5> -M_B_DQS[7:0]

    <5> M_B_DQS[7:0]

    <5> M_B_A[16:0]

    VCC1R2A VCC1R2A
    D D

    JDDR1B
    VCC1R2A VCC1R2A
    JDDR1A
    M_B_A3 131 132 M_B_A2
    A3 A2
    M_B_A1 133 134 JDDR_EVENT_N
    A1 EVENT_n/NF
    1 2 135 136
    VSS_1 VSS_2 VDD_9 VDD_10
    M_B_DQ12 3 4 M_B_DQ13 M_B_DDRCLK0_1200M 137 138 M_B_DDRCLK1_1200M
    DQ5 DQ4 <5> M_B_DDRCLK0_1200M 139 CK0_t CK1_t/NF
    140 M_B_DDRCLK1_1200M <5>
    5 6 -M_B_DDRCLK0_1200M -M_B_DDRCLK1_1200M
    VSS_3 VSS_4 <5> -M_B_DDRCLK0_1200M 141 CK0_c CK1_c/NF
    142 -M_B_DDRCLK1_1200M <5>
    M_B_DQ8 7 8 M_B_DQ9
    DQ1 DQ0 VDD_11 VDD_12
    9 10 M_B_PARITY 143 144 M_B_A0
    VSS_5 VSS_6 <5> M_B_PARITY Parity A0
    -M_B_DQS1 11 12
    DQS0_C DM0_n/DBI0_n
    M_B_DQS1 13 14
    DQS0_t VSS_7 145 146
    15 16 M_B_DQ10 M_B_BS1 M_B_A10
    VSS_8 DQ6 <5> M_B_BS1 147 BA1 A10/AP
    148
    M_B_DQ15 17 18
    DQ7 VSS_9 VDD_13 VDD_14
    19 20 M_B_DQ14 -M_B_CS0 149 150 M_B_BS0
    VSS_10 DQ2 <5> -M_B_CS0 151 CS0_n BA0
    152 M_B_BS0 <5>
    M_B_DQ11 21 22 M_B_A14 M_B_A16
    DQ3 VSS_11 WE_n/A14 RAS_n/A16
    23 24 M_B_DQ0 153 154
    VSS_12 DQ12 VDD_15 VDD_16
    M_B_DQ3 25 26 M_B_ODT0 155 156 M_B_A15
    DQ13 VSS_13 <5> M_B_ODT0 157 ODT0 CAS_n/A15
    158
    27 28 M_B_DQ2 -M_B_CS1 M_B_A13 M_B_VREF_CA
    VSS_14 DQ8 <5> -M_B_CS1 159 CS1_n/NC A13
    160
    M_B_DQ7 29 30
    DQ9 VSS_15 VDD_17 VDD_18
    31 32 -M_B_DQS0 M_B_ODT1 161 162
    VSS_16 DQS1_c <5> M_B_ODT1 163 ODT1/NC C0/CS2_n/NC
    164
    33 34 M_B_DQS0
    DM1_n/DBl1_n DQS1_t VDD_19 VREFCA
    35 36 165 166
    VSS_17 VSS_18 C1/CS3_n/NC RFU/SA2
    M_B_DQ6 37 38 M_B_DQ1 167 168
    DQ15 DQ14 VSS_53 VSS_54
    39 40 M_B_DQ39 169 170 M_B_DQ33
    VSS_19 VSS_20 DQ37 DQ36
    M_B_DQ5 41 42 M_B_DQ4 171 172
    DQ10 DQ11 VSS_55 VSS_56
    43 44 M_B_DQ38 173 174 M_B_DQ32
    VSS_21 VSS_22 DQ33 DQ32
    M_B_DQ21 45 46 M_B_DQ20 175 176
    DQ21 DQ20 VSS_57 VSS_58
    47 48 -M_B_DQS4 177 178
    VSS_23 VSS_24 DQS4_c DM4_n/DBl4_n
    M_B_DQ17 49 50 M_B_DQ16 M_B_DQS4 179 180
    DQ17 DQ16 DQS4_t VSS_59
    51 52 181 182 M_B_DQ34
    VSS_25 VSS_26 VSS_60 DQ39
    -M_B_DQS2 53 54 M_B_DQ36 183 184
    DQS2_c DM2_n/DBl2_n DQ38 VSS_61
    M_B_DQS2 55 56 185 186 M_B_DQ35
    DQS2_t VSS_27 VSS_62 DQ35
    57 58 M_B_DQ22 M_B_DQ37 187 188
    VSS_28 DQ22 DQ34 VSS_63
    M_B_DQ23 59 60 189 190 M_B_DQ44
    DQ23 VSS_29 VSS_64 DQ45
    61 62 M_B_DQ19 M_B_DQ40 191 192
    VSS_30 DQ18 DQ44 VSS_65
    M_B_DQ18 63 64 193 194 M_B_DQ45
    DQ19 VSS_31 VSS_66 DQ41
    65 66 M_B_DQ28 M_B_DQ41 195 196
    VSS_32 DQ28 DQ40 VSS_67
    M_B_DQ29 67 68 197 198 -M_B_DQS5
    DQ29 VSS_33 VSS_68 DQS5_c
    69 70 M_B_DQ24 199 200 M_B_DQS5
    VSS_34 DQ24 DM5_n/DBl5_n DQS5_t
    M_B_DQ25 71 72 201 202
    DQ25 VSS_35 VSS_69 VSS_70
    73 74 -M_B_DQS3 M_B_DQ47 203 204 M_B_DQ46
    VSS_36 DQS3_c DQ46 DQ47
    75 76 M_B_DQS3 205 206
    DM3_n/DBl3_n DQS3_t VSS_71 VSS_72
    77 78 M_B_DQ43 207 208 M_B_DQ42
    VSS_37 VSS_38 DQ42 DQ43
    M_B_DQ31 79 80 M_B_DQ30 209 210
    DQ30 DQ31 VSS_73 VSS_74
    81 82 M_B_DQ49 211 212 M_B_DQ52
    VSS_39 VSS_40 DQ52 DQ53
    M_B_DQ26 83 84 M_B_DQ27 213 214
    DQ26 DQ27 VSS_75 VSS_76
    C 85 86 M_B_DQ53 215 216 M_B_DQ48 C
    VSS_41 VSS_42 DQ49 DQ48
    JDDR1_CB5 87 88 JDDR1_CB4 217 218
    CB5/NC CB4/NC VSS_77 VSS_78
    89 90 -M_B_DQS6 219 220
    VSS_43 VSS_44 DQS6_c DM6_n/DBl6_n
    JDDR1_CB1 91 92 JDDR1_CB0 M_B_DQS6 221 222
    CB1/NC CB0/NC DQS6_t VSS_79
    93 94 223 224 M_B_DQ50
    VSS_45 VSS_46 VSS_80 DQ54
    -M_B_DQS8 95 96 M_B_DQ51 225 226
    DQS8_c/NC DM8_n/DBI_n/NC DQ55 VSS_81
    M_B_DQS8 97 98 227 228 M_B_DQ55
    DQS8_t/NC VSS_47 VSS_82 DQ50
    99 100 JDDR1_CB6 M_B_DQ54 229 230
    VSS_48 CB6/NC DQ51 VSS_83
    JDDR1_CB2 101 102 231 232 M_B_DQ61
    CB2/NC VSS_49 VSS_84 DQ60
    103 104 JDDR1_CB7 M_B_DQ56 233 234
    VSS_50 CB7/NC DQ61 VSS_85
    JDDR1_CB3 105 106 235 236 M_B_DQ57
    CB3/NC VSS_51 VSS_86 DQ57
    107 108 -DRAMRST M_B_DQ60 237 238 VCC3B
    VSS_52 RESET_n -DRAMRST <5,33> DQ56 VSS_87
    M_B_CKE0 109 110 M_B_CKE1 239 240 -M_B_DQS7
    <5> M_B_CKE0 CKE0 CKE1/NC M_B_CKE1 <5> VSS_88 DQS7_c
    111 112 241 242 M_B_DQS7
    VDD_1 VDD_2 DM7_n/DBl7_n DQS7_t
    M_B_BG1 113 114 -M_B_ACT 243 244
    <5> M_B_BG1 BG1 ACT_n -M_B_ACT <5> VSS_89 VSS_90

    1
    M_B_BG0 115 116 -M_B_ALERT M_B_DQ58 245 246 M_B_DQ59
    <5> M_B_BG0 BG0 ALERT_n -M_B_ALERT <5> DQ62 DQ63
    117 118 VCC2R5A VCC3B 247 248 R3501 VCC0R6B
    VDD_3 VDD_4 VSS_91 VSS_92
    M_B_A12 119 120 M_B_A11 M_B_DQ62 249 250 M_B_DQ63 0_0201_SP
    A12 A11 DQ58 DQ59
    M_B_A9 121 122 M_B_A7 251 252
    A9 A7 VSS_93 VSS_94
    123 124 SMB_CLK_3B 253 254 SMB_DATA_3B
    SCL SDA

    2
    125 VDD_5 VDD_6
    126 <89,93> SMB_CLK_3B 255 256 SMB_DATA_3B <89,93>
    M_B_A8 A8 A5
    M_B_A5 VDDSPD SA0 JDDR_SA0
    M_B_A6 127 128 M_B_A4 257 258
    A6 A4 VPP_1 Vtt
    129 130 259 260
    VDD_7 VDD_8 VPP_2 SA1
    261 262
    GND1 GND2 SPD ADDRESS: 51H
    ARGOS_D4ASL-26010-1P40 ARGOS_D4ASL-26010-1P40
    @ @

    VCC1R2A M_B_VREF_CA
    2

    R3502
    1/20W_1K_1%_0201

    VCC2R5A VCC3B VCC1R2A


    1

    1 2
    B <4> M_B_VREF_CA_CPU B
    VCC3B VCC2R5A
    R3503 M_B_VREF_CA
    2

    2 1/20W_2_1%_0201
    R3504
    C3501 1/20W_1K_1%_0201

    47P_25V_J_NPO_0201
    47P_25V_J_NPO_0201

    100P_25V_J_NPO_0201
    100P_25V_J_NPO_0201
    0.022UC_6.3VC_KC_X5RC_0201

    100P_25V_J_NPO_0201
    2.2UC_6.3VC_KC_X5RC_0402

    47P_25V_J_NPO_0201
    1 1 1 1 1
    1

    RF@ C3506
    RF@ C3504
    0.1U_6.3V_K_X5R_0201

    RF@ C3509
    RF@ C3507
    RF@ C3505

    RF@ C3508
    2 2
    1

    C3503
    C3502

    1U_6.3V_K_X5R_0402
    10U_6.3V_M_X5R_0402

    0.1U_6.3V_K_X5R_0201
    2

    2.2UC_6.3VC_KC_X5RC_0402
    2 2 2

    C3511
    C3510

    C3513
    2 OGC

    @ C3512
    2 2 2 2 2 2
    1 1
    1 1 1 1
    R3505
    1/20W_24.9_1%_0201
    1

    VCC1R2A
    Near JDDR1
    1
    1
    1

    @ R3506 @ R3507 @ R3508 @ R3509


    1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201
    2
    2
    2

    JDDR1_CB0
    JDDR1_CB1
    JDDR1_CB2
    JDDR1_CB3
    1
    1
    1

    @ R3510 @ R3511 @ R3512 @ R3513


    1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201
    2
    2
    2

    JDDR1_CB4
    JDDR1_CB5
    JDDR1_CB6
    A JDDR1_CB7 A
    1

    1
    1

    @ R3514 @ R3515 @ R3516


    1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201
    2

    2
    2

    JDDR_EVENT_N
    -M_B_DQS8
    M_B_DQS8

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 DDR4 SUB CHANNEL-B SODIMM_1

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 35 of 125
    5 4 3 2 1

    Vinafix.com
    A
    B
    C
    D

    5
    5

    Vinafix.com
    4
    4

    1
    2
    1
    2

    1
    2

    EMC_NS@ C3627 @ C3614 @ C3601

    VCC1R2A
    VCC1R2A
    VCC1R2A

    0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 1U_6.3V_K_X5R_0402

    1
    2
    1
    2

    1
    2

    EMC_NS@ C3628 @ C3615 @ C3602


    0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 1U_6.3V_K_X5R_0402

    1
    2
    1
    2
    1
    2

    EMC_NS@ C3629 @ C3616 @ C3603


    0.1U_6.3V_K_X5R_0201
    1 0.1U_6.3V_K_X5R_0201 1U_6.3V_K_X5R_0402
    2
    1
    2
    1
    2

    EMC_NS@ C3630
    0.1U_6.3V_K_X5R_0201 @ C3617 @ C3604
    0.1U_6.3V_K_X5R_0201 1U_6.3V_K_X5R_0402
    1
    2

    1
    2

    1
    2

    EMC_NS@ C3631 @ C3618 @ C3605


    0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 1U_6.3V_K_X5R_0402

    1
    2
    1
    2
    1
    2
    1
    2

    C3636 C3632 C3619 C3606


    VCC0R6B
    VCC0R6B
    VCC1R2A
    VCC1R2A

    10U_6.3V_M_X5R_0402 0.1U_6.3V_K_X5R_0201 10U_6.3V_M_X5R_0402 1U_6.3V_K_X5R_0402


    1
    2

    C3637
    10U_6.3V_M_X5R_0402

    3
    3

    1
    2

    1
    2
    1
    2

    C3633 C3620 C3607


    0.1U_6.3V_K_X5R_0201 22U_6.3V_M_X5R_0603 1U_6.3V_K_X5R_0402
    1
    2
    1
    2

    C3634 C3608
    0.1U_6.3V_K_X5R_0201 1U_6.3V_K_X5R_0402
    1
    2
    1
    2
    1
    2

    C3635 C3622 C3609


    0.1U_6.3V_K_X5R_0201 10U_6.3V_M_X5R_0402 1U_6.3V_K_X5R_0402
    1
    2
    1
    2

    C3623 C3610
    10U_6.3V_M_X5R_0402 1U_6.3V_K_X5R_0402
    1
    2
    1
    2

    C3624 C3611
    10U_6.3V_M_X5R_0402 1U_6.3V_K_X5R_0402
    1
    2
    1
    2

    C3625 C3612
    10U_6.3V_M_X5R_0402 1U_6.3V_K_X5R_0402
    2
    2

    Issued Date
    Security Classification
    1
    2
    1
    2

    C3626 C3613
    10U_6.3V_M_X5R_0402 1U_6.3V_K_X5R_0402
    2018/01/12
    Deciphered Date
    LC Future Center Secret Data

    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    2018/01/12

    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

    Date:
    Custom
    Title

    1
    1

    Size Document Number

    Tuesday, December 18, 2018


    DDR4 SUB CHANNEL-B SODIMM_2

    Sheet
    36
    Drift/Ironhide
    of
    125
    Rev
    0.1
    A
    B
    C
    D
    5 4 3 2 1

    VCC1R8VIDEO_AON

    1
    SWG@
    R3701
    1/20W_10K_5%_0201 10uF 2pc change to 22uF 1pc ???mA
    @
    UGPU1A VCC1R0VIDEO

    2
    1/14 PCI_EXPRESS Place under GPU Place near GPU Place between GPU and PS
    <41> -PEX_RST
    D D

    4.7UC_6.3VC_KC_X6SC_0603

    10UC_6.3VC_MC_X5RC_0603
    4.7UC_6.3VC_KC_X6SC_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    D3701 SWG@ 1 2 RB521CM-30T2R_VMN2M
    <13,64,67,73,85,93,94> -PLTRST_FAR
    1 1 1 1 1 1 1
    AA22 SWG@ SWG@ SWG@ SWG@ @ SWG@ SWG@
    PEX_DVDD_1
    D3702 SWG@ 1 2 RB521CM-30T2R_VMN2M AC7 AB23 C3702 C3703 C3704 C3705 C3706 C3707 C3708
    <3> -GPU_RST PEX_RST* PEX_DVDD_2
    AC24 1U_6.3V_K_X5R_0402 4.7UC_6.3VC_KC_X6SC_0603
    PEX_DVDD_3 2 2 2 2 2 2 2
    -CLKREQ_PCIE9_VGA AC6 AD25
    PEX_CLKREQ* PEX_DVDD_4
    AE26
    PEX_DVDD_5
    AE8 AE27
    <12> PCIE9_CLK_100M AD8 PEX_REFCLK PEX_DVDD_6
    <12> -PCIE9_CLK_100M PEX_REFCLK* NEAR BALLS
    PCIE9_L0_RXP C3701 1 2 0.22U_6.3V_K_X5R_0201 SWG@ PCIE9_L0_RXP_C AC9
    <10> PCIE9_L0_RXP AB9 PEX_TX0
    PCIE9_L0_RXN C3709 1 2 0.22U_6.3V_K_X5R_0201 SWG@ PCIE9_L0_RXN_C ???mA
    <10> PCIE9_L0_RXN PEX_TX0*
    VCC1R8VIDEO_MAIN
    PCIE9_L0_TXP AG6
    <10> PCIE9_L0_TXP AG7 PEX_RX0
    AA10
    PCIE9_L0_TXN
    <10> PCIE9_L0_TXN PEX_RX0* PEX_HVDD_1
    AA12
    PEX_HVDD_2
    PCIE9_L1_RXP C3710 1 2 0.22U_6.3V_K_X5R_0201 SWG@ PCIE9_L1_RXP_C AB10 AA13
    <10> PCIE9_L1_RXP PEX_TX1 PEX_HVDD_3

    4.7UC_6.3VC_KC_X6SC_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    4.7UC_6.3VC_KC_X6SC_0603
    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402

    10UC_6.3VC_MC_X5RC_0603
    PCIE9_L1_RXN C3711 1 2 0.22U_6.3V_K_X5R_0201 SWG@ PCIE9_L1_RXN_C AC10 AA16
    <10> PCIE9_L1_RXN PEX_TX1* PEX_HVDD_4
    AA18
    PEX_HVDD_5 1 1 1 1 1 1 1 1 1
    PCIE9_L1_TXP AF7 AA19 SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ C3718 SWG@ SWG@
    <10> PCIE9_L1_TXP AE7 PEX_RX1 PEX_HVDD_6
    AA20
    PCIE9_L1_TXN C3712 C3713 C3714 C3715 C3716 C3717 @ C3719 C3720
    <10> PCIE9_L1_TXN PEX_RX1* PEX_HVDD_7
    AA21
    PEX_HVDD_8 2 2 2 2 2 2 2 2 2
    PCIE9_L2_RXP C3721 1 2 0.22U_6.3V_K_X5R_0201 SWG@ PCIE9_L2_RXP_C AD11 AB22
    <10> PCIE9_L2_RXP AC11 PEX_TX2 PEX_HVDD_9
    AC23
    PCIE9_L2_RXN C3722 1 2 0.22U_6.3V_K_X5R_0201 SWG@ PCIE9_L2_RXN_C
    <10> PCIE9_L2_RXN PEX_TX2* PEX_HVDD_10
    AD24
    PEX_HVDD_11
    PCIE9_L2_TXP AE9 AE25
    <10> PCIE9_L2_TXP AF9 PEX_RX2 PEX_HVDD_12
    AF26
    PCIE9_L2_TXN
    <10> PCIE9_L2_TXN PEX_RX2* PEX_HVDD_13
    AF27
    PEX_HVDD_14
    PCIE9_L3_RXP C3723 1 2 0.22U_6.3V_K_X5R_0201 SWG@ PCIE9_L3_RXP_C AC12
    <10> PCIE9_L3_RXP AB12 PEX_TX3
    PCIE9_L3_RXN C3724 1 2 0.22U_6.3V_K_X5R_0201 SWG@ PCIE9_L3_RXN_C
    <10> PCIE9_L3_RXN PEX_TX3*
    PCIE9_L3_TXP AG9 10uF 2pc change to 22uF 1pc
    <10> PCIE9_L3_TXP AG10 PEX_RX3
    PCIE9_L3_TXN
    <10> PCIE9_L3_TXN PEX_RX3*
    AB13
    Cap near U208 side AC13 PEX_TX4
    PEX_TX4*
    AF10 210mA
    PEX_RX4
    C AE10 C
    PEX_RX4*
    VCC1R8VIDEO_MAIN
    AD14
    PEX_TX5
    AC14 AA8
    PEX_TX5* PEX_PLL_HVDD_1
    AA9
    PEX_PLL_HVDD_2
    AE12
    PEX_RX5
    AF12 1
    PEX_RX5*
    SWG@
    AC15 C3725
    PEX_TX6
    AB15 0.1UC_10VC_KC_X7RC_0402
    PEX_TX6* 2
    AG12
    PEX_RX6
    AG13
    PEX_RX6*
    AB16
    PEX_TX7
    AC16
    PEX_TX7*
    AF13
    PEX_RX7
    VCC1R8VIDEO_AON AE13
    PEX_RX7*
    AD17
    PEX_TX8
    AC17
    PEX_TX8*
    VCC3_SUS AE15
    PEX_RX8
    1

    SWG@ AF15
    PEX_RX8*
    R3704
    1/20W_10K_5%_0201 AC18
    PEX_TX9
    AB18
    PEX_TX9*

    PEX LANES 15 - 4 ARE DEFEATURED


    2
    5

    AG15
    PEX_RX9
    1 AG16
    P

    <41,95,115,116> GFXCORE_D_PWRGD B
    4
    PEX_RX9*
    2 Y DGFX_PWRGD <11> AB19
    <116> 1R35VIDEO_PWRGD A PEX_TX10
    G

    AC19
    PEX_TX10*
    SWG@
    3

    U3701 AF16
    PEX_RX10
    MC74VHC1G09DFT2G_SC70-5 AE16
    PEX_RX10*
    AD20
    PEX_TX11
    2

    B AC20 B
    PEX_TX11*
    R3705
    0_0402_SP AE18
    PEX_RX11
    VCC1R8VIDEO_AON AF18
    PEX_RX11*
    1

    AC21
    PEX_TX12
    AB21
    PEX_TX12*
    N3703
    AG18
    PEX_RX12
    1

    SWG@ AG19
    PEX_RX12*
    R3706
    2

    SWG@ AD23
    G

    1/20W_10K_5%_0201 PEX_TX13
    Q3701 AE23
    PEX_TX13*
    RUM002N05MGT2L_VMT3
    2

    AF19
    PEX_RX13
    S

    -CLKREQ_PCIE9_VGA 3 1 AE19
    -CLKREQ_PCIE9 <12> PEX_RX13*
    AF24
    PEX_TX14
    AE24
    PEX_TX14*
    AE21
    PEX_RX14
    AF21
    PEX_RX14*
    AG24
    PEX_TX15
    AG25
    PEX_TX15*
    AG21
    PEX_RX15
    AG22
    PEX_RX15*

    AF25 PEX_TERMP
    PEX_TERMP

    N17S-G1-A1_GB2C64-595

    1
    SWG@
    R3707
    2 1/20W_2.49K_1%_0201

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 N17S-G1 (1/6) : PEG I/F
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 37 of 125
    5 4 3 2 1
    5 4 3 2 1

    <45> FBA_D[63:0]

    @
    UGPU1B
    2/14 FBA
    FBA_D0 E18
    FBA_D0
    FBA_D1 F18
    FBA_D1
    FBA_D2 E16
    FBA_D2
    FBA_D3 F17
    FBA_D3
    FBA_D4 D20
    FBA_D4
    D FBA_D5 D21 D
    FBA_D5
    FBA_D6 F20
    FBA_D6
    FBA_D7 E21
    FBA_D7
    FBA_D8 E15
    FBA_D8
    FBA_D9 D15
    FBA_D9
    FBA_D10 F15
    FBA_D10
    FBA_D11 F13
    FBA_D11
    FBA_D12 C13
    FBA_D12
    FBA_D13 B13
    FBA_D13
    FBA_D14 E13
    FBA_D14
    FBA_D15 D13
    FBA_D15
    FBA_D16 B15
    FBA_D16
    FBA_D17 C16
    FBA_D17
    FBA_D18 A13
    FBA_D18
    FBA_D19 A15
    FBA_D19
    FBA_D20 B18
    FBA_D20
    FBA_D21 A18
    FBA_D21
    FBA_D22 A19
    FBA_D22
    FBA_D23 C19
    FBA_D23
    FBA_D24 B24
    FBA_D24
    FBA_D25 C23
    FBA_D25
    FBA_D26 A25
    FBA_D26
    FBA_D27 A24
    FBA_D27
    FBA_D28 A21
    FBA_D28
    FBA_D29 B21
    FBA_D29
    FBA_D30 C20
    FBA_D30
    FBA_D31 C21
    FBA_D31
    FBA_D32 R22
    FBA_D32
    FBA_D33 R24 C27 -FBA_CS_L
    T22 FBA_D33 FBA_CMD0
    C26 -FBA_CS_L <45>
    FBA_D34 FBA_BA3_L
    R23 FBA_D34 FBA_CMD1
    E24 FBA_BA3_L <45>
    FBA_D35 FBA_BA0_L
    N25 FBA_D35 FBA_CMD2
    F24 FBA_BA0_L <45>
    FBA_D36 FBA_BA2_L
    N26 FBA_D36 FBA_CMD3
    D27 FBA_BA2_L <45>
    FBA_D37 FBA_BA1_L
    N23 FBA_D37 FBA_CMD4
    D26 FBA_BA1_L <45>
    FBA_D38 -FBA_WE_L
    N24 FBA_D38 FBA_CMD5
    F25 -FBA_WE_L <45>
    FBA_D39 FBA_MA8_L
    V23 FBA_D39 FBA_CMD6
    F26 FBA_MA8_L <45>
    FBA_D40 FBA_MA11_L
    V22 FBA_D40 FBA_CMD7
    F23 FBA_MA11_L <45>
    FBA_D41 -FBA_ABI_L
    T23 FBA_D41 FBA_CMD8
    G22 -FBA_ABI_L <45>
    FBA_D42 FBA_RFU_L
    U22 FBA_D42 FBA_CMD9
    G23 FBA_RFU_L <45>
    FBA_D43 FBA_MA10_L
    Y24 FBA_D43 FBA_CMD10
    G24 FBA_MA10_L <45>
    C FBA_D44 FBA_MA9_L C
    AA24 FBA_D44 FBA_CMD11
    F27 FBA_MA9_L <45>
    FBA_D45 -FBA_RAS_L
    Y22 FBA_D45 FBA_CMD12
    G25 -FBA_RAS_L <45>
    FBA_D46 -FBA_RST_L
    AA23 FBA_D46 FBA_CMD13
    G27 -FBA_RST_L <45>
    FBA_D47 -FBA_CKE_L
    AD27 FBA_D47 FBA_CMD14
    G26 -FBA_CKE_L <45>
    FBA_D48 -FBA_CAS_L
    AB25 FBA_D48 FBA_CMD15
    M24 -FBA_CAS_L <45>
    FBA_D49 -FBA_CS_H
    AD26 FBA_D49 FBA_CMD16
    M23 -FBA_CS_H <45>
    FBA_D50 FBA_BA3_H
    AC25 FBA_D50 FBA_CMD17
    K24 FBA_BA3_H <45>
    FBA_D51 FBA_BA0_H
    AA27 FBA_D51 FBA_CMD18
    K23 FBA_BA0_H <45>
    FBA_D52 FBA_BA2_H
    AA26 FBA_D52 FBA_CMD19
    M27 FBA_BA2_H <45>
    FBA_D53 FBA_BA1_H
    W26 FBA_D53 FBA_CMD20
    M26 FBA_BA1_H <45>
    FBA_D54 -FBA_WE_H
    Y25 FBA_D54 FBA_CMD21
    M25 -FBA_WE_H <45>
    FBA_D55 FBA_MA8_H
    R26 FBA_D55 FBA_CMD22
    K26 FBA_MA8_H <45>
    FBA_D56 FBA_MA11_H
    T25 FBA_D56 FBA_CMD23
    K22 FBA_MA11_H <45>
    FBA_D57 -FBA_ABI_H
    N27 FBA_D57 FBA_CMD24
    J23 -FBA_ABI_H <45>
    FBA_D58 FBA_RFU_H
    R27 FBA_D58 FBA_CMD25
    J25 FBA_RFU_H <45>
    FBA_D59 FBA_MA10_H
    V26 FBA_D59 FBA_CMD26
    J24 FBA_MA10_H <45>
    FBA_D60 FBA_MA9_H
    FBA_D60 FBA_CMD27
    K27 FBA_MA9_H <45>
    FBA_D61 V27 -FBA_RAS_H
    FBA_D61 FBA_CMD28
    K25 -FBA_RAS_H <45>
    FBA_D62 W27 -FBA_RST_H
    FBA_D62 FBA_CMD29
    J27 -FBA_RST_H <45>
    FBA_D63 W25 -FBA_CKE_H VCC1R35VIDEO
    FBA_D63 FBA_CMD30
    J26 -FBA_CKE_H <45>
    -FBA_CAS_H
    FBA_CMD31
    B19 -FBA_CAS_H <45>
    FBA_CMD32
    D19 F22 FBA_CMD34 R3801 1 @ 2 1/16W_60.4_1%_0402
    <45> FBA_DBI0 D14 FBA_DQM0 FBA_CMD34
    J22 R3802 1 @ 2 1/16W_60.4_1%_0402
    FBA_CMD35
    <45> FBA_DBI1 C17 FBA_DQM1 FBA_CMD35
    <45> FBA_DBI2 C22 FBA_DQM2
    <45> FBA_DBI3 P24 FBA_DQM3
    <45> FBA_DBI4 W24 FBA_DQM4
    <45> FBA_DBI5 AA25 FBA_DQM5
    <45> FBA_DBI6 U25 FBA_DQM6
    <45> FBA_DBI7 FBA_DQM7

    E19
    <45> FBA_EDC0 C15 FBA_DQS_WP0
    <45> FBA_EDC1 B16 FBA_DQS_WP1 D24
    <45> FBA_EDC2 FBA_DQS_WP2 FBA_CLK0
    D25 FBA_CLK0 <45>
    B22
    <45> FBA_EDC3 FBA_DQS_WP3 FBA_CLK0*
    N22 -FBA_CLK0 <45>
    R25
    <45> FBA_EDC4 FBA_DQS_WP4 FBA_CLK1
    M22 FBA_CLK1 <45>
    W23
    <45> FBA_EDC5 FBA_DQS_WP5 FBA_CLK1* -FBA_CLK1 <45>
    AB26
    B <45> FBA_EDC6 T26 FBA_DQS_WP6 B
    <45> FBA_EDC7 FBA_DQS_WP7

    F19 D18
    FBA_DQS_RN0 FBA_WCK01
    C18 FBA_WCK0 <45>
    C14
    FBA_DQS_RN1 FBA_WCK01*
    D17 -FBA_WCK0 <45>
    A16
    FBA_DQS_RN2 FBA_WCK23
    D16 FBA_WCK1 <45>
    A22
    FBA_DQS_RN3 FBA_WCK23*
    T24 -FBA_WCK1 <45>
    P25
    FBA_DQS_RN4 FBA_WCK45
    U24 FBA_WCK2 <45>
    W22
    FBA_DQS_RN5 FBA_WCK45*
    V24 -FBA_WCK2 <45>
    AB27
    FBA_DQS_RN6 FBA_WCK67
    V25 FBA_WCK3 <45>
    T27
    FBA_DQS_RN7 FBA_WCK67* -FBA_WCK3 <45>
    1.5A
    VCC1R8VIDEO_MAIN
    R3803 FL3801
    F16 Place under GPU FB_PLL_AVDD 1 2 N3802 SWG@ 1 2 MPZ1608S300AT_2P
    FB_PLL_AVDD_1
    P22 1 1 1
    FB_PLL_AVDD_2 0_0603_SP
    SWG@ SWG@ SWG@
    H22 N3801 C3801 C3802 C3803
    FB_REFPLL_AVDD
    0.1UC_10VC_KC_X7RC_0402 0.1UC_10VC_KC_X7RC_0402 22U_6.3V_M_X5R_0603
    2 2 2

    R3804
    Test_Point_20MIL 1 2
    TP3801 1 FB_VREF D23
    FB_VREF
    1 1 0_0603_SP
    SWG@ SWG@
    N17S-G1-A1_GB2C64-595 C3804 C3805
    0.1UC_10VC_KC_X7RC_0402 0.1UC_10VC_KC_X7RC_0402
    2 2

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 N17S-G1 (2/6) : VRAM I/F
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 38 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 VIDEO
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 39 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC1R8VIDEO_MAIN
    30ohm@100MHz ESR=0.01
    FL4001
    1 2
    D MPZ1608S300AT_2P D
    1 1 1 1
    SWG@ SWG@ SWG@ SWG@ SWG@
    C4001 C4002 C4003 C4004
    22U_6.3V_M_X5R_0603 4.7U_6.3V_M_X5R_0402 0.1UC_10VC_KC_X7RC_0402
    2 2 2 2
    0.1UC_10VC_KC_X7RC_0402

    1 UGPU1L
    SWG@ 9/14 XTAL_PLL
    C4005 GM108
    0.1UC_10VC_KC_X7RC_0402 N4001 L6
    2 XS_PLLVDD PLLVDD
    M6
    SP_PLLVDD
    F11
    GPCPLL_AVDD NC
    N6
    VID_PLLVDD NC

    1
    SWG@
    C4006
    0.1UC_10VC_KC_X7RC_0402
    2 N4002A10 C10 N4003
    XTAL_SSIN XTAL_OUTBUFF

    C C
    C11 B10
    XTAL_IN XTAL_OUT
    N17S-G1-A1_GB2C64-595

    1
    1
    SWG@ @ SWG@
    R4001 R4002
    1/20W_10K_5%_0201 R4003 1 @ 2 1/20W_1M_5%_020127MHZ_OUT 1/20W_10K_5%_0201

    1
    SWG@

    2
    2
    SWG@ R4004
    Y4001 1/20W_1.8K_5%_0201
    27MHZ_7PF_8Y27000005
    Crystal

    2
    4 3 N4004
    GND2 OUT
    27MHZ_IN 1 2
    IN GND1

    1 1
    SWG@ SWG@
    C4007 C4008
    10PC_25VC_JC_NPOC_0201 10PC_25VC_JC_NPOC_0201
    2 2

    B B

    Y4001 CRYSTAL 27MHz- 7pF 20ppm


    Vendor P/N LCFC P/N
    TXC 8Y27000005 SJ10000IB00
    KDS 1ZZHAE27000CC0A SJ10000I800

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 N17S-G1 (6/6) : GPIO / XTAL
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 40 of 125
    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    VCC1R8VIDEO_AON

    SWG@

    SWG@
    SWG@

    SWG@

    1 R4104

    SWG@

    1 R4106

    SWG@
    1 R4102

    1 R4103

    1 R4105

    1 R4107
    VCC1R8VIDEO_AON

    1
    D SWG@ D

    1/20W_2.2K_5%_02012

    1/20W_2.2K_5%_02012
    1/20W_2.2K_5%_02012

    1/20W_2.2K_5%_02012

    1/20W_2.2K_5%_02012

    1/20W_2.2K_5%_02012
    R4101
    1/20W_10K_5%_0201 UGPU1M
    8/14 MISC1

    2
    SWG@
    U4101 D9 I2CS_SCL
    RUM002N05MGT2L_VMT3 I2CS_SCL
    D8 I2CS_SDA
    1 3 I2CS_SDA
    -OVERT A6
    <86,95> -SHUTDOWN OVERT
    AE2 A9 N4101
    D

    TS_VREF I2CC_SCL
    B9 N4102 VCC1R8VIDEO_AON
    I2CC_SDA

    1/20W_100K_5%_0201
    E12
    G
    2

    THERMDN

    1/20W_10K_5%_0201
    R4108

    R4110
    1/20W_10K_5%_0201
    R4109
    C9 N4103
    I2CB_SCL

    1
    1
    F12 C8 N4104
    THERMDP I2CB_SDA

    <37> -PEX_RST

    SWG@

    SWG@
    SWG@
    2

    2
    2
    C6
    GPIO0
    GC6_FB_EN VIDEO_PWM_VID <115>
    B2
    GPIO1 SWG@ D4101 2 1 RB521CM-30T2R_VMN2M GC6_FB_EN <11,116>
    D6 N4105
    GPIO2 -GPU_EVENT <11>
    C7
    GPIO3 R4111 1 @ 2 1/20W_0_5%_0201
    F9 1R8VIDEO_MAIN_ON
    GPIO4
    A3
    GPIO5
    A4
    GPIO6
    SWG@ D4102 2 1 RB521CM-30T2R_VMN2M VGA_CORE_PSI <115>
    B6
    GPIO7
    E9 MEM_VDD_VID
    GPIO8
    F8 N4106 R4112 1 @ 2 1/20W_0_5%_0201
    GPIO9 -VIDEO_THERM_ALERT <87>
    C5
    GPIO10 FB_VREF_ACTIVE <45>
    E7
    GPIO11 R4113 1 @ 2 1/20W_0_5%_0201
    D7 N4107
    GPIO12 -VIDEO_POWER_LIMIT <87>
    B4
    GPIO13 SWG@ D4103 2 1 RB521CM-30T2R_VMN2M
    B3
    GPIO14
    C3
    GPIO15
    D5 MEM_VDD_VID <116>
    GPIO16
    D4
    GPIO17
    C2

    1
    GPIO18 SWG@
    F7 SWG@
    C GPIO19 R4114 C
    E6 R4145
    GPIO20 1/20W_100K_5%_0201
    GM108 C4 1/20W_10K_5%_0201
    GPIO21
    A7
    I2CA_SDA GPIO22
    B7

    2
    I2CA_SCL GPIO23

    N17S-G1-A1_GB2C64-595
    @

    VCC3_SUS VCC3_SUS
    SWG@
    U4102

    1 5
    VCC1R8VIDEO_AON <37,95,115,116> GFXCORE_D_PWRGD IN B VCC
    VCC3_SUS

    2
    2
    GFX_PWR_EN 2 Enable: Vh:2.0V Vl:0.8V
    SWG@ IN A
    SWG@
    SWG@ VCC1R8VIDEO_AON R4116 R4117 3 4
    U4103 SWG@ 1/16W_10K_5%_0402 1/16W_10K_5%_0402 SWG@
    GND OUT Y 1R0VIDEO_EN <114>
    1 8 1/20W_200K_5%_0201 1 2 R4118 GFXCORE_D_PWRGD U4104

    1
    1

    GND EN

    1
    2 7 N4108 NL17SZ08DFT2G_SC70-5
    VREF1 VREF2
    I2CS_SCL 3 6 N4110 1 5 SWG@
    SCL1 SCL2 I2C_CLK_VIDEO <87> IN B VCC
    2

    I2CS_SDA 4 5 R4119
    SDA1 SDA2 I2C_DATA_VIDEO <87> 2 1/16W_100K_5%_0402
    SWG@
    IN A

    3
    PCA9306DQER_X2SON8P_1P4x1 R4120 SWG@

    2
    1/16W_10K_5%_0402 Q4101 3 4
    GND OUT Y GFX_PWR_EN <95>
    1
    1

    SWG@ N4109 1 2 LSK3541G1ET2L_VMT3


    C4101 SWG@ NL17SZ08DFT2G_SC70-5
    1

    1
    100P_25V_J_NPO_0201 Q4102 D
    2 1R8VIDEO_MAIN_ON 2 SWG@
    G R4121
    1/16W_100K_5%_0402 VCC3_SUS
    S
    3

    2
    RUM002N05MGT2L_VMT3

    2
    SWG@
    R4122
    <3,117> 1R8VIDEO_AON_ON 1/16W_10K_5%_0402

    1
    SWG@
    B R4123 B
    1/16W_10K_5%_0402
    VCC1R0VIDEO_PWRGD

    1
    VCC1R8VIDEO_AON VCC1R0VIDEO_PWRGD <116>

    VCC1R8VIDEO_AON

    3
    SWG@
    UGPU1K Q4103
    10/14 MISC2 VCC1R0VIDEO
    1

    1
    1

    SWG@ SWG@ SWG@ N4111 1 LSK3541G1ET2L_VMT3


    1

    1
    1

    1
    1

    2
    VX76@ VX76@ VX76@ @ @ @ R4130 R4131 R4132
    R4125 R4126 R4127 R4124 R4128 R4129 1/20W_100K_1%_02011/20W_100K_1%_0201 1/20W_100K_1%_0201

    1
    1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201
    1/20W_100K_1%_0201 SWG@
    D12 Q4104
    2

    ROM_CS*
    2
    2

    2 DTC015TMT2L NPN VMT3


    2

    2
    2

    2
    2

    B12 N4114
    ROM_SI
    A12 N4113
    ROM_SO
    STRAP0 D1 C12 N4112
    STRAP0 ROM_SCLK

    3
    STRAP1 D2
    STRAP1
    STRAP2 E4
    STRAP2
    1
    1

    STRAP3 E3 @ @ SWG@ SWG@


    STRAP3
    STRAP4 D3 R4133 R4134 R4135 D4104
    STRAP4
    STRAP5 C1 1/20W_100K_1%_02011/20W_100K_1%_0201 1/20W_100K_1%_0201 2 1
    STRAP5 NC GM108
    RB751S40T1G_SOD523-2
    2
    1
    1

    1
    1

    2
    1

    VX76@ VX76@ VX76@ SWG@ SWG@ SWG@ VCC3_SUS


    R4136 R4137 R4138 R4139 R4140 R4141 D11 SWG@
    RESERVED BUFRST*
    1/20W_100K_1%_0201
    1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201 U4105

    1 5
    Delay core power disable for around 100us to make
    2
    2

    2
    2

    sure PCIE power drop earlier than core power.


    2

    <117,118> 1R8_MAIN_PWRGD IN B VCC


    GFX_PWR_EN 2 SWG@
    IN A
    D4105 Enable: Vh:1.5V Vl:0.7V
    3 4 N4115 2 1
    GND OUT Y GFXCORE_D_EN <115>
    RB751S40T1G_SOD523-2
    NL17SZ08DFT2G_SC70-5

    1
    1 2 SWG@

    1
    N17S-G1-A1_GB2C64-595 R4144
    @ @ @ R4142 1/20W_100K_5%_0201
    ZZZ ZZZ R4143 1/16W_1K_1%_0402
    1/16W_100K_5%_0402
    N17-G2 VX76 Config (VRAM + Resistance)

    2
    2
    STRAP 0 STRAP 1 STRAP 2
    A Memory Density Vendor Manufacturer P/N RAMCFG Setting Number A
    R4125 R4136 R4126 R4137 R4127 R4138 Micron 2G Hynix 2G
    MT51J256M32HF-80:B X7645Q0100B X7645Q0100C
    Micron B-die SA00007Z920 9 (0x0009) No ASM ASM ASM ASM No ASM ASM M17G@ H17G@
    8Gb (256M x 32) H5GC8H24AJR-R2C
    Hynix A-die A (0x000A) ASM No ASM ASM ASM No ASM ASM ZZZ ZZZ

    N19M-Q1 VX76 Config (VRAM + Resistance)


    STRAP 0 STRAP 1 STRAP 2
    Memory Density Vendor Manufacturer P/N RAMCFG Setting Number Micron 2G Hynix 2G Title
    R4125 R4136 R4126 R4137 R4127 R4138 Security Classification LC Future Center Secret Data
    X7645Q0100D X7645Q0100E
    Vinafix.com MT51J256M32HF-70:B Issued Date 2019/01/12 Deciphered Date 2019/04/12 N17S-G1 (6/6) : GPIO / XTAL
    Micron B-die SA000081720 4 (0x0004) No ASM ASM No ASM ASM ASM No ASM M19Q@ H19Q@
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    8Gb (256M x 32) H5GC8H24AJR-R0C AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom C 0.1
    Hynix A-die SA000081620 5 (0x0005) ASM No ASM No ASM ASM ASM No ASM DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 41 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCCGFXCORE_D

    Place under GPU @


    UGPU1C
    11/14 NVVDD
    K10
    VDD_001
    1 1 1 2 2 2 2 2 2 2 2 K12
    VDD_002
    SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ K14
    VDD_003
    C4201 C4202 C4211 C4203 C4204 C4205 C4206 C4207 C4208 C4209 C4210 K16
    VDD_004
    1U_6.3V_K_X5R_0402 1U_6.3V_K_X5R_0402 1U_6.3V_K_X5R_0402 4.7U_6.3V_M_X5R_0402 4.7U_6.3V_M_X5R_0402 4.7U_6.3V_M_X5R_0402 4.7U_6.3V_M_X5R_0402 4.7U_6.3V_M_X5R_0402 4.7U_6.3V_M_X5R_0402 4.7U_6.3V_M_X5R_0402 4.7U_6.3V_M_X5R_0402 K18
    2 2 2 1 1 1 1 1 1 1 1 VDD_005
    L13
    VDD_006
    L15
    VDD_007
    M10
    VDD_008
    D M12 D
    VDD_009
    M16
    VDD_010
    M18
    VDD_011
    N11
    VDD_012
    Place near GPU N13
    VDD_013
    N15
    VDD_014
    N17
    VDD_015

    4.7UC_6.3VC_KC_X6SC_0603
    4.7UC_6.3VC_KC_X6SC_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    4.7UC_6.3VC_KC_X6SC_0603

    4.7UC_6.3VC_KC_X6SC_0603

    22U_6.3V_M_X5R_0603
    P14
    VDD_016

    10U_6.3V_M_X5R_0402
    1 1 1 1 1 1 1 1 1 1 R11
    VDD_017
    SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ R13
    VDD_018
    C4212 C4213 C4214 C4215 C4216 C4217 C4218 C4219 C4220 C4221 R15
    VDD_019
    10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 R17
    2 2 2 2 2 2 2 2 2 2 VDD_020
    T10
    VDD_021
    T12
    VDD_022
    T16
    VDD_023
    T18
    VDD_024
    U13
    VDD_025
    NV recommand Add U15
    VDD_026
    V10
    VDD_027
    V12
    VDD_028
    1 V14
    VDD_029
    1 1 SWG@ V16
    + VDD_030
    SWG@ SWG@ C4222 V18
    VDD_031
    C4223 C4224 330U_D2_2V_R9M
    10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402
    2 2 2
    F2
    VDD_SENSE
    F1 GPU_VDD_SENSE <115>
    GND_SENSE GPU_GND_SENSE <115>

    trace width: 16mils


    N17S-G1-A1_GB2C64-595
    differential voltage sensing.
    differential signal routing.
    C C
    VCC1R35VIDEO
    @
    Place under GPU UGPU1D
    12/14 FBVDDQ

    B26
    FBVDDQ_01
    1 1 1 1 1 1 1 1 1 1 C25
    SWG@ SWG@ SWG@ FBVDDQ_02
    SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ E23
    C4225 C4229 C4233 FBVDDQ_03
    C4226 C4227 C4228 C4230 C4231 C4232 C4234 E26
    1U_6.3V_K_X5R_0402 1U_6.3V_K_X5R_0402 1U_6.3V_K_X5R_0402 10U_6.3V_M_X5R_0402 FBVDDQ_04
    1U_6.3V_K_X5R_0402 1U_6.3V_K_X5R_0402 1U_6.3V_K_X5R_0402 1U_6.3V_K_X5R_0402 1U_6.3V_K_X5R_0402 10U_6.3V_M_X5R_0402 F14
    2 2 2 2 2 2 2 2 2 2 FBVDDQ_05
    F21
    FBVDDQ_06
    G13
    FBVDDQ_07
    G14
    FBVDDQ_08
    G15
    FBVDDQ_09
    G16
    FBVDDQ_10
    G18
    FBVDDQ_11
    G19
    FBVDDQ_12
    Place near GPU G20
    FBVDDQ_13
    G21
    FBVDDQ_14
    L22
    FBVDDQ_19
    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    L24
    FBVDDQ_20
    1 1 1 1 L26
    SWG@ FBVDDQ_21
    SWG@ SWG@ SWG@ M21
    C4237 FBVDDQ_22
    C4235 C4236 C4238 N21
    FBVDDQ_23
    10U_6.3V_M_X5R_0402 R21
    2 2 2 2 T21 FBVDDQ_24
    FBVDDQ_25
    V21
    FBVDDQ_26
    W21
    FBVDDQ_27
    H24
    FBVDDQ_15
    H26
    FBVDDQ_16
    J21
    FBVDDQ_17
    K21
    FBVDDQ_18

    B B

    VCC1R35VIDEO

    1
    SWG@
    R4201
    1/16W_40.2_1%_0402

    2
    D22 FB_CAL_PD_VDDQ
    FB_CAL_PD_VDDQ

    C24 FB_CAL_PU_GND
    FB_CAL_PU_GND

    B25 N4203
    FB_CAL_TERM_GND

    1
    1
    SWG@
    SWG@ R4203
    R4202 1/16W_40.2_1%_0402
    1/16W_60.4_1%_0402

    2
    2
    N17S-G1-A1_GB2C64-595

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 N17S-G1 (3/6) : POWER 1
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 42 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCCGFXCORE_D

    VCCGFXCORE_D @
    UGPU1F
    Place under GPU 7/14 VDDS

    @
    L11 UGPU1G
    VDDS_1
    D L17 6/14 XVDD D
    VDDS_2
    M14
    VDDS_3
    P10
    VDDS_4
    2 2 2 2 2 2 P12 G1 N4
    VDDS_5 XVDD_1 XVDD_36
    SWG@ SWG@ SWG@ SWG@ SWG@ SWG@ P16 G2 N5
    VDDS_6 XVDD_2 XVDD_37
    C4301 C4302 C4305 C4303 C4304 C4306 P18 G3 N7
    VDDS_7 XVDD_3 XVDD_38
    1U_6.3V_K_X5R_0402 1U_6.3V_K_X5R_0402 4.7U_6.3V_M_X5R_0402 4.7U_6.3V_M_X5R_0402 4.7U_6.3V_M_X5R_0402 4.7U_6.3V_M_X5R_0402 T14 G4 P3
    1 1 1 1 1 1 VDDS_8 XVDD_4 XVDD_39
    U11 G5 P4
    VDDS_9 XVDD_5 XVDD_40
    U17 G6 P6
    VDDS_10 XVDD_6 XVDD_41
    G7 R1
    XVDD_7 XVDD_42
    H3 R2
    XVDD_8 XVDD_43
    H4 R3
    XVDD_9 XVDD_44
    H6 R4
    XVDD_10 XVDD_45
    J1 R5
    XVDD_11 XVDD_46
    GM108 J2 R6
    XVDD_12 XVDD_47
    J3 R7
    Place near GPU RSVD F4 J4 XVDD_13 XVDD_48
    T1
    VDDS_SENSE XVDD_14 XVDD_49
    RSVD
    F3 J5 T2
    GNDS_SENSE XVDD_15 XVDD_50
    J6 T3
    XVDD_16 XVDD_51
    J7 T4
    XVDD_17 XVDD_52

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    N17S-G1-A1_GB2C64-595 K1 T5
    XVDD_18 XVDD_53

    10U_25V_M_X5R_0603
    10U_25V_M_X5R_0603

    2 1 2 1 2 K2 T6
    XVDD_19 XVDD_54
    @ SWG@ @ SWG@ SWG@ K3 T7
    XVDD_20 XVDD_55
    C4307 C4308 C4309 C4310 C4311 K4 U3
    XVDD_21 XVDD_56
    10U_25V_M_X5R_0603 K5 U4
    1 2 1 2 1 XVDD_22 XVDD_57
    K6 U6
    XVDD_23 XVDD_58
    K7 V1
    XVDD_24 XVDD_59
    L3 V2
    XVDD_25 XVDD_60
    L4 V3
    XVDD_26 XVDD_61
    M1 GM108 XVDD_62 V4
    XVDD_27
    M2 V5
    XVDD_28 XVDD_63
    M3 V6
    XVDD_29 XVDD_64
    10uF 4pc change to 22uF 2pc M4 RSVD XVDD_65
    V7
    XVDD_30
    M5 W1
    XVDD_31 XVDD_66
    M7 W2
    XVDD_32 XVDD_67
    N1 W3
    XVDD_33 XVDD_68
    N2 W4
    XVDD_34 XVDD_69
    22UC_6.3VC_MC_X5RC_0805C_H1.25

    N3
    XVDD_35
    1 2
    C SWG@ SWG@ C
    C4312 C4313
    10U_6.3V_M_X5R_0402
    2 1

    N17S-G1-A1_GB2C64-595

    VCC1R8VIDEO_MAIN

    B B
    0.1UC_10VC_KC_X7RC_0402
    1U_6.3V_K_X5R_0402

    0.1UC_10VC_KC_X7RC_0402
    4.7U_6.3V_M_X5R_0402

    2 1 1 1
    SWG@ SWG@ SWG@ SWG@
    C4314 C4315 C4316 C4317
    @
    UGPU1E 1 2 2 2
    14/14 VDD18

    G8
    VDD18_1
    G9
    VDD18_2
    G10
    1V8_AON_1
    G12
    1V8_AON_2

    VCC1R8VIDEO_AON
    NV recommand change to 4.7uF
    0.1UC_10VC_KC_X7RC_0402

    1U_6.3V_K_X5R_0402
    0.1UC_10VC_KC_X7RC_0402

    4.7U_6.3V_M_X5R_0402

    1 1 2 2
    SWG@ SWG@ SWG@ SWG@
    C4318 C4319 C4320 C4321
    2 2 1 1
    N17S-G1-A1_GB2C64-595

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 N17S-G1 (4/6) : POWER 2
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 43 of 125
    5 4 3 2 1
    5 4 3 2 1

    @
    UGPU1H
    13/14 GND

    A2 K11
    GND_001 GND_057
    AB17 K13
    GND_005 GND_058
    AB20 K15 @
    GND_006 GND_059
    AB24 K17 UGPU1I
    GND_007 GND_060
    AC2 L10 5/14 NC
    GND_008 GND_061
    AC22 L12 @
    GND_009 GND_062
    AC26 L14 GM108 UGPU1J
    GND_010 GND_063
    AC5 L16 TP4401 1Test_Point_20MIL N4407 AA14 PEX_PLLVDD 4/14 IFPAB
    GND_011 GND_064 NC_1
    AC8 L18 TP4402 1Test_Point_20MIL N4408 AA15 PEX_PLLVDD
    GND_012 GND_065 NC_2
    AD12 L5 AB6 DVI HDMI DP
    GND_013 GND_069 NC_3
    D AD13 M11 TP4403 1Test_Point_20MIL N4409 AB8 PEX_SVDD_3V3 SL/DL D
    GND_014 GND_070 NC_4
    A26 M13 AD10
    GND_002 GND_071 NC_5
    AD15 M15 AD7 AC4
    GND_015 GND_072 NC_6 IFPA_L3*
    AD16 M17 TP4404 1Test_Point_20MIL N4410 AE22 PEX_TSTCLK* TXC/TXC AC3
    GND_016 GND_073 NC_7 IFPA_L3
    AD18 N10 AE3
    GND_017 GND_074 NC_8
    AD19 N12 AE4 AA6
    GND_018 GND_075 NC_9 IFPAB_RSET
    AD21 N14 AF2 TXD0/0 Y3
    GND_019 GND_076 NC_10 IFPA_L2*
    AD22 N16 TP4405 1Test_Point_20MIL N4411 AF22 PEX_TSTCLK Y4
    GND_020 GND_077 NC_11 IFPA_L2
    AE11 N18 AF3
    GND_021 GND_078 NC_12
    AE14 P11 AF4
    GND_022 GND_079 NC_13
    AE17 P13 AG3 TXD1/1 AA2
    GND_023 GND_080 NC_14 IFPA_L1*
    AE20 P15 D10 W7 AA3
    GND_024 GND_081 NC_15 IFPAB_PLLVDD IFPA_L1
    AB11 P17 E10
    GND_003 GND_082 NC_16
    AF1 P23 F10
    GND_025 GND_084 NC_17
    AF11 P26 F5 TXD2/2 AA1
    GND_026 GND_085 NC_18 IFPA_L0*
    AF14 R10 F6 MLS_REF0 AB1
    GND_027 GND_087 NC_19 IFPA_L0
    AF17 R12 W5
    GND_028 GND_088 NC_20
    AF20 R14
    GND_029 GND_089
    AF23 R16 GM108 COMPATIBLE DESIGNS MUST AA5
    GND_030 GND_090 IFPA_AUX_SDA*
    AF5 R18 LEAVE NC PINS FLOATING EXCEPT AA4
    GND_031 GND_091 IFPA_AUX_SCL
    AF8 T11 FOR THOSE
    GND_032 GND_092 SHOWN
    AG2 T13
    GND_033 GND_093
    AG26 T15 N17S-G1-A1_GB2C64-595 AB4
    GND_034 GND_094 IFPB_L3*
    AB14 T17 TXC AB5
    GND_004 GND_095 IFPB_L3
    B1 U10
    GND_035 GND_096
    B11 U12
    GND_036 GND_097
    B14 U14 W6 TXD0/3 AB2
    GND_037 GND_098 IFP_IOVDD_1 IFPB_L2*
    B17 U16 AB3
    GND_038 GND_099 IFPB_L2
    B20 U18 Y6
    GND_039 GND_100 IFP_IOVDD_2
    B23 U23
    GND_040 GND_102
    B27 U26 TXD1/4 AD2
    GND_041 GND_103 IFPB_L1*
    B5 V11 AD3
    GND_042 GND_105 IFPB_L1
    B8 V13
    GND_043 GND_106
    E11 V15
    GND_044 GND_107
    E14 V17 TXD2/5 AD1
    GND_045 GND_108 IFPB_L0*
    E17 Y2 AE1
    GND_046 GND_109 IFPB_L0
    E2 Y23
    GND_047 GND_110
    E20 Y26
    GND_048 GND_111
    E22 Y5 AD5
    GND_049 GND_112 IFPB_AUX_SDA*
    C E25 AA7 AD4 C
    GND_050 GND_F IFPB_AUX_SCL
    E5 AB7
    GND_051 GND_H
    E8
    GND_052

    IFPAB (DEFEATURED 0N GM108)

    N17S-G1-A1_GB2C64-595
    OPTIONAL GND:

    XVDD AREA

    H2 P2
    GND_053 GND_083
    H5 P5
    GND_056 GND_086
    L2 U2
    GND_066 GND_101
    U5
    GND_104

    PCB ADR/CMD

    PWR REFERENCE
    H23 L23
    GND_054 GND_067
    H25 L25
    GND_055 GND_068
    N17S-G1-A1_GB2C64-595

    B B
    @
    UGPU1N
    3/14 JTAG

    R4401 1 @ 21/20W_10K_5%_0201 N4401 AE5


    TP4406 1Test_Point_20MIL JTAG_TCK
    N4402 AE6
    TP4407 1Test_Point_20MIL JTAG_TDI
    N4403 AF6
    JTAG_TDO
    TP4408 1Test_Point_20MIL N4404 AD6
    JTAG_TMS
    R4402 2 SWG@ 11/20W_10K_5%_0201 N4405 AG4
    JTAG_TRST*
    R4403 2 SWG@ 11/20W_10K_5%_0201 N4406 AD9
    NVJTAG_SEL

    N17S-G1-A1_GB2C64-595

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date Deciphered Date 2019/04/12 N17S-G1 (5/6) : GND
    2019/01/12
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 44 of 125
    5 4 3 2 1
    5 4 3 2 1

    <38> FBA_D[0..63]

    MF=0 UV2

    UV1 MF=0 MF=1 MF=1 MF=0

    MF=0 MF=1 MF=1 MF=0 VCC1R35VIDEO A4 FBA_D38


    DQ24 DQ0
    FBA_EDC4 C2 A2 FBA_D36
    VCC1R35VIDEO FBA_D4 <38> FBA_EDC4 FBA_EDC5 C13 EDC0 EDC3 DQ25 DQ1
    B4 FBA_D32
    A4
    FBA_EDC0 DQ24 DQ0
    FBA_D6 <38> FBA_EDC5 FBA_EDC6 R13 EDC1 EDC2 DQ26 DQ2
    B2 FBA_D37
    C2 A2 BYTE4
    <38> FBA_EDC0 FBA_EDC1 EDC0 EDC3 DQ25 DQ1
    FBA_D0 <38> FBA_EDC6 R2 EDC2 EDC1 DQ27 DQ3
    E4
    C13 B4 FBA_EDC7 FBA_D33
    <38> FBA_EDC1 EDC1 EDC2 DQ26 DQ2 <38> FBA_EDC7 EDC3 EDC0 DQ28 DQ4
    E2
    FBA_EDC2 R13 B2 FBA_D7 BYTE0 FBA_D39
    <38> FBA_EDC2 FBA_EDC3 EDC2 EDC1 DQ27 DQ3 DQ29 DQ5
    F4
    D R2 E4 FBA_D5 FBA_D34 D
    <38> FBA_EDC3 EDC3 EDC0 DQ28 DQ4 DQ30 DQ6

    1
    E2 FBA_D1 SWG@ FBA_DBI4 D2 F2 FBA_D35
    <38> FBA_DBI4 DBI0# DBI3# DQ31 DQ7
    1
    DQ29 DQ5 D13 A11
    SWG@ F4 FBA_D2 R4501 FBA_DBI5 FBA_D40
    R4502 D2 DQ30 DQ6
    FBA_D3 <38> FBA_DBI5 P13 DBI1# DBI2# DQ16 DQ8
    A13
    FBA_DBI0 F2 1/16W_10K_5%_0402 FBA_DBI6 FBA_D42
    1/16W_10K_5%_0402 <38> FBA_DBI0 <38> FBA_DBI6
    DBI0# DBI3# DQ31 DQ7 DBI2# DBI1# DQ17 DQ9
    FBA_DBI1 D13 A11 FBA_D8 FBA_DBI7 P2 B11 FBA_D44
    <38> FBA_DBI1 P13 DBI1# DBI2# DQ16 DQ8 <38> FBA_DBI7 DBI3# DBI0# DQ18 DQ10
    B13
    FBA_DBI2 A13 FBA_D11 FBA_D45 BYTE5
    <38> FBA_DBI2

    2
    DBI2# DBI1# DQ17 DQ9 DQ19 DQ11
    FBA_DBI3 P2 B11 FBA_D10 FBA_CLK1 J12 E11 FBA_D41
    <38> FBA_DBI3
    2

    DBI3# DBI0# DQ18 DQ10


    FBA_D15 <38> FBA_CLK1 J11 CK DQ20 DQ12
    E13
    B13 BYTE1 -FBA_CLK1 FBA_D46
    DQ19 DQ11
    FBA_D9 <38> -FBA_CLK1 J3 CK# DQ21 DQ13
    F11
    FBA_CLK0 J12 E11 -FBA_CKE_H FBA_D47
    <38> FBA_CLK0 CK DQ20 DQ12
    FBA_D12 <38> -FBA_CKE_H CKE# DQ22 DQ14
    F13
    -FBA_CLK0 J11 E13 FBA_D43
    <38> -FBA_CLK0 CK# DQ21 DQ13
    FBA_D13
    DQ23 DQ15
    U11
    -FBA_CKE_L J3 F11 FBA_D51
    <38> -FBA_CKE_L CKE# DQ22 DQ14 H11 DQ8 DQ16
    U13
    F13 FBA_D14 FBA_BA0_H FBA_D50
    DQ23 DQ15
    U11 <38> FBA_BA0_H K10 BA0/A2 BA2/A4 DQ9 DQ17
    T11
    FBA_D16 FBA_BA1_H FBA_D55
    H11 DQ8 DQ16
    U13 <38> FBA_BA1_H K11 BA1/A5 BA3/A3 DQ10 DQ18
    T13
    FBA_BA0_L FBA_D18 FBA_BA2_H FBA_D48
    <38> FBA_BA0_L BA0/A2 BA2/A4 DQ9 DQ17
    T11 <38> FBA_BA2_H H10 BA2/A4 BA0/A2 DQ11 DQ19
    N11
    FBA_BA1_L K10 FBA_D17 FBA_BA3_H FBA_D52 BYTE6
    <38> FBA_BA1_L BA1/A5 BA3/A3 DQ10 DQ18
    T13 <38> FBA_BA3_H BA3/A3 BA1/A5 DQ12 DQ20
    N13
    FBA_BA2_L K11 FBA_D19 BYTE2 FBA_D53
    <38> FBA_BA2_L BA2/A4 BA0/A2 DQ11 DQ19
    N11
    DQ13 DQ21
    M11
    FBA_BA3_L H10 FBA_D22 FBA_D54
    <38> FBA_BA3_L BA3/A3 BA1/A5 DQ12 DQ20
    N13 K4 DQ14 DQ22
    M13
    FBA_D20 FBA_MA8_H FBA_D49
    DQ13 DQ21 <38> FBA_MA8_H A8/A7 A10/A0 DQ15 DQ23
    M11 FBA_D23 FBA_MA9_H H5 U4 FBA_D63
    DQ14 DQ22 <38> FBA_MA9_H A9/A1 A11/A6 DQ0 DQ24
    FBA_MA8_L K4 M13 FBA_D21 FBA_MA10_H H4 U2 FBA_D62
    <38> FBA_MA8_L A8/A7 A10/A0 DQ15 DQ23 <38> FBA_MA10_H A10/A0 A8/A7 DQ1 DQ25
    FBA_MA9_L H5 U4 FBA_D28 FBA_MA11_H K5 T4 FBA_D61
    <38> FBA_MA9_L A9/A1 A11/A6 DQ0 DQ24 <38> FBA_MA11_H A11/A6 A9/A1 DQ2 DQ26
    FBA_MA10_L H4 U2 FBA_D31 FBA_RFU_H J5 T2 FBA_D57
    <38> FBA_MA10_L A10/A0 A8/A7 DQ1 DQ25 <38> FBA_RFU_H A12/RFU/NC DQ3 DQ27
    FBA_MA11_L K5 T4 FBA_D24 N4 FBA_D60
    <38> FBA_MA11_L
    FBA_RFU_L J5 A11/A6 A9/A1 DQ2 DQ26
    T2 FBA_D25 A5
    DQ4 DQ28
    N2 FBA_D59
    BYTE7
    <38> FBA_RFU_L A12/RFU/NC DQ3 DQ27 VPP/NC1 DQ5 DQ29
    N4 FBA_D27 U5 M4 FBA_D56
    A5
    DQ4 DQ28
    N2 FBA_D30
    BYTE3 VPP/NC2 DQ6 DQ30
    M2 FBA_D58
    VPP/NC1 DQ5 DQ29 DQ7 DQ31
    U5 M4 FBA_D26
    VPP/NC2 DQ6 DQ30 R4503 2 SWG@ 1 1/16W_1K_1%_0402 VCC1R35VIDEO
    DQ7 DQ31
    M2 FBA_D29 N4504J1 MF
    J10
    R4504 2 SWG@ 1 1/16W_1K_1%_0402 N4505 SEN
    R4505 2 SWG@ 1 1/16W_1K_1%_0402 N4501 J1 VCC1R35VIDEO J13
    R4506 2 SWG@ 1 1/16W_120_1%_0402 N4506 B1
    MF ZQ VDDQ1
    R4507 2 SWG@ 1 1/16W_1K_1%_0402 N4502J10 D1
    R4508 2 SWG@ 1 1/16W_120_1%_0402 N4503J13 SEN VDDQ2
    B1 F1
    ZQ VDDQ1 VDDQ3
    D1 -FBA_ABI_H J4 M1
    VDDQ2 <38> -FBA_ABI_H ABI# VDDQ4
    F1 -FBA_RAS_H G3 P1
    VDDQ3 <38> -FBA_RAS_H RAS# CAS# VDDQ5
    -FBA_ABI_L J4 M1 -FBA_CS_H G12 T1
    <38> -FBA_ABI_L ABI# VDDQ4 <38> -FBA_CS_H CS# WE# VDDQ6
    -FBA_RAS_L G3 P1 -FBA_CAS_H L3 G2
    <38> -FBA_RAS_L RAS# CAS# VDDQ5 <38> -FBA_CAS_H CAS# RAS# VDDQ7
    -FBA_CS_L G12 T1 -FBA_WE_H L12 L2
    <38> -FBA_CS_L CS# WE# VDDQ6 <38> -FBA_WE_H WE# CS# VDDQ8
    -FBA_CAS_L L3 G2 B3
    <38> -FBA_CAS_L CAS# RAS# VDDQ7 VDDQ9
    -FBA_WE_L L12 L2 D3
    <38> -FBA_WE_L WE# CS# VDDQ8 VDDQ10
    B3 F3
    VDDQ9 VDDQ11
    D3 -FBA_WCK2 D5 H3
    VDDQ10 <38> -FBA_WCK2 WCK01# WCK23# VDDQ12
    F3 FBA_WCK2 D4 K3
    VDDQ11 <38> FBA_WCK2 WCK01 WCK23 VDDQ13
    -FBA_WCK0 D5 H3 M3
    <38> -FBA_WCK0 WCK01# WCK23# VDDQ12 VDDQ14
    FBA_WCK0 D4 K3 -FBA_WCK3 P5 P3
    <38> FBA_WCK0 WCK01 WCK23 VDDQ13 <38> -FBA_WCK3 WCK23# WCK01# VDDQ15
    M3 FBA_WCK3 P4 T3
    VDDQ14 <38> FBA_WCK3 WCK23 WCK01 VDDQ16
    C -FBA_WCK1 P5 P3 E5 C
    <38> -FBA_WCK1 WCK23# WCK01# VDDQ15 VDDQ17
    FBA_WCK1 P4 T3 N5
    <38> FBA_WCK1 WCK23 WCK01 VDDQ16 VDDQ18
    E5 A10 E10
    VDDQ17 VREFD1 VDDQ19
    N5 U10 N10
    VDDQ18 J14 VREFD2 VDDQ20
    A10 E10 FBA_VREFC B12
    VREFD1 VDDQ19 VREFC VDDQ21
    U10 N10 D12
    VREFD2 VDDQ20 VDDQ22
    FBA_VREFC J14 B12 F12
    VREFC VDDQ21 VDDQ23
    D12 H12
    VDDQ22 VDDQ24
    F12 -FBA_RST_H J2 K12
    VDDQ23 <38> -FBA_RST_H RESET# VDDQ25
    H12 M12
    VDDQ24 VDDQ26
    -FBA_RST_L J2 K12 P12
    <38> -FBA_RST_L RESET# VDDQ25 VDDQ27

    1
    M12 SWG@ T12
    VDDQ26 VDDQ28
    P12 R4509 G13
    1

    SWG@ VDDQ27 VDDQ29


    T12 1/16W_10K_5%_0402 H1 L13
    R4510 VDDQ28 VSS1 VDDQ30
    G13 K1 B14
    1/16W_10K_5%_0402 VDDQ29 VSS2 VDDQ31
    H1 L13 B5 D14
    VSS3 VDDQ32

    2
    VSS1 VDDQ30 G5 F14
    K1 B14 VSS4 VDDQ33
    VSS2 VDDQ31 L5 M14
    B5 D14
    2

    VSS3 VDDQ32 VSS5 VDDQ34


    G5 F14 T5 P14
    VSS4 VDDQ33 VSS6 VDDQ35
    L5 M14 B10 T14
    VSS5 VDDQ34 VSS7 VDDQ36
    T5 P14 D10
    VSS6 VDDQ35 VSS8
    B10 T14 G10
    VSS7 VDDQ36 VSS9
    D10 L10 A1
    VSS10 VSSQ1

    For U93
    VSS8 P10 C1
    G10 VSS11 VSSQ2
    VSS9

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    L10 A1 T10 E1
    VSS12 VSSQ3

    For U91
    VSS10 VSSQ1 H14 N1
    P10 C1 VSS13 VSSQ4 VCC1R35VIDEO 10uF 6pc change to 22uF 3pc

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    VSS11 VSSQ2

    22U_6.3V_M_X5R_0603
    T10 E1 K14 R1
    VSS12 VSSQ3 VSS14 VSSQ5

    10UC_6.3VC_MC_X5RC_0603
    U1

    10UC_6.3VC_MC_X5RC_0603
    H14 N1 VCC1R35VIDEO VCC1R35VIDEO
    10uF 6pc change to 22uF 3pc VSSQ6

    1U_6.3V_K_X5R_0402
    VSS13 VSSQ4

    1U_6.3V_K_X5R_0402
    H2

    1U_6.3V_K_X5R_0402
    K14 R1
    VSS14 VSSQ5 VSSQ7

    10UC_6.3VC_MC_X5RC_0603
    G1 K2

    10UC_6.3VC_MC_X5RC_0603
    VCC1R35VIDEO U1 VDD1 VSSQ8

    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402

    SWG@ C4508
    @ C4503
    VSSQ6

    1U_6.3V_K_X5R_0402

    C4506

    C4507

    SWG@ C4513
    @ C4505
    L1

    C4504
    A3

    SWG@ C4512
    H2 VDD2 VSSQ9 2 1 1 1 1 1 1 1
    VSSQ7 G4 C3
    G1 K2 VDD3 VSSQ10

    @ C4509

    C4515
    VDD1

    C4511

    C4514
    VSSQ8

    C4502
    E3

    C4501

    C4510
    L4

    C4516
    L1 A3 2 1 1 1 1 1 1 1 VDD4 VSSQ11
    VDD2 VSSQ9 C5 N3
    G4 C3 VSSQ12 2
    VDD3 VSSQ10 VDD5 1 2 2 2 2 2

    SWG@
    R3 2

    SWG@
    SWG@
    L4 E3 R5
    VDD4 VSSQ11 VDD6 VSSQ13
    C5 N3 C10 U3
    VSSQ12 1 2 2 2 2 2 VDD7 VSSQ14

    SWG@
    SWG@
    2

    SWG@
    VDD5 2

    SWG@
    @

    C4

    SWG@

    SWG@
    R5 R3 R10
    VDD6 VSSQ13 VDD8 VSSQ15
    C10 U3 D11 R4
    VDD7 VSSQ14 VDD9 VSSQ16
    R10 C4 G11 F5
    VDD8 VSSQ15 VDD10 VSSQ17
    D11 R4 L11 M5
    VSSQ16 VDD11 VSSQ18

    22U_6.3V_M_X5R_0603
    G11 VDD9 F5 P11 F10
    VDD10 VSSQ17 VDD12 VSSQ19
    22U_6.3V_M_X5R_0603

    L11 M5 G14 M10


    VDD13 VSSQ20

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    VDD11 VSSQ18

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402
    L14 C11

    10UC_6.3VC_MC_X5RC_0603

    1U_6.3V_K_X5R_0402
    P11 F10 VDD14 VSSQ21
    VDD12 VSSQ19 R11
    G14 M10 VSSQ22

    1U_6.3V_K_X5R_0402

    C4524
    VDD13

    C4526
    VSSQ20

    C4523
    10UC_6.3VC_MC_X5RC_0603

    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402
    1U_6.3V_K_X5R_0402

    1U_6.3V_K_X5R_0402
    A12

    C4520

    SWG@ C4522
    C4517

    C4518

    C4521
    L14 C11

    SWG@ C4525
    B VSSQ23 1 2 1 1 1 1 1 1 1 B
    VDD14 VSSQ21 C12
    R11 VSSQ24
    C4527

    VSSQ22

    C4533
    C4519

    E12

    SWG@ C4530
    C4528

    C4531

    C4534
    C4529

    C4532
    A12 1 2 1 1 1 1 1 1 1 VSSQ25
    VSSQ23 N12
    C12 VSSQ26 2 2
    2 2 2

    SWG@
    2

    SWG@
    SWG@
    VSSQ24 1 2

    SWG@
    R12

    SWG@

    @
    2

    SWG@
    E12 VSSQ27
    VSSQ25 170-BALL U12
    N12 1 2 VSSQ28
    @

    2 2 2

    SWG@
    VSSQ26 2 2 2 2
    SWG@

    H13
    SWG@

    SWG@

    SWG@
    SWG@

    SWG@
    R12 VSSQ29
    VSSQ27 SGRAM GDDR5 K13
    170-BALL U12 VSSQ30
    VSSQ28 A14
    H13 VSSQ31
    VSSQ29 C14
    SGRAM GDDR5 K13 VSSQ32
    VSSQ30 E14
    A14 VSSQ33
    VSSQ31 N14
    C14 VSSQ34
    VSSQ32

    CLOSE TO THE MEMORY


    E14 R14
    VSSQ33 VSSQ35
    N14 U14
    VSSQ34 VSSQ36

    K4G80325FB-HC03_BGA170
    VSSQ35
    VSSQ36
    X76@
    R14
    U14
    CLOSE TO THE MEMORY K4G80325FB-HC03_BGA170 X76@

    VCC1R35VIDEO FBA_CLK1 SWG@R4511 1 2 1/16W_40.2_1%_0402


    SWG@R4512 1 2 1/16W_40.2_1%_0402
    FBA_CLK0

    2
    @
    1

    SWG@ R4515
    2

    @ R4514 1/16W_160_1%_0402 N4508


    R4513 N4507 1/16W_549_1%_0402
    1/16W_160_1%_0402

    1
    SWG@
    16 mil
    2

    R4517 -FBA_CLK1 SWG@R4518 1 2 1/16W_40.2_1%_0402


    1

    -FBA_CLK0 SWG@R4516 1 2 1/16W_40.2_1%_0402 1 2 FBA_VREFC


    820PC_50VC_KC_X7RC_0402
    0.01UC_25VC_KC_X7RC_0402

    820PC_50VC_KC_X7RC_0402
    SWG@ C4535

    SWG@ C4536
    1/16W_931_1%_0402 1 1
    1

    SWG@ 1
    SWG@ C4537

    1 R4519 SWG@
    1/16W_1.33K_1%_0402 C4538
    2 2 0.01UC_25VC_KC_X7RC_0402
    2
    2
    2

    NV recommand close Vram


    1 N4509

    Q4501 D
    A 2 A
    <41> FB_VREF_ACTIVE G Change to Vgs(th) < 1.0V
    N-MOS, For
    TABLE S FBVREF_ACTIVE = 1.8V
    3

    RUM002N05MGT2L_VMT3
    GDDR5 VIDEO MEMORY SWG@

    SAMSUNG 8GBITS MICRON 8GBITS Hynix

    U91 K4G80325FB-HC28 MT51J256M32HF-70:A H5GC824MJR-R0C


    U93
    Vinafix.com Security Classification LC Future Center Secret Data Title
    Issued Date 2019/01/12 Deciphered Date 2019/04/12 VRAM CHANNEL-A
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom Drift/Ironhide 0.1
    LOGIC Date: Tuesday, December 18, 2018 Sheet 45 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 VIDEO
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 46 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 VIDEO
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 47 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 VIDEO
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 48 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 49 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 50 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC3M

    VCC3M VCC3P

    2
    F5101
    0.5A_32V_ERBRD0R50X
    Q5101
    TABLE : Q5101 AON7408L_DFN8-5

    1
    TOSHIBA : SSM6K504NU 1
    S1
    5 2 @
    ROHM : RF4E080BNTR D S2
    3 JPWR1
    S3 R5101
    D FAIRCHILD : FDMA8878 VCC3M_F5101 1
    1 D

    G
    -LED_PWR 1 2 -LED_PWR_R5101 2
    <85> -LED_PWR 2
    -PWRSWITCH 3
    <17,62,93,94> -PWRSWITCH

    4
    3
    4
    1/16W_240_5%_0402 4

    2
    R5102 5
    GND1

    3
    1/20W_47_5%_0201 6
    GND2
    EMC@ HIGHS_FC1AF041-2201H

    1
    D5101

    R5103
    AZ5125-02S.R7G_SOT23-3 2 2 2

    0.1U_6.3V_K_X5R_0201
    EMC@ C5134

    0.1U_6.3V_K_X5R_0201
    EMC@ C5133

    0.1U_6.3V_K_X5R_0201
    EMC@ C5132
    R5101
    1 1 1

    1
    2

    2
    R5103
    1/20W_100_5%_0201 D5102
    RB521CM-30T2R_VMN2M-2 VSYS15 VBL15

    1
    F5102
    1 2
    VCC3P_DRV
    <95> VCC3P_DRV

    2200P_25V_K_X7R_0201
    1U_25V_K_X5R_0402

    0.1U_25V_K_X5R_0201

    0.01U_25V_K_X7R_0201

    47P_25V_J_NPO_0201
    1 3A_32V_ERBRD3R00X
    C5101 2 2 2 2 2

    C5102

    C5106
    C5103

    C5105
    C5104
    VCC3B VCC3B VCC3LCD 0.01U_25V_K_X7R_0201
    2

    1 1 1 1 1

    RF@
    RF@
    2
    2

    R5106
    R5105
    R5104

    0.5A_32V_ERBRD0R50X
    2
    0.1U_25V_K_X5R_0201
    VCC3B C5107 1/20W_47K_5%_0201
    0.1U_25V_K_X5R_0201
    1

    F5103
    2
    1

    2
    2
    C5108
    C C
    R5109

    1
    1 2 Size CTL 1

    EMC@

    1
    1

    47P_25V_J_NPO_0201
    1/20W_100K_5%_0201

    1/20W_10K_5%_0201
    1/20W_100K_5%_0201

    1000P_25V_K_X7R_0201
    2 2 VCC3P VCC3LCD

    C5110
    C5109
    1 1 F5104

    RF@
    LCD siza control

    RF@
    1 2 VCC3LCD
    Low:14"

    2200P_25V_K_X7R_0201
    1U_6.3V_M_X5R_0201
    0.1U_6.3V_K_X5R_0201

    47P_25V_J_NPO_0201
    0.01U_6.3V_K_X7R_0201
    High:15" 3A_32V_ERBRD3R00X
    2 2 2 2 2

    C5112

    C5113

    C5114
    C5111

    C5115
    PANEL_BKLT_CTRL_CPU D5105 2 1 RB520CM-30T2R_VMN2M2 PANEL_BKLT_CTRL
    <3> PANEL_BKLT_CTRL_CPU
    1 1 1 1 1
    1/20W_10K_5%_0201

    RF@

    RF@
    LCD_SELF_TEST_ON D5106 2 1 RB520CM-30T2R_VMN2M2
    2
    R5110

    LCD CONNECTOR
    1

    JLCD1 @
    40 52
    40 GND12
    39 51
    39 GND11
    38 50
    38 GND10
    37 49
    37 GND9
    36 48
    36 GND8
    35 47
    35 GND7
    -LID_CLOSE D5103 1 2 RB521CM-30T2R_VMN2M-2 -LID_CLOSE_D 34 46
    <52,86,89> -LID_CLOSE 33 34 GND6
    45
    PANEL_BKLT_CTRL
    B 33 GND5 B
    BACKLIGHT_ON 32 44
    <85> BACKLIGHT_ON 31 32 GND4
    43
    31 GND3
    30 42
    30 GND2
    R5107,R5108 USBP6-_CONN 29 41
    29 GND1
    EVT FVT SIT SVT USBP6+_CONN 28
    28
    Resistor V 27
    R-short
    <3> EDP_HPD 26 27
    26
    25
    <8> Size CTL 24 25
    <3,87> LCD_SELF_TEST_ON 23 24
    23
    22
    22
    21
    21
    20
    20
    19
    19
    18
    18
    17
    <8> EPRIVACY_ON 16 17
    16
    C5116 1 2 0.1U_6.3V_K_X5R_0201 EDP_AUXN_CONN 15
    <3> EDP_AUXN C5117 1 2 0.1U_6.3V_K_X5R_0201 14 15
    EDP_AUXP_CONN
    <3> EDP_AUXP 13 14
    C5118 1 2 0.1U_6.3V_K_X5R_0201 13
    EDP_TXP0_CONN 12
    <3> EDP_TXP0 C5119 1 2 0.1U_6.3V_K_X5R_0201 11 12
    EDP_TXN0_CONN
    <3> EDP_TXN0 10 11
    C5120 1 2 0.1U_6.3V_K_X5R_0201 10
    EDP_TXP1_CONN 9
    <3> EDP_TXP1 C5121 1 2 0.1U_6.3V_K_X5R_0201 8 9
    EDP_TXN1_CONN
    <3> EDP_TXN1 7 8
    C5122 1 2 0.1U_6.3V_K_X5R_0201 7
    EDP_TXP2_CONN 6
    <3> EDP_TXP2 C5123 1 2 0.1U_6.3V_K_X5R_0201 5 6
    EDP_TXN2_CONN
    <3> EDP_TXN2 4 5
    C5124 1 2 0.1U_6.3V_K_X5R_0201 4
    EDP_TXP3_CONN 3
    <3> EDP_TXP3 C5125 1 2 0.1U_6.3V_K_X5R_0201 2 3
    EDP_TXN3_CONN
    <3> EDP_TXN3 1 2
    1
    1000P_25V_K_X7R_0201

    I-PEX_20654-040E-01
    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201
    0.1U_6.3V_K_X5R_0201

    2 2 2 2
    EMC_HC@ C5127
    C5126

    EMC_HC@ C5129
    EMC_HC@ C5128

    A A
    1 1 1 1
    RF@

    L5101 EMC@
    USBP6+ 4 3 USBP6+_CONN
    <10> USBP6+ 4 3

    USBP6- 1 2 USBP6-_CONN
    <10> USBP6- 1 2
    EXC24CH900U_4P
    Security Classification LC Future Center Secret Data Title
    Issued Date 2018/01/12 Deciphered Date 2018/01/12 LCD INTERFACE
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 51 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    For IR_LED

    VCC3B VCC3M VCC3B

    2
    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201
    F5204 F5205 F5206

    2A_32V_ERBRD2R00X
    0.5A_32V_ERBRD0R50X
    0.5A_32V_ERBRD0R50X
    2 2

    1
    1 1

    C5209

    C5207
    JCAM1
    30 41
    30 GND11
    29 40
    29 GND10
    28 39
    28 GND9
    27 38
    27 GND8
    26 37
    26 GND7
    25 36
    25 GND6
    C -LED_LOGO R5207 1 2 1/16W_3.9K_5%_0402 -LED_LOGO_R 24 35 C
    <85> -LED_LOGO 24 GND5
    23 34
    23 GND4
    22 33
    22 GND3
    21 32
    21 GND2
    20 31
    20 GND1
    19
    19
    18
    18
    17
    17
    16
    16
    15
    15
    14
    14
    13
    13
    12
    12
    11
    11
    R5214 0_0201_SP USBP8+_CONN 10
    10
    CAM_FW_WR_EN 1 2 USBP8-_CONN 9
    9
    8
    8
    R5215 1 @ 2 1/20W_0_5%_0201 -IR_CAM_DTCT_R 7
    <8> -IR_CAM_DTCT 7
    -INT_MIC_DTCT 6
    <8> -INT_MIC_DTCT EMC@ R5210 1 2 1/16W_33_5%_0402 6
    DMIC_DATA0_CONN 5
    <78> DMIC_DATA0 R5209 1 2 0_0402_SP 5
    DMIC_CLK0_CONN 4
    <78> DMIC_CLK0 4
    3
    3
    R5213 1 @ 2 1/20W_0_5%_0201 CAM_FW_WR_EN_R 2
    <87> CAM_FW_WR_EN 2
    1
    1

    1
    EMC@
    R5212 I-PEX_20654-030E-01
    1/20W_10_5%_0201 @
    1
    EMC_NS@

    2
    C5210
    0.1UC_25VC_KC_X5RC_0402
    2
    1 1
    EMC@ EMC@
    C5208 C5211
    33P_25V_J_NPO_0201 33P_25V_J_NPO_0201
    2 2

    B B

    VCC3SW VCC3SW

    1
    R5211
    1/20W_100K_5%_0201
    @
    JHLSR1

    2
    1
    1
    2
    <51,86,89> -LID_CLOSE 3 2
    3

    2200P_25V_K_X7R_0201
    4
    4
    5
    GND1
    2 6
    GND2

    C5212
    HIGHS_FC1AF041-2201H

    -LID_CLOSE USBP8-_CONN USBP8+_CONN 1

    D5201 D5202
    1

    1 EMC@ EMC@
    PESD5V0H1BSF_SOD962-2

    EMC@
    PESD5V0H1BSF_SOD962-2

    FL5201 EMC@
    1

    C5206 USBP8- 4 3 USBP8-_CONN


    <10> USBP8- 4 3
    10PC_25VC_JC_NPOC_0201
    2
    USBP8+ 1 2 USBP8+_CONN
    A <10> USBP8+ 1 2 A

    EXC24CH900U_4P
    2

    SM070003X00
    2

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 LID/CAMERA/MIC/TOUCH INTERFACE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. C Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 52 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK
    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 HDMI RE-TIMER
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 53 of 125
    5 4 3 2 1
    5 4 3 2 1

    No need diode here because TPS2553 has


    VCC5B_HDMI VCC5B_HDMI
    reverse voltage protection function.

    D D

    2
    R5401 R5402
    1/20W_2.2K_5%_0201 1/20W_2.2K_5%_0201

    FL5401

    1
    HDMI_DATA2N 4 3 HDMI_DATA2N_CONN
    <68> HDMI_DATA2N 4 3
    @ JHDMI1
    HDMI_DATA2P 1 2 HDMI_DATA2P_CONN HDMI_DATA2P_CONN 1 2
    <68> HDMI_DATA2P 1 2 HDMI_DATA2N_CONN TMDS_Data2+ TMDS_Data2_Shield
    HDMI_DATA1P_CONN
    3 4
    TMDS_Data2- TMDS_Data1+
    EXC24CH900U_4P 5 6 HDMI_DATA1N_CONN
    TMDS_Data1 shield TMDS_Data1-
    EMC@ HDMI_DATA0P_CONN 7 8
    TMDS_Data0+ TMDS_Data0 shield
    HDMI_DATA0N_CONN 9 10 HDMI_CLKP_CONN
    TMDS_Data0- TMDS_CLOCK+
    11 12 HDMI_CLKN_CONN
    TMDS_CLOCK shield TMDS_CLOCK-
    13 14
    CEC RESERVED
    FL5402 HDMI_DDC_CLK 15 16 HDMI_DDC_DATA
    HDMI_DATA1N 4 HDMI_DATA1N_CONN <68> HDMI_DDC_CLK SCL SDA
    VCC5B_MDMI HDMI_DDC_DATA <68>
    3 17 18
    <68> HDMI_DATA1N 4 3
    HDMI_HPD_CONN DDC/CEC GND +5V
    19
    <68> HDMI_HPD_CONN HPD
    20
    GND1
    HDMI_DATA1P 1 2 HDMI_DATA1P_CONN 21
    <68> HDMI_DATA1P 1 2 GND2
    22
    GND3
    EXC24CH900U_4P 23
    GND4
    EMC@
    ALLTO_C128AU-K1935-L

    1000P_25V_K_X7R_0201
    FL5403
    HDMI_DATA0N 4 3 HDMI_DATA0N_CONN
    <68> HDMI_DATA0N 4 3

    HDMI_DATA0P 1 2 HDMI_DATA0P_CONN D5401 D5402 D5403


    <68> HDMI_DATA0P 1 2

    1
    1
    1

    680P_25V_K_X7R_0201
    EMC_NS@
    EMC@ EMC@ EMC@
    EXC24CH900U_4P

    PESD5V0H1BSF_SOD962-2
    PESD5V0H1BSF_SOD962-2
    PESD5V0H1BSF_SOD962-2

    1
    1
    1

    680P_25V_K_X7R_0201
    EMC_NS@
    EMC@
    2 2

    EMC@
    2

    C5406
    FL5404
    1 1

    C5401
    HDMI_CLKN 4 3 HDMI_CLKN_CONN
    <68> HDMI_CLKN 4 3

    2
    2
    2

    C5402
    1

    2
    2
    2
    HDMI_CLKP 1 2 HDMI_CLKP_CONN
    <68> HDMI_CLKP 1 2
    EXC24CH900U_4P
    EMC@
    C C

    VCC5B_HDMI

    1
    VCC5B R5403
    0_1%_0603_LE
    2

    D5404 D5405
    U5401
    6 1 N5401 HDMI_DATA2P_CONN 1 HDMI_DATA0P_CONN 1
    IN OUT CH1 CH1
    1/20W_61.9K_1%_0201

    2 N5402 HDMI_DATA2N_CONN 2 9 HDMI_DATA2P_CONN HDMI_DATA0N_CONN 2 9 HDMI_DATA0P_CONN


    ILIM CH2 NC_4 CH2 NC_4
    3
    FAULT
    2

    4 5 2 8 HDMI_DATA2N_CONN 8 HDMI_DATA0N_CONN
    EN GND NC_3 NC_3
    R5404

    2 C5405
    C5404 7 4.7U_6.3V_M_X5R_0402 3 3
    GND_PAD VN VN
    0.1U_6.3V_K_X5R_0201
    TPS2553DRVR_SON6_2X2 1 7 HDMI_DATA1P_CONN 7 HDMI_CLKP_CONN
    1

    1 NC_2 NC_2
    HDMI_DATA1P_CONN 4 6 HDMI_DATA1N_CONN HDMI_CLKP_CONN 4 6 HDMI_CLKN_CONN
    CH3 NC_1 CH3 NC_1

    HDMI_DATA1N_CONN 5 HDMI_CLKN_CONN 5
    CH4 CH4

    R5403 AOZ8808DI-05_DFN-10-10-9_2P5X1
    AOZ8808DI-05_DFN-10-10-9_2P5X1
    EVT FVT SIT SVT
    Resistor V EMC@ EMC@
    R-short

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 HDMI CONNECTOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    D 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 54 of 125
    5 4 3 2 1

    Vinafix.com
    C
    5 4 3 2 1

    VCC3_SUS

    1
    R5501
    1/20W_10K_5%_0201

    VCC3_SUS

    2
    UAR1A
    C5501 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L0_TXP_C Y23 V23 PCIE5_L0_RXP_C C5503 1 2 0.22U_6.3V_K_X5R_0201
    <10> PCIE5_L0_TXP PCIE_RX0_P PCIE_TX0_P PCIE5_L0_RXP <10>
    C5504 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L0_TXN_C Y22 V22 PCIE5_L0_RXN_C C5505 1 2 0.22U_6.3V_K_X5R_0201 1
    <10> PCIE5_L0_TXN PCIE_RX0_N PCIE_TX0_N PCIE5_L0_RXN <10>
    C5522
    C5506 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L1_TXP_C T23 P23 PCIE5_L1_RXP_C C5507 1 2 0.22U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201

    PCIe GEN3
    <10> PCIE5_L1_TXP PCIE_RX1_P PCIE_TX1_P PCIE5_L1_RXP <10>
    C5508 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L1_TXN_C T22 P22 PCIE5_L1_RXN_C C5509 1 2 0.22U_6.3V_K_X5R_0201
    <10> PCIE5_L1_TXN PCIE_RX1_N PCIE_TX1_N PCIE5_L1_RXN <10> 2
    M23 K23
    NC_M23 NC_K23
    D M22 K22 D
    NC_M22 NC_K22
    U5503

    6
    H23 F23 74AUP1G08GF_SOT891-6_1X1
    NC_H23 NC_F23
    H22 F22

    Vcc
    NC_H22 NC_F22
    2
    4 A
    5 -PLTRST_NEAR <13,76,98>
    V19 L4 -TBT_PERST_R R5547 1 2 0_0201_SP U5503_TBT_OUTPUT
    <12> PCIE5_CLK_100M PCIE_REFCLK_100_IN_P PERST_N Y NC
    1
    T19
    <12> -PCIE5_CLK_100M B -TBT_PERST <9>

    Gnd
    PCIE_REFCLK_100_IN_N
    R5503 1 2 0_0201_SP UAR1_AC5 AC5 N16 PCIE_RBIAS R5504 1 2 1/16W_3.01K_1%_0402
    <12> -CLKREQ_PCIE5 PCIE_CLKREQ_N PCIE_RBIAS

    2
    C5510 1 2 0.1U_6.3V_K_X5R_0201 DDIP1_0P_C AB7 R2 @ R5548

    3
    <3> DDIP1_0P DPSNK0_ML0_P NC_R2
    R5502
    C5511 1 2 0.1U_6.3V_K_X5R_0201 DDIP1_0N_C AC7 R1 1/20W_100K_5%_0201
    <3> DDIP1_0N DPSNK0_ML0_N NC_R1
    1/20W_10K_5%_0201
    C5512 1 2 0.1U_6.3V_K_X5R_0201 DDIP1_1P_C AB9 N2
    <3> DDIP1_1P

    1
    DPSNK0_ML1_P NC_N2
    C5513 1 2 0.1U_6.3V_K_X5R_0201 DDIP1_1N_C AC9 N1

    1
    <3> DDIP1_1N DPSNK0_ML1_N NC_N1
    C5514 1 2 0.1U_6.3V_K_X5R_0201 DDIP1_2P_C AB11 L2
    <3> DDIP1_2P C5502 1 2 0.1U_6.3V_K_X5R_0201 DPSNK0_ML2_P NC_L2
    L1
    DDIP1_2N_C AC11
    <3> DDIP1_2N DPSNK0_ML2_N NC_L1

    SOURCE PORT 0
    C5515 1 2 0.1U_6.3V_K_X5R_0201 DDIP1_3P_C AB13 J2
    <3> DDIP1_3P DPSNK0_ML3_P NC_J2

    SINK PORT 0
    C5516 1 2 0.1U_6.3V_K_X5R_0201 DDIP1_3N_C AC13 J1
    <3> DDIP1_3N DPSNK0_ML3_N NC_J1
    C5517 1 2 0.1U_6.3V_K_X5R_0201 DDIP1_AUXP_C Y11 W19
    <3> DDIP1_AUXP W11 DPSNK0_AUX_P NC_W19
    Y19
    C5518 1 2 0.1U_6.3V_K_X5R_0201 DDIP1_AUXN_C
    <3> DDIP1_AUXN DPSNK0_AUX_N NC_Y19
    AA2 G1
    <3> DDIP1_HPD DPSNK0_HPD NC_G1
    Y5 N6
    NC_Y5 NC_N6
    @ TP5501Test_Point_20MIL 1 R4
    NC_R4
    U1 I2C_DATA_TBT
    GPIO_0 I2C_DATA_TBT <59,61>
    AB15 U2 I2C_CLK_TBT
    AC15 NC_AB15 GPIO_1
    V1 I2C_CLK_TBT <59,61>
    -TBT_EE_WP

    LC GPIO
    NC_AC15 GPIO_2
    V2 TBT_TMU_CLK_OUT R5505 1 2 0_0201_SP
    AB17
    GPIO_3
    W1 R5506 1 @ 21/20W_0_5%_0201 -TBT_PCIE_WAKE <9>
    -PCIE_WAKE_R
    AC17 NC_AB17 GPIO_4
    W2 -PCIE_WAKE <13,67,76,94>
    -TBT_PLUG_EVENT

    SINK PORT 1
    NC_AC17 GPIO_5
    Y1 -TBT_PLUG_EVENT <6>
    DPSRC_CTRLDATA
    GPIO_6
    AB19 Y2 DPSRC_CTRLCLK
    NC_AB19 GPIO_7
    AC19 AA1 TBT_SRC0_CFG1
    NC_AC19 GPIO_8
    J4 -TBT_I2C_INT
    AB21 POC_GPIO_0
    E2 -TBT_I2C_INT <59>
    AR_POC_GPIO1

    POC GPIO
    NC_AB21 POC_GPIO_1 R5507 1 2 0_0201_SP
    C AC21 D4 TBT_RTD3_USB_PWR_EN C
    NC_AC21 POC_GPIO_2
    H4 TBT_FORCE_USB_PWR <9>
    TBT_FORCE_PWR
    Y12
    POC_GPIO_3
    F2 D5502 1 2 RB521CM-30T2R_VMN2M-2 TBT_FORCE_PWR <8>
    -BATLOW_TBT
    W12 NC_Y12 POC_GPIO_4
    D2 D5503 1 2 RB521CM-30T2R_VMN2M-2 -BATLOW <13,87>
    -PCH_SLP_S3_TBT
    NC_W12 POC_GPIO_5
    F1 R5508 1 2 0_0201_SP -PCH_SLP_S3 <13,17,86,94,95>
    TBT_RTD3_CIO_PWR_EN
    Y6
    POC_GPIO_6 TBT_RTD3_PWR_EN <9>
    RSV_Y6
    E1 UAR1_E1 R5509 1 2 1/20W_100_5%_0201
    TEST_EN
    Y8

    Misc
    NC_Y8 R5510 1 2 1/20W_100_5%_0201
    N4 AB5 UAR1_AB5
    NC_N4 TEST_PWR_GOOD
    VCC3_TBT_LC
    R5511 1 Y18
    2 1/16W_14K_1%_0402 DPSINK_RBIAS F4 -TBT_RESET_R 2
    RB521CM-30T2R_VMN2M-2 1 D5504
    DPSNK_RBIAS RESET_N 2
    RB521CM-30T2R_VMN2M-2 1 D5505 -TBT_RESET_EC <87>
    R5512 1 2 1/16W_10K_5%_0402 UAR1_Y4 Y4 D22 -TBT_RESET_PD <59>
    TBT_XTAL_25_IN
    TDI XTAL_25_IN
    R5513 1 2 1/16W_10K_5%_0402 UAR1_V4 V4 D23 TBT_XTAL_25_OUT
    TMS XTAL_25_OUT
    R5514 1 2 1/16W_10K_5%_0402 UAR1_T4 T4
    TCK
    R5515 1 2 1/16W_10K_5%_0402 UAR1_W4 W4 MISC AB3 TBT_EE_DI
    TDO EE_DI
    AC4 TBT_EE_DI <59>
    TBT_EE_DO
    EE_DO TBT_EE_DO <59>
    R5516 1 2 1/16W_4.75K_0.5%_0402UAR1_H6H6 AC3 -TBT_EE_CS
    RBIAS EE_CS_N -TBT_EE_CS <59>
    UAR1_J6 J6 AB4 TBT_EE_CLK
    RSENSE EE_CLK TBT_EE_CLK <59>
    A15 B7
    <62> TBT_RX2P B15 PA_RX1_P PB_RX0_P
    A7
    <62> TBT_RX2N PA_RX1_N PB_RX0_N
    A17 A9 VCC3_LDO_PD
    <62> TBT_TX2P B17 PA_TX1_P PB_TX0_P
    B9
    <62> TBT_TX2N PA_TX1_N PB_TX0_N
    A19 A11
    <62> TBT_TX1P B19 PA_TX0_P NC_A11
    B11

    2
    <62> TBT_TX1N PA_TX0_N NC_B11
    B21 A13 D5506

    Port A

    PORT B
    <62> TBT_RX1P A21 PA_RX0_P NC_A13
    B13 RB520CM-30T2R_VMN2M2

    1
    <62> TBT_RX1N PA_RX0_N NC_B13
    Y15 Y16 VCC3_LDO_TBT_SPI
    <60> TBT_AUXP PA_DPSRC_AUX_P NC_Y16

    R5518 1/20W_3.3K_5%_0201

    R5521 1/20W_3.3K_5%_0201
    R5519 1/20W_3.3K_5%_0201
    W15 W16

    TBT PORTS

    R5520 1/20W_3.3K_5%_0201
    <60> TBT_AUXN PA_DPSRC_AUX_N NC_W16
    E20 E19
    PA_USB2_D_P NC_E19

    0.1U_6.3V_K_X5R_0201
    D20 D19
    PA_USB2_D_N NC_D19

    C5519
    1

    2
    2

    2
    A5 B4
    B <60> TBT_LSTX A4 PA_LSTX NC_B4
    B5 B

    POC
    <60> TBT_LSRX PA_LSRX NC_B5
    M4 G2
    <59> TBT_HPD PA_DPSRC_HPD NC_G2 2
    POC
    1/20W_100K_5%_0201

    R5517 1 2 1/20W_499_1%_0201 H19


    UAR1_H19 F19

    1
    1
    PA_USB2_RBIAS NC_F19

    1
    1/20W_1M_5%_0201

    1/20W_1M_5%_0201

    AC23 D6
    THERMDA_1 MONDC_SVR
    AB23
    THERMDA_2

    8
    A23 U5502
    ATEST_P
    V18 B23

    VCC
    PCIE_ATEST ATEST_N
    AC1 E18
    2
    2

    TEST_EDM USB2_ATEST
    2

    -TBT_EE_CS 1 5 TBT_EE_DI
    /CS DI(IO0)
    L15 W13
    FUSE_VQPS MONDC_DPSNK_0
    N15
    NC_N15
    DEBUG NC_W18
    W18 TBT_EE_DO 2
    DO(IO1) CLK
    6 TBT_EE_CLK
    C23
    R5522 1
    R5525 1

    MONDC_CIO_0
    R5526 1

    C22 AB2
    NC_C22 NC_AB2
    U5502_3 3 7 U5502_7
    /WP(IO2) /HOLD(IO3)

    GND
    JHL6240_BGA337

    W25Q80DVSSIG_SO8

    4
    R5529 1 21/16W_0_5%_0402TBT_XTAL_25_OUT

    VCC3_SUS TBT_XTAL_25_IN
    DPSRC_CTRLDATA R5530 1 21/20W_100K_5%_0201 Y5501 25MHZ_18PF_8Y25000004
    Y5501_1

    -TBT_PERST_R R5532 1 @ 21/20W_10K_5%_0201 DPSRC_CTRLCLK R5531 1 21/20W_100K_5%_0201 1 3 Vendor P/N LCFC P/N
    1 3
    R5533 1 21/20W_10K_5%_0201 R5534 1 21/20W_100K_5%_0201 GND1 GND2 W25Q80DVSSIG SA000078K00
    AR_POC_GPIO1 TBT_TMU_CLK_OUT

    TBT_RTD3_CIO_PWR_EN R5535 1 @ 21/20W_10K_5%_0201 R5536 1 21/16W_10K_5%_0402 1


    2 4 MX25L8006EM2I-12G SA000086B00
    TBT_FORCE_PWR 1
    A
    TBT_RTD3_USB_PWR_EN R5537 1 @ 21/20W_10K_5%_0201 TBT_RTD3_USB_PWR_EN R5538 1 21/20W_10K_5%_0201 C5520 C5521 A
    27P_50V_J_NPO_0402 27P_50V_J_NPO_0402
    R5539 1 21/20W_10K_5%_0201 2 2
    -TBT_PLUG_EVENT -BATLOW_TBT R5540 1 21/20W_10K_5%_0201

    -TBT_RESET_R R5541 1 21/20W_10K_5%_0201 -PCH_SLP_S3_TBT R5542 1 21/20W_10K_5%_0201

    -TBT_PCIE_WAKE R5543 1 21/20W_10K_5%_0201 R5544 1 21/20W_10K_5%_0201


    -TBT_EE_WP

    TBT_SRC0_CFG1 R5545 1 21/20W_1M_5%_0201 TBT_RTD3_CIO_PWR_EN R5546 1 21/20W_10K_5%_0201

    Y3 CRYSTAL 25MHZ 18PF 30PPM Security Classification LC Future Center Secret Data Title

    Vendor P/N LCFC P/N Issued Date 2019/01/12 Deciphered Date 2018/01/12 ALPINE RIDGE (1/2)
    Vinafix.com TXC 8Y25000004 SJ10000H00J THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom C 0.1
    KDS 1ZZHAE25000CC0F SJ10000P300 DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 55 of 125
    5 4 3 2 1
    5 4 3 2 1

    IN from outside of Alpine Ridge

    VCC3_TBT_LC

    MAX MAX
    VCC3_TBT_S0 VCC3_SUS
    0.1A 0.9A
    Internal Use (TBD) (TBD)
    L5601 OUT
    1 2
    D
    VCC3_SUS D
    1UH_PCFE20161T-1R0MDR_2.1A_20% VCC0R9_TBT_CIO VCC0R9_TBT_USB VCC0R9_TBT_PCIE VCC0R9_TBT_DP VCC3_SUS VCC3_TBT_S0 VCC0R9_TBT_SVR

    0.1UC_25VC_KC_X5RC_0402
    47U_6.3V_M_X5R_0603

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402

    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402
    C5601

    C5602 1 1 1 1 IN

    C5605

    C5606

    C5607

    C5608
    C5603

    C5604
    2 2 2 2

    VCC0R9_TBT_DP

    R13

    H9
    R6

    F8
    UAR1B
    L8 A2

    VCC3P3A
    VCC3P3_LC

    VCC3P3_S0
    VCC3P3_SX
    VCC0P9_DP_1 VCC3P3_SVR_1
    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402 L11
    NC_L11 VCC3P3_SVR_2
    A3
    L12 B3 VCC 0.9V from SVR (Step Voltage Regulator)
    NC_L12 VCC3P3_SVR_3
    M8
    VCC0P9_DP_2

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    C5609

    C5619

    C5610

    C5612

    C5613
    C5618

    C5611
    T11
    VCC0P9_DP_3
    T12 L9
    VCC0P9_DP_4 VCC0P9_SVR_1
    L6 M9
    NC_L6 VCC0P9_SVR_2

    C5620

    C5615

    C5616
    C5622

    C5623
    C5621

    C5614
    M6 E12
    NC_M6 VCC0P9_SVR_ANA_1
    V11 E13
    VCC0P9_ANA_DPSNK_1 VCC0P9_SVR_ANA_2
    V12 F11
    VCC0P9_ANA_DPSNK_2 VCC0P9_SVR_ANA_3
    V13 F12
    VCC0P9_ANA_DPSNK_3 VCC0P9_SVR_ANA_4 VCC0R9_TBT_SVR
    F13
    VCC0P9_SVR_ANA_5
    M13 F15
    VCC0P9_PCIE_1 VCC0P9_SVR_ANA_6
    M15 J9
    VCC0P9_PCIE_2 VCC0P9_SVR_SENSE
    VCC0R9_TBT_USB M16
    VCC0P9_PCIE_3
    L19
    N19 NC_L19
    C1 TBT_SVR_IND 1 2 L5602 OUT
    VCC0P9_ANA_PCIE_1 SVR_IND_1

    47U_6.3V_M_X5R_0603
    47U_6.3V_M_X5R_0603

    47U_6.3V_M_X5R_0603
    L18 C2
    VCC0P9_ANA_PCIE_2_1 SVR_IND_2
    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402

    M18 D1 0.6UH_CMME051B-R60MS_7A_20%
    VCC0P9_ANA_PCIE_2_2 SVR_IND_3
    N18 1 1 1
    VCC0P9_ANA_PCIE_2_3

    C5626
    C5625

    C5627
    XFL4012-601MEC
    C5617
    C5624

    R15 A1

    VCC
    VCC0P9_USB_1 SVR_VSS_1
    R16 B1
    VCC0P9_USB_2 SVR_VSS_2 2 2 2
    C B2 C
    SVR_VSS_3
    R8
    VCC0P9_CIO_1
    R9
    VCC0P9_CIO_2
    R11
    VCC0P9_CIO_3
    R12 F18 VCC0R9_TBT_LVR
    VCC0P9_CIO_4 VCC0P9_LVR_1
    H18
    VCC0P9_LVR_2 VCC 0.9V from LVR (Linear Voltage Regulator)
    VCC0R9_TBT_PCIE VCC3_TBT_ANA_PCIE L16 J11
    VCC3P3_ANA_PCIE VCC0P9_LVR_3 Internal Use
    VCC3_TBT_ANA_USB2 J16

    1/20W_10K_5%_0201
    H11
    VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE

    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402
    A6 V5
    VSS_ANA_1 VSS_ANA_81

    10U_6.3V_M_X5R_0402
    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402

    10U_6.3V_M_X5R_0402
    A8 V6

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    VSS_ANA_2 VSS_ANA_82
    V8

    R5601
    A10 1 1
    VSS_ANA_3 VSS_ANA_83

    C5636
    C5634
    V9

    C5633

    C5637
    C5632

    C5635
    A12
    VSS_ANA_4 VSS_ANA_84
    V15
    C5628

    C5629

    C5631
    C5630

    A14
    VSS_ANA_5 VSS_ANA_85
    A16 V16
    VSS_ANA_86

    2
    VSS_ANA_6 V20 2 2
    A18
    VSS_ANA_7 VSS_ANA_87
    A20 W5
    VSS_ANA_8 VSS_ANA_88
    A22 W6
    VSS_ANA_9 VSS_ANA_89
    B6 W8
    VSS_ANA_10 VSS_ANA_90
    B8 W9
    VSS_ANA_11 VSS_ANA_91
    B10 W20
    VSS_ANA_12 VSS_ANA_92
    B12 W22
    VSS_ANA_13 VSS_ANA_93
    VCC0R9_TBT_CIO B14 W23
    VSS_ANA_14 VSS_ANA_94
    B16 Y9
    VSS_ANA_15 VSS_ANA_95
    B18 Y13
    VSS_ANA_16 VSS_ANA_96
    B20 Y20
    VSS_ANA_17 VSS_ANA_97
    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402

    B22 AA22
    VSS_ANA_18 VSS_ANA_98
    D8 AA23
    VSS_ANA_19 VSS_ANA_99
    D9 AB6
    VSS_ANA_20 VSS_ANA_100
    D11
    C5638

    C5639

    AB8
    C5640

    VSS_ANA_21 VSS_ANA_101
    D12 AB10
    VSS_ANA_22 VSS_ANA_102
    D13 AB12
    VSS_ANA_23 VSS_ANA_103
    D15 AB14
    VSS_ANA_24 VSS_ANA_104
    D16 AB16
    VSS_ANA_25 VSS_ANA_105
    D18 AB18
    VSS_ANA_26 VSS_ANA_106
    E8 AB20

    GND
    VSS_ANA_27 VSS_ANA_107
    E9 AB22
    VSS_ANA_28 VSS_ANA_108
    E11 AC6
    VSS_ANA_29 VSS_ANA_109
    E15 AC8
    VSS_ANA_30 VSS_ANA_110
    B E16 AC10 B
    VSS_ANA_31 VSS_ANA_111
    E22 AC12
    VSS_ANA_32 VSS_ANA_112
    E23 AC14
    VSS_ANA_33 VSS_ANA_113
    F9 AC16
    VSS_ANA_34 VSS_ANA_114
    F16 AC18
    VSS_ANA_35 VSS_ANA_115
    F20 AC20
    VSS_ANA_36 VSS_ANA_116
    G22 AC22
    VSS_ANA_37 VSS_ANA_117
    G23 D5
    VSS_ANA_38 VSS_1
    H1 E4
    VSS_ANA_39 VSS_2
    H2 E5
    VSS_ANA_40 VSS_3
    H12 E6
    VSS_ANA_41 VSS_4
    H13 F5
    VSS_ANA_42 VSS_5
    H15 F6
    VSS_ANA_43 VSS_6
    H16 H5
    VSS_ANA_44 VSS_7
    H20 H8
    VSS_ANA_45 VSS_8
    J5 J8
    VSS_ANA_46 VSS_9
    J18 J12
    VSS_ANA_47 VSS_10
    J19 J13
    VSS_ANA_48 VSS_11
    J20 J15
    VSS_ANA_49 VSS_12
    J22 L13
    VSS_ANA_50 VSS_13 M11
    J23
    VSS_ANA_51 VSS_14
    K1 M12
    VSS_ANA_52 VSS_15
    K2 N8
    VSS_ANA_53 VSS_16
    L5 N9
    VSS_ANA_54 VSS_17
    L20 N11
    VSS_ANA_55 VSS_18
    L22 N12
    VSS_ANA_56 VSS_19
    L23 N13
    VSS_ANA_57 VSS_20
    M1 T6
    VSS_ANA_58 VSS_21
    M2 T8
    VSS_ANA_59 VSS_22
    M5 T9
    VSS_ANA_60 VSS_23
    M19 T13
    VSS_ANA_77
    VSS_ANA_78
    VSS_ANA_79
    VSS_ANA_80
    VSS_ANA_72
    VSS_ANA_73
    VSS_ANA_74
    VSS_ANA_75
    VSS_ANA_76
    VSS_ANA_67
    VSS_ANA_68
    VSS_ANA_69
    VSS_ANA_70
    VSS_ANA_71

    VSS_ANA_61 VSS_24
    M20 T15
    VSS_ANA_62 VSS_25
    N5 T16
    VSS_ANA_63 VSS_26
    N20 T18
    VSS_ANA_64 VSS_27
    N22 AB1
    VSS_ANA_65 VSS_28
    N23 AC2
    VSS_ANA_66 VSS_29
    JHL6240_BGA337
    T5
    T20
    U22
    U23
    R20
    R22
    R23
    T1
    T2
    P1
    P2
    R5
    R18
    R19

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2018/01/12 ALPINE RIDGE (2/2)
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 56 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size CDocument Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
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    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 57 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document
    C Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 58 of 125
    5 4 3 2 1
    5 4 3 2 1

    TABLE BUSPOWER Configuration - ADCIN1 TABLE BUSPOWER Configuration - ADCIN2

    DIV = R2/ (R1+R2) DIV = R2/ (R1+R2) I2C Unique Address [3:1]
    Configuration
    I2C_ADDR_DECODE_C1 I2C_ADDR_DECODE_C2
    DIV MIN DIV MAX DIV MIN DIV MAX
    VCC3_LDO_PD
    0.00 0.18 BP_NoRespones 0.00 0.18 000b 100b

    10U_6.3V_M_X5R_0402
    @ U5902 0.20 0.38 BP_WaitFor3V3_Internal 0.20 0.38
    D 2
    001b 101b D

    C5901
    6 1
    0.40 0.58 BP_WaitFor3V3_External 0.40 0.58 010b 110b

    2
    VCC5M_PD VCC5M_PD VCC3M 1 5 2
    R5901 0.60 1.00 BP_NoWait 0.60 1.00
    0_0603_SP
    011b 111
    4 3

    1
    1

    1
    R5902 R5903 R5904
    0_1%_0603_LE 0_1%_0603_LE 0_1%_0603_LE FDG316P_SC70-6

    VCC3_LDO_PD_R
    2

    2
    2
    VCC3_LDO_PD VCC3_LDO_PD

    U5901_9 U5901_1

    1
    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    10U_6.3V_M_X5R_0402
    22U_6.3V_M_X5R_0603
    C5902
    47P_25V_J_NPO_0201
    TBT_VBUS20 USBC_VBUS20 R5913
    2 2 2 2 2 2 1/20W_10K_5%_0201 1/20W_10K_5%_0201

    C5907
    R5906

    C5905
    C5903

    C5906
    C5904
    RF_NS@

    NSR20F30NXT5G_DSN2-2

    NSR20F30NXT5G_DSN2-2

    2
    1
    1

    1
    1 1 1 1 1 1 ADCIN1 ADCIN2

    1U_25V_K_X5R_0402

    1U_25V_K_X5R_0402
    4.7U_6.3V_M_X5R_0402_MURATA
    2 2

    1
    C5909
    D5902

    C5908
    D5901
    VCC3_SUS VCC3M
    R5914
    1 1 VCC5M_PD 1/20W_100K_5%_0201 1/20W_100K_5%_0201
    2

    2
    47P_25V_J_NPO_0201
    R5909

    C5910
    C5911
    2

    2
    1
    2

    2
    1

    1
    RF_NS@
    R5905

    U5901_30
    1

    U5901_5

    U5901_7
    0_1%_0603_LE

    2
    2

    2
    2

    1/20W_10K_5%_0201
    1/20W_10K_5%_0201
    1/20W_3.3K_5%_0201

    1/20W_3.3K_5%_0201
    1/20W_3.3K_5%_0201

    1/20W_3.3K_5%_0201

    R5907
    R5923

    R5908

    R5921
    R5920

    R5922

    U5901_3

    2
    U5901

    30
    10

    11
    12
    1
    1

    1
    1

    7
    9

    1
    2

    3
    4
    C C

    22U_6.3V_M_X5R_0603
    4.7UC_6.3VC_KC_X6SC_0603
    VIN_3V3

    LDO_3V3

    LDO_1V8
    PP_HV1_1
    PP_HV1_2

    PP_HV2_1
    PP_HV2_2

    VBUS1_1
    VBUS1_2

    VBUS2_1
    VBUS2_2
    2 2
    @

    C5913
    C5912
    1 1

    TBT_EE_CLK 33 VCC5M_PD
    <55> TBT_EE_CLK SPI_CLK/GPIO10
    TBT_EE_DO 31
    <55> TBT_EE_DO SPI_MISO/GPIO8
    TBT_EE_DI 32 6 ADCIN1
    <55> TBT_EE_DI SPI_MOSI/GPIO9 ADCIN1
    -TBT_EE_CS 34
    <55> -TBT_EE_CS SPI_SS#/GPIO11
    20 U5901_20

    1
    PP1_CABLE
    R5910

    R5911 1 2
    1/20W_1M_5%_0201
    U5901_45 45
    PD CONTROLLER C1_CC1
    19
    21
    TBT_CC1
    TBT_CC2
    TBT_CC1 <62>
    0_1%_0603_LE

    R5912 1 2 C1_USB_P/GPIO18 C1_CC2 TBT_CC2 <62>


    U5901_46 46

    2
    C1_USB_N/GPIO19
    1/20W_1M_5%_0201 25 TBT_HPD
    24 HPD1/GPIO3 TBT_HPD <55>
    -PD_I2C_INT
    <87> -PD_I2C_INT I2C1_IRQ#
    43 TBT_HV_GATE
    PP_EXT1/GPIO16 TBT_HV_GATE <100>
    I2C_DATA_PD 23
    <61,68,87> I2C_DATA_PD 22 I2C1_SDA
    I2C_CLK_PD
    <61,68,87> I2C_CLK_PD I2C1_SCL

    22U_6.3V_M_X5R_0603
    4.7UC_6.3VC_KC_X6SC_0603
    2 2
    @

    C5914

    C5915
    39 1 1
    HRESET

    8 ADCIN2
    ADCIN2
    R5915 1 2 1/20W_1M_5%_0201
    U5901_47 47 41 U5901_41
    C2_USB_P/GPIO20 PP2_CABLE
    R5916 1 2 1/20W_1M_5%_0201
    U5901_48 48
    C2_USB_N/GPIO21
    -TBT_I2C_INT 29 40 USBC_CC1
    <55> -TBT_I2C_INT I2C2_IRQ# C2_CC1 USBC_CC1 <63>
    42 USBC_CC2
    C2_CC2 USBC_CC2 <63>
    I2C_DATA_TBT 28
    B <55,61>
    <55,61>
    I2C_DATA_TBT
    I2C_CLK_TBT
    I2C_CLK_TBT 27 I2C2_SDA
    I2C2_SCL SN1701012RJTR HPD2/GPIO4
    26 USBC_HPD
    USBC_HPD <61,68>
    B

    44 USBC_HV_GATE
    PP_EXT2/GPIO17 USBC_HV_GATE <100>

    15
    <62> TBT_DISCHARGE GPIO2
    R5917 1 2 1/20W_1M_5%_0201
    U5901_1314 38 USBC_USB_MODE
    GPIO1 GPIO15/PWM2 USBC_USB_MODE <61>
    -TBT_RESET_PD 13 37 USBC_POL
    <55> -TBT_RESET_PD GPIO0 GPIO14/PWM1 USBC_POL <61>
    TBT_DP_MODE 16
    <60> TBT_DP_MODE GPIO5

    220P_25V_K_X7R_0201

    220P_25V_K_X7R_0201
    220P_25V_K_X7R_0201

    220P_25V_K_X7R_0201
    TBT_POL 17 49 U5901_NC1
    <60> TBT_POL GPIO6 NC1

    C5917

    C5919
    C5916

    C5918
    TBT_TBT_MODE 18 50 U5901_NC2 2 2 2 2
    <60> TBT_TBT_MODE GPIO7 NC2
    35
    <63> USBC_DISCHARGE GPIO12
    USBC_DP_MODE 36 1 1 1 1
    <61> USBC_DP_MODE GPIO13
    51
    GND
    AP1

    AP2

    AP3

    AP4
    1/20W_1M_5%_0201
    1/20W_1M_5%_0201

    2
    2

    @ R5919
    @ R5918

    EMC@ EMC@ EMC@ EMC@


    A1

    A2

    A3

    A4

    SN1701012RJTR_VQFN48_6X6
    1
    1

    U5901_NC1 1 @ TP5901
    Test_Point_20MIL

    U5901_NC2 1 @ TP5902
    Test_Point_20MIL

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 THUNDERBOLT PD
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 59 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    VCC3M

    1
    R6001
    0_1%_0603_LE
    VCC3_LDO_PD

    2
    2 2
    VCC3M 0.1U_6.3V_K_X7R_0201 C6002
    C6001 1U_6.3V_K_X5R_0402

    R6001, R6003, R6004 1 1

    2
    EVT FVT SIT SVT
    Resistor V
    R-short 1/20W_100K_5%_0201
    U6001 R6002
    TS3DS10224RUKR_WQFN20_3X3

    1
    U6001_13
    13 18 TBT_AUXP_C C6003 1 2 0.1U_6.3V_K_X7R_0201 TBT_AUXP
    VCC OUTA0+ TBT_AUXP <55>
    17 TBT_AUXN_C C6004 1 2 0.1U_6.3V_K_X7R_0201 TBT_AUXN
    OUTA0- TBT_AUXN <55>
    TBT_DP_MODE 16
    <59> TBT_DP_MODE ENA
    20
    OUTA1+
    TBT_SBU1 1 19
    <62> TBT_SBU1 INA+ OUTA1-
    TBT_SBU2 2
    <62> TBT_SBU2 INA-
    15 TBT_POL
    SAO TBT_POL <59>
    2 1 U6001_1414
    R6003 0_0201_SP
    SAI MUX 8 TBT_LSTX
    TBT_LSTX <55>
    OUTB0+
    TBT_TBT_MODE 10 9 TBT_LSRX
    <59> TBT_TBT_MODE ENB OUTB0- TBT_LSRX <55>
    3 6
    INB+ OUTB1+
    4 7
    R6004 INB- OUTB1-

    E-PAD
    2 1 U6001_1212 11

    GND
    SBI SBO
    C C
    0_0201_SP

    21

    2
    1/20W_100K_5%_0201
    R6005

    1
    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 USB PD CONTROLLER(2/2)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 60 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC3_SUS VCC3_PS8747

    VCC3_PS8747
    R6101
    1 2

    0_1%_0603_LE
    D D

    2 2 2 2 2
    R6101,R6102,R6103
    EVT FVT SIT SVT C6101 C6102 C6103 C6104 C6105
    Resistor V 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 2 2 2
    R-short 1 1 1 1 1 C6106 C6107 C6108
    0.01U_6.3V_K_X7R_0201 0.01U_6.3V_K_X7R_0201 0.01U_6.3V_K_X7R_0201
    1 1 1

    20
    28

    17
    6
    U6101
    C6109 1 2 0.1U_6.3V_K_X5R_0201 XBAR_DDIP2_0P_C 9

    VDD33_1
    VDD33_2
    VDD33_3

    VDD_DCI
    <68> XBAR_DDIP2_0P 1 2 ML0P
    C6110 0.1U_6.3V_K_X5R_0201 XBAR_DDIP2_0N_C 10
    <68> XBAR_DDIP2_0N 1 2 ML0N
    C6111 0.1U_6.3V_K_X5R_0201 XBAR_DDIP2_3P_C 18
    <68> XBAR_DDIP2_3P ML3P
    C6112 1 2 0.1U_6.3V_K_X5R_0201 XBAR_DDIP2_3N_C 19
    <68> XBAR_DDIP2_3N ML3N
    PS8747_SSDE 11 30
    SSDE/DCI_DATA RX1P USBC_RX1P <63>
    PS8747_CDE 14 31
    CDE/DCI_CLK RX1N USBC_RX1N <63>
    40
    C6113 1 2 0.1U_6.3V_K_X5R_0201 RX2P USBC_RX2P <63>
    USB3P2_RXP_C 5 39
    <10> USB3P2_RXP C6114 1 2 0.1U_6.3V_K_X5R_0201 SSRXP RX2N USBC_RX2N <63>
    USB3P2_RXN_C 4
    <10> USB3P2_RXN C6115 1 2 0.1U_6.3V_K_X5R_0201 SSRXN
    USB3P2_TXP_C 8
    <10> USB3P2_TXP SSTXP
    C6116 1 2 0.1U_6.3V_K_X5R_0201 USB3P2_TXN_C 7
    <10> USB3P2_TXN SSTXN
    33
    TX1P USBC_TX1P <63>
    34
    TX1N USBC_TX1N <63>
    C C6117 1 2 0.1U_6.3V_K_X5R_0201 XBAR_DDIP2_2P_C 15 37 C
    <68> XBAR_DDIP2_2P ML2P TX2P USBC_TX2P <63>
    C6118 1 2 0.1U_6.3V_K_X5R_0201 XBAR_DDIP2_2N_C 16 36
    <68> XBAR_DDIP2_2N ML2N TX2N USBC_TX2N <63>
    C6119 1 2 0.1U_6.3V_K_X5R_0201 XBAR_DDIP2_1P_C 12
    <68> XBAR_DDIP2_1P ML1P
    C6120 1 2 0.1U_6.3V_K_X5R_0201 XBAR_DDIP2_1N_C 13
    <68> XBAR_DDIP2_1N ML1N
    R6102 1 2 0_0201_SP XBAR_DDIP2_AUXP_C 24
    <68> XBAR_DDIP2_AUXP R6103 1 2 0_0201_SP AUXP
    XBAR_DDIP2_AUXN_C 25 1 U6101_1
    <68> XBAR_DDIP2_AUXN AUXN CEXT
    23
    CE_DP
    35 USBC_DP_MODE <59>
    PS8747_I2C_CTL 29
    I2C_EN CE_USB
    38 USBC_USB_MODE <59>
    PS8747_DCICFG_ADDR 3
    DCICFG/ADDR FLIP
    27 USBC_POL <59>
    R6104 1 2 0_0201_SP 21 SBU1
    26 USBC_SBU1 <63>
    PS8747_DPEQ_SCL
    <59,68,87> I2C_CLK_PD R6105 1 2 0_0201_SP DPEQ/CSCL SBU2 USBC_SBU2 <63>
    PS8747_CEQ_SDA 22 32
    <59,68,87> I2C_DATA_PD CEQ/CSDA IN_HPD USBC_HPD <59,68>

    EPAD
    R6106 1 @ 2 1/20W_0_5%_0201 U6101_2 2
    <55,59> I2C_CLK_TBT REXT
    R6107 1 @ 2 1/20W_0_5%_0201 2
    <55,59> I2C_DATA_TBT C6121

    41
    1
    PS8747BQFN40GTR-B1_QFN40_6X4 2.2UC_6.3VC_KC_X5RC_0402
    R6108
    1/20W_4.99K_1%_0201 1

    B B
    VCC3_SUS

    R6109 1 @ 2 1/16W_4.7K_5%_0402 PS8747_DPEQ_SCL R6110 1 @ 2 1/16W_4.7K_5%_0402


    VCC3_SUS

    R6111 1 @ 2 1/16W_4.7K_5%_0402 PS8747_CEQ_SDA R6112 1 @ 2 1/16W_4.7K_5%_0402

    R6113 1 2 1/20W_100K_1%_0201 XBAR_DDIP2_AUXN_C

    R6114 1 2 1/16W_4.7K_5%_0402 PS8747_I2C_CTL R6115 1 @ 2 1/16W_4.7K_5%_0402


    R6116 1 2 1/20W_100K_1%_0201 XBAR_DDIP2_AUXP_C

    R6117 1 @ 2 1/16W_4.7K_5%_0402 PS8747_DCICFG_ADDR R6118 1 2 1/16W_4.7K_5%_0402

    R6119 1 @ 2 1/16W_4.7K_5%_0402 PS8747_SSDE

    R6120 1 @ 2 1/16W_4.7K_5%_0402 PS8747_CDE

    R6121 1 @ 2 1/20W_20K_5%_0201 USBC_USB_MODE

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 Type-C Switch
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 61 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC3M TABLE U6203


    TBT_VBUS20_CONN
    R6201 R6212
    VCC3_LDO_PD Pericom PI3USB102ZMEX
    EVT FVT SIT SVT 1 2

    0.47UC_25VC_KC_X5RC_0402

    0.47UC_25VC_KC_X5RC_0402
    Resistor V 2 2 2

    0.1U_6.3V_K_X5R_0201
    0.1U_6.3V_K_X5R_0201

    1U_6.3V_M_X5R_0201

    @ C6214
    0.1U_6.3V_K_X5R_0201
    R-short TBT_VBUS20_CONN TBT_VBUS20
    0_0201_SP

    C6212

    C6213
    1

    C6201

    1U_25V_K_X5R_0402
    1

    1U_25V_K_X5R_0402
    1 1 1

    0_0201_SP
    R6201
    U6202
    2
    B3 A2
    IN1 OUT1
    C2 A3

    2
    U6201 IN2 OUT2
    VCC3_LDO_PD C3 B2
    IN3 OUT3
    2 2 2 2

    9
    0.1U_25V_K_X5R_0201
    U6201_10 -TBT_PWR_DTCT

    1/5W_100_5%_0603
    10 A1 B1 1 @ TP6201 U6203
    VPWR EN# ACOK#

    2
    2 R6204 4 2 TBT_USB5N_R

    VDD
    M- Y-

    C6206

    R6203
    D TBT_SBU1 15 1 TBT_SBU1_CONN 1 2 U6202_C1 C1 Test_Point_20MIL D

    GND_1
    GND_2
    GND_3
    <60> TBT_SBU1 SBU1 C_SBU1 1 1 1 1 OVLO

    C6202

    C6203

    C6204
    C6205
    TBT_SBU2 14 2 TBT_SBU2_CONN @ 5 1 TBT_USB5P_R
    <60> TBT_SBU2 SBU2 C_SBU2

    1
    M+ Y+
    1/20W_1M_1%_0201

    1/20W_51.1K_1%_0201
    ACOK# is not longer monitored by EC

    2
    TBT_CC1 12 4 TBT_CC1_CONN 1 TBT_USB5N_CONN 6 10
    <59> TBT_CC1

    1
    CC1 C_CC1 @ @ D- SEL

    R6205
    TBT_CC2 11 5 TBT_CC2_CONN R6202 FPF2281BUCX-F130_WLCSP12
    <59> TBT_CC2

    A4
    B4
    C4
    CC2 C_CC2
    1/20W_10K_5%_0201 TBT_USB5P_CONN 7 8

    GND
    D+ OE -TBT_USB2_BUS_EN <87>
    20 7

    2
    D1 RPD_G1
    19

    1
    D2
    17 6

    Q6021_1

    3
    NC1 RPD_G2
    16 PI3USB102ZMEX_UQFN10_1P4X1P8 1 2
    NC2
    9 U6201_9
    FLT
    U6201_33 @ R6214
    VBIAS
    8 Over Voltage Lock Out Trip Threshold = 1.20 * (1 + R6204 / R6205) 1/20W_0_5%_0201
    GND1
    13
    GND2
    0.1U_50V_K_X5R_0402

    18
    GND3

    1
    2 21 @ Q6201 D
    THERMAL_PAD
    C6207

    2
    <59> TBT_DISCHARGE G
    SN1710033RUKR_WQFN20_3X3
    SSM3K72KFS_2-2H1S
    1 S

    3
    TBT_VBUS20

    1
    @ R6213
    1K_1206_5%

    2
    TBT_VBUS20_CONN
    TBT_VBUS20_CONN
    JDOCK1 @

    15 16
    SHELL1 SHELL2

    17 18
    SHELL3 SHELL5
    19
    SHELL4
    C C

    A1 B12
    GND1 GND4
    TBT_TX2P C6208 1 2 0.22U_6.3V_K_X5R_0201 TBT_TX2P_C A2 B11 TBT_RX2P
    <55> TBT_TX2P TX1+ RX1+ TBT_RX2P <55>
    TBT_TX2N C6209 1 2 0.22U_6.3V_K_X5R_0201 TBT_TX2N_C A3 B10 TBT_RX2N
    <55> TBT_TX2N TX1- RX1- TBT_RX2N <55>
    A4 B9
    VBUS1 VBUS4
    TBT_CC2_CONN A5 B8 TBT_SBU1_CONN
    CC1 SBU2
    TBT_USB5P_CONN A6 B7 TBT_USB5N_CONN
    D1+ D2-
    TBT_USB5N_CONN A7 B6 TBT_USB5P_CONN
    D1- D2+
    TBT_SBU2_CONN A8 B5 TBT_CC1_CONN
    SBU1 CC2
    A9 B4
    VBUS2 VBUS3
    TBT_RX1N A10 B3 TBT_TX1N_C C6210 1 2 0.22U_6.3V_K_X5R_0201TBT_TX1N
    <55> TBT_RX1N RX2- TX2- TBT_TX1N <55>
    TBT_RX1P A11 B2 TBT_TX1P_C C6211 1 2 0.22U_6.3V_K_X5R_0201 TBT_TX1P
    <55> TBT_RX1P RX2+ TX2+ TBT_TX1P <55>
    A12 B1
    GND2 GND3
    VCC3LAN

    20

    0.35A_6V_0603L035YR
    SHELL6
    21 22
    SHELL7 SHELL8

    2
    F6201 23 24
    SHELL9 SHELL10

    1
    MDI_2N_CONN 1 8 MDI_3N_CONN
    MDI_2N MDI_3N
    MDI_2P_CONN 2 9 MDI_3P_CONN
    MDI_2P MDI_3P
    -DOCK_LINKUP_SYS R6206 1 2 1/16W_330_5%_0402 -DOCK_LINKUP_SYS_LED 3 10
    <74> -DOCK_LINKUP_SYS -LINK_LED GND
    DOCK_4 4 11 -PWRSWITCH
    LED_PWR -PWRSWITCH -PWRSWITCH <17,51,93,94>
    -DOCK_ACTIVITY_SYS R6207 1 2 1/16W_330_5%_0402 -DOCK_ACTIVITY_SYS_LED 5 12 -DOCK_RJ45_DET
    <74> -DOCK_ACTIVITY_SYS -ACT_LED -DOCK_RJ45_DET -DOCK_RJ45_DET <74>
    MDI_1N_CONN 6 13 MDI_0N_CONN
    MDI_1N MDI_0N
    MDI_1P_CONN 7 14 MDI_0P_CONN
    MDI_1P MDI_0P

    HIGHS_DK11197-D20A2-1H

    B B

    D6215 EMC@ Trace through package


    MDI_0P_CONN 1
    CH1
    D6201 EMC@ D6209 EMC@
    MDI_0N_CONN 2 9 MDI_0P_CONN
    CH2 NC_4
    FL6201 EMC@ TBT_TX2P_C 1 2 2 1 TBT_RX2P
    1 2 2 1 8
    DOCK_MDI_0+ 4 3 MDI_0P_CONN MDI_0N_CONN
    <74> DOCK_MDI_0+ 4 3 NC_3

    PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 3
    VN
    DOCK_MDI_0- 1 2 MDI_0N_CONN
    <74> DOCK_MDI_0- 1 2 D6202 EMC@ D6210 EMC@ 7
    NC_2 MDI_1P_CONN
    EXC24CH900U_4P
    TBT_TX2N_C 1 2 2 1 TBT_RX2N MDI_1P_CONN 4 6 MDI_1N_CONN
    1 2 2 1 CH3 NC_1

    FL6202 EMC@ PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 MDI_1N_CONN 5


    CH4
    DOCK_MDI_1+ 4 3 MDI_1P_CONN
    <74> DOCK_MDI_1+ 4 3
    D6203 EMC_NS@ D6211 EMC_NS@
    AOZ8808DI-05_DFN-10-10-9_2P5X1
    DOCK_MDI_1- 1 2 MDI_1N_CONN TBT_CC2_CONN 1 2 2 1 TBT_SBU1_CONN
    <74> DOCK_MDI_1- 1 2 1 2 2 1
    EXC24CH900U_4P
    PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

    D6204 EMC@ D6205 EMC@


    FL6203 EMC@
    DOCK_MDI_2+ 4 3 MDI_2P_CONN 1
    TBT_USB5P_CONN 2 1 2 TBT_USB5N_CONN D6216 EMC@
    <74> DOCK_MDI_2+ 4 3 1 2 1 2 Trace through package
    MDI_2P_CONN 1
    CH1
    DOCK_MDI_2- 1 2 MDI_2N_CONN PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
    <74> DOCK_MDI_2- 1 2
    2 9
    MDI_2N_CONN CH2 NC_4 MDI_2P_CONN
    EXC24CH900U_4P D6206 EMC_NS@ D6212 EMC_NS@
    8 MDI_2N_CONN
    NC_3
    TBT_SBU2_CONN1 1 2
    2 2 1 TBT_CC1_CONN
    2 1 3
    VN
    FL6204 EMC@
    DOCK_MDI_3+ 4 3 MDI_3P_CONN PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 7 MDI_3P_CONN
    <74> DOCK_MDI_3+ 4 3 NC_2
    D6207 EMC@ D6213 EMC@ MDI_3P_CONN 4 6 MDI_3N_CONN
    CH3 NC_1
    DOCK_MDI_3- 1 2 MDI_3N_CONN
    <74> DOCK_MDI_3- 1 2 1 2 2 1
    A TBT_RX1N 1 2 2 1 TBT_TX1N_C A
    EXC24CH900U_4P MDI_3N_CONN 5
    CH4
    PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
    AOZ8808DI-05_DFN-10-10-9_2P5X1
    D6208 EMC@ D6214 EMC@

    TBT_RX1P 1 2 2 1 TBT_TX1P_C
    1 2 2 1

    PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
    FL6205 EMC@
    TBT_USB5P_R 4 3 TBT_USB5P
    4 3 TBT_USB5P <10>

    TBT_USB5N_R 1 2 TBT_USB5N
    1 2 TBT_USB5N <10>
    Security Classification LC Future Center Secret Data Title
    EXC24CH900U_4P
    Issued Date 2018/01/12 Deciphered Date 2018/01/12 .DOCKING CONNECTOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    D 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 62 of 125
    5 4 3 2 1

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    5 4 3 2 1

    VCC3M
    R6320
    1 2
    USBC_VBUS20_CONN 2 2 2

    0.1U_6.3V_K_X5R_0201

    1U_6.3V_M_X5R_0201

    0.1U_6.3V_K_X5R_0201
    C6312

    C6313

    @ C6314
    TABLE U6303 0_0201_SP

    0.47UC_25VC_KC_X5RC_0402

    0.47UC_25VC_KC_X5RC_0402
    1 1 1
    VCC3_LDO_PD
    Pericom PI3USB102ZMEX
    R6301

    1U_25V_K_X5R_0402
    1U_25V_K_X5R_0402
    0.1U_6.3V_K_X5R_0201
    EVT FVT SIT SVT USBC_VBUS20_CONN
    Resistor V 1 USBC_VBUS20

    9
    C6301
    R-short U6303

    1
    4 2 USBC_USB2N_R

    VDD
    R6301 M- Y-
    U6302
    2
    0_0201_SP 5 1 USBC_USB2P_R
    M+ Y+
    B3 A2
    2 2 2 2 IN1 OUT1
    C2 A3 USBC_USB2N_CONN 6 10

    2
    U6301 IN2 OUT2 D- SEL
    C3 B2
    IN3 OUT3

    0.1U_25V_K_X5R_0201
    VCC3_LDO_PD USBC_USB2P_CONN 7 8

    GND
    1 1 D+ OE -USBC_USB2_BUS_EN <87>
    10 U6301_10

    1/5W_100_5%_0603
    1 1 A1 B1 -USBC_PWR_DTCT 1 @ TP6301
    VPWR R6304

    2
    EN# ACOK#

    C6303
    C6302

    C6304

    C6305
    2

    C6306
    D USBC_SBU1 15 1 USBC_SBU1_CONN 1 2 U6302_C1 C1 Test_Point_20MIL D

    GND_1
    GND_2
    GND_3
    <61> USBC_SBU1

    3
    SBU1 C_SBU1 OVLO

    R6303
    USBC_SBU2 14 2 USBC_SBU2_CONN @ PI3USB102ZMEX_UQFN10_1P4X1P8 1 2
    <61> USBC_SBU2 SBU2 C_SBU2

    1/20W_51.1K_1%_0201
    @ @ 1/20W_1M_1%_0201

    2
    USBC_CC1 12 4 USBC_CC1_CONN 1 @ R6322
    <59> USBC_CC1

    1
    CC1 C_CC1

    R6305
    USBC_CC2 11 5 USBC_CC2_CONN FPF2281BUCX-F130_WLCSP12 1/20W_0_5%_0201
    <59> USBC_CC2

    A4
    B4
    C4
    CC2 C_CC2
    R6302
    20 7 1/20W_10K_5%_0201
    D1 RPD_G1
    19

    1
    D2
    17 6

    Q6301_1
    NC1 RPD_G2
    16
    NC2
    9 U6301_9
    FLT
    U6301_3 3
    VBIAS
    8
    GND1
    13
    GND2 Over Voltage Lock Out Trip Threshold = 1.20 * ( 1 + R3022 / R3023 )

    1
    0.1U_50V_K_X5R_0402

    18 @ Q6301 D
    GND3
    2 21 2
    THERMAL_PAD <59> USBC_DISCHARGE USBC_VBUS20
    C6307

    G
    SSM3K72KFS_2-2H1S
    SN1710033RUKR_WQFN20_3X3 S

    3
    1

    2
    USBC_SBU1_CONN R6318 1 2 1/20W_2M_5%_0201
    USBC_SBU2_CONN R6319 1 2 1/20W_2M_5%_0201 @ R6321
    1K_1206_5%

    1
    USBC_VBUS20_CONN

    29
    28
    27
    26
    25
    JUSBC1
    @

    GND29
    GND28
    GND27
    GND26
    GND25
    A1 B12
    GND_A1 GND_B12
    USBC_TX1P_CONN A2 B11 USBC_RX1P_CONN
    TX1+_A2 RX1+B11
    USBC_TX1N_CONN A3 B10 USBC_RX1N_CONN
    TX1-_A3 RX1-_B10
    C A4 B9 C
    VBUS_A4 VBUS_B9
    USBC_CC1_CONN A5 B8 USBC_SBU2_CONN
    CC1_A5 SBU2_B8
    USBC_USB2P_CONN A6 B7 USBC_USB2N_CONN
    D+_A6 D-_B7
    USBC_USB2N_CONN A7 B6 USBC_USB2P_CONN
    D-_A7 D+_B6
    USBC_SBU1_CONN A8 B5 USBC_CC2_CONN
    SBU1_A8 CC2_B5
    A9 B4
    VBUS_A9 VBUS_B4
    USBC_RX2N_CONN A10 B3 USBC_TX2N_CONN
    RX2-_A10 TX2-_B3
    USBC_RX2P_CONN A11 B2 USBC_TX2P_CONN
    RX2+_A11 TX2+_B2
    A12 B1
    GND_A12 GND_B1

    GND30
    30
    HIGHS_UB11247-A600C-1H

    D6301 EMC@ D6309 EMC@


    0.22U_6.3V_K_X5R_0201 L6301 EMC@
    C6310 1
    USBC_TX1N 2 USBC_TX1N_C 1 2 USBC_TX1N_CONN 1
    USBC_TX1P_CONN 2 2 1 USBC_RX1P_CONN
    <61> USBC_TX1N 1 2 1 2 2 1
    B B

    C6311 1
    USBC_TX1P 2 4
    USBC_TX1P_C 3 USBC_TX1P_CONN PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
    <61> USBC_TX1P 4 3
    EXC24CH900U_4P D6302 EMC@ D6310 EMC@
    0.22U_6.3V_K_X5R_0201
    1
    USBC_TX1N_CONN 2 2 1 USBC_RX1N_CONN
    1 2 2 1
    0.22U_6.3V_K_X5R_0201 L6302 EMC@
    C6308 1
    USBC_TX2P 2 USBC_TX2P_C4 3 USBC_TX2P_CONN
    <61> USBC_TX2P 4 3 PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

    C6309 1
    USBC_TX2N 2 1
    USBC_TX2N_C 2 USBC_TX2N_CONN D6303 EMC_NS@ D6311 EMC_NS@
    <61> USBC_TX2N 1 2
    EXC24CH900U_4P 1
    USBC_CC2_CONN 2 2 1 USBC_SBU1_CONN
    1 2 2 1
    0.22U_6.3V_K_X5R_0201

    L6303 EMC@ PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2


    USBC_RX1N 4 3 USBC_RX1N_CONN
    <61> USBC_RX1N 4 3 D6304 EMC@ D6305 EMC@

    USBC_RX1P 1 2 USBC_RX1P_CONN 1
    USBC_USB2P_CONN 2 2 1 USBC_USB2N_CONN
    <61> USBC_RX1P 1 2 1 2 2 1

    EXC24CH900U_4P
    PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

    L6304 EMC@ D6306 EMC_NS@ D6312 EMC_NS@


    USBC_RX2P 1 2 USBC_RX2P_CONN
    <61> USBC_RX2P 1 2 2 1
    1
    USBC_SBU2_CONN 2 2 1 USBC_CC1_CONN
    1 2
    USBC_RX2N 4 3 USBC_RX2N_CONN
    <61> USBC_RX2N 4 3 PESD5V0H1BSF_SOD962-2
    PESD5V0H1BSF_SOD962-2
    EXC24CH900U_4P
    D6307 EMC@ D6313 EMC@

    L6305 EMC@ 1
    USBC_RX2N_CONN 2 2 1 USBC_TX2N_CONN
    1 2 2 1
    USBC_USB2P_R 4 3 USBC_USB2P
    4 3 USBC_USB2P <10>
    PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
    USBC_USB2N_R 1 2 USBC_USB2N
    1 2 USBC_USB2N <10> D6308 EMC@ D6314 EMC@
    EXC24CH900U_4P
    1
    USBC_RX2P_CONN 2 2 1 USBC_TX2P_CONN
    1 2 2 1

    PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 TYPE-C CONNECTOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    D 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 63 of 125
    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    D D

    M.2 Socket 3 (Key-M) for 2280 S3 SSD R6401


    EVT FVT SIT SVT
    H=3.00mm Connector Resistor
    R-short
    V

    VCC3B

    VCC3B

    2
    R6401 1

    2
    0_1%_0603_LE
    C6409 R6403
    47P_25V_J_NPO_0201 1/20W_10K_5%_0201

    1
    @ 2
    JSSD1
    RF_NS@

    1
    -SSD_DTCT 1 2 VCC3B_SSD
    <87> -SSD_DTCT GND_1 3.3V_1
    3 4
    GND_2 3.3V_2
    5 6 D6401
    <10> PCIE13_L3_RXN PERN3 N/C_2
    2 1
    C 7 8 -PLP_INT C
    <10> PCIE13_L3_RXP PERP3 N/C_3 -PWRSW_EC <13,86>
    9 10
    GND_3 DAS/DSS#
    C6401 1 2 0.22U_6.3V_K_X5R_0201 PCIE13_L3_TXN_CONN 11 12 RB520CM-30T2R_VMN2M2
    <10> PCIE13_L3_TXN PETN3 3.3V_3
    C6402 1 2 0.22U_6.3V_K_X5R_0201 PCIE13_L3_TXP_CONN 13 14 VCC3B
    <10> PCIE13_L3_TXP PETP3 3.3V_4
    15 16
    GND_4 3.3V_5
    17 18
    <10> PCIE13_L2_RXN PERN2 3.3V_6
    19 20
    <10> PCIE13_L2_RXP PERP2 N/C_4
    21 22
    N/C_5

    2
    GND_5
    C6403 1 2 0.22U_6.3V_K_X5R_0201 PCIE13_L2_TXN_CONN 23 24
    <10> PCIE13_L2_TXN C6404 1 2 0.22U_6.3V_K_X5R_0201 PETN2 N/C_6
    R6402
    PCIE13_L2_TXP_CONN 25 26 @ TP6401
    <10> PCIE13_L2_TXP PETP2 N/C_7
    27 28 Test_Point_20MIL 1/20W_10K_5%_0201
    GND_6 N/C_8
    29 30 -PLP_FDBK 1
    <10> PCIE13_L1_RXN PERN1 N/C_9
    32
    31

    1
    <10> PCIE13_L1_RXP PERP1 N/C_10
    34
    33
    GND_7 N/C_11
    C6405 1 2 0.22U_6.3V_K_X5R_0201 PCIE13_L1_TXN_CONN 35 36
    <10> PCIE13_L1_TXN C6406 1 2 0.22U_6.3V_K_X5R_0201 PETN1 N/C_12
    38
    PCIE13_L1_TXP_CONN 37
    <10> PCIE13_L1_TXP PETP1 DEVSLP
    40 SATA1_DEVSLP <10>
    39
    GND_8 N/C_13
    PCIE13_L0_SATA1_RXP 41 42
    <10> PCIE13_L0_SATA1_RXP PERN0/SATA-B+ N/C_14
    44
    PCIE13_L0_SATA1_RXN 43
    <10> PCIE13_L0_SATA1_RXN PERP0/SATA-B- N/C_15
    46
    45
    GND_9 N/C_16
    PCIE13_L0_SATA1_TXN C6407 1 2 0.22U_6.3V_K_X5R_0201 PCIE13_L0_SATA1_TXN_CONN 47 48
    <10> PCIE13_L0_SATA1_TXN C6408 1 2 0.22U_6.3V_K_X5R_0201 PETN0/SATA-A- N/C_17
    50
    PCIE13_L0_SATA1_TXP PCIE13_L0_SATA1_TXP_CONN 49 -PLTRST_FAR
    <10> PCIE13_L0_SATA1_TXP PETP0/SATA-A+ PERST#
    52 -PLTRST_FAR <13,37,67,73,85,93,94>
    51 -CLKREQ_PCIE13
    GND_10 CLKREQ# -CLKREQ_PCIE13 <12>
    -PCIE13_CLK_100M 53 54
    <12> -PCIE13_CLK_100M 55 REFCLKN PEWAKE#
    56
    PCIE13_CLK_100M
    <12> PCIE13_CLK_100M 57 REFCLKP N/C_18
    58
    GND_11 N/C_19

    67 68
    N/C_1 SUSCLK
    -SATA_DTCT 69 70
    <10> -SATA_DTCT PEDET 3.3V_7
    72
    71
    GND_12 3.3V_8
    73 74
    GND_13 3.3V_9
    75
    GND_14

    77 76 2 2
    PEG1 PEG2
    PEDET (-SATA_DTCT) C6410 C6411
    B SATA Device GND ARGOS_NASM0-S6705-TS20
    10U_6.3V_M_X5R_0402 0.01U_6.3V_K_X7R_0201 B
    PCIe Device Open 1 1

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 M.2 SOCKET 3 MODULE I/F
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 64 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 65 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC3WLAN_R VCC3WLAN_R

    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402
    0.1U_6.3V_K_X5R_0201
    0.01U_6.3V_K_X7R_0201

    0.01U_6.3V_K_X7R_0201
    0.1U_6.3V_K_X5R_0201
    100PC_50VC_JC_NPOC_0402
    47PC_50VC_JC_NPOC_0402
    1 1 2 2 2 2 2 2

    RF_NS@ C6608

    CNV@ C6605
    C6602
    RF_NS@ C6607

    C6601

    C6603

    CNV@ C6604

    C6606
    2 2 1 1 1 1 1 1

    CNV@
    D D

    CNV@

    CNV@
    CNV@
    VCC3WLAN VCC3WLAN_R
    R6601 C6604,C6605,C6606 close to M.2 pin72 and pin73
    1 2
    C6601,C6602,C6603 close to M.2 pin 4 and pin5
    0_1%_0603_LE

    R6601
    EVT FVT SIT SVT
    Resistor V
    R-short

    TABLE
    M.2 Type 1216 Module for WLAN / Bluetooth Companion RF (CRF)
    Jefferson Peak (JfP)
    CNVio
    Gen1
    REFCLK
    Supported
    CLKREQ
    Supported
    Harrison Peak (HrP) Gen2 Not Supported Not Supported
    VCC3WLAN_R

    TABLE
    UWLAN1A Platform CNVio PCH IP REFCLK
    1 4 Whiskey Lake Gen1 Pulsar 38.4MHz Clock form JfP Module VCC3WLAN_R
    UIM_POWER_SRC/GPIO1 3.3V_4
    2 5
    C 3 UIM_PWR_SNK 3.3V_5
    72 Ice Lake Gen2 Quasar Generated inside SoC C
    UIM_SWP 3.3V_72
    73 @
    3.3V_73
    BDC_ON R6602 2 1 1/20W_10K_5%_0201
    8 7
    ALERT# RESERVED_7
    9 16 -WLAN_RF_KILLR6603 2 @ 1 1/20W_10K_5%_0201
    I2C_CLK RESERVED_16
    10 18
    I2C_DATA RESERVED_18
    19
    RESERVED_19
    21 VCC3WLAN_R
    R6602,R6603 close to M.2
    RESERVED_21
    11 22
    COEX_TXD RESERVED_22
    12 24
    COEX_RXD RESERVED_24
    13 25
    COEX3 RESERVED_25
    66
    RESERVED_66
    67 UWLAN1B
    RESERVED_67
    69
    USB_D-
    70 6 A48 65
    USB_D+ GND_6 3.3V_A48 LED1#
    17 A49 64
    GND_17 3.3V_A49 LED2#
    20
    GND_20
    33 23 27 SUSCLK_32K
    34 REFCLKN0 GND_23
    26 SUSCLK SUSCLK_32K <12,85>
    A25
    REFCLKP0 GND_26 C_P32K
    32 A08
    GND_32 A4WP_IRQ#
    30 35 A09 28 -WLAN_RF_KILL
    CLKREQ# GND_35
    38 A4WP_CLK W_DISABLE1# -WLAN_RF_KILL <85>
    A10 63
    36
    GND_38
    41 A4WP_DATA W_DISABLE2# BDC_ON <10>
    PERN0 GND_41
    37 62
    PERP0 GND_62
    68 A19 CNV_WT_CLKP
    39
    GND_68
    71 WT_CLKP CNV_WT_CLKP <11>
    A20 CNV_WT_CLKN
    40 PETN0 GND_71 WT_CLKN CNV_WT_CLKN <11>
    VCC1R8_SUS
    PETP0
    74 A11 A21 CNV_WT_D0P
    31
    GND_74
    75 RESERVED_A11 WT_D0P CNV_WT_D0P <11>
    A12 A22 CNV_WT_D0N
    29 PERST# GND_75
    76 A13 RESERVED_A12 WT_D0N CNV_WT_D0N <11> R6604,R6605 close to PCH
    PEWAKE# GND_76 RESERVED_A13
    77 A14 A23 CNV_WT_D1P BRI_RSP_CNVI R6604 @1 2 1/16W_20K_5%_0402
    GND_77 RESERVED_A14 WT_D1P CNV_WT_D1P <11>
    78 A16 A24 CNV_WT_D1N RGI_RSP_CNVI R6605 @1 2 1/16W_20K_5%_0402
    GND_78 RESERVED_A16 WT_D1N CNV_WT_D1N <11>
    42 79 A17 BRI_DT_R6608 R6606 @1 2 1/16W_10K_5%_0402
    CLINK_CLK GND_79 RESERVED_A17
    43 80 A18 RGI_DT_R6610 R6607 1 2 1/16W_20K_5%_0402
    CLINK_DATA GND_80 RESERVED_A18
    44 81 A27 A32 CNV_WR_CLKP
    CLINK_RESET GND_81 RESERVED_A27 WGR_CLKP CNV_WR_CLKP <11>
    82 A28 A33 CNV_WR_CLKN
    GND_82
    83 A29 RESERVED_A28 WGR_CLKN CNV_WR_CLKN <11> R6607,R6606 close to M.2
    GND_83 RESERVED_A29
    14 84 A30 A34 CNV_WR_D0P
    SYSCLK/GNSS0 GND_84 RESERVED_A30 WGR_D0P CNV_WR_D0P <11>
    15 85 A46 A35 CNV_WR_D0N
    TX_BLANKING/GNSS1 GND_85 RESERVED_A46 WGR_D0N CNV_WR_D0N <11>
    B 86 A47 B
    GND_86 RESERVED_A47
    87 A36 CNV_WR_D1P
    GND_87 WGR_D1P CNV_WR_D1P <11>
    52 88 A37 CNV_WR_D1N -CNV_RF_RESET
    SDIO_CLK GND_88 WGR_D1N CNV_WR_D1N <11>
    51 89
    SDIO_CMD GND_89
    90 R6609,R6611 close to M.2 CNV_CLKREQ
    GND_90
    50 91 A45 A38 BRI_DT_R6608 R6608 1 CNV@ 2 1/20W_33_5%_0201 BRI_DT_CNVI
    SDIO_DATA0 GND_91 NO CONNECT BRI_DT BRI_DT_CNVI <8>
    49 92 A39 BRI_RSP_R6609 R6609 1 CNV@ 2 1/20W_22_5%_0201 BRI_RSP_CNVI
    SDIO_DATA1 GND_92 BRI_RSP BRI_RSP_CNVI <8>
    48 93
    SDIO_DATA2 GND_93
    47 94 A15 A40 RGI_DT_R6610 R6610 1 2 1/20W_33_5%_0201 RGI_DT_CNVI
    SDIO_DATA3 GND_94 LNA_EN RGI_DT RGI_DT_CNVI <8>
    95 A41 RGI_RSP_R6611 R6611 1 CNV@ 2 1/20W_22_5%_0201 RGI_RSP_CNVI
    GND_95 RGI_RSP RGI_RSP_CNVI <8>
    45 96
    SDIO_RESET# GND_96
    46 A07
    SDIO_WAKE# G1 A26 GND_A07
    A42 R6610,R6608 close to PCH -CNV_RF_RESET
    GND_G1 GND_A26 RF_RESET_B -CNV_RF_RESET <9>
    G2 A31 A43 CNV_CLKREQ
    GND_G2 GND_A31 CLKREQ0 CNV_CLKREQ <9>
    58 G3 A50 A44 CNV_REFCLK
    PCM_SYNC/I2S_WS GND_G3 GND_A50 REFCLK0 CNV_REFCLK <12>
    61 G4
    PCM_CLK/I2S_CLK GND_G4
    59
    PCM_OUT/I2S_SD_OUT G5
    60
    PCM_IN/I2S_SD_IN GND_G5
    G6 9560PD2WGPLQ_146P
    GND_G6

    2
    G7 CNV@ CNV@
    GND_G7 CVN@
    55 G8 R6613 R6614
    LPSS_UART_RXD/BRI_RSP GND_G8
    56 G9 1/20W_75K_5%_0201 1/20W_71.5K_1%_0201
    LPSS_UART_TXD/RGI_DT GND_G9
    54 G10
    LPSS_UART_RTS/BRI_DT GND_G10
    57 G11
    GND_G11

    1
    LPSS_UART_CTS/RGI_RSP

    1
    53 G12
    UART_WAKE# GND_G12
    R6613 close to PCH
    9560PD2WGPLQ_146P
    CNV@

    A A

    CNVi
    TABLE of CNVi (UWLAN1A & UWLAN1B)
    ZZZ ZZZ
    Vendor Model LCFC P/N
    Intel Jefferson Peak 2 9560 2*2ac+BT5.0 vPro M.2 1216 LGA PK29S001400
    Intel
    Intel Jefferson Peak 2 9560 2*2ac+BT5.0 non-vPro M.2 1216 LGA PK29S001500 Title
    VP WLINT JP29560 NVP WLINT JP29560 Security Classification LC Future Center Secret Data
    X7645Q01006 X7645Q01005 Issued Date 2018/01/12 Deciphered Date 2018/01/12 M.2 TYPE 1216 MODULE
    66_V@ Vinafix.com 66_NV@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 66 of 125
    5 4 3 2 1
    5 4 3 2 1

    M.2 Socket 2 (Key-B) for 3042 S3 WWAN


    H=2.00mm Connector VCC3B_WAN
    VCC3B VCC3B
    VCC3_SUS

    R6702 R6703
    D R6710 VCC3B VCC3B_WAN D

    2
    2

    1/20W_10K_5%_0201
    1/20W_100K_5%_0201

    @ 1/20W_100K_5%_0201
    @
    R6701
    1 2

    1
    1

    1
    0_1%_0603_LE
    R6701,R6704,R6705
    EVT FVT SIT SVT
    Resistor V
    R-short

    JWWAN1
    WWAN_CFG3 1 2
    <8> WWAN_CFG3 CONFIG_3 3.3VAUX1
    3 4
    GND1 3.3VAUX2
    5 6 -FULL_CARD_POWER_OFF
    GND2 FULL_CARD_POWER_OFF# -FULL_CARD_POWER_OFF <8>
    USBP7+ R6704 1 2 0_0201_SP USBP7+_CONN 7 8 -WWAN_DISABLE
    <10> USBP7+ USB_D+ W_DISABLE#1 -WWAN_DISABLE <6>
    USBP7- R6705 1 2 0_0201_SP USBP7-_CONN 9 10
    <10> USBP7- USB_D- GPIO9/LED1#/DAS/DSS#
    11
    GND3

    2
    NC 12 R6716
    13 NC NC 14 1/20W_100K_5%_0201
    15 NC KEY-B NC 16
    17 NC NC 18
    19 NC 20

    1
    GPIO_5
    WWAN_CFG0 21 22
    <8> WWAN_CFG0 CONFIG_0 GPIO_6
    JSIM1
    23 24
    GPIO_11 GPIO_7
    25 26
    DPR GPIO_10
    27 28
    GND4 GPIO_8 GND1
    29 30 UIM_RESET
    PERn1/USB3.0-RX-/SSIC-RxN UIM-RESET GND1
    31 32 UIM_CLK_R6706 R6706 1 2 1/20W_200_1%_0201 UIM_CLK GND2
    PERp1/USB3.0-RX+/SSIC-RxP UIM-CLK GND2
    33 34 UIM_DATA C7 GND3
    GND5 UIM-DATA I/O GND3
    35 36 UIM_PWR C6 GND4
    PETn1/USB3.0-TX-/SSIC-TxN UIM-PWR VPP GND4
    37 38 C5 GND5
    PETp1/USB3.0-TX+/SSIC-TxP DEVSLP GND GND5
    39 40 R6711 @ 1/20W_0_5%_0201 GND6
    GND6 GPIO_0 GND6
    PCIE7_RXN R6707 1 2 0_0201_SP PCIE7_RXN_R 41 42 1 2 GND7
    <10> PCIE7_RXN R6708 1 2 0_0201_SP PERn0/SATA-B+ GPIO_1 -PLTRST_FAR <13,37,64,73,85,93,94> C3 GND7
    C PCIE7_RXP PCIE7_RXP_R 43 44 C
    <10> PCIE7_RXP PERp0/SATA-B- GPIO_2
    46 C2 CLOCK
    DSW2
    45
    GND7 GPIO_3 RST GND8
    PCIE7_TXN C6703 1 2 0.1U_6.3V_K_X5R_0201 PCIE7_TXN_C 47 48 C1 DSW1
    <10> PCIE7_TXN C6704 1 2 0.1U_6.3V_K_X5R_0201 PETn0/SATA-A- GPIO_4
    50
    VCC GND9
    PCIE7_TXP PCIE7_TXP_C 49 -WWAN_PERST_R6712 R6712 1 2 0_0201_SP
    <10> PCIE7_TXP PETp0/SATA-A+ PERST#
    52 -WWAN_PERST <3> JAE_SF70S006VBAR2000
    51 -CLKREQ_PCIE7
    GND8 CLKREQ#
    54 1 2 -CLKREQ_PCIE7 <12>
    -PCIE7_CLK_100M 53 -WWAN_PEWAKE_R6714

    CDZCGT2RA6P8B_VMN2-2
    CDZCGT2RA6P8B_VMN2-2
    CDZCGT2RA6P8B_VMN2-2

    CDZCGT2RA6P8B_VMN2-2
    12> -PCIE7_CLK_100M REFCLKN PEWake# -WWAN_PEWAKE <8> 2 @

    1/20W_2.2K_1%_0201
    PCIE7_CLK_100M 55 56 @ R6714 1/20W_0_5%_0201
    12> PCIE7_CLK_100M

    1
    REFCLKP NC1
    57 58 C6705

    1
    1
    NC2

    1
    GND9

    1
    R6713
    59 60 4.7U_6.3V_M_X5R_0402
    ANTCTRL0 COEX3 1

    D6704
    D6703
    D6702

    D6701
    61 62 1 2
    ANTCTRL1 COEX2
    64 -PCIE_WAKE <13,55,76,94>
    63 @ R6715 1/20W_0_5%_0201
    ANTCTRL2 COEX1

    1/20W_0_5%_0201
    65 66

    EMC@ 2
    2

    EMC@ 2
    EMC@ 2

    EMC@ 2
    R6709 1 2 0_0201_SP ANTCTRL3 SIM_DETECT R6717 1 20_0201_SP
    RESET_R6709 67 68
    <11> -WWAN_RESET RESET# SUSCLK
    70 -WWAN_ANTENNA <9>
    WWAN_CFG1 69
    <8> WWAN_CFG1 71 CONFIG_1 3.3VAUX3
    72
    GND10 3.3VAUX4
    73 74
    GND11 3.3VAUX5
    WWAN_CFG2 75
    <8> WWAN_CFG2 CONFIG_2

    47P_25V_J_NPO_0201

    100P_25V_J_NPO_0201
    76 77 2 2
    PEG1 PEG2

    C6706

    C6707
    R6717

    1
    ARGOS_NASB0-S6705-TSH4 EVT FVT SIT SVT
    @ Resistor ASM
    1 1

    @
    R-short

    RF@

    RF@

    2
    AOZ8231ADI-03_DFN1P0X0P6-2
    AOZ8231ADI-03_DFN1P0X0P6-2

    TABLE of WWAN (Pin68#)

    R6718
    1
    1

    M.2 module side Description MIMO mode


    1
    1

    D6706
    D6705

    L850-GL,L830-EB #68=NC 2
    L860-GL (#68= antenna cfg) #68=internal pull up(100KΩ ) 4
    2
    2

    EMC_NS@
    EMC_NS@

    2
    2

    VCC3B_WAN

    VCC3B_WAN
    B B

    18PC_25VC_JC_COGC_0201
    6.8PC_25VC_C_NPOC_0201

    39PC_50VC_JC_NPOC_0402
    8.2PC_50VC_C_NPOC_0402

    1U_6.3V_K_X5R_0402
    0.1U_6.3V_K_X5R_0201

    10U_6.3V_M_X5R_0402
    0.1U_6.3V_K_X5R_0201

    1000P_25V_K_X7R_0201

    33P_25V_J_NPO_0201
    2 1 1 1 1 1 1 2 2 2

    RF@ C6713
    RF@ C6711

    C6708
    @ C6716
    @ C6717

    C6709
    RF@ C6715
    RF@ C6712

    RF@ C6714

    C6710
    @
    1 2 2 2 2 2 2 1 1 1

    TABLE:

    Module Configuration Decodes Module Type


    and Port Module
    State # CONFIG_0 CONFIG_3 CONFIG_2 CONFIG_1 Configuration
    (Pin 21) (Pin 1) (Pin 75) (Pin 69) Main Host Interface
    0 GND GND GND GND SSD - SATA N/A RF Reserved Parts
    1 GND GND GND NC SSD - PCIe N/A
    2 GND GND NC GND WWAN - PCIe 0
    3 GND GND NC NC WWAN - PCIe 1
    4 GND NC GND GND WWAN - PCIe, USB 3.1 Gen1 0 WWAN L850
    5 GND NC GND NC WWAN - PCIe, USB 3.1 Gen1 1
    6 GND NC NC GND WWAN - PCIe, USB 3.1 Gen1 2
    7 GND NC NC NC WWAN - PCIe, USB 3.1 Gen1 3
    8 NC GND GND GND WWAN - SSIC 0 WWAN L830
    9 NC GND GND NC WWAN - SSIC 1
    A A
    10 NC GND NC GND WWAN - SSIC 2
    11 NC GND NC NC WWAN - SSIC 3
    12 NC NC GND GND WWAN - PCIe 2
    13 NC NC GND NC WWAN - PCIe 3
    14 NC NC NC GND WWAN - PCIe, USB 3.1 Gen1 Vendor Defined WWAN L860
    15 NC NC NC NC No Module Present N/A Security Classification LC Future Center Secret Data Title
    Issued Date 2018/01/12 Deciphered Date 2018/01/12 M.2 SOCKET 2 MODULE I/F
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 67 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC3B

    D @ D
    DDIP2_HPD 1 Test_Point_20MIL TP6801
    VCC3B USBC_HPD 1 Test_Point_20MIL TP6802
    2 2 2 2 2 @
    C6801 C6802 C6803 C6804 C6805
    0.1UC_10VC_KC_X5RC_0402 0.01UC_25VC_KC_X7RC_0402
    0.1UC_10VC_KC_X5RC_0402 0.01U_6.3V_K_X7R_0201
    0.1UC_10VC_KC_X5RC_0402
    1 1 1 1 1

    R6801

    R6803
    R6802
    U6801

    R6804
    14 8 PS8337B_PEQ
    VDD33_1 PEQ
    28
    VDD33_2

    1
    1
    41 5
    56 VDD33_3 IN_HPD DDIP2_HPD <3> VCC3B
    11
    VDD33_4 IN_CA_DET
    @ @

    1/20W_10K_5%_0201
    1 2

    1/20W_10K_5%_0201
    C6806 0.1U_6.3V_K_X5R_0201 DDIP2_0P_C 3 40 XBAR_DDIP2_0P
    <3> DDIP2_0P C6807 1 2 0.1U_6.3V_K_X5R_0201 IN_D0p DP_D0p XBAR_DDIP2_0P <61>
    DDIP2_0N_C 4 39 XBAR_DDIP2_0N

    2
    <3> DDIP2_0N XBAR_DDIP2_0N <61>

    2
    2
    IN_D0n DP_D0n

    1
    1 2 DDIP2_1P_C 6 37 XBAR_DDIP2_1P

    1/20W_4.7K_5%_0201
    C6808 0.1U_6.3V_K_X5R_0201
    <3> DDIP2_1P IN_D1p DP_D1p XBAR_DDIP2_1P <61>
    1 2 DDIP2_1N_C 7 36 XBAR_DDIP2_1N

    1/16W_4.7K_5%_0402
    C6809 0.1U_6.3V_K_X5R_0201 R6805
    <3> DDIP2_1N IN_D1n DP_D1n XBAR_DDIP2_1N <61>
    C6810 1 2 0.1U_6.3V_K_X5R_0201 DDIP2_2P_C 9 34 XBAR_DDIP2_2P @ 1/20W_100K_5%_0201
    <3> DDIP2_2P IN_D2P DP_D2p XBAR_DDIP2_2P <61>
    C6811 1 2 0.1U_6.3V_K_X5R_0201 DDIP2_2N_C 10 33 XBAR_DDIP2_2N
    <3> DDIP2_2N 12 IN_D2n DP_D2n XBAR_DDIP2_2N <61>
    C6812 1 2 0.1U_6.3V_K_X5R_0201 DDIP2_3P_C 31 XBAR_DDIP2_3P
    <3> DDIP2_3P XBAR_DDIP2_3P <61>

    2
    IN_D3p DP_D3p
    C6813 1 2 0.1U_6.3V_K_X5R_0201 DDIP2_3N_C 13 30 XBAR_DDIP2_3N
    <3> DDIP2_3N IN_D3n DP_D3n XBAR_DDIP2_3N <61>
    50 55 XBAR_DDIP2_AUXP
    <3> DDIP2_CTRLCLK 49 IN_DDC_SCL DP_AUXp_SCL
    54 XBAR_DDIP2_AUXP <61>
    XBAR_DDIP2_AUXN
    <3> DDIP2_CTRLDATA IN_DDC_SDA DP_AUXn_SDA XBAR_DDIP2_AUXN <61>
    45 16 HDMI_CLKP
    <9> DDI_PRIORITY1 SW/SDA_CTL TMDS_CLKp HDMI_CLKP <54>

    1
    46 15 HDMI_CLKN
    PD TMDS_CLKn HDMI_CLKN <54>
    R6806
    DDIP2_AUXP C6814 1 2 0.1U_6.3V_K_X5R_0201 DDIP2_AUXP_C 52 19 HDMI_DATA0P @ 1/20W_100K_5%_0201
    <3> DDIP2_AUXP IN_AUXp TMDS_CH0p HDMI_DATA0P <54>
    DDIP2_AUXN C6815 1 2 0.1U_6.3V_K_X5R_0201 DDIP2_AUXN_C 51 18 HDMI_DATA0N
    <3> DDIP2_AUXN IN_AUXn TMDS_CH0n HDMI_DATA0N <54>
    I2C_DATA_PD 1 @ 2 22 HDMI_DATA1P
    <59,61,87> I2C_DATA_PD HDMI_DATA1P <54>

    2
    TMDS_CH1p
    R6807 U6801_3838 21 HDMI_DATA1N HDMI_DATA1N <54>
    I2C_CTL_EN TMDS_CH1n
    1/20W_0_5%_0201 25 HDMI_DATA2P
    TMDS_CH2p HDMI_DATA2P <54>
    PS8337B_MODE 53 24 HDMI_DATA2N
    MODE TMDS_CH2n HDMI_DATA2N <54>
    VCC3B U6801_1 1 48 HDMI_DDC_CLK
    CEXT TMDS_SCL HDMI_DDC_CLK <54>
    U6801_2727 47 HDMI_DDC_DATA
    R6808 REXT TMDS_SDA HDMI_DDC_DATA <54>
    C C
    1 2 DDIP2_AUXN_C USBC_HPD 32 20 PS8337B_TMDS_PRE
    <59,61> USBC_HPD DP_HPD TMDS_PRE
    U6801_4242
    DP_CA_DET
    1/20W_1M_5%_0201 23 PS8337B_TMDS_RT
    TMDS_RT
    PS8337B_TMDS_DDCBUF 2
    TMDS_DDCBUF
    HDMI_HPD_CONN 17 26
    <54> HDMI_HPD_CONN TMDS_HPD GND1
    35
    GND2
    I2C_CLK_PD 1 @ 2 PS8337B_DP_CFG0 44 43
    <59,61,87> I2C_CLK_PD 29 DP_CFG0/SCL_CTL GND3
    57
    R6809 PS8337B_DP_CFG1
    DP_CFG1 EPAD
    1/20W_0_5%_0201

    R6811
    C6816

    R6812
    R6810
    HDMI_DDC_DATA
    PS8337BQFN56GTR2-A2_QFN56_7X7 HDMI_DDC_CLK

    1
    1
    1
    @
    2
    2 EMC_NS@ 2 EMC_NS@

    2.2UC_6.3VC_KC_X5RC_0402

    1/20W_1M_5%_0201 2

    2
    2
    C6817 C6818
    47P_25V_J_NPO_0201

    1/20W_27K_5%_0201
    47P_25V_J_NPO_0201

    1/20W_4.99K_1%_0201
    1 1

    TABLE: Automat i c S witc hi ng Mode ( MODE= H, M


    )
    SW(DDI_PRIORITY1)

    L DP Port has higher priority when both ports are plugged DEFAULT
    B B
    H TMDS Port has higher priority when both ports are pulgged

    MODE = VCC3B

    H : Automatic Switching mode,HDMI ID Disabled


    @ @
    M : Automatic Switching mode,HDMI ID Enabled DEFAULT R6813 1 2 1/16W_4.7K_5%_0402 PS8337B_DP_CFG0 R6814 1 2 1/16W_4.7K_5%_0402

    L : Control Switching mode,HDMI ID Disabled


    R6815 1 @ 2 1/16W_4.7K_5%_0402 PS8337B_DP_CFG1 R6816 1 @ 2 1/16W_4.7K_5%_0402

    R6817 1 2 1/16W_4.7K_5%_0402 PS8337B_MODE R6818 1 2 1/16W_4.7K_5%_0402

    R6819 1 2 1/16W_4.7K_5%_0402 PS8337B_TMDS_RT

    R6820 1 2 1/16W_4.7K_5%_0402 PS8337B_PEQ R6821 1 2 1/16W_4.7K_5%_0402

    @
    R6822 1 2 1/16W_4.7K_5%_0402 PS8337B_TMDS_PRE R6823 1 2 1/16W_4.7K_5%_0402

    R6824 1 @ 2 1/16W_4.7K_5%_0402 PS8337B_TMDS_DDCBUF R6825 1 @ 2 1/16W_4.7K_5%_0402


    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 DDI DEMUX/HDMI LEVEL SHIFTE
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 68 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC5M

    @
    C6901 1 2 4.7U_6.3V_M_X5R_0402 USB_PWR_S1
    D D

    C6902 1 2 0.1U_6.3V_K_X5R_0201

    U6901
    9
    GND_2
    1 8
    GND_1 OUT_8
    2 7
    IN_2 OUT_7
    3 6
    IN_3 OUT_6
    USB_ON1 4 5 -USB_PORT4_OC2
    <86> USB_ON1 EN/EN FLT -USB_PORT4_OC2 <10>
    TPS2069CDGNR MSOP 8P

    TABLE of USB3.0 Single (U6901)


    Vendor P/N LCFC P/N
    TI TPS2069CDGNR SA00005TE00
    Rohm BD82032FVJ-GE2 SA000084S00

    USB_PWR_S1
    PLACE NEAR USB CONN

    C C
    1
    2 2
    EMC@ EMC@ + C6905
    C6903 C6904 150U_B2_6.3VM_R35M
    0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201
    1 1 2

    @ JUSB2

    USB3P4_TXP_CONN 9
    StdA_SSTX+
    1
    VBUS
    USB3P4_TXN_CONN 8
    StdA_SSTX-
    USBP4+_CONN 3
    D+
    7
    GND_DRAIN
    USBP4-_CONN 2 10
    D- GND_2
    USB3P4_RXP_CONN 6 11
    StdA_SSRX+ GND_3
    4 12
    GND_1 GND_4
    USB3P4_RXN_CONN 5 13
    StdA_SSRX- GND_5

    ALLTO_C190FA-10935-L

    R6911,R6917,R6918,R6922,R6923,R6924
    EVT FVT SIT SVT
    CMC/ESD V
    Resistor

    B B

    C6906 1 2 0.1U_6.3V_K_X5R_0201 USB3P4_TXP_C R6911 1 2 0_0201_SP USB3P4_TXP_CONN


    <10> USB3P4_TXP

    C6907 1 2 0.1U_6.3V_K_X5R_0201 USB3P4_TXN_C R6917 1 2 0_0201_SP USB3P4_TXN_CONN


    <10> USB3P4_TXN

    EMC@
    D6902
    USB3P4_TXP_CONN 1 10 USB3P4_TXP_CONN
    CH1 NC4

    USB3P4_TXN_CONN 2
    CH2
    9 USB3P4_TXN_CONN
    NC3
    EMC@
    D6901
    USBP4+_CONN 6 1 USBP4-_CONN
    <10> USB3P4_RXP R6918 1 2 0_0201_SP USB3P4_RXP_CONN 3 8
    VN1 VN2

    R6922 1 2 0_0201_SP USB3P4_RXN_CONN 5 2


    <10> USB3P4_RXN
    USB3P4_RXP_CONN 4 7 USB3P4_RXP_CONN
    CH3 NC2
    4 3
    USB3P4_RXN_CONN 5 6 USB3P4_RXN_CONN
    CH4 NC1
    AOZ8904CIL_SOT23-6
    AOZ8858DI-03_DFN10_2P5X1

    A A

    EMC@
    FL6904
    USBP4+ 1 2 USBP4+_CONN
    <10> USBP4+ 1 2

    USBP4- 4 3 USBP4-_CONN
    <10> USBP4- 4 3
    EXC24CH900U_4P

    Vinafix.com Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 USB TYPE-A CONNECTOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 69 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    VCC5M

    2
    F7001
    3A_32V_ERBRD3R00X

    1
    JUSB1
    USB3P3_TXP 20
    <10> USB3P3_TXP 20
    C USB3P3_TXN 19 C
    <10> USB3P3_TXN 19
    18
    18
    USB3P3_RXP 17
    <10> USB3P3_RXP 17
    USB3P3_RXN 16 21
    <10> USB3P3_RXN 16 GND1
    15 22
    15 GND2
    USBP3- 14
    <10> USBP3- 14
    USBP3+ 13
    <10> USBP3+ 13
    12
    12
    11
    <86> AOU_SEL1 11
    10
    10
    9
    9
    8
    8
    7
    7
    6
    6
    5
    <86> AOU_SEL2 5
    4
    <86> -AOU_IFLG 4
    3
    3
    2
    <86> USB_ON2 2
    1
    <10> -USB_PORT3_OC3 1
    HIGHS_FC5AF201-2931H
    @

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Vinafix.com Issued Date 2019/01/12 Deciphered Date 2019/04/12 USB TYPE-A CONNECTOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 70 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    BLANK
    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    Drift/Ironhide
    Vinafix.com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date: Tuesday, December 18, 2018 Sheet 71 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    VCC3B
    VCC5B

    1/16W_10K_5%_0402

    1A_32V_ERBRD1R00X
    0.1U_6.3V_K_X5R_0201
    2

    2
    @

    R7201

    C7201

    F7201
    1
    1

    1
    JSC1
    C C
    VCC5B_F 1
    1
    USBP1-_CONN 2
    2
    USBP1+_CONN 3
    3
    SC@ R7204 1 2 1/20W_0_5%_0201 4
    <9> -SC_DTCT 4
    5
    5
    6
    6

    0.1UC_25VC_KC_X5RC_0402

    1/20W_0_5%_0201
    7
    GND1
    2 8
    GND2

    C7202

    RFID@ R7205
    HIGHS_FC5AF061-2131H
    @

    1
    1

    B B

    FL7201 EMC@
    USBP1- 4 3 USBP1-_CONN
    <10> USBP1- 4 3
    For Smart card USBP1+ 1 2 USBP1+_CONN
    <10> USBP1+ 1 2
    EXC24CH900U_4P

    PLACE NEAR JSC1


    A A

    R7202,R7203 Title
    EVT FVT SIT SVT Security Classification LC Future Center Secret Data
    Resistor V
    R-short
    Issued Date 2018/01/12 Deciphered Date 2018/01/12 Smart Card Reader
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 72 of 125
    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    place near the PHY


    VCC3LAN VCC3GBE

    R7312
    1 2

    0_1%_0603_LE
    2 2 2 2
    C7316 C7317 C7318 C7319
    0.1UC_10VC_KC_X5RC_04020.1UC_10VC_KC_X5RC_0402 22U_6.3V_M_X5R_0603 0.1U_6.3V_K_X5R_0201
    1 1 1 1

    D D

    U7301 U7301

    R7312
    EVT FVT SIT SVT
    Resistor V
    R-short WGI219LM SLKJ2 WGI219V SLKJ4
    SA000073020 SA000072Z10
    GBE_V@ GBE_NV@

    VCC3GBE VCC3B VCC3GBE

    1/20W_100K_5%_0201
    TABLE SKU Dscription LCFC P/N

    2
    2
    R7301 @R7302
    vPRO WGI219LM SLKJ2 SA000073020

    R7315
    1/20W_10K_5%_0201 1/20W_10K_5%_0201
    vPro Capability
    C non-vPRO WGI219V SLKJ4 SA000072Z10 C

    1
    GbE

    1
    Yes No
    PHY

    U13 Jacksonville-LM Jacksonville-V

    LOGIC

    U7301

    -CLKREQ_PCIE8 48 13 MDI_0P
    <12> -CLKREQ_PCIE8 CLK_REQ_N MDI_PLUS[0] MDI_0P <74>
    -PLTRST_FAR 36 14 MDI_0N
    <13,37,64,67,85,93,94> -PLTRST_FAR PE_RST_N MDI_MINUS[0] MDI_0N <74>
    PCIE8_CLK_100M 44 17 MDI_1P
    <12> PCIE8_CLK_100M PE_CLKP MDI_PLUS[1] MDI_1P <74>
    -PCIE8_CLK_100M 45 18 MDI_1N
    <12> -PCIE8_CLK_100M PE_CLKN MDI_MINUS[1] MDI_1N <74>

    PCIE
    MDI
    PCIE8_RXP C7301 1 2 0.1U_6.3V_K_X5R_0201 PCIE8_RXP_C 38 20 MDI_2P
    <10> PCIE8_RXP PETp MDI_PLUS[2] MDI_2P <74>
    PCIE8_RXN C7302 1 2 0.1U_6.3V_K_X5R_0201 PCIE8_RXN_C 39 21 MDI_2N
    <10> PCIE8_RXN PETn MDI_MINUS[2] MDI_2N <74>
    PCIE8_TXP C7303 1 2 0.1U_6.3V_K_X5R_0201 PCIE8_TXP_C 41 23 MDI_3P
    <10> PCIE8_TXP PERp MDI_PLUS[3] MDI_3P <74>
    PCIE8_TXN C7304 1 2 0.1U_6.3V_K_X5R_0201 PCIE8_TXN_C 42 24 MDI_3N
    <10> PCIE8_TXN PERn MDI_MINUS[3] MDI_3N <74>
    VCC3GBE
    SML0_CLK R7303 1 2 1/20W_100_5%_0201 SML0_CLK_R 28 6 7309R7310 1 2 1/20W_0_5%_0201
    SMBUS DEVICE ADDRESSES<7> SML0_CLK
    SML0_DATA R7304 1 2 1/20W_100_5%_0201 SML0_DATA_R 31 SMB_CLK SVR_EN_N

    SMBUS
    <7> SML0_DATA SMB_DATA
    1
    0XC8 7310R7311 1 2 1/20W_4.7K_5%_0201
    RSVD1_VCC3P3

    <13> -LANWAKE -LANWAKE 2 5


    LANWAKE_N VDD3P3_IN
    LANPHYPC 1 2 LANPHYPC_R 3
    <13> LANPHYPC R7314 0_0201_SP LAN_DISABLE_N
    4
    B VDD3P3_4 B
    15 C7311 1 2 1U_6.3V_K_X5R_0402
    VDD3P3_15
    -RJ45_LINKUP 26 19
    <74,86> -RJ45_LINKUP 27 LED0 VDD3P3_19
    29
    -RJ45_ACTIVITY
    <74> -RJ45_ACTIVITY 25 LED1 VDD3P3_29

    LED
    LED2
    VCC3GBE 47
    VDD0P9_47
    46
    VDD0P9_46
    32 37
    JTAG_TDI VDD0P9_37
    34
    @ R7305 1 2 1/20W_10K_5%_0201 7302 33 JTAG_TDO
    43
    KEEP SHORT AND WIDE

    JTAG
    @ R7306 1 2 1/20W_10K_5%_0201 7303 35 JTAG_TMS VDD0P9_43 PATTERN
    JTAG_TCK
    11
    VDD0P9_11
    R7309 1 2 1/20W_470_5%_0201 7312 9 40
    XTAL_OUT VDD0P9_40
    7304 10 22
    XTAL_IN VDD0P9_22
    16
    VDD0P9_16
    8
    VDD0P9_8
    7305 30
    TEST_EN FL7301
    7307 7306 12 7 7308 1 2 7311
    RBIAS CTRL0P9
    4.7UH_NRS2012T4R7MGJ_20%
    49
    GND
    Y7301 2 2 2
    WGI219LM-QREF-A0_QFN48_6X6
    4 3 C7312 C7313 @ C7314
    2 NC2 3 2 @
    2

    2
    2

    C7305 C7306 place near the PHY 22U_6.3V_M_X5R_0603 0.1U_6.3V_K_X5R_02010.1U_6.3V_K_X5R_0201


    1 2 @ R7313 R7307 R7308 1 1 1
    1 NC1
    15P_0201_25V8-J 15P_0201_25V8-J 1/20W_1K_5%_02011/20W_3.01K_1%_0201
    1 1 1/20W_10K_5%_0201
    25MHZ_10PF_7R25080002
    1

    1
    1

    A A

    Y7301 CRYSTAL - 25MHz 10pF 30ppm 2016


    Vendor P/N LCFC P/N
    TXC 7R25080002 SJ10000PP00
    KDS 1ZZNAE25000CC0B TBD
    Epson Q22FA1280055900 SJ10000PU00 Title
    Security Classification LC Future Center Secret Data
    Issued Date 2018/01/12 Deciphered Date 2018/01/12 GBE JACKSONVILLE
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 73 of 120
    5 4 3 2 1
    5 4 3 2 1

    D D

    VCC3GBE

    0.1U_6.3V_K_X5R_0201
    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201
    VCC3GBE

    2 2 2 2 2

    2
    1 1 1 1 1

    C7403
    C7401

    C7402

    C7404

    C7405
    R7401
    1/20W_4.7K_5%_0201

    39
    30
    21
    14
    8
    4
    1
    U7401
    C C

    VDD7
    VDD6
    VDD5
    VDD4
    VDD3
    VDD2
    VDD1
    38 DOCK_MDI_3-
    B0+ DOCK_MDI_3- <62>
    37 DOCK_MDI_3+
    B0- DOCK_MDI_3+ <62>
    MDI_3N 2
    <73> MDI_3N A0+
    34 DOCK_MDI_2-
    B1+ DOCK_MDI_2- <62>
    MDI_3P 3 33 DOCK_MDI_2+
    <73> MDI_3P A0- B1- DOCK_MDI_2+ <62>
    29 DOCK_MDI_1-
    B2+ DOCK_MDI_1- <62>
    MDI_2N 6 28 DOCK_MDI_1+
    <73> MDI_2N A1+ B2- DOCK_MDI_1+ <62>
    MDI_2P 7 25 DOCK_MDI_0-
    <73> MDI_2P A1- B3+ DOCK_MDI_0- <62>
    24 DOCK_MDI_0+
    B3- DOCK_MDI_0+ <62>
    MDI_1N 9 17 -DOCK_ACTIVITY_SYS -DOCK_ACTIVITY_SYS <62>
    <73> MDI_1N A2+ LEDB0
    18 -DOCK_LINKUP_SYS -DOCK_LINKUP_SYS <62>
    LEDB1
    MDI_1P 10 41
    <73> MDI_1P A2- LEDB2
    36 SYS_MDI_3-
    MDI_0N C0+ SYS_MDI_3- <75>
    11 35 SYS_MDI_3+
    <73> MDI_0N A3+ C0- SYS_MDI_3+ <75>
    MDI_0P 12 32 SYS_MDI_2-
    <73> MDI_0P A3- C1+ SYS_MDI_2- <75>
    31 SYS_MDI_2+
    C1- SYS_MDI_2+ <75>
    -DOCK_RJ45_DET 13 27 SYS_MDI_1-
    <62> -DOCK_RJ45_DET SEL C2+ SYS_MDI_1- <75>
    26 SYS_MDI_1+
    C2- SYS_MDI_1+ <75>
    -RJ45_ACTIVITY 15 23 SYS_MDI_0-
    <73> -RJ45_ACTIVITY LEDA0 C3+ SYS_MDI_0- <75>
    -RJ45_LINKUP 16 22 SYS_MDI_0+
    <73,86> -RJ45_LINKUP 42 LEDA1 C3- SYS_MDI_0+ <75>
    LEDA2
    19 -RJ45_ACTIVITY_SYS
    LEDC0 -RJ45_ACTIVITY_SYS <75>
    5 20 -RJ45_LINKUP_SYS
    PD LEDC1 -RJ45_LINKUP_SYS <75>
    40
    LEDC2
    43
    PAD_GND

    PI3L720ZHE+CX_TQFN42_9X3P5
    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 GBE LAN SWITCH
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 74 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    VCC3GBE

    2
    F7501

    1A_32V_ERBRD1R00X
    1
    C C

    JLAN1 @
    1 2
    1 2
    3 4 SYS_MDI_1-
    3 4 SYS_MDI_1- <74>
    5 6 SYS_MDI_1+
    5 6 SYS_MDI_1+ <74>
    7 8
    7 8
    -RJ45_ACTIVITY_SYS 9 10 SYS_MDI_2-
    <74> -RJ45_ACTIVITY_SYS 9 10 SYS_MDI_2- <74>
    -RJ45_LINKUP_SYS 11 12 SYS_MDI_2+
    <74> -RJ45_LINKUP_SYS 11 12 SYS_MDI_2+ <74>
    13 14
    13 14
    SYS_MDI_0- 15 16 SYS_MDI_3-
    <74> SYS_MDI_0- 15 16 SYS_MDI_3- <74>
    SYS_MDI_0+ 17 18 SYS_MDI_3+
    <74> SYS_MDI_0+ 17 18 SYS_MDI_3+ <74>
    19 20
    19 20

    21 22
    GND1 GND2

    HIGHS_BT5P0201-1001H

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Vinafix.com
    Issued Date Deciphered Date GBE MAGNETICS
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 75 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC3B VCC3B_RTS5232S
    RTS5232S RTS5232S_DV12 RTS5232S_AV12
    R7601 40 mils
    1 2 VCC3B_RTS5232S

    VCC3B_RTS5232S
    20 mils RTS5232S_DV12
    20 mils RTS5232S_AV12
    20 mils
    0_1%_0603_LE
    1 1 1 1 1 1 1
    C7605 C7606 C7619 C7620 C7603 C7604 C7615
    0.1UC_10VC_KC_X7RC_0402 10U_6.3V_M_X5R_0603 4.7U_6.3V_K_X5R_0603 0.1UC_10VC_KC_X7RC_0402 4.7U_6.3V_K_X5R_0603 0.1UC_10VC_KC_X7RC_0402 0.1UC_10VC_KC_X7RC_0402
    2 2 2 2 2 2 2
    D D
    Close to pin 11
    Close to pin 27 Close to pin 14 Close to pin 10

    VCC3B_RTS5232S

    R7601
    EVT FVT SIT SVT

    2
    Resistor V SD_MMC_CD
    R-short R7618
    1/20W_100K_5%_0201

    3
    Q7601

    SD_MMC_CD_CONN 1 LSK3541G1ET2L_VMT3

    2
    VCC3B_RTS5232S

    VCC3B_RTS5232S VCC3B_RTS5232S
    R7607 R7620
    non-RTD3 ASM non-ASM

    1
    RTD3 non-ASM ASM
    R7607

    2
    C 1/16W_10K_5%_0402 C
    R7619
    1/20W_10K_5%_0201

    2
    @
    1 U7601
    R7606 1/16W_0_5%_0402
    VCC33_18 11 30 SD_MMC_CD 1 @ 2 SD_MMC_CD_CONN
    3V3_IN SD_CD# SD_MMC_CD_CONN <77>
    VCC33_18 18 31
    DV33_18 MS_INS#
    1 @
    RTS5232S_AV12 10 32 RTS5232S_WAKE# R7620 1 2 1/16W_0_5%_0402
    C7607 AV12 WAKE# -PCIE_WAKE <13,55,67,94>
    1U_10V_K_X5R_0402R7603 1 2 0_0603_SP RTS5232S_DV12 14
    2 DV12S

    DV12 connects with AV12, due


    to DV12 need a external input. 15 SD_MMC_D1 R7608 1 2 0_0402_SP SD_MMC_D1_CONN
    SP1 SD_MMC_D1_CONN <77>
    VCC3_MC 12 16 SD_MMC_D0 R7609 1 2 0_0402_SP SD_MMC_D0_CONN
    VCC3_MC Card_3V3 SP2 SD_MMC_D0_CONN <77>
    17 SD_MMC_CLK R7610 1 2 0_0402_SP SD_MMC_CLK_CONN
    27 SP3 SD_MMC_CLK_CONN <77>
    VCC3B_RTS5232S
    3V3aux
    19 SD_MMC_CMD R7611 1 2 0_0402_SP SD_MMC_CMD_CONN
    SP4 SD_MMC_CMD_CONN <77>
    R7604 1 2 1/16W_6.2K_1%_0402
    RTS5232S_RREF 9 20 SD_MMC_D3 R7612 1 2 0_0402_SP SD_MMC_D3_CONN
    RREF SP5 SD_MMC_D3_CONN <77>
    1. Close to R7604 21 SD_MMC_D2 R7613 1 2 0_0402_SP SD_MMC_D2_CONN
    SP6 SD_MMC_D2_CONN <77>
    2. 12mils, lengths < 200mils
    C7613 1 2 0.1UC_10VC_KC_X7RC_0402
    PCIE1_TXP_C 3 29 SD_MMC_WPI
    <10> PCIE1_TXP HSIP SP7
    C7614 1 2 0.1UC_10VC_KC_X7RC_0402
    PCIE1_TXN_C 4
    <10> PCIE1_TXN HSIN
    C7608 1 2 0.1UC_10VC_KC_X7RC_0402
    PCIE1_RXP_C 7
    B
    <10> PCIE1_RXP HSOP B
    C7609 1 2 0.1UC_10VC_KC_X7RC_0402
    PCIE1_RXN_C 8 13
    <10> PCIE1_RXN HSON NC1
    22
    NC2
    PCIE1_CLK_100M 5 23
    <12> PCIE1_CLK_100M REFCLKP NC3

    1
    -PCIE1_CLK_100M 6 24
    <12> -PCIE1_CLK_100M REFCLKN NC4
    R7617
    25 0_0402_SP
    NC5
    Check inet name -PLTRST or -PLTRST_NEAR -PLTRST_NEAR 1 26

    2
    <13,55,98> -PLTRST_NEAR PERST# NC6

    -CLKREQ_PCIE1 2
    <12> -CLKREQ_PCIE1 CLK_REQ#

    R7605 1 2 28
    1/16W_10K_5%_0402
    7601 33
    VCC3B_RTS5232S GPIO GND
    SD_MMC_D0_CONN C7610 1 2 5.6P_50V_D_NPO_0402
    EMC_NS@
    RTS5232S-GR_QFN32_4X4 SD_MMC_D3_CONN C7611 1 2 5.6P_50V_D_NPO_0402
    EMC_NS@
    SD_MMC_D2_CONN C7612 1 2 5.6P_50V_D_NPO_0402
    EMC_NS@

    Part Number Vendor SD_MMC_CMD_CONN C7618 1


    EMC_NS@
    2 5.6P_50V_D_NPO_0402

    SD_MMC_CLK_CONN C7617 1 2 5.6P_50V_D_NPO_0402


    SA000077K00 RTS5232S-GR REALTEK SD_MMC_D1_CONN
    EMC_NS@
    C7616 1 2 5.6P_50V_D_NPO_0402
    EMC_NS@

    A
    SA00009JG00 GL9750-OIYL3 GENESYS A
    EMC, close to U7601
    U7601 U7601

    Security Classification LC Future Center Secret Data Title


    Vinafix.com RTS5232S-GR GL9750-OIYL3 Issued Date 2019/01/12 Deciphered Date 2019/04/12 MEDIA CARD CONTROLLER
    SA000077K00 SA00009JG00
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    M@ S@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 76 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC3_MC

    40 mils VCC3_MC

    D D
    1 1
    C7701 C7702
    0.1UC_10VC_KC_X7RC_0402 10U_6.3V_M_X5R_0603
    2 2 Mode Detect
    Normal short
    Card Insert open

    Close to JREAD1 @ JREAD1

    SD_MMC_D2_CONN 1 GND1
    <76> SD_MMC_D2_CONN DAT2 GND1
    SD_MMC_D3_CONN 2 GND2
    <76> SD_MMC_D3_CONN CD/DAT3 GND2
    SD_MMC_CMD_CONN 3 GND3
    <76> SD_MMC_CMD_CONN CMD GND3
    4 GND4
    VDD GND4
    SD_MMC_CLK_CONN 5 GND5
    <76> SD_MMC_CLK_CONN CLK GND5
    6 GND6
    VSS GND6
    SD_MMC_D0_CONN 7 GND7
    <76> SD_MMC_D0_CONN DAT0 GND7
    SD_MMC_D1_CONN 8 GND8
    <76> SD_MMC_D1_CONN DAT1 GND8
    SD_MMC_CD_CONN 9
    <76> SD_MMC_CD_CONN DSW2
    10
    C DSW1 C

    JAE_ST11S008V4HR2000

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 MEDIA CARD CONTROLLER
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 77 of 125
    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    VCC3B_CODEC VCC5B_CODEC VCC3B VCC3B_CODEC VCC5B VCC5BA

    R7804
    R7807 TABLE MIC HW ENABLE/DISABLE
    1 2 0_0402_SP 1 2

    VCC5B VCC5B_CODEC
    1 1 1 1 1 1 0_0402_SP ENABLE DISABLE
    R7805
    C7802 C7803 C7804 C7805 C7806 C7808 1 1 1
    0.1U_6.3V_K_X5R_0201 2.2U_6.3V_K_X5R_0402 0.1U_6.3V_K_X5R_0201 10U_6.3V_M_X5R_0402 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 1 2 0_0402_SP
    2 2 2 2 2 2 @C7824 C7825 C7826
    0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 4.7U_6.3V_M_X5R_0402
    R0805 ASM NO ASM
    VCC1R8_SUS VCC1R8_SUS_CODEC 2 2 2
    @C7827
    R7806
    Near U7801 pin3 Near U7801 pin18 Near U7801 pin41 Near U7801 pin46 1 2 0_0402_SP 1 2

    D D
    R7804,R7805,R7806,R7807 0.01U_6.3V_K_X7R_0201
    EVT FVT SIT SVT
    VCC1R8_SUS_CODEC Resistor V V AGND LOGIC
    R-short

    1 1 VCC3B_CODEC VCC5B_CODEC VCC5BA VCC1R8_SUS_CODEC


    R7808,R7809
    C7809 C7810 EVT FVT SIT SVT
    0.1U_6.3V_K_X5R_0201 4.7U_6.3V_M_X5R_0402 Resistor V V
    2 2 R-short

    46

    41

    40
    18

    20
    3
    U7801
    Near U7801 pin20

    PVDD2

    PVDD1

    AVDD1

    CPVDD/AVDD2
    DVDD

    DVDD-IO
    AGND 2 -SPK_MUTE_R R7808 1 2 0_0201_SP -SPK_MUTE
    PDB -SPK_MUTE <85>
    14 HDA_BCLK_R R7809 1 2 0_0201_SP HDA_BCLK
    <84> HP_L_JACK R7801 1 2 1/20W_47_5%_0201 27 BCLK HDA_BCLK <9>
    HP_L_JACK HP_L_JACK_R
    HPOUT-L
    15 HDA_SYNC
    <84> HP_R_JACK R7802 1 2 1/20W_47_5%_0201 26 SYNC HDA_SYNC <9>
    HP_R_JACK HP_R_JACK_R
    HPOUT-R
    47
    <81> MIC2_VREFO_L JD2
    MIC2_VREFO_L 28
    MIC2-VREFO-L
    48 SENSE_A
    <81> MIC2_VREFO_R 29 JD1 SENSE_A <80>
    MIC2_VREFO_R
    MIC2-VREFO-R
    1 DMIC_DATA series resistor need to close device
    SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
    4 DMIC_DATA0
    <81> MIC_RING2_CODEC 30 GPIO0/DMIC-DATA12 DMIC_DATA0 <52>
    MIC_RING2_CODEC
    MIC2-L/RING2
    5 DMIC_CLK0_R 1 2 DMIC_CLK0
    <81> MIC_SLEEVE_CODEC 31 GPIO1/DMIC-CLK
    EMC@ R7810 1/16W_43_5%_0402 DMIC_CLK0 <52>
    MIC_SLEEVE_CODEC
    C MIC2-R/SLEEVE C
    6
    <83> BEEP_MIX_ATT I2C-DATA
    BEEP_MIX_ATT C7811 2 1 0.1U_6.3V_K_X5R_0201 BEEP_MIX_ATT_C 34 1
    PCBEEP
    7 1 1
    I2C-CLK @C7828
    47P_25V_J_NPO_0201 C7829 C7830
    R7803 2
    8 33P_25V_J_NPO_0201 33P_25V_J_NPO_0201
    NC1 2 2
    2 1 33
    VCC5BA 5VSTB
    9
    NC2
    1/20W_10K_5%_0201 35
    LINE2-R
    36
    LINE2-L
    Analog NC3
    10

    11
    Plane NC4

    NC5
    12

    23 45 SP_OUTR+
    C7812 CBP CBP SPK-OUT-R+ SP_OUTR+ <82>
    1 2 CBN 24 44 SP_OUTR-
    CBN SPK-OUT-R- SP_OUTR- <82>
    2 2
    43 SP_OUTL-
    @ C7819 @ 1U_25V_K_X5R_0402 SPK-OUT-L- SP_OUTL- <82>
    C7818
    33P_25V_J_NPO_0201 33P_25V_J_NPO_0201 42 SP_OUTL+
    1 1 C7813 1 22.2U_6.3V_K_X5R_0402 MIC2_CAP
    32 SPK-OUT-L+ SP_OUTL+ <82>
    AGND MIC2-CAP
    13
    DC DET/EAPD
    C7814 1 22.2U_6.3V_K_X5R_0402 38
    VREF
    AGND VREF R7811
    C7815 1 19
    22.2U_6.3V_K_X5R_0402 LDO3_CAP 16 HDA_SDIN0_R 1 2 1/20W_33_5%_0201 HDA_SDIN0
    LDO3-CAP SDATA-IN HDA_SDIN0 <9>
    C7816 1 21
    22.2U_6.3V_K_X5R_0402 LDO2_CAP 17 HDA_SDO
    AGND LDO2-CAP SDATA-OUT HDA_SDO <9>
    C7817 1 39
    22.2U_6.3V_K_X5R_0402 LDO1_CAP
    AGND LDO1-CAP
    25 CPVEE
    CPVEE

    Thermal Pad
    B AGND AGND B

    1000P_25V_K_X7R_0201
    1000P_25V_K_X7R_0201
    1000P_25V_K_X7R_0201
    1000P_25V_K_X7R_0201
    C7820

    C7821

    AVSS1

    AVSS2
    1 2 2 2 2 2
    @ C7832
    @ @ C7831 47P_25V_J_NPO_0201
    2 2 ALC3287-CG_MQFN48_6X6 1U_25V_K_X5R_0402

    49
    37

    22
    2 1 1 1 1 1

    C7836
    C7835
    C7834
    C7833
    AGND
    1 1
    33P_25V_J_NPO_0201

    33P_25V_J_NPO_0201

    AGND AGND
    PLACE NEAR CODEC
    EMC@ C7847 1 2 0.1U_6.3V_K_X5R_0201
    AGND
    EMC@ C7846 1 2 0.1U_6.3V_K_X5R_0201

    EMC@ C7845 1 2 0.1U_6.3V_K_X5R_0201


    PLACE UNDER ALC3287
    EMC@ C7844 1 2 0.1U_6.3V_K_X5R_0201

    EMC_NS@ C7822 1 2 0.01U_6.3V_K_X7R_0201 EMC@ C7843 1 2 0.1U_6.3V_K_X5R_0201


    EMC@ C7837 0.1UC_25VC_KC_X5RC_0402
    1 2 EMC@ C7842 1 2 0.1U_6.3V_K_X5R_0201
    EMC@ C7838 0.1UC_25VC_KC_X5RC_0402
    1 2 EMC@ C7841 1 2 0.1U_6.3V_K_X5R_0201
    EMC@ C7839 0.1UC_25VC_KC_X5RC_0402
    A 1 2 EMC@ C7840 1 2 0.1U_6.3V_K_X5R_0201 A
    AGND

    AGND AGND

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 AUDIO ALC3287
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 78 of 125
    5 4 3 2 1

    Vinafix.com
    C
    5 4 3 2 1

    D D

    NEAR AUDIO CONN

    HP_L_JACK_L 1 2
    <84> HP_L_JACK_L
    EMC@ FL7901
    MMZ1005Y152CT_2P

    HP_R_JACK_L 1 2
    <84> HP_R_JACK_L
    EMC@ FL7902
    MMZ1005Y152CT_2P

    2 2

    2
    @ R7901 @ R7902 C7901 C7902
    1/20W_220_5%_0201
    1/20W_220_5%_0201 1000P_25V_K_X7R_0201
    1000P_25V_K_X7R_0201
    1 1

    1
    AGND AGND

    C C

    WIDE AND SHORT PATTERN

    VCC3B
    EMC@ C7903

    1 2
    WIDE PATTERN
    2

    1U_6.3V_K_X5R_0402
    R7903
    1/20W_10K_5%_0201
    AGND
    1

    @ JHP1

    3 MIC_RING2
    G/M MIC_RING2 <81>
    1 MIC_SLEEVE
    L
    HP_L_JACK_CONN MIC_SLEEVE <81>
    5 7901 HP_R_JACK_CONN
    5
    6 HP_JACK_IN
    6 HP_JACK_IN <80,85>
    2
    R
    4
    M/G
    7
    MS
    2

    B B
    ALLTO_C18207-10735-L R7904
    1/20W_100K_5%_0201
    1

    1
    1

    1
    1

    D7901 EMC@ D7902 EMC@ D7903 EMC@ D7904 EMC@


    1
    1

    1
    1

    AOZ8231ADI-03_DFN1P0X0P6-2 AOZ8231ADI-03_DFN1P0X0P6-2 AOZ8231ADI-03_DFN1P0X0P6-2 AOZ8231ADI-03_DFN1P0X0P6-2


    AGND
    2
    2

    2
    2
    2
    2

    2
    2

    Pin 4 and 5 : Normal Open

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 AUDIO CONNECTOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 79 of 125
    5 4 3 2 1
    5 4 3 2 1

    EMC@
    1 2
    VCC3B
    R8002
    1/20W_0_5%_0201

    AGND
    D D

    1
    R8004
    1/20W_100K_5%_0201

    2
    SENSE_A_R R8003 1 2 1/20W_200K_1%_0201 SENSE_A
    SENSE_A <78>

    3
    Q8001
    R8001
    1/20W_22K_5%_0201
    HP_JACK_IN 1 2 HP_JACK_IN_R 1 LSK3541G1ET2L_VMT3
    <79,85> HP_JACK_IN

    2
    C C

    1
    @ C8001
    2.2U_6.3V_K_X5R_0402
    2

    AGND AGND

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 AUDIO JACK SENSE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 80 of 125
    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    MIC2_VREFO_R
    <78> MIC2_VREFO_R

    1
    R8101
    1/20W_2.2K_5%_0201
    D R8103,8104,8105,8107 D
    EVT FVT SIT SVT

    2
    Resistor V
    R-short

    MIC2_VREFO_L
    <78> MIC2_VREFO_L
    R8103
    MIC2_VREFO_R_R 1 2

    0_0201_SP

    1
    R8102
    1/20W_2.2K_5%_0201

    2
    R8104
    MIC2_VREFO_L_R 1 2

    0_0201_SP

    R8105
    MIC_SLEEVE 1 2 MIC_SLEEVE_CODEC
    <79> MIC_SLEEVE MIC_SLEEVE_CODEC <78>

    C
    0_0402_SP C

    1
    1
    @ R8106
    1/20W_0_5%_0201 C8103
    1000P_25V_K_X7R_0201
    2

    2
    AGND AGND

    R8107
    MIC_RING2 1 2 MIC_RING2_CODEC
    <79> MIC_RING2 MIC_RING2_CODEC <78>

    0_0402_SP

    1
    1
    @ R8108
    1/20W_0_5%_0201 C8104
    1000P_25V_K_X7R_0201
    2

    2
    AGND AGND

    B B

    NEAR EXT MIC CONN EMC@


    1 2

    R8109
    1/20W_0_5%_0201

    AGND

    1 2

    EMC@ C8105
    0.01U_6.3V_K_X7R_0201

    AGND

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 AUDIO EXT MIC I/F
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size CDocument Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 81 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    JSPK1 @
    SP_OUTR+ EMC@ FL82011 2 BLM18PG221SN1D_2P SP_OUTR+_L 1
    <78> SP_OUTR+ 1
    SP_OUTR- EMC@ FL82021 2 BLM18PG221SN1D_2P SP_OUTR-_L 2
    <78> SP_OUTR- 2
    SP_OUTL+ EMC@ FL82031 2 BLM18PG221SN1D_2P SP_OUTL+_L 3
    <78> SP_OUTL+ 3
    SP_OUTL- EMC@ FL82041 2 BLM18PG221SN1D_2P SP_OUTL-_L 4
    <78> SP_OUTL- 4
    C 5 C
    GND1
    6
    GND2

    HIGHS_WS33040-S0351-HF

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 AUDIO SPEAKER
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 82 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    EC_SPKR 2 1
    <85> EC_SPKR
    D8301
    RB521CM-30T2R_VMN2M-2

    PCH_SPKR 2 1 8301
    <9> PCH_SPKR
    D8302
    RB521CM-30T2R_VMN2M-2

    RFID_BEEP 2 1
    <89> RFID_BEEP
    RFID@
    D8303
    RB521CM-30T2R_VMN2M-2

    2
    R8301
    1/20W_10K_5%_0201

    1
    C C

    1
    R8302
    1/20W_10K_5%_0201

    2
    BEEP_MIX_ATT
    BEEP_MIX_ATT <78>

    3
    Q8301

    -BEEP_ENABLE 1 LSK3541G1ET2L_VMT3
    <85> -BEEP_ENABLE

    2
    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 AUDIO BEEP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 83 of 125
    5 4 3 2 1
    5 4 3 2 1

    D TABLE: D

    Mode Audio UART


    VCC3M VCC3M VCC5M
    UART_EN L H

    1
    R8405 @ R8406 @
    1/20W_10K_5%_0201 1/20W_10K_5%_0201

    2
    UART_EN
    <87> UART_EN
    U8401 @
    HP_R_JACK_L @ R8403 1 2 1/20W_0_5%_0201 HP_R_JACK_SW 9 1 UART_RX
    <79> HP_R_JACK_L VBUS D- UART_RX <85>
    7 10 UART_TX
    D+/R D+ UART_TX <85>
    HP_L_JACK_L @ R8404 1 2 1/20W_0_5%_0201 HP_L_JACK_SW 6 5
    <79> HP_L_JACK_L D-/L VAUDIO
    8 2 HP_R_JACK_R_SW@ R8407 1 2 1/20W_0_5%_0201 HP_R_JACK
    ASEL R HP_R_JACK <78>
    4 3 HP_L_JACK_R_SW@ R8408 1 2 1/20W_0_5%_0201 HP_L_JACK
    GND L HP_L_JACK <78>
    TS5USBA224RSWR_UQFN10_1P8X1P4
    SA00007RR00

    R8403,R8404,R8405,R8406,R8407,R8408
    EVT FVT SIT SVT
    Resistor V V V
    C unmount V C

    HP_R_JACK_L R8409 2 1 0_0201_SP HP_R_JACK_L_RR R8401 2 1 0_0201_SP HP_R_JACK


    R8401,R8402,R8409,R8410
    HP_L_JACK_L R8410 2 1 0_0201_SP HP_L_JACK_L_RR R8402 2 1 0_0201_SP HP_L_JACK EVT FVT SIT SVT
    Resistor V V V
    R-short V

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 AUDIO DEBUG
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 84 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC3M VCC3B VCC3M

    2 1/20W_10K_5%_0201

    2 1/20W_10K_5%_0201
    2 1/20W_10K_5%_0201

    2 1/20W_10K_5%_0201
    2 1/20W_10K_5%_0201
    2 1/20W_10K_5%_0201

    2 1/20W_10K_5%_0201

    2 1/20W_10K_5%_0201
    2 1/20W_4.7K_5%_0201

    2 1/20W_4.7K_5%_0201
    D D

    VCC3M VCC3SW

    1/20W_100K_5%_0201

    1/20W_100K_5%_0201

    2 1/20W_20K_5%_0201
    @ R8527 1

    @ R8530 1
    @ R8529 1
    @ R8528 1
    R8503 1

    R8505 1
    R8502 1
    R8501 1

    R8506 1
    R8504 1

    2
    UEC1A
    DRV[17:0] <88>
    -EC_RESET C2 L9 DRV0
    <94> -EC_RESET RESETI# GPIO040/KSO0
    C10 DRV1

    R8509 1
    R8507 1

    R8508 1
    GPIO045/KSO1/GANG_MODE
    D9 DRV2
    GPIO046/KSO2
    SUSCLK_32K A9 B10 DRV3
    <12,66> SUSCLK_32K GPIO165/32KHZ_IN GPIO047/KSO3
    J11 DRV4
    GPIO107/KSO4
    -KBRC F2 H9 DRV5
    <7> -KBRC GPIO060/KBRST/GANG_ERROR GPIO112/KSO5
    H8 DRV6
    GPIO113/KSO6/GANG_DATA1
    J10 DRV7
    GPIO120/KSO7
    -EC_SCI G3 A11 DRV8
    <8> -EC_SCI GPIO100/nEC_SCI GPIO121/KSO8
    E8 DRV9
    GPIO122/KSO9
    -EC_WAKE D2 A10 DRV10
    <8> -EC_WAKE GPIO011/nSMI GPIO123/KSO10
    H12 DRV11
    GPIO124/KSO11
    -SUS_STAT K4 J8 DRV12
    <7,93> -SUS_STAT GPIO061/LPCPD#/GANG_START GPIO125/KSO12

    Keyboard/TrackPoint
    TP8501 1 Test_Point_40MIL C9 DRV13
    GPIO126/KSO13

    HOST I/F
    -CLKRUN L1 L11 DRV14
    <7,93> -CLKRUN CLKRUN# GPIO132/KSO14
    L8 DRV15
    GPIO151/KSO15
    IRQSER M5
    <7,93> IRQSER SER_IRQ
    M8 DRV16
    KSO16/GPIO152
    -PLTRST_FAR K3 C11 DRV17
    <13,37,64,67,73,93,94> -PLTRST_FAR LRESET# KSO17/GPIO175
    SENSE[7:0] <88>
    -LPC_FRAME M1
    <7,93> -LPC_FRAME LFRAME#
    H7 SENSE0
    C GPIO017/KSI0 C
    LPCCLK_EC_24M L2 L4 SENSE1
    <7> LPCCLK_EC_24M PCI_CLK GPIO020/KSI1
    E3 SENSE2
    GPIO021/KSI2/GANG_FULL
    LPC_AD0 L3 K11 SENSE3
    LAD0 GPIO026/KSI3
    LPC_AD1 M2 K12 SENSE4
    LAD1 GPIO027/KSI4
    LPC_AD2 M3 J12 SENSE5
    LAD2 GPIO030/KSI5
    LPC_AD3 M4 M10 SENSE6
    LAD3 GPIO031/KSI6
    M9 SENSE7
    <7,93> LPC_AD[3:0] GPIO032/KSI7

    B2 -HOTKEY
    R8510 1 2 1/20W_1K_5%_0201 G1
    VCI_IN2#/GPIO161 -HOTKEY <88>
    M_TEMP M_TEMP_R
    <101> M_TEMP ADC0/GPIO200
    K6 KBD_BL_PWM
    PWM0/GPIO053 KBD_BL_PWM <88>

    Battery
    I2C_DATA_BT A5 A12 -KBD_BL_DTCT
    <101> I2C_DATA_BT GPIO003/SMB00_DATA GPIO036 -KBD_BL_DTCT <88>
    I2C_CLK_BT A6
    <101> I2C_CLK_BT GPIO004/SMB00_CLK
    J6 IPDCLK_R R8511 1 2 1/20W_33_5%_0201 IPDCLK
    PS2_CLK0A/GPIO114/NEC_SCI IPDCLK <89>
    M12 IPDDATA_R R8512 1 2 1/20W_33_5%_0201 IPDDATA
    R8513 1 2 1/20W_100_5%_0201 A7
    PS2_DAT0A/GPIO115/GANG_DATA0 IPDDATA <89>
    I2C_DATA_CHARGE SMB02_DATA
    <102> I2C_DATA_CHARGE GPIO154/SMB02_DATA/PS2_CLK1B
    I2C_CLK_CHARGE R8514 1 2 1/20W_100_5%_0201 SMB02_CLK C6 GPIO155/SMB02_CLK/PS2_DAT1B/GANG_DATA3 F9 TP4_RESET
    <102> I2C_CLK_CHARGE GPIO133 TP4_RESET <88>
    PMB_DATA_IMVP R8525 1 @ 2 1/20W_0_5%_0201 F8 PAD_DISABLE
    <108> PMB_DATA_IMVP R8526 1 @ 2 1/20W_0_5%_0201 GPIO134 PAD_DISABLE <89>
    PMB_CLK_IMVP
    <108> PMB_CLK_IMVP
    -LED_LOGO D8
    <52> -LED_LOGO LED0/GPIO156 LCD
    GPIO143/SMB04_DATA/GANG_BUSY
    B7 VGA_BLON
    VGA_BLON <3>
    -LED_PWR E7 E4 BACKLIGHT_ON
    <51> -LED_PWR LED1/GPIO157 GPIO144/SMB04_CLK/GANG_DATA5 BACKLIGHT_ON <51>

    -LED_MICMUTE D6
    <87,88> -LED_MICMUTE GPIO150/JTAG_TMS

    Wireless
    -LED_MUTE D7
    <87,88> -LED_MUTE GPIO147/JTAG_CLK
    H6 -WLAN_RF_KILL
    GPIO035 -WLAN_RF_KILL <66>

    LED
    -LED_FNLOCK A8
    <87,88> -LED_FNLOCK GPIO146/JTAG_TDO

    -LED_CAPSLOCK B8
    <87,88> -LED_CAPSLOCK GPIO145/JTAG_TDI

    B G4 EC_SPKR B
    R8515 1 2 0_0402_SP D12
    PWM2/GPIO055 EC_SPKR <83>
    LED_AC_CON

    Audio
    GPIO104/UART_TX
    K5 -BEEP_ENABLE
    R8516 1 2 0_0402_SP D10
    GPIO052 -BEEP_ENABLE <83>
    LED_AC_CHG
    GPIO105/UART_RX
    G9 -SPK_MUTE
    GPIO171 -SPK_MUTE <78>
    H5 HP_JACK_IN
    GPIO170 HP_JACK_IN <79,80>
    <84> UART_TX

    CDZCGT2RA6P8B_VMN2-2
    <84> UART_RX

    220P_25V_K_X7R_0201

    220P_25V_K_X7R_0201

    1/20W_100K_5%_0201

    1/20W_10K_5%_0201
    1/20W_100K_5%_0201
    MEC1663-WC_WFBGA144

    A1 Pin : ORANGE
    A2 Pin : WHITE 1
    EMC@
    C8503
    0.1U_6.3V_K_X5R_0201
    LED1 2
    LED_AC_CHG R8517 1 2 1/20W_120_5%_0201 LED_AC_CHG_R 1 + - 4
    ORG

    2
    1

    2
    2 2
    LED_AC_CON 1 2 LED_AC_CON_R 2 + - 3 UEC1
    R8518 1/20W_150_5%_0201 WHI
    19-223-S2T1D-C01-2T-WSN_ORG_WHI

    2
    1 1

    EMC_NS@

    R8521 1

    R8524 1
    R8522 1
    1 1

    C8501

    C8502
    D8501
    EMC_NS@ EMC_NS@
    C8505 C8504
    0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201
    2 2

    A A

    Security Classification LC Future Center Secret Data Title


    MEC1663(1/3)
    Vinafix.com Issued Date 2019/01/12 Deciphered Date 2019/04/12
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 85 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC3M VCC3M VCC3M

    1/20W_100K_5%_0201

    1/20W_2.2K_5%_0201
    1/20W_2.2K_5%_0201
    1/20W_10K_5%_0201

    1/20W_100K_5%_0201
    1/20W_100K_5%_0201

    1/20W_10K_5%_0201
    D D

    2
    2
    2
    2

    R8605 1

    R8607 1
    R8606 1
    R8603 1
    R8601 1

    R8602 1

    R8604 1
    UEC1B

    -PWRSW B12 B6 I2C_DATA_GSENSE_R R8608 1 2 1/20W_22_5%_0201 I2C_DATA_GSENSE


    <94> -PWRSW GPIO127 SMB01_DATA/GPIO005 I2C_DATA_GSENSE <91>

    Sensor
    -PWRSW_EC E1 D3 I2C_CLK_GSENSE_R R8609 1 2 1/20W_22_5%_0201 I2C_CLK_GSENSE
    <13,64> -PWRSW_EC GPIO106 SMB01_CLK/GPIO006 I2C_CLK_GSENSE <91>
    A3 GSENSE_INT
    D8601 1 2 RB521CM-30T2R_VMN2M-2 BGPO3/GPIO172 GSENSE_INT <91>
    -EXTPWR -EXTPWR_R B1
    <94,102> -EXTPWR GPIO162/VCI_IN1#
    -SHUTDOWN
    -SHUTDOWN <41,95>
    AC_PRESENT B11
    <13> AC_PRESENT GPIO034
    H2 FAN_ID
    ADC3/GPIO203 FAN_ID <90>

    Power Management
    -PCH_SLP_SUS H1
    <13,95> -PCH_SLP_SUS GPIO201/ADC1

    1
    <107> SUS_ON1 SUS_ON1 A4 M6 FAN_ON VCC3B
    BGPO1/GPIO101 PWM1/GPIO054 FAN_ON <90>

    FAN
    Q8601
    SUS_ON2 B3 BPWRG 2 DTC015EMT2L_VMT3
    <113> SUS_ON2 BGPO2/GPIO102
    B9 FAN_FRQ
    FAN_TACH0/GPIO050 FAN_FRQ <90>
    -PCH_SLP_S3 H10
    <13,17,55,94,95> -PCH_SLP_S3

    3
    GPIO110
    VCCST
    -PCH_SLP_S4 H11 8601
    <13,17,94,112> -PCH_SLP_S4

    2
    GPIO111/GANG_DATA2
    E9
    GPIO044/VREF_VTT
    BPWRG D1 R8611
    <13,89,93,95> BPWRG VCC_PWRGD

    0.1U_6.3V_K_X5R_0201
    E10 PECI_R R8610 1 2 1/20W_43_5%_0201 PECI 1/20W_4.7K_5%_0201
    GPIO042/PECI_DAT PECI <6>

    1/20W_1K_5%_0201
    2

    C8601
    1

    R8613
    -LID_CLOSE B5
    <51,52,89> -LID_CLOSE VCI_IN3#/GPIO000
    D5 R8612 1 2 1/20W_100_5%_0201
    SMB03_DATA EC_SDA2
    SMB03_DATA/GPIO007/PS2_CLK0B EC_SDA2 <7> 1
    -PCH_SLP_WLAN D11 D4 SMB03_CLK R8614 1 2 1/20W_100_5%_0201 EC_SCL2
    <13> -PCH_SLP_WLAN EC_SCL2 <7>

    1
    GPIO043 SMB03_CLK/GPIO010/PS2_DAT0B/GANG_DATA4

    R8615
    -RJ45_LINKUP E2
    <73,74> -RJ45_LINKUP GPIO033
    F10 1 2
    C
    -THRM_EC -THRM C
    GPIO041/SYS_SHDN#

    Thermal
    PROCHOT_EC E6
    GPIO153/LED2 0_0201_SP
    G11 DP1_DN4
    DP1_DN4

    2200P_25V_K_X7R_0201

    2SCR523MT2L_VMT3

    1
    22P_25V_J_NPO_0201
    G12

    22P_25V_J_NPO_0201
    DN1_DP4

    E
    3
    DN1_DP4

    C
    2 2 REMOTE 2
    DIODE 4
    B

    C8603
    C8602

    C Q8602

    C8604
    AOU_SEL1 K8 F11 DP2_DN5 2 Q8603
    <70> AOU_SEL1 GPIO015 DP2_DN5 2 B 2SCR523MT2L_VMT3
    AOU_SEL2 H4 1 1 1
    <70> AOU_SEL2 GPIO016/GANG_STROBE

    USB/AOU
    F12 DN2_DP5 REMOTE
    DN2_DP5

    E
    3
    -AOU_IFLG L12 DIODE 1

    1
    <70> -AOU_IFLG GPIO025/UART_CLK
    E12 DP3_DN6
    DP3_DN6
    USB_ON1 A2 PLACE NEAR MEC1663 PLACE NEAR DIODE 4 PLACE NEAR DIODE 1
    <69> USB_ON1 BGPO4/GPIO173
    USB_ON2 A1 E11 DN3_DP6
    <70> USB_ON2 BGPO5/GPIO174 DN3_DP6

    2 1/20W_10K_5%_0201
    1/20W_100K_5%_0201
    1/20W_100K_5%_0201

    1/20W_100K_5%_0201

    2200P_25V_K_X7R_0201

    2SCR523MT2L_VMT3

    1
    22P_25V_J_NPO_0201
    22P_25V_J_NPO_0201

    E
    3
    Check list Suggest

    C
    R8615 2 2 REMOTE 2
    EVT FVT SIT SVT DIODE 5
    B

    C Q8604
    C8605

    C8507
    C8506
    1 Resistor V 2 Q8605
    EMC_NS@ R-short 2 B 2SCR523MT2L_VMT3
    MEC1663-WC_WFBGA144 C8612 1 1 1
    0.1U_6.3V_K_X5R_0201 REMOTE
    2

    E
    3
    DIODE 2

    1
    2
    2

    PLACE NEAR MEC1663 PLACE NEAR DIODE 5 PLACE NEAR DIODE 2


    R8619 1
    R8621 1
    R8620 1

    R8616 1

    2200P_25V_K_X7R_0201

    2SCR523MT2L_VMT3

    1
    22P_25V_J_NPO_0201
    22P_25V_J_NPO_0201

    E
    3

    C
    2 2 REMOTE 2 REMOTE
    @ DIODE 6 DIODE 3
    @ B

    C Q8606
    @

    C8610
    C8608

    C8609
    2 Q8607
    2 B 2SCR523MT2L_VMT3
    1 1 1

    E
    3
    1
    PLACE NEAR MEC1663 PLACE NEAR DIODE 6 PLACE NEAR DIODE 3
    B R8617 B

    PROCHOT_EC_Q 1 2
    -PROCHOT <6,87,102,108>
    1/20W_75_5%_0201
    3

    Q8608
    LSK3541G1ET2L_VMT3
    place near Q16
    PROCHOT_EC 1 1
    2

    C8611
    2

    47P_25V_J_NPO_0201
    R8618 2
    1/20W_100K_5%_0201 TABLE
    1

    Sensor Device Placed on

    DIODE1 Battery Charger BOTTOM


    DIODE2 WLAN/WWAN BOTTOM
    DIODE3 SSD BOTTOM
    DIODE4 CPU FIN BOTTOM
    DIODE5 GPU DC/DC BOTTOM
    DIODE6 DDR4 BOTTOM

    A A

    Vinafix.com Security Classification LC Future Center Secret Data Title


    Issued Date 2019/01/12 Deciphered Date 2019/04/12 MEC1663(2/3)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 86 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC3M_EC

    VCC3M VCC3M_EC
    R8702
    VCC3M
    1 2

    VCC3M_ADC

    0.01U_6.3V_K_X7R_0201
    1 2
    0_0603_SP

    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201
    R8701
    1/16W_10_5%_0402
    2
    C8702
    D 10U_6.3V_M_X5R_0402 D
    1

    VCC3SW 2 2 2
    VCC3SW VCC3M

    R8703,R8702 1 1 1

    C8704
    C8703

    C8705
    EVT FVT SIT SVT
    Resistor V
    R-short VCC3M VCC3_SUS

    2
    R8703
    0_0402_SP

    Check list Suggest


    1/20W_10K_5%_0201
    1/20W_10K_5%_0201

    1/20W_10K_5%_0201
    1/20W_10K_5%_0201
    1/20W_10K_5%_0201
    1/20W_100K_5%_0201

    1/20W_10K_5%_0201
    1/20W_10K_5%_0201
    1
    1/20W_100K_5%_0201

    1/20W_4.7K_5%_0201

    1/20W_4.7K_5%_0201
    1/20W_10K_5%_0201
    VR_CAP

    VCC3SW_VBAT
    VCC3M_EC C8701
    4.7U_6.3V_M_X5R_0402
    1

    2
    2

    2
    2
    2
    2

    2
    2
    1
    1

    1
    1

    G10

    R8711 1
    R8705 1

    @ R8738 1
    R8709 1
    R8708 1
    R8710 1

    R8737 1
    @ R8736 1
    C3

    C8

    H3
    K7

    F1
    J3
    UEC1C

    R8712 2
    R8704 2

    R8713 2
    @ R8722 2

    VR_CAP
    VBAT

    VTR_REG
    VTR

    VTR_FLASH

    AVTR_ADC
    VREF_ADC
    SWG@
    SWG@

    SWG@
    @

    ECSPI_CLK J5 K9 I2C_DATA_PD
    <94> ECSPI_CLK GPIO230/SPI_CLK GPIO012/SMB07_DATA I2C_DATA_PD <59,61,68>

    USB PD
    ECSPI_MOSI L5 J9 I2C_CLK_PD
    <94> ECSPI_MOSI GPIO231/SPI_MOSI GPIO013/SMB07_CLK I2C_CLK_PD <59,61,68>

    SPI
    ECSPI_MISO L6
    <94> ECSPI_MISO GPIO233/SPI_MISO
    K2 -PD_I2C_INT
    -ECSPI_SS ADC12/GPIO214 -PD_I2C_INT <59>
    C M7 C
    <94> -ECSPI_SS GPIO002/SPI_CS#/20MHz_OUT
    J2 -TBT_RESET_EC
    ADC13/GPIO215 -TBT_RESET_EC <55>

    GPU Only
    L10 F4 -SSD_DTCT
    <41> I2C_DATA_VIDEO GPIO130/SMB10_DATA GPIO001/PWM4 -SSD_DTCT <64>

    M11 C12 IMVP_PMBUS_EN


    <41> I2C_CLK_VIDEO GPIO131/SMB10_CLK GPIO051/FAN_TACH1 IMVP_PMBUS_EN <108>

    LCD_SELF_TEST_ON J1 J7 -CHG_PROCHOT
    <3,51> LCD_SELF_TEST_ON ADC10/GPIO212 GPIO014/PWM6 -CHG_PROCHOT <102>
    GPU Only
    K1 G5
    <41> -VIDEO_POWER_LIMIT ADC11/GPIO213 GPIO135/PWM11 -TBT_USB2_BUS_EN <62>

    L7 K10
    <41> -VIDEO_THERM_ALERT GPIO056 GPIO140/PWM13/GANG_DATA7 -USBC_USB2_BUS_EN <63>
    VCC3M
    GPU Only VIDEO_ID C5 C7 T_contrl
    GPIO234/VCI_IN4# GPIO141/SMB05_DATA/PWM14
    2

    G8 E5
    @ R8714 <88> -LED_NUMBER GPIO220/VIN GPIO142/SMB05_CLK/PWM15/GANG_DATA6 UART_EN <84>
    1/20W_10K_5%_0201
    TOP_SWAP_EN G2 C1 CAM_FW_WR_EN
    <9> TOP_SWAP_EN ADC2/GPIO202 VCI_IN0#/GPIO163 CAM_FW_WR_EN <52>
    1

    C4 EC_PWRREQ
    VCI_OUT EC_PWRREQ <94>

    -EC_JTAG_RST F5 B4 -BATLOW
    JTAG_RST# BGPO0 -BATLOW <13,55>

    1/20W_100K_5%_0201

    2 1/20W_100K_5%_0201

    2 1/20W_100K_5%_0201
    2 1/20W_10K_5%_0201
    VSS_ADC
    VSS_RO
    1/20W_10K_5%_0201
    1/20W_10K_5%_0201

    1/20W_10K_5%_0201
    0.1U_6.3V_K_X5R_0201

    1/20W_10K_5%_0201

    100P_25V_J_NPO_0201
    1/20W_10K_5%_0201

    1/20W_100K_5%_0201
    1/20W_10K_5%_0201
    2

    BGND
    VSS0
    VSS1
    VSS2
    2
    R8715
    C8706

    1/20W_10K_5%_0201
    MEC1663-WC_WFBGA144

    F7
    G6
    G7
    F3

    J4

    F6
    1
    1

    0.1U_6.3V_K_X5R_0201
    1

    EMC_HC@ C8708
    B B
    2
    2
    2
    2
    2

    2
    2
    2

    R8739 1

    @ R8728 1

    R8729 1
    @ R8727 1
    @

    1
    R8723 1
    R8720 1
    R8719 1
    R8717 1
    R8716 1

    R8721 1
    R8718 1

    C8707

    @
    UMA@
    UMA@
    UMA@

    UMA@
    UMA@

    JTAG Debug Port

    VCC3M
    Enable Disable VCCSTG -CHG_PROCHOT
    JTAG1
    -LED_MICMUTE 1
    <85,88> -LED_MICMUTE 2 1
    -LED_CAPSLOCK R544
    <85,88> -LED_CAPSLOCK 2 ASM NO_ASM

    1
    -LED_FNLOCK 3
    <85,88> -LED_FNLOCK 4 3
    @ Q8701
    -LED_MUTE R545
    <85,88> -LED_MUTE 5 4 NO_ASM ASM 2 DTC015TMT2L NPN VMT3
    R8734 1 @ 2 1/16W_49.9_1%_0402 5
    VCC3M_JTAG 6
    6 R10484 ASM NO_ASM
    7

    3
    GND1
    8
    GND2 R732 ASM NO_ASM
    HIGHS_WS32061-S0471-HF
    @
    R570 ASM NO_ASM -PROCHOT <6,86,102,108>

    R571 ASM NO_ASM


    A A
    R572 ASM NO_ASM

    Vinafix.com
    Security Classification LC Future Center Secret Data Title
    Issued Date 2019/01/12 Deciphered Date 2019/04/12 MEC1663(3/3)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 87 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC3M VCC3M

    2 1/20W_15K_5%_0201

    2 1/20W_15K_5%_0201

    2 1/20W_15K_5%_0201

    2 1/20W_15K_5%_0201
    2 1/20W_15K_5%_0201

    2 1/20W_15K_5%_0201

    2 1/20W_15K_5%_0201

    2 1/20W_15K_5%_0201

    2
    F8800
    0.5A_32V_ERBRD0R50X VCC5B VCC3B

    0.01U_6.3V_K_X7R_0201
    1A_32V_ERBRD1R00X

    1A_32V_ERBRD1R00X
    1 2 2

    2
    @ C8803
    @
    C8801 F8801 F8802 C8804
    0.1U_6.3V_K_X5R_0201 0.01U_6.3V_K_X7R_0201

    R8801 1

    R8807 1
    R8804 1

    R8805 1

    R8808 1
    R8803 1

    R8806 1
    R8802 1
    2 1 1

    D D

    1
    40 42
    40 GND2
    39 41
    -LED_NUMBER -LED_NUMBER_R 39 GND1
    R8816 1 2 1/20W_100_5%_0201 38
    <87> -LED_NUMBER 38
    DRV17 37
    37
    DRV16 36
    36
    TP4MIDDLE 35
    35
    TP4RIGHT 34
    34
    TP4LEFT 33 VCC_TP VCC_TP VCC_TP VCC5B
    33
    32
    -LED_CAPSLOCK -LED_CAPSLOCK_R 32
    R8809 1 2 1/20W_100_5%_0201 31
    <85,87> -LED_CAPSLOCK 31
    30
    30
    -HOTKEY 29
    <85> -HOTKEY 29
    -LED_MICMUTE R8810 1 2 1/20W_100_5%_0201 -LED_MICMUTE_R 28
    <85,87> -LED_MICMUTE 28
    -LED_MUTE 2 1/20W_100_5%_0201 -LED_MUTE_R

    1A_32V_ERBRD1R00X
    R8811 1 27
    <85,87> -LED_MUTE 27

    1/20W_10K_5%_0201
    -LED_FNLOCK R8812 1 2 1/20W_100_5%_0201 -LED_FNLOCK_R 26

    1/20W_4.7K_5%_0201
    1/20W_4.7K_5%_0201
    <85,87> -LED_FNLOCK

    2
    VCC3M_KBD 26
    25

    2
    25

    2
    2
    DRV11 24 F8803
    <85> DRV[17:0] 24

    R8814
    R8813
    DRV8 23

    R8815
    23
    DRV10 22
    22
    DRV12 21
    21
    DRV9 20

    1
    1
    1
    20
    DRV13 19
    19
    DRV15 18 JTP2
    18
    DRV5 17 12 14
    17 12 GND2
    DRV7 16 -KBD_BL_DTCT 11 13
    16 <85> -KBD_BL_DTCT KBD_BL_PWM 10 11 GND1
    DRV6 15
    15 <85> KBD_BL_PWM VCC5B_TP 9 10
    DRV3 14
    <85> SENSE[7:0] 14
    8 9
    DRV1 13 TP4CLK
    13 <89> TP4CLK 7 8
    SENSE5 12
    12 7
    DRV2 11 TP4LEFT 6
    11 6
    DRV4 10 TP4RIGHT 5
    10 5
    SENSE0 9 TP4MIDDLE 4
    9 4
    SENSE2 8 TP4_RESET 3
    8 <85> TP4_RESET 2 3
    DRV0 7 TP4DATA
    7 <89> TP4DATA VCC_TP 1 2
    SENSE1 6
    6 1
    SENSE4 5
    5
    DRV14 4 HIGHS_FC1AF121-1151H
    4
    SENSE6 3 @
    3

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    SENSE7 2
    2

    220P_25V_K_X7R_0201
    SENSE3 1
    1
    2 2 2

    C8805

    C8806

    C8807
    JKBL2
    2 HIGHS_FC5AF401-3181H
    EMC@ C8802 @
    0.1U_6.3V_K_X5R_0201 1 1 1

    1
    C C

    PLACE NEAR JKBL2

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 KEYBOARD/TRACK POINT
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    D 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 88 of 125
    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    VCC3B VCC3B VCC3B

    R8913

    1/20W_100K_5%_0201
    C8901 1 VCC3B VCC5B

    2
    R8901 R8902 F8903

    2
    2
    4700P_6.3V_K_X7R_0201

    0.5A_32V_ERBRD0R50X
    1/20W_4.7K_5%_0201
    1/20W_4.7K_5%_0201
    2 NFC@ NFC@

    2
    F8901 F8902
    D D

    0.5A_32V_ERBRD0R50X

    0.5A_32V_ERBRD0R50X
    1
    1

    1
    JNFC1
    VCC5B_NFC 1
    1
    VCC3B_NFCIO 2
    2
    JCP1 I2C0_DATA_NFC 3
    3
    12 14 I2C0_CLK_NFC 4
    12 GND2 4
    SMB_CLK_3B 11 13 5
    <35,93> SMB_CLK_3B 11 GND1
    NFC_INT 6 5
    10
    10 <10> NFC_INT 6
    TP4DATA 9 -NFC_DTCT NFC@ R8916 1 2 1/20W_0_5%_0201 JNFC_07 7
    <88> TP4DATA 9 <7> -NFC_DTCT 8 7
    TP4CLK 8 NFC_ON NFC@ R8917 1 2 1/20W_0_5%_0201 JNFC_08
    <88> TP4CLK 8 <10> NFC_ON 9 8
    SMB_DATA_3B 7 NFC_ACTIVE NFC@ R8903 1 2 1/20W_0_5%_0201 JNFC_09
    <35,93> SMB_DATA_3B 7 <9> NFC_ACTIVE 10 9
    VCC3B_PAD 6 JNFC_10
    6 10
    1 2 5 JNFC_11 11 13
    <51,52,86> -LID_CLOSE 5
    NFC_DLREQ 12 11 GND1
    14
    IPDCLK D8909 RB521CM-30T2R_VMN2M-2 4 NFC@ R8918 1 2 1/20W_0_5%_0201 JNFC_12
    <85> IPDCLK 4 <8> NFC_DLREQ 12 GND2
    IPDDATA 3
    <85> IPDDATA 3
    HIGHS_FC5AF121-2131H
    NFC_ACTIVE 2
    2
    PAD_DISABLE 1 @
    <85> PAD_DISABLE 1

    1/16W_100K_5%_0402
    1/16W_100K_5%_0402

    1/16W_100K_5%_0402
    2
    HIGHS_FC5AF121-2131H
    EMC@ C8906 @

    2
    1

    2
    NFC@ R8905
    NFC@ R8906

    NFC@ R8904
    1U_6.3V_M_X5R_0201
    1
    RFID Module Smart Card + NFC
    (RFID@) (SC@/NFC@)

    1
    2

    1
    JSC#01 VBUS_5V VBUS_5V
    JSC#02 USB_D- USB_D-
    C VCC3B JSC#03 USB_D+ USB_D+ C
    Health care-FPR JSC#04
    JSC#05
    GND
    NC
    -SC_DTCT
    NC
    JSC#06 NC GND
    F8905 RFID@ R8919 1 2 1/20W_0_5%_0201 JNFC_07
    <83> RFID_BEEP
    2

    0.5A_32V_ERBRD0R50X RFID@ R8920 1 2 1/20W_0_5%_0201 JNFC_08 JNFC1#01 NC VBUS_5V_NFC


    <8> -RFID_LOW_POWER
    RFID@ R8921 1 2 1/20W_0_5%_0201 JNFC_09 JNFC1#02 NC VBUS_3V_NFC
    <8> -RFID_CARD_READ
    RFID@ R8922 1 2 1/20W_0_5%_0201 JNFC_10 JNFC1#03 NC I2C0_DATA_NFC
    <8> -RFID_COIL_ACTIVE RFID@ R8923 1 2 1/20W_0_5%_0201 JNFC_11 JNFC1#04 NC I2C0_CLK_NFC
    RFID@ R8924 1 2 1/20W_0_5%_0201 JNFC_12 JNFC1#05 NC GND
    JNFC1#06 NC NFC_INT
    1

    JNFC1#07 BEEP -NFC_DTCT


    JNFC1#08 LOW_POWER NFC_ON
    JNFC1#09 CARD_READ NFC_ACTIVE
    JFPR1
    JNFC1#10 COIL_ACTIVE NC
    1 JNFC1#11 GND NC
    1
    2 JNFC1#12 GND NFC_DLREQ
    2
    3
    3
    4
    4
    5
    5
    USBP9+_CONN 6
    6
    USBP9-_CONN 7
    7
    FUSEVCC3FP 8
    8
    9
    GND1
    10 VCC3B
    GND2

    HIGHS_FC5AF081-2121H
    D8903 D8904 @
    1

    EMC@ EMC@ 2
    C8902
    PESD5V0H1BSF_SOD962-2

    PESD5V0H1BSF_SOD962-2
    1

    2.2U_6.3V_K_X5R_0402
    1

    2
    VCC5M VCC3_SUS
    R8907 R8908
    1/20W_2.2K_5%_0201 1/20W_2.2K_5%_0201
    2

    B B
    2

    1
    2

    U8901
    I2C0_CLK_NFC 1 5
    A Vcc
    I2C0_DATA_NFC

    2
    2 R8909 R8910
    B
    1/20W_2.2K_5%_0201 1/20W_2.2K_5%_0201
    PLACE NEAR JFPR1 3 4

    1
    GND OE

    SN74LVC1G66DCK_SSOP5
    I2C0_CLK
    I2C0_CLK <8>
    I2C0_DATA
    I2C0_DATA <8>
    BPWRG
    <13,86,93,95> BPWRG
    SMB_CLK_3B SMB_DATA_3B
    U8902
    1 5
    1

    A Vcc
    1

    D8901 D8902
    1

    EMC@ EMC@ 2
    B
    2
    C8903
    TABLE of U183/U184 3 4 0.01U_6.3V_K_X7R_0201
    GND OE
    2

    AOZ8231ADI-03_DFN1P0X0P6-2 AOZ8231ADI-03_DFN1P0X0P6-2 R8914,R8915 Vendor P/N LCFC P/N 1


    2

    EVT FVT SIT SVT SN74LVC1G66DCK_SSOP5


    CMC/ESD V TI SN74LVC1G66DCK SA00005BE0J
    Resistor
    NXP 74LVC1G66GW SA00007KS00

    0.1U_6.3V_K_X5R_0201
    1

    EMC_HC@ C8904
    ONSemi MC74VHC1G66DFT2G SA00008JQ00
    2
    IPDCLK IPDDATA TP4CLK TP4DATA

    D8905 D8906 D8907 D8908 FL8901 EMC@


    1

    1
    1

    A EMC@ A
    EMC@ EMC@ EMC@ USBP9+ 4 3 USBP9+_CONN
    <10> USBP9+ 4 3
    PESD5V0H1BSF_SOD962-2

    PESD5V0H1BSF_SOD962-2

    PESD5V0H1BSF_SOD962-2
    PESD5V0H1BSF_SOD962-2
    1

    1
    1

    USBP9- 1 2 USBP9-_CONN
    <10> USBP9- 1 2
    EXC24CH900U_4P
    2

    2
    2
    2

    2
    2

    Security Classification LC Future Center Secret Data Title


    PLACE NEAR JFPR1
    Issued Date 2019/01/12 Deciphered Date 2019/04/12 TOUCH PAD/NFC/FPR
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 89 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    VCC5B

    2
    F9001
    2A_32V_ERBRD2R00X

    1
    @
    VCC5B_F4 1
    1
    FAN_ON 2
    <86> FAN_ON 2
    C 3 C
    3
    4
    4
    5
    5
    6
    GND1
    7
    GND2
    JFAN1
    HIGHS_WS33050-S0351-HF

    FAN_ID
    FAN_ID <86>

    FAN_FRQ
    FAN_FRQ <86>

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 FAN CONNECTOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 90 of 125
    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    TABLE : G-Sensor Power

    D HDD Support VCC3M D

    SSD Only VCC3B

    VCC3M VCC3M

    2
    @ R9101 2 2 2
    1/20W_10K_5%_0201
    @ C9101 C9103 C9102
    C C
    0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 10U_6.3V_M_X5R_0402

    1
    1 1 1

    U9101

    Close to pin 3 Close to pin 7


    TABLE

    P/N ADDR_SEL Address


    U9101
    H 32h (W) & 33h (R) ADDR_SEL 1 12 I2C_CLK_GSENSE
    SDO/SA0 SCL/SPC I2C_CLK_GSENSE <86>
    LIS2DWLTR I2C_DATA_GSENSE 2 11
    <86> I2C_DATA_GSENSE SDA/SDI/SDO NC
    L 30h (W) & 31h (R) 3 10 GSENSE_CS
    VDD_IO CS
    4 9
    RES GND_2
    GSENSE_INT 5 8
    <86> GSENSE_INT INT1 GND_1
    1 INT2 6 7
    INT2 VDD
    B H 3Eh (W) & 3Fh (R) B
    KX022-1020 TP9101 LIS2DWLTR_LGA12_2X2 VCC3M
    L 3Ch (W) & 3Dh (R) Test_Point_20MIL
    R9103
    GSENSE_CS 1 2

    2
    R9102 0_0201_SP
    1/20W_10K_5%_0201
    TABLE of G-Sensor (U9101)

    1
    Vendor P/N LCFC P/N
    ST LIS2DWLTR SA00009AQ00
    Kionix KX022-1020 SA000081E00

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 APS G-SENSOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 91 of 125
    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    D D

    C
    BLANK C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 92 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    VCC3B

    VCC3_SUS

    VCC5M

    1/20W_10K_5%_0201

    1/20W_10K_5%_0201

    1/20W_10K_5%_0201

    1/20W_10K_5%_0201
    2

    2
    R9301

    R9302

    R9303

    R9304
    1

    1
    U9301
    SMB_CLK_3B 1 5 SMB_CLK
    <35,89> SMB_CLK_3B A Vcc SMB_CLK <7>

    2
    B
    C C
    3 4
    GND C
    SMB_DATA
    SMB_DATA <7>
    BPWRG SN74LVC1G66DCKR_SC70-5
    <13,86,89,95> BPWRG

    U9302
    SMB_DATA_3B 1 5
    <35,89> SMB_DATA_3B A Vcc

    2
    B

    3 4 2
    GND C
    C9301
    0.01U_6.3V_K_X7R_0201
    SN74LVC1G66DCKR_SC70-5 1

    B TABLE B

    REF DES ENABLE DISABLE

    J5 ASM NO_ASM

    R220 ASM NO_ASM

    LOGIC

    @
    J9301

    LPCCLK_DEBUG_24M 1 2 -PWRSWITCH
    <7> LPCCLK_DEBUG_24M 1 2 -PWRSWITCH <17,51,62,94>
    3 4 LPC_AD0
    3 4
    -LPC_FRAME 5 6 LPC_AD1
    <7,85> -LPC_FRAME 5 6
    -CLKRUN 7 8 LPC_AD2
    <7,85> -CLKRUN 7 8
    IRQSER 9 10 LPC_AD3
    <7,85> IRQSER 9 10
    -PLTRST_FAR 11 12
    <13,37,64,67,73,85,94> -PLTRST_FAR 11 12
    B_ON 13 14 -SUS_STAT
    <94,95,120> B_ON 13 14 -SUS_STAT <7,85> LPC_AD[3:0] <7,85>
    15 16
    GND1 GND2
    HRS_DF12L3P014DP0P5V86A

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 SMBUS SWITCH
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 93 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC3SW

    R9401

    1 2 -EXTPWR_ASIC
    V5M_3V3LDO
    1/20W_47K_5%_0201
    R9402
    1 2

    1/20W_10K_5%_0201

    3
    EMC@ C9401
    D 1 2 Q9401 D
    LSK3541G1ET2L_VMT3
    1000P_25V_K_X7R_0201 1

    2
    -EXTPWR
    <86,102> -EXTPWR

    UTE1A

    -EXTPWR_ASIC 22 52 M_ON
    EXTPWR# MON M_ON <103,104,105>

    -PCH_SLP_S3 19 51 VCCLAN_ON
    <13,17,55,86,95> -PCH_SLP_S3 SLP_S3# LANON VCCLAN_ON <95>
    -PCH_SLP_S4 18
    <13,17,86,112> -PCH_SLP_S4 SLP_S4#
    50 A_ON
    AON A_ON <15,112,120>
    -PCH_SLP_S5 17
    <13,17> -PCH_SLP_S5 SLP_S5#
    -PCH_SLP_LAN 16 49 B_ON
    <13> -PCH_SLP_LAN SLP_LAN# BON B_ON <93,95,120>
    -PCH_SLP_M 15
    <13,17> -PCH_SLP_M SLP_M#
    48 CPUCORE_ON
    CPUON CPUCORE_ON <13,108>
    14
    SUSPWRACK
    -PLTRST_FAR 7
    <13,37,64,67,73,85,93> -PLTRST_FAR PLTRST#
    ThinkEngine-3
    8 -EC_RESET
    1/2 ECRST# -EC_RESET <85>
    -PWRSW_ASIC 21
    C PWRSW# C
    -PCIE_WAKE 20
    <13,55,67,76> -PCIE_WAKE PME#

    -RSMRST 9 6 ECSPI_CLK_R R9403 1 2 1/20W_33_5%_0201 ECSPI_CLK


    <13,19> -RSMRST PGPIO0 SPICLK ECSPI_CLK <87>
    EC_PWRREQ 10 5 ECSPI_MOSI_R R9404 1 2 1/20W_33_5%_0201 ECSPI_MOSI
    <87> EC_PWRREQ PGPIO1 SPIMOSI ECSPI_MOSI <87>
    11 4 -ECSPI_SS_R R9405 1 2 1/20W_33_5%_0201 -ECSPI_SS
    PGPIO2 SPISS# -ECSPI_SS <87>
    12 3 ECSPI_MISO_R R9406 1 2 1/20W_0_5%_0201 ECSPI_MISO
    PGPIO3 SPIMISO ECSPI_MISO <87>

    2 1/20W_100K_5%_0201
    13

    2 1/20W_100K_5%_0201
    PGPIO4

    2 1/20W_100K_5%_0201
    2 1/20W_100K_5%_0201
    2 1/20W_100K_5%_0201
    2 1/20W_100K_5%_0201
    2 1/20W_100K_5%_0201

    BD4179MWV_UQFN56_7X7

    R9408 1
    R9407 1
    R9413 1
    R9412 1
    R9411 1
    R9410 1
    R9409 1

    B VCC3SW B

    2
    @ R9416
    1/20W_1M_5%_0201 -RSMRST

    3
    3
    VCC3M VCC3SW @ Q9402 @ Q9403

    MPWRG 1 LSK3541G1ET2L_VMT3 1 LSK3541G1ET2L_VMT3


    <13,95> MPWRG

    2
    2
    2

    R9414
    1/20W_10K_5%_0201 R9415
    1/20W_4.7K_5%_0201
    1

    1 2 -PWRSW
    -PWRSW <86>
    D9401
    RB521CM-30T2R_VMN2M-2

    A A
    -PWRSWITCH 1 2 -PWRSW_ASIC
    <17,51,62,93> -PWRSWITCH
    D9402
    RB521CM-30T2R_VMN2M-2 2
    C9402
    0.22U_6.3V_K_X5R_0201 Title
    1 Security Classification LC Future Center Secret Data
    Issued Date 2018/01/12 Deciphered Date 2018/01/12 THINK ENGINE-3 (1/2)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 94 of 125
    5 4 3 2 1

    Vinafix.com

    C
    5 4 3 2 1

    VCC3M VCC5M VDD10

    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201
    2 2 2

    C9503
    C9501

    C9502
    TBTB_VBUS20_F
    1 1 1 VCC5B VCC3SW
    F9501 D9501
    1 2 TBT_POWER 2 1 VREGIN20
    Need Anti-surge Chip Resistors

    0.5A_32V_ERBRD0R50X RB530CM-30T2R_SOD923-2

    1/4W_20_5%_0603
    TBTC_VBUS20_F

    1/4W_20_5%_0603

    2
    2

    1/20W_100_5%_0201
    D D

    R9502
    R9501
    F9502 D9502

    2
    Total capacitance of VCC3SW MLCCs must

    1U_6.3V_K_X5R_0402
    R9503
    1 2 TYPEC_POWER 2 1
    be less than 4.7uF.

    1
    1
    0.5A_32V_ERBRD0R50X RB530CM-30T2R_SOD923-2 2

    C9504
    1
    2
    MBAT_PWR15_R VCC5M
    1

    TE_5B_R
    R9504
    1/16W_1M_1%_0402
    F9503 D9503

    1
    1 2 BAT_POWER 2 1

    0.5A_32V_ERBRD0R50X RB530CM-30T2R_SOD923-2 R9505


    VDD10 VCC5M
    TE_NO1 1 2
    TE_VREGIN20
    D9501, D9502, D9503
    0_0402_SP
    Vendor P/N LCFC P/N 1 2 TE_CP10OUT_D_D_C 1 2
    ROHM RB530CM-30 SCS0000AA00

    2
    2 2 D9504 D9505
    R9506 RB521CM-30T2R_VMN2M-2 RB521CM-30T2R_VMN2M-2
    Toshiba 1SS417 SCS0000AC00 1/16W_1.82M_1%_0402 C9505 C9506 2 2
    470P_25V_K_X7R_0201 2.2U_25V_K_X5R_0402
    1 1 C9507 C9508

    45

    31
    28

    47

    32
    UTE1B

    1
    1U_25V_K_X5R_0402 1U_25V_K_X5R_0402
    1 1

    VREGIN20

    VCC3SW

    VDD10
    VCC5M
    5B
    2

    TE_OMG 1 2
    S9501 R9508
    1/20W_33K_5%_0201 R9509
    1/20W_0_5%_0201
    1
    3

    TE_BAT_VOLT 44 30 TE_CP10OUT
    BAT_VOLT CP10OUT

    S9501_RST 1 2 -BAT_RST 43 VCC3SW VCC3B VCC3M


    R9519 3SW_OFF#
    R9518
    R9507 1 2
    VCC3M

    2 1/20W_33K_5%_0201
    1/4W_20_5%_0603

    2 1/20W_10K_5%_0201
    1 2 TE_RD0_ON 29 35
    RD0_ON/5MUBAY RD0_DRV/UBAY_DRV

    2 1/20W_2K_5%_0201
    C 1/20W_10K_5%_0201 1/20W_0_5%_0201 C
    2 27 36
    4

    EMC@ <94> VCCLAN_ON RD1_ON RD1_DRV VCC3LAN_DRV <123>


    SKRPABE010_4P C9509 R9521 1 2 0_0201_SP -PCH_SLP_SUS_R 26 38
    0.1U_25V_K_X5R_0201 <13,86> -PCH_SLP_SUS RD2_ON RD2_DRV SUS_DRV <121,125>
    1 25 39
    <3> PANEL_POWER_ON RD3_ON RD3_DRV VCC3P_DRV <51>
    1 2 B_ON_D 24 40
    <93,94,120> B_ON D9506 RD4_ON RD4_DRV VCCIO_DRV <124>
    RB521CM-30T2R_VMN2M TE_RD5_ON 23 2/2 41 R9516
    1 2 RD5_ON RD5_DRV/WLAN_DRV 1R8VIDEO_MAIN_DRV <118> EVT FVT SIT SVT
    <11,15,120> -CPU_C10_GATE @ D9507 42 Resistor V
    RD6_DRV/WWAN_DRV VCC3WLAN_DRV <125>

    1/20W_1M_1%_0201
    RB521CM-30T2R_VMN2M R-short

    2
    1 2 34

    R9512 1
    <13,17,55,86,94> -PCH_SLP_S3

    R9513 1
    VCC3B_DRV <124>

    R9514 1
    3B_DRV

    R9520
    D9510
    R9511
    RB521CM-30T2R_VMN2M 33
    2 1 SWG_1V8_ON 1 2 5B_DRV VCC5B_DRV <124>
    <37,41,115,116> GFXCORE_D_PWRGD

    1
    SWG@D9508 1 TE_MPWRG_R R9516 1 2 0_0201_SP
    RB521CM-30T2R_VMN2M 0_0201_SP M_PGS MPWRG <13,94>
    2 1 56
    <41> GFX_PWR_EN B_PGS BPWRG <13,86,89,93>
    55
    SWG@D9509 SHUTDOWNIN#
    RB521CM-30T2R_VMN2M TE_TH_DTCT 54 53
    TH_DTCT PWRSHUTDOWN# -PWRSHUTDOWN <100,101>

    BD4179MWV_UQFN56_7X7
    VCC3SW 5M_3M_PWRG R9517 1 2 0_0201_SP
    <103,104,105> 5M_3M_PWRG

    DGND
    PGND
    AGND

    PAD

    0.1U_6.3V_K_X5R_0201
    2

    EMC_HC@ C9510
    2

    2
    37
    46

    57
    R9515
    1/20W_33K_5%_0201 ThinkEngine-3 1
    1

    <41,86> -SHUTDOWN

    B B
    540_0402NEW_30%_PRF15BB541NB6RC

    540_0402NEW_30%_PRF15BB541NB6RC
    540_0402NEW_30%_PRF15BB541NB6RC

    TABLE
    540_0402NEW_30%_PRF15BB541NB6RC

    540_0402NEW_30%_PRF15BB541NB6RC
    540_0402NEW_30%_PRF15BB541NB6RC
    ID Target
    RT9501 Thunderbolt Port A VBUS FET (PQ0001,PQ0002,PQ0005,PQ0006)
    1

    1
    1
    1

    1
    RT9501

    RT9507
    RT9509
    RT9503

    RT9502

    RT9511
    0.1U_6.3V_K_X5R_0201

    RT9505 Battery Buck Charger VBUS Dual FET (PQ0201)


    RT9503 Battery Boost Charger VBUS Dual FET (PQ0202)
    2

    2
    2
    2

    2
    RT9502 Battery Charger FET (PQ0203)

    540_0402NEW_30%_PRF15BB541NB6RC
    540_0402NEW_30%_PRF15BB541NB6RC
    540_0402NEW_30%_PRF15BB541NB6RC

    540_0402NEW_30%_PRF15BB541NB6RC
    540_0402NEW_30%_PRF15BB541NB6RC

    RT9506 Battery Charger FET (PQ0101)


    RT9504 VCCCPUCORE Dr MOS Phase2 (PU0902)
    RT9507 VCCCPUCORE Dr MOS Phase1 (PU0901)
    1
    1
    1

    1
    1

    2
    RT9510
    RT9504
    RT9506

    RT9508
    RT9505

    RT9511 VCCGFXCORE_I (PU1001)


    1 RT9510 CPU Die (UCPU1)
    2
    2
    2

    2
    2
    EMC@ C9511

    RT9509 VCCGFXCORE_D EFT(PQ1501)


    RT9508 VCCGFXCORE_D EFT(PQ1502)

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 THINK ENGINE-3 (2/2)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 95 of 125
    Vinafix.com
    5 4 3 2 1
    5 4 3 2 1

    D D

    BLANK
    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    Drift/Ironhide
    Vinafix.com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date: Tuesday, December 18, 2018 Sheet 96 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2018/01/12 Deciphered Date 2018/01/12 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    Drift/Ironhide
    Vinafix.com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date: Tuesday, December 18, 2018 Sheet 97 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    VCC3_SUS

    1
    R9801
    0_1%_0603_LE

    2
    VCC3_SUS_TPM

    2 2 2 2
    C9801 C9802 @ C9803 C9804

    2
    R9802 1 1 1 1
    1/20W_10K_5%_0201 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 10U_6.3V_M_X5R_0402

    1
    @ Close to Pin1, Pin8, Pin22

    TABLE
    C C
    Pin TCG Nuvoton ST Micro
    No
    PTP Spec (v38) NPCT750LABYX ST33HTPH2E32AHC0

    1 VDD VSB NC

    22
    U9801

    1
    2 GND NC GND

    VHIO2

    VHIO1

    VSB
    3 NC NC NC
    -TPM_IRQ 18 2 4 GPIO/PP PP
    <8> -TPM_IRQ PIRQ#/GPIO2 NC1
    3
    GPIO
    NC2
    4 5 NC NC NC
    SPI_MOSI_IO0 R9803 1 2 1/20W_33_5%_0201 SPI_MOSI_IO0_2_R 21 PP/GPIO6
    5 6 GPIO GPIO3 NC
    <7,21> SPI_MOSI_IO0 MOSI/GPIO7 NC3
    <7,21> SPI_MISO_IO1
    SPI_MISO_IO1 R9804 1 2 1/20W_33_5%_0201 SPI_MISO_IO1_2_R 24
    MISO NC5
    9 7 GPIO NC GPIO
    10 8 VHIO
    NC6
    11 VDD NC
    NC7
    12
    NC8
    -SPI_CS2 R9805 1 2 1/20W_0_5%_0201 -SPI_CS2_R 20 13
    <7> -SPI_CS2 SCS#/GPIO5 GPIO4
    14
    NC9
    SPI_CLK R9806 1 2 1/20W_33_5%_0201 SPI_CLK_2_R 19 15 9 NC NC NC
    <7,21> SPI_CLK SCLK NC10
    NPCT750LABYX_QFN32_5X5 16
    -PLTRST_NEAR 17 GND1
    25 10 NC NC NC
    <13,55,76> -PLTRST_NEAR PLTRST# NC11
    11 NC NC
    NC12
    26 NC
    6 27 12 NC NC
    GPIO3 NC13
    28
    NC
    7 NC14
    31 13 GPIO GPIO4 NC
    NC4 NC15
    32 14 NC NC NC
    NC16
    15 NC NC NC
    29 16 GND NC
    SDA/GPIo0
    30 GND
    SCL/GPIO1

    GND3
    GND2
    17 SPI_RST# RST# SPI_RST#

    33
    23
    18 SPI_PIRQ# PIRQ#/GPIO2 SPI_PIRQ#
    19 SPI_CLK SCLK SPI_CLK
    B
    20 SPI_CS# SCS#/GPIO5 SPI_CS# B
    21 MOSI MOSI/GPIO7 MOSI
    22 VDD VHIO VPS
    23 GND GND NC
    24 MISO MISO MISO

    25 NC NC NC
    26 NC NC NC
    27 NC NC NC
    TABLE of TPM (U9801) 28 NC NC NC
    29 SDA/GPIO1 SDA/GPIO1 NC
    Vendor P/N LCFC P/N 30 SDA/GPIO0 SDA/GPIO0 NC
    Nuvoton NPCT750LABYX SA00008KS10 Import Nuvoton on EVT 31 NC NC NC
    32 NC NC NC
    ST Micro ST33HTPH2E32AHC0 SA000089E20

    A A

    R9805 Title
    EVT FVT SIT SVT Security Classification LC Future Center Secret Data
    Resistor V
    R-short
    Issued Date 2018/01/12 Deciphered Date 2018/01/12 DISCRETE TPM 2.0
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Drift/Ironhide
    Date: Tuesday, December 18, 2018 Sheet 98 of 125
    5 4 3 2 1
    5 4 3 2 1

    @ H1 @ H2 @ H3
    HOLEA HOLEA HOLEA
    PAD_OB6P1X7P0D2P1X3P0 PAD_CT6P0D2P8 PAD_CT6P0D3P3

    1
    1

    1
    D D

    @ H4 @ H5 @ H6 @ H7 @ H8
    HOLEA HOLEA HOLEA HOLEA HOLEA
    PAD_C6P5D2P5 PAD_C6P5D2P5 PAD_C6P5D2P5 PAD_C6P5D2P5 PAD_C6P5D2P5
    1

    1
    @ H9 @ H10 @ H11 @ H12 @ H15 @ H16
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
    PAD_C6P5D2P5 PAD_C6P5D2P5 PAD_C5P2D2P5 PAD_CT6P0D3P2 PAD_C6P0D3P2 PAD_C6P0D3P2
    C C

    1
    1
    1
    1

    1
    1
    @ H19 @ H20 @ H21 @ H17 @ H18
    HOLEA HOLEA HOLEA HOLEA HOLEA
    pad_c2p6d2p6n PAD_C2P5D2P5N PAD_O2P0X2P3D2P0X2P3N PAD_C6P0D3P2 PAD_C6P0D3P2

    1
    1
    1

    1
    1

    @ H22
    HOLEA
    PAD_C2P0D2P0N
    B B
    1

    @ FD1 @ FD2
    FIDUCIAL_C40M80 FIDUCIAL_C40M80
    1
    1

    @ FD3 @ FD4
    FIDUCIAL_C40M80 FIDUCIAL_C40M80
    1

    A A

    Title
    @ FD5 @ FD6 SCREW HOLES
    FIDUCIAL_C40M80 FIDUCIAL_C40M80
    Size Document Number Rev
    1
    1

    Vinafix.com
    A Drift/Ironhide 0.1

    Date: Tuesday, December 18, 2018 Sheet 99 of 125


    5 4 3 2 1
    5 4 3 2 1

    TABLE PQ0001,PQ0002

    VISHAY : SI7153DN
    D
    AOS : AON7409 D

    VINT20_IN
    TBT_VBUS20 TBTB_VBUS20_F
    PQ0001 PQ0002
    SI7153DNT1GE_POWERPAK1212-8-5 SI7153DNT1GE_POWERPAK1212-8-5
    1 1
    PF0001 2 2
    1 2 5 3 3 5 EMC@ EMC@ RF_NS@ RF_NS@

    100P_25V_J_NPO_0201
    5A_32V_0438005.WR

    2200P_25V_K_X7R_0201
    0.047U_25V_K_X7R_0402

    0.1U_25V_K_X5R_0201

    47P_25V_J_NPO_0201
    4
    4

    1000P_25V_K_X7R_0201
    1/20W_100K_1%_0201
    2 2

    1/20W_100_5%_0201
    2 2 2 2

    PC0011

    PC0012

    PC0015

    PC0016
    PC0001 PC0002

    2
    1U_25V_K_X5R_0402 2 2 22U_25V_M_X5R_0805_H1.25
    1 1

    PR0002

    PC0004

    PC0005
    PR0003
    PR0001
    1/20W_100_5%_0201 1 1 1 1

    1 1

    1
    2
    PR0004
    1/20W_10K_1%_0201

    1
    C C

    3
    PQ0003
    LSK3541G1ET2L_VMT3
    TBT_HV_GATE 1
    <34> TBT_HV_GATE

    2
    2

    PR0006
    1/20W_100K_5%_0201
    1

    3
    PQ0004
    LSK3541G1ET2L_VMT3
    -PWRSHUTDOWN 1 TABLE PQ0005,PQ0006
    <66,76,77> -PWRSHUTDOWN

    2
    VISHAY : SI7153DN
    AOS : AON7409

    USBC_VBUS20 TBTC_VBUS20_F
    PQ0005 PQ0006
    SI7153DNT1GE_POWERPAK1212-8-5 SI7153DNT1GE_POWERPAK1212-8-5
    1 1
    PF0002 2 2
    1 2 5 3 3 5 EMC@ EMC@
    5A_32V_0438005.WR

    2200P_25V_K_X7R_0201
    0.047U_25V_K_X7R_0402
    1/20W_100K_1%_0201

    4
    4

    1000P_25V_K_X7R_0201

    0.1U_25V_K_X5R_0201
    1/20W_100_5%_0201
    2
    B B
    2

    2
    2

    PC0006 2 2 2 2 2
    PR0008

    PC0014
    PR0009

    PC0013
    PC0007

    PC0010
    1U_25V_K_X5R_0402 PR0007
    1 1/20W_100_5%_0201 PC0008
    22U_25V_M_X5R_0805_H1.25
    1 1 1 1 1
    1

    1
    1

    PR0010
    1/20W_10K_1%_0201
    1
    3

    PQ0007
    LSK3541G1ET2L_VMT3
    USBC_HV_GATE 1
    <34> USBC_HV_GATE
    2
    2

    PR0012
    1/20W_100K_5%_0201
    1

    PQ0008
    A A
    LSK3541G1ET2L_VMT3
    -PWRSHUTDOWN 1
    2

    Security Classification LC Future Center Secret Data Title


    Issued Date Deciphered Date DC-IN
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 100 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D
    TABLE PQ0101
    VCC3M
    VISHAY : SiI153DN
    AOS : AON7409

    2
    PR0101 PR0107 MBAT_PWR15_R BAT_PWR15
    1/20W_6.19K_1%_0201 0_0805_SP
    1 2
    PQ0101

    1
    SI7153DNT1GE_POWERPAK1212-8-5
    JDC1 PR0108 1
    8
    8 WIDE PATTERN 0_0805_SP 2
    9 7 MBAT_PWR15_IN 1 2 3 5
    PTH1 7
    6 I2C_CLK_BT_R
    6
    10 5 I2C_DATA_BT_R
    PTH2 5
    4 PR0102 1 2 1/20W_100_5%_0201
    I2C_CLK_BT <55>

    4
    4
    11 3
    PTH3 3
    2
    2
    12 1 PR0103 1 2 1/20W_100_5%_0201
    PTH4 1 I2C_DATA_BT <55>

    2
    2
    C C
    HIGHS_WS33081-S0201-HF PR0104 PR0105
    @ 1/20W_510K_5%_0201 1/20W_100_5%_0201
    M_TEMP <55>

    1
    1
    390P_25V_K_X7R_0201

    2200P_25V_K_X7R_0201
    390P_25V_K_X7R_0201

    2200P_25V_K_X7R_0201

    EMC@
    EMC@
    2 2 2 2
    PC0103
    PC0101

    PC0104
    PC0102

    1 1 1 1
    @ @

    2
    PR0106
    1/20W_150K_5%_0201

    1
    B B

    3
    PQ0102
    LSK3541G1ET2L_VMT3
    1
    <66,76> -PWRSHUTDOWN

    2
    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date Deciphered Date BATTERY INPUT
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 101 of 125
    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    PL0201
    PQ0201 PQ0202
    CYNTEC : CMLE063T-2R2MS-88
    Infineon : BSC0924NDI
    MURATA: FDSD0630-H-2R2M=P3
    VISHAY : SIZ340DT VSYS15
    AOS : AON6998 AOS : AON7934
    VINT20_IN
    PR0201 PL0201
    1W_0.01_1%_1206_LE PQ0201 CMLE063T-2R2MS-88_10A_20% PQ0202
    1 2 VINT20 RF_NS@ RF_NS@ BSC0924NDI_PG-TISON-8-9 1 2 SIZ340DTT1_POWERPAIR_3X3-9-10

    9
    22U_25V_M_X5R_0805_H1.25

    22U_25V_M_X5R_0805_H1.25

    0.01UC_25VC_KC_X5RC_0201
    2 EMC_NS@ 1 EMC_NS@ 2 EMC@ EMC@ RF_NS@ RF_NS@

    1000P_25V_K_X7R_0201

    100P_25V_J_NPO_0201
    D
    4 5 PC0203 1 7 10 D

    47P_25V_J_NPO_0201
    3 6 PC0202 0.047U_25V_K_X7R_0402 PC0204 PC0205 6 4

    2200P_25V_K_X7R_0201

    10U_25V_M_X5R_0603
    10U_25V_M_X5R_0603

    10U_25V_M_X5R_0603
    10U_25V_M_X5R_0603

    10U_25V_M_X5R_0603

    10U_25V_M_X5R_0603
    0.1U_25V_K_X5R_0201

    100P_25V_J_NPO_0201
    2 7 330P_25V_K_X7R_0201 0.047U_25V_K_X7R_0402 330P_25V_K_X7R_0201 5 3

    1
    1 2 1

    47P_25V_J_NPO_0201
    2 2 2 2 2 2 2
    2

    PC0210
    PC0201

    PC0209

    PC0239
    PC0238
    PC0207

    PR0202 PR0203
    0_0201_SP 0_0201_SP 1 1 1 1 1 1 1 1 2 2

    PC0216
    PC0241

    PC0213
    PC0240

    PC0214

    PC0242

    PC0243
    PC0211

    PC0212

    PC0215
    2
    1 1 1 1 1 1
    EMC_NS@

    1
    1

    2
    2
    PR0207
    PR0204 PR0205 PR0206 1/16W_56_5%_0402 2 2 2 2 2 2 2 2 1 1
    1/16W_56_5%_0402 0_0402_SP 0_0402_SP
    EMC_NS@

    1
    @ @

    1
    1
    PU0201
    BQ25700ARSNR_QFN32_4X4

    2
    PR0208 PR0209 30 25
    TABLE PQ0203
    BTST1 BTST2
    1/20W_4.99_1%_0201 1/20W_4.99_1%_0201

    LX1_CHG 32 23 LX2_CHG
    VISHAY : SI7153DN
    1 AOS : AON7409

    1
    SW1 SW2

    DL1_CHG 29 26 DL2_CHG
    LODRV1 LODRV2

    PR0210 PR0211
    0_0402_SP 0_0402_SP PQ0203
    1 2 31
    HIDRV1 HIDRV2
    24 DH2_CHG 1 2 SI7153DNT1GE_POWERPAK1212-8-5 BAT_PWR15
    1 PR0212
    2 1W_0.01_1%_1206_LE
    3 5 1 2

    0.01UC_25VC_KC_X5RC_0201

    10U_25V_M_X5R_0603
    10U_25V_M_X5R_0603
    1U_25V_K_X5R_0402
    @ PC0217

    4
    C C
    0.033U_25V_K_X7R_0402 1 1 22 2 2
    VBUS VSYS

    PC0221
    PC0220
    2 1 2 2 2 2

    PC0223
    PC0222
    PC0237
    PC0218 PC0219 1U_25V_K_X5R_0402
    0.033U_25V_K_X7R_0402 2 PR0214 1 1
    1 0.033U_25V_K_X7R_0402 1 1
    1 PC0224 PR0213 0_0402_SP
    CH_AGND 1800P_25V_K_X7R_0201 1/20W_40.2K_1%_0201 21 BATDRV# 1 2 @
    BATDRV#
    CH_AGND CH_AGND 1 2 1 2

    PC0225
    PC0226 PR0215 PC0227 0.1U_25V_K_X5R_0201
    33P_25V_J_NPO_0201 1/20W_10K_1%_0201 680P_25V_K_X7R_0201 1 2
    1 2 16 17 1 2 1 2
    COMP1 COMP2
    2 2
    PC0230
    15P_25V_J_NPO_0201 PC0228 PC0229
    1 2 0.1U_25V_K_X5R_0201 0.1U_25V_K_X5R_0201
    1 1
    CH_AGND

    CH_AGND CH_AGND CH_AGND


    2 20 PR0216 1 2 0_0201_SP
    ACN SRP

    3 19 PR0217 1 2 0_0201_SP
    ACP SRN

    PR0218 1 2 0_0402_SP 13
    <55> I2C_CLK_CHARGE SCL
    SWG@PR0220
    1/20W_0_5%_0201
    PR0219 1 2 0_0402_SP 12 11 1 2
    <55> I2C_DATA_CHARGE SDA PROCHOT# -CHG_PROCHOT <87>
    UMA@ PR0233
    6 8 1/20W_75_5%_0201
    ILIM_HIZ IADPT
    B
    1 2 B
    -PROCHOT <6,56,84,90>
    PR0221 1 2 1/10W_10_5%_0603 28 9
    REGN IBAT PSYS_MAX:100W at
    REG0x30[11:9]:001b
    7 10
    VDDA PSYS PSYS <90>
    2

    PR0223 1 2 1/20W_71.5K_1%_0201 18 4
    CELL_BATPRES CHRG_OK
    PR0222
    1/20W_174K_1%_0201
    @ PR0224 1 2 1/20W_10K_5%_0201 5
    ENZ_OTG
    TABLE : Drift / Ironhide
    1

    14 15
    CMPIN CMPOUT VCC3SW UMA SWG

    PGND

    PAD

    100P_25V_J_NPO_0201
    100P_25V_J_NPO_0201

    100P_25V_J_NPO_0201

    1/20W_137K_1%_0201
    PR0220 No_ASM ASM
    PR0233 ASM No_ASM

    33
    27

    2
    2.2UC_10VC_KC_X5RC_0402

    2 2 2

    PC0232
    PC0231

    PC0233

    PR0225
    1/20W_100K_1%_0201

    2
    1U_25V_K_X5R_0402
    2

    PR0231 PR0227
    2

    1 1 1
    2

    PR0226 2 2 1/20W_100K_5%_0201 1/20W_100K_5%_0201

    1
    PC0234

    1/20W_100K_1%_0201
    PC0235

    PR0230
    PR0229

    PR0228
    1/20W_10K_5%_0201 1/20W_10K_5%_0201

    1
    1

    1 1 PR0232
    1
    1

    -EXTPWR <56,65>
    1

    0_0402_SP
    1 2

    3
    PQ0204 2
    CH_AGND CH_AGND CH_AGND CH_AGND CH_AGND LSK3541G1ET2L_VMT3
    1 PC0236

    2
    47P_25V_J_NPO_0201
    CH_AGND 1
    A TABLE : ILIM_HIZ CH_AGND CH_AGND
    A

    IDPM V (ILIM) PR0222


    500mA 1.2V TABLE CH_AGND CH_AGND
    TABLE : CELL_BATPRES
    1.0A 1.4V
    # of CELL V (CELL_PRES) PR0223 Inductor R(IADP) Fsw@POR
    1.5A 1.6V
    1-CELL 1.5V 301K 1.0uH 93kohm 800KHz Security Classification LC Future Center Secret Data Title
    2.0A 1.8V 237K
    2-CELL 2.5V 140K 2.2uH 137kohm 800KHz Issued Date Deciphered Date BATTERY CHARGER(BQ25700A)
    3.0A 2.2V 174K
    3.25A 2.3V 162K
    LOGIC 3-CELL 3.5V 71.5K LOGIC 3.3uH 169kohm 800KHz LOGIC
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    4.5V Custom 0.1
    4-CELL 33.2K DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 102 of 125
    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    D D

    VSYS15

    1
    @ PJ0301

    1
    JUMP_43X79
    V5M_3V3LDO

    2
    VCC5M

    2
    RF_NS@ RF_NS@
    Int 3.3V LDO Output TDC = 6.3A

    47P_25V_J_NPO_0201
    100P_25V_J_NPO_0201
    1
    PC0301
    2 2 EMC@ 2 EMC@ 2
    + PC0304 2 2
    22U_25V_M_B2_ESR100M_H1.9

    PC0320
    PC0319
    2.2U_6.3V_M_X5R_0201 PC0302 PC0316 PC0303
    0.1U_25V_K_X5R_0201 2200P_25V_K_X7R_0201 22U_25V_M_X5R_0805_H1.25 VCC5M
    1 1 1 1 2
    1 1

    AGND_5M
    C C

    PU0301

    12
    9

    2
    2
    NB690GRP-C669-Z_QFN12_2X2P5
    PL0301

    VIN_1

    VIN_2
    3V3LDO

    2
    2
    @ PJ0302 @ PJ0303
    PR0301 JUMP_43X79 JUMP_43X79

    1
    1
    1/20W_0_5%_0201 CYNTEC : CMLE053T-1R5MS
    M_ON 1 2 5 6
    <65,80,81> M_ON 5M_3M_PWRG <66,80,81>

    1
    1
    EN PG
    1

    PR0302 PC0307
    @ PR0308 0_0402_SP 0.22U_25V_KC_X5R_0402
    1/20W_100K_1%_0201 8 1 2 1 2
    BST
    PL301
    1.5UH_CMLE053T-1R5MS_8.2A_20%
    EMC@ EMC@ RF_NS@ RF_NS@
    2

    4 7 1 2
    MODE SW
    PR0304
    1

    1/16W_3.3_1%_0402
    PGND_1

    PGND_2

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    2200P_25V_K_X7R_0201

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    11

    100P_25V_J_NPO_0201
    1 2

    0.1U_6.3V_K_X5R_0201
    PR0303
    VOUT
    AGND

    47P_25V_J_NPO_0201
    0_0201_SP

    2 2 2 2 2 2 2 2 2 2
    2

    PC0310
    PC0309

    PC0313
    PC0311

    PC0321
    PC0314
    PC0312
    PC0308

    PC0322
    PC0317
    1 EMC_NS@
    10

    PC0318
    1000PC_50VC_KC_X7RC_0201 1 1 1 1 1 1 1 1 1 1
    2

    2
    2
    PC0315 @ PR0305
    0.1U_6.3V_K_X5R_0201 1/20W_100K_1%_0201
    EMC_NS@

    1
    AGND_5M
    1 PR0307

    1
    1/4W_2.2_5%_0603
    TABLE : NB690 Mode Control

    2
    B B
    RMode MODE VOUT 3V3LDO
    0 Ceramic Cout 5.1V 3.3V LOGIC
    60K POSCAP Cout 5.1V 3.3V
    120K Ceramic Cout 5V 3.3V
    180K POSCAP Cout 5V 3.3V PR0306
    Floating X 3.3V 3.3V 0_0402_SP
    1 2

    AGND_5M

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date Deciphered Date DC/DC VCC5M (NB690)
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 103 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    VSYS15

    1
    @ PJ0401

    1
    JUMP_43X79
    VCC5M_PD

    2
    TDC = 7.2A

    2
    2 EMC@ 2 EMC@ 2 2 2 2
    PC0402 PC0416 PC0403 PC0404 PC0405 PC0406 VCC5M_PD
    0.1U_25V_K_X5R_0201 2200P_25V_K_X7R_0201 10U_25V_K_X5R_0805_H1.25 10U_25V_K_X5R_0805_H1.25 10U_25V_K_X5R_0805_H1.25 10U_25V_K_X5R_0805_H1.25
    1 1 1 1 1 1

    Table PL0401

    2
    2

    2
    CYNTEC : CMLE053T-1R5MS @ PJ0402 @ PJ0403

    16

    1
    C PR0402 JUMP_43X79 JUMP_43X79 C

    1
    1/16W_2.2_5%_0402

    NC2

    VIN
    10 1 2

    1
    BST

    1
    PR0401
    0_0201_SP PC0407
    1 2 15 0.22U_25V_KC_X5R_0402
    <65,79,81> M_ON EN 2 PL0401
    PU0401 1.5UH_CMLE053T-1R5MS_8.2A_20%
    NB693GQ-C669-Z_QFN16_3X3 9 1 2 EMC@ EMC@
    SW
    PR408 8
    NC1
    1/20W_91K_1%_0201 PR0409 PC0415

    2200P_25V_K_X7R_0201

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    0.1U_6.3V_K_X5R_0201
    1 2 11 1/20W_274K_1%_0201 220P_25V_K_X7R_0201
    CLM

    1
    1 2 1 2
    PR0404
    1/20W_110K_1%_0201 2 2 2 2 2 2 2 2

    PC0414
    PC0417

    PC0408

    PC0412

    PC0413
    PC0409

    PC0410

    PC0411
    13
    FB

    2
    PR0403

    1
    1/16W_5.1_5%_0402 1 1 1 1 1 1 1 1
    1 2 3 12 PR0407
    VCC3M 3V3 PG 5M_3M_PWRG<66,79,81>
    1/20W_499_1%_0201

    14
    PGND1

    PGND3
    PGND2

    PGND4

    PGND5

    2
    MODE

    1
    PC0401
    2

    5
    4

    1
    2.2UC_10VC_KC_X5RC_0603 @ PR0410
    1/20W_0_5%_0201 PR0405
    2 1/20W_10K_1%_0201

    2
    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date Deciphered Date DC/DC VCC5M_PD_AB (NB693)
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 104 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    VSYS15
    VCC3M
    1

    @ PJ0501
    TDC = 7.5A
    1

    JUMP_43X79
    2
    2

    RF_NS@ RF_NS@
    VCC3M

    100P_25V_J_NPO_0201

    47P_25V_J_NPO_0201
    EMC@ 1
    2 2 EMC@ +
    2 2 2

    PC0520

    PC0521
    PC0502 PC0503
    0.1U_25V_K_X5R_0201 PC0517 22U_25V_M_B2_ESR100M_H1.9 PC0504
    C 2200P_25V_K_X7R_0201 22U_25V_M_X5R_0805_H1.25 C
    1 1 2 1 1 1
    Table PL0501

    2
    2
    CYNTEC : CMLE053T-1R5MS

    2
    2
    @ PJ0502 @ PJ0503
    JUMP_43X79 JUMP_43X79

    1
    1
    PU0501 PR0502 PC0507
    TPS51393PRJER_VQFN20_3X3 0_0402_SP 0.22U_25V_KC_X5R_0402

    1
    1
    2 1 1 2 1 2
    BST
    3 VIN1
    4 VIN2
    PR0501 5 VIN3 PL0501
    VIN4
    0_0201_SP 1.5UH_CMLE053T-1R5MS_8.2A_20%
    M_ON 1 2 12 6 1 2 EMC@ EMC@ RF_NS@ RF_NS@
    <65,79,80> M_ON EN SW1
    19
    SW2
    17 20
    VCC SW3

    2200P_25V_K_X7R_0201

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    100P_25V_J_NPO_0201
    0.1U_6.3V_K_X5R_0201
    11
    ENLDO

    47P_25V_J_NPO_0201
    15 14
    LDO VOUT
    PR0504 PC0516 2 2 2 2 2 2 2 2 2 2

    PC0518

    PC0512

    PC0522
    PC0510

    PC0513
    PC0508

    PC0511

    PC0514
    THERMAL PAD

    PC0509

    PC0523
    1/20W_240K_1%_0201 470P_25V_K_X7R_0201
    4.7U_6.3V_M_X5R_0402

    13 1 2 1 2
    FB
    10
    NC1
    1

    1 1 1 1 1 1 1 1 1 1

    PGOOD
    PGND3
    PGND2
    PGND1
    1 1
    PC0501

    PC0515 PR0503 16
    NC2
    1U_6.3V_M_X5R_0201 0_0201_SP
    @
    2 2 1 EMC_NS@ @

    21
    18
    8
    7

    9
    2

    PC0519
    1000PC_50VC_KC_X7RC_0201
    2
    @ 5M_3M_PWRG <66,79,80>

    EMC_NS@

    1
    PR0505
    B 1/4W_2.2_5%_0603 B

    A A

    Vinafix.com Security Classification LC Future Center Secret Data Title


    Issued Date Deciphered Date DC/DC VCC3M (TPS51393)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 105 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    BLANK

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Vinafix.com
    Issued Date Deciphered Date BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 106 of 125
    5 4 3 2 1
    5 4 3 2 1

    VCC5M
    D D

    1
    @ PJ0701

    1
    JUMP_43X79

    2
    VCC1R8_SUS

    2
    TDC = 1.81A

    2 EMC@ 2 EMC@ 2
    PC0701 PC0707 PC0702
    0.1U_25V_K_X5R_0201 2200P_25V_K_X7R_0201 10UC_10VC_KC_X5RC_0805C_H1.25
    1 1 1 VCC1R8_SUS
    Table PL0701

    MURATA DFE252012F-1R0M=P2

    2
    C CYNTEC HMLQ25201B-1R0MSR C

    2
    @ PJ0702
    JUMP_43X79

    1
    PU0701

    3
    MP1603LGTF-C669-Z_SOT563-6 PL0701

    1
    1UH_DFE252012F-1R0M-P2_3.9A_20%
    EMC@ EMC@

    VIN
    2 1 2
    SW
    PR0702

    2200P_25V_K_X7R_0201

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    0.1U_6.3V_K_X5R_0201
    0_0201_SP
    1 2 4 6
    77 SUS_ON1 EN OUT

    2 2 2 2 2

    PC0705

    PC0706
    PC0703
    PC0708

    PC0704
    5
    FB

    1
    GND
    PR0701
    1 1/20W_200K_1%_0201 1 1 1 1 1

    2
    @ @

    B B

    1
    PR0703
    1/20W_100K_1%_0201

    2
    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date Deciphered Date DC/DC VCC1R8_SUS (MP1603L)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 107 of 125
    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    VCC1R8_MP2949

    1
    1
    1
    @ PR0852 @ PR0854 @ PR0856
    VCC3M VCC1R8_MP2949
    1/20W_10K_1%_0201 1/20W_10K_1%_0201 1/20W_10K_1%_0201
    VCCST VCCSTG VCC3M

    2
    2
    2

    1
    1 PR0801 1
    1/16W_4.7_1%_0402
    D PC0801 PC0803 D
    0.1U_6.3V_K_X5R_0201 1U_6.3V_M_X5R_0201

    2
    2 2

    1/20W_10K_1%_0201

    1/20W_10K_1%_0201
    1/20W_10K_1%_0201

    1/20W_10K_1%_0201
    1
    1

    1
    1

    1
    1
    @ PR0853 @ PR0855 @ PR0857

    PR0803

    PR0805
    @ PR0804

    PR0806
    1/20W_10K_1%_0201 1/20W_10K_1%_0201 1/20W_10K_1%_0201 1 @ PR0802 PR0807
    GND_MP2949 1/20W_510_5%_0201 1/20W_100K_1%_0201
    PC0802

    2
    2

    2
    4.7U_6.3V_M_X5R_0402

    2
    2

    2
    2
    2
    2

    PU0801
    GND_MP2949 MP2949AGQKT-024E-C669-Z_TQFN48_6X6

    44

    26
    GND_MP2949 GND_MP2949 GND_MP2949 PR0808 1 2 1/20W_1.43K_+-1%_0201 6 37 PR0813 1 2 0_0201_SP CPUCORE_ON CPUCORE_ON 13,60

    VDD33

    VDD18
    VDIFFA EN
    PR0809 1 2 1/20W_2.49K_1%_0201 10 30 CPUCORE_PWRGD
    PR0810 1 2 1/20W_8.06K_1%_0201 VDIFFB VRRDY CPUCORE_PWRGD 13
    14
    VDIFFC
    31 PR0814 1 2 1/20W_75_5%_0201 -PROCHOT -PROCHOT 6,86,87
    VRHOT#
    @ PC0804 1 2 1U_6.3V_M_X5R_0201 @ PR0815 1 2 1/20W_10K_1%_0201 7 36 PR0864 1 2 0_0201_SP IMVP_PMBUS_EN
    @ PC0805 1 2 1U_6.3V_M_X5R_0201 11 VFBA PE IMVP_PMBUS_EN 53
    @ PR0816 1 2 1/20W_10K_1%_0201 GND_MP2949 PR0811 1 2 1/20W_10K_1%_0201
    VFBB
    @ PC0806 1 2 1U_6.3V_M_X5R_0201 @ PR0812 1 2 1/20W_10K_1%_0201 15 32 PMB_DATA_IMVP
    VFBC SDA_P
    33 PMB_DATA_IMVP 51
    PMB_CLK_IMVP
    SCL_P PMB_CLK_IMVP 51
    GND_MP2949 GND_MP2949 GND_MP2949 34 MODE_SEL
    8 STB MODE_SEL 68,69,70
    VCC_SENSE PR0817 1 2 0_0201_SP
    14 VCC_SENSE PR0818 1 2 0_0201_SP 9 VOSENA
    35
    VSS_SENSE @ PR0819 1 2 1/20W_0_5%_0201 -PCH_SLP_S0 -PCH_SLP_S0 13,17,72,74,79
    14 VSS_SENSE 12 VORTNA SLP_S0# PR0821 1 2 1/20W_100_5%_0201
    VCCGT_SENSE PR0820 1 2 0_0201_SP
    15 VCCGT_SENSE 13 VOSENB
    VSSGT_SENSE PR0822 1 2 0_0201_SP
    15
    15
    VSSGT_SENSE
    VCCSA_SENSE
    VCCSA_SENSE PR0823 1 2 0_0201_SP 16 VORTNB
    VOSENC
    PR0824 1 2 1/20W_47_5%_0201 VCCST
    VSSSA_SENSE PR0825 1 2 0_0201_SP 17 27 PR0826 1 2 1/20W_51_5%_0201 SVID_CLK
    15 VSSSA_SENSE VORTNC SCLK
    28 PR0827 1 2 1/20W_10_5%_0201 SVID_CLK 14
    CSSUMA 18 SVID_DATA
    CSSUMA SDIO
    29 PR0868 1 2 0_0201_SP SVID_DATA 14
    CSSUMB 19 -SVID_ALERT
    CSSUMB ALT# -SVID_ALERT 14
    CSSUMC 20
    CSSUMC
    PR0828 1 2 1/20W_61.9K_1%_0201 38 PWM_SA
    GND_MP2949 PWM6 PWM_SA 70
    39 PWM_GT
    PC0807 1 2 330P_25V_K_X7R_0201
    PWM5
    40 PWM_GT 69
    GND_MP2949 PWM4
    PR0829 PR0830 24 41 PR0866 1 2 0_0201_SP PWM_CORE3
    1/20W_118K_1%_0201 1/20W_0_5%_0201 PR0832 1 2 1/20W_2.1K_1%_0201 21 IREF PWM3
    42 PR0833 1 2 0_0201_SP PWM_CORE3 68
    PR0831 1 2 1/20W_51.1K_1%_0201 PWM_CORE2
    1 2 1 2 22 IMONA PWM2
    43 PWM_CORE2 68
    C
    GND_MP2949 PWM_CORE1 C
    23 IMONB PWM1 PWM_CORE1 68
    CS_CORE1
    PC0808 PR0835 2 1 1/20W_10K_1%_0201 IMONC PR0836 1 2 0_0201_SP CS_CORE1 68
    PR0834 1 2 1/20W_619K_1%_0201 CS_CORE2
    180P_25V_K_X7R_0201 PR0867 1 2 0_0201_SP CS_CORE3 CS_CORE2 68
    GND_MP2949 CS_CORE3 68
    1 2 PC0809 1 2 47P_25V_J_NPO_0201 5 PR0837 1 2 1/20W_1.5K_1%_0201
    CS1
    @ PR0839 4 PR0838 1 2 1/20W_1.5K_1%_0201
    CS2
    1/20W_0_5%_0201 3 PR0865 1 2 1/20W_1.5K_1%_0201 CSSUMA
    CS3
    1 2 25 2
    VCC1R8_MP2949 PR0842
    ADDR_P CS4
    1 CS_GT
    CS5 CS_GT 69
    0_0201_SP 48
    CS6
    PSYS 1 2 46 PR0840 1 2 1/20W_1.5K_1%_0201 CSSUMB
    65 PSYS PR0844
    PSYS
    47 CS_SA
    VIN_SEN CS_SA 70

    AGND
    0_0201_SP
    TEMP_FAULT 1 2 45 PR0841 1 2 1/20W_1.5K_1%_0201 CSSUMC
    68,69,70 TEMP_FAULT TEMP
    1

    49
    PC0810 PR0845
    1000P_25V_K_X7R_0201 1/20W_7.87K_1%_0201 PR0843 1 2 1/20W_2M_5%_0201
    VSYS15

    1
    2 1
    PC0812 PR0848
    2

    1UC_6.3VC_KC_X5RC_0402 1/20W_49.9K_1%_0201
    PR0846

    1
    0_0201_SP 2
    1

    2
    PR0847
    VCC1R8_MP2949
    1

    GND_MP2949 1/20W_133K_1%_0201 PC0811


    2

    GND_MP2949 PR0851 0.01U_25V_K_X7R_0201


    1/20W_130_1%_0201 2

    2
    GND_MP2949
    2

    GND_MP2949 GND_MP2949
    GND_MP2949 GND_MP2949
    1
    1
    1

    PR0850 @ PJ0801
    PR0858 PR0860 PR0862 0_0201_SP HIGHS_WS83040-S0171-HF PR0849
    1/20W_10K_1%_0201 1/20W_10K_1%_0201 1/20W_10K_1%_0201 IMVP_PMBUS_EN 1 2 1 0_0402_SP
    PMB_CLK_IMVP 2 1 1 2
    B PMB_DATA_IMVP 3 2 B
    2
    2

    4 3
    2

    @ @ @ 4
    5 GND_MP2949
    GND1
    CSSUMA CSSUMB CSSUMC 6
    GND2
    1

    1
    1

    PR0859 PR0861 PR0863


    1/20W_10K_1%_0201 1/20W_10K_1%_0201 1/20W_10K_1%_0201
    Active PWM Pins
    2

    2
    2

    @ @ @
    MFR_PHASE_CFG[4:0]
    Rail A Rail B Rail C

    GND_MP2949 GND_MP2949 GND_MP2949


    00100b 1,2,3,4 5 6

    00111b 1,2,3 4,5 6

    WHL- U42 01001b 1,2,3 5 6

    PU401 MP2949AGQKT-024E-C669-Z 01100b 1,2 4,5 6

    PR0833 0_0201_5% 01110b 1,2 5 6

    PR0836 0_0201_5% 10001b 1 5 6

    PR0838 1.5K_0201_1%
    A A

    PR0832 2.1K_0201_1%

    PR0831 51.1K_0201_1%

    PC0807 330P_0201_25V7-K

    PR0839 NA Security Classification LC Future Center Secret Data Title


    Issued Date Deciphered Date DC/DC IMVP8 (MP2949AGQKT)
    PR0846 0_0201_5%
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Vinafix.com Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 108 of 120
    5 4 3 2 1
    5 4 3 2 1

    VSYS15 EMC@
    PL0901
    MPZ1608S300AT_2P~D
    1 2 EMC@ EMC@ RF@ For WHL VCCCPUCORE
    2pcs 330uF +18pcs 22uF+4pcs 10uF+10pcs 1uF

    10U_25V_M_X5R_0603

    10U_25V_M_X5R_0603
    10U_25V_M_X5R_0603

    2200P_25V_K_X7R_0201

    1U_25V_K_X5R_0402

    100P_25V_J_NPO_0201
    1

    68U_D3L_25VM_R70M

    68U_D3L_25VM_R70M
    68U_D3L_25VM_R70M
    +
    1 1 1 1 1 1 1 RF@

    PC0907

    @ PC0908

    PC0911
    PC0906

    PC0910
    PC0909
    Table PC0901,PC0902,PC0903 1 1 1 PC0904
    22U_25V_M_B2_ESR100M_H1.9 PC0981
    + + +

    @ PC0901

    @ PC0903
    PC0902
    Panasonic: 25TQC68MYF 2 2 2 2 2 2 2 2
    47P_25V_J_NPO_0201
    KEMET: T521D686M025ATE070
    2 2 VCCCPUCORE VCCCPUCORE
    2
    Table PC0914,PC0915
    U42
    Panasonic ETPE330MA9L
    TDC= 48A NEC TOKIN TEPSGB20E337M9
    D D
    IccMax= 70A KEMET T520B337M2R5ATE009

    VCC3M TABLE PL0902


    1

    15
    1

    1
    8
    + PC0915
    1 +
    PC0912 PC0914 330U_2.5V_M_B2_ESR9M_H1.9

    VIN1
    VIN2

    BST
    PR0901 1U_25V_K_X5R_0402 330U_2.5V_M_B2_ESR9M_H1.9
    2
    0_0402_SP
    1 2 14
    VCC
    2 CYNTEC CMLE062E-R15MS0R907-88 VCCCPUCORE 2
    1 PU0901
    PC0916 MP86901-CGLT-C669-Z_TQFN21-15_3X4
    1UC_6.3VC_KC_X5RC_0402
    2 PL0902
    2 SW1

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    3 0.15UH_CMLE062ER15MS0R90788_40A_20%
    SW2 1 2
    13 4
    AGND SW3

    1 1 1 1 1 1 1 1 1 1

    PC0920

    PC0925
    PC0919

    PC0922

    PC0927
    PC0921

    PC0924

    PC0926
    PC0918

    PC0923
    PWM_CORE1 9 11 TEMP_FAULT
    67 PWM_CORE1 PWM VTEMP/FLT TEMP_FAULT 67,69,70
    MODE_SEL 10 12 CS_CORE1
    1 EMC@
    67,69,70 MODE_SEL SYNC CS CS_CORE1 67 2 2 2 2 2 2 2 2 2 2
    PC0917
    1000PC_50VC_KC_X7RC_0201

    PGND1

    PGND2

    PGND3
    2
    @ @

    EMC@

    1
    PR0902

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    Table 1/4W_1_5%_0603

    2
    SYNC (MODE_SEL) 1 1 1 1 1 1 1 1 1 1

    PC0929

    PC0933
    PC0928

    PC0934
    PC0932

    PC0935
    PC0931
    PC0930

    PC0936

    PC0937
    High Normal Operation 2 2 2 2 2 2 2 2 2 2
    H.Z. Standby Mode
    Low Diode Emulation Mode
    @ @

    VSYS15 EMC@

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    PL0903
    MPZ1608S300AT_2P~D
    1 2 EMC@ EMC@ RF@
    1 1 1 1 1 1

    @ PC0946
    PC0940

    @ PC0947
    PC0938

    PC0941
    PC0939
    10U_25V_M_X5R_0603
    10U_25V_M_X5R_0603

    10U_25V_M_X5R_0603

    2200P_25V_K_X7R_0201

    1U_25V_K_X5R_0402

    100P_25V_J_NPO_0201
    C 2 2 2 2 2 2 C
    1
    @ @ @
    1 1 1 1 1 1 1 RF@

    PC0951

    PC0955
    PC0950
    +

    PC0954
    @ PC0952

    PC0953
    PC0949
    22U_25V_M_B2_ESR100M_H1.9 PC0993
    47P_25V_J_NPO_0201
    2 2 2 2 2 2 2 2

    10U_6.3V_M_X5R_0402

    22U_6.3V_M_X5R_0603
    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402

    22U_6.3V_M_X5R_0603
    10U_6.3V_M_X5R_0402

    22U_6.3V_M_X5R_0603
    1 1 1 1 1 1 1

    PC0966
    PC0964
    PC0961

    PC0962

    PC0965
    PC0963

    PC0967
    2 2 2 2 2 2 2
    VCC3M
    15
    1
    8

    TABLE PL0904
    VIN1
    VIN2

    BST

    1
    PR0903 PC0958
    0_0402_SP 1U_25V_K_X5R_0402
    1 2 14
    VCC 2
    CYNTEC CMLE062E-R15MS0R907-88 VCCCPUCORE
    1 PU0902
    PC0959 MP86901-CGLT-C669-Z_TQFN21-15_3X4

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402
    2 PL0904 1 1 1 1 1 1 1
    2 SW1 1 1 1

    PC0977

    PC0980
    PC0971

    PC0975
    3

    PC0973

    PC0978
    PC0974
    0.15UH_CMLE062ER15MS0R90788_40A_20%

    PC0972

    PC0976

    PC0979
    SW2
    13 4 1 2
    AGND SW3
    2 2 2 2 2 2 2 2 2 2
    PWM_CORE2 9 11 TEMP_FAULT
    67 PWM_CORE2 PWM VTEMP/FLT

    MODE_SEL 10 12 CS_CORE2
    1 EMC@
    SYNC CS CS_CORE2 67 PC0960
    1000PC_50VC_KC_X7RC_0201
    PGND1

    PGND2

    PGND3

    EMC@
    1
    5

    PR0904
    1/4W_1_5%_0603
    2

    B B

    VSYS15 EMC@
    PL0905
    MPZ1608S300AT_2P~D
    1 2 EMC@ EMC@ RF@
    2200P_25V_K_X7R_0201
    10U_25V_M_X5R_0603

    10U_25V_M_X5R_0603

    10U_25V_M_X5R_0603

    1U_25V_K_X5R_0402

    100P_25V_J_NPO_0201

    1 1 1 1 1 1 1 1 RF@
    PC0986
    PC0983

    PC0984

    PC0987
    @ PC0985

    PC0988

    PC0982 +
    PC0989
    22U_25V_M_B2_ESR100M_H1.9 47P_25V_J_NPO_0201
    2 2 2 2 2 2 2
    2

    VCC3M
    15
    1
    8

    TABLE PL0909
    1
    VIN1
    VIN2

    BST

    PR0905 PC0990
    0_0402_SP 1U_25V_K_X5R_0402
    1 2 14
    VCC 2
    CYNTEC CMLE062E-R15MS0R907-88 VCCCPUCORE
    1 PU0903
    PC0991 MP86901-CGLT-C669-Z_TQFN21-15_3X4
    1UC_6.3VC_KC_X5RC_0402
    2 PL0909
    2 SW1
    3 0.15UH_CMLE062ER15MS0R90788_40A_20%
    SW2
    13 4 1 2
    AGND SW3

    PWM_CORE3 9 11 TEMP_FAULT
    67 PWM_CORE3 PWM VTEMP/FLT
    MODE_SEL 10 12 CS_CORE3
    1 EMC@
    SYNC CS CS_CORE3 67 PC0992
    1000PC_50VC_KC_X7RC_0201
    PGND1

    PGND2

    PGND3

    EMC@
    1
    5

    PR0906
    A
    1/4W_1_5%_0603 A
    2

    Vinafix.com Security Classification LC Future Center Secret Data Title


    Issued Date Deciphered Date DC/DC VCCCPUCORE (MP86901C)

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 109 of 120
    5 4 3 2 1
    5 4 3 2 1

    For WHL VCCGFXCORE_I


    D
    1pcs 330uF +14pcs 22uF+4pcs 10uF+10pcs 1uF D

    VCCGFXCORE_I
    Table PC1001
    Panasonic ETPE330MA9L
    NEC TOKIN TEPSGB20E337M9
    KEMET T520B337M2R5ATE009
    1
    + PC1001
    330U_2.5V_M_B2_ESR9M_H1.9

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    VSYS15 1 1 1 1 1 1 1 1 1 1

    PC1013
    PC1011

    PC1019
    PC1012

    PC1015

    PC1017

    PC1018
    PC1016

    PC1020
    PC1010
    EMC@
    PL1001
    MPZ1608S300AT_2P~D 2 2 2 2 2 2 2 2 2 2
    C 1 2 EMC@ EMC@ RF@ C

    @ @

    10U_25V_M_X5R_0603

    2200P_25V_K_X7R_0201
    10U_25V_M_X5R_0603
    10U_25V_M_X5R_0603

    1U_25V_K_X5R_0402

    100P_25V_J_NPO_0201
    1
    1 1 1 1 1 1 1 RF@

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    +

    22U_6.3V_M_X5R_0603
    PC1002

    PC1004

    PC1008
    PC1007
    @ PC1006
    PC1005

    PC1009
    22U_25V_M_B2_ESR100M_H1.9 PC1062
    47P_25V_J_NPO_0201
    2 2 2 2 2 2 2 2
    1 1 1 1 1 1 1 1 1 1

    PC1024

    PC1032
    PC1027

    PC1028

    PC1031
    PC1025
    PC1022

    PC1030
    PC1026
    PC1023
    VCCGFXCORE_I 2 2 2 2 2 2 2 2 2 2

    TDC= 18A
    @ @ @
    TABLE PL1002 IccMax= 31A @
    VCC3M
    15
    1
    8

    1
    CYNTEC CMLE062E-R15MS0R907-88
    VIN1
    VIN2

    BST

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    PR1001 PC1014
    0_0402_SP 1U_25V_K_X5R_0402
    1 2 14
    VCC
    2 VCCGFXCORE_I
    1 PU1001 1 1 1 1 1 1

    PC1035
    PC1033

    PC1034

    PC1036

    @ PC1039
    @ PC1038
    PC1021 MP86901-CGLT-C669-Z_TQFN21-15_3X4
    1UC_6.3VC_KC_X5RC_0402
    2 PL1002
    2 SW1
    3 0.15UH_CMLE062ER15MS0R90788_40A_20% 2 2 2 2 2 2
    13 SW2
    4 1 2
    EMC@ EMC@
    AGND SW3

    PWM_GT 9 11 TEMP_FAULT @ @
    67 PWM_GT PWM VTEMP/FLT TEMP_FAULT 67,68,70

    2200P_25V_K_X7R_0201

    0.1U_6.3V_K_X5R_0201
    MODE_SEL 10 12 CS_GT
    67,68,70 MODE_SEL SYNC CS CS_GT 67 1 EMC@

    22U_6.3V_M_X5R_0603
    10U_6.3V_M_X5R_0402

    22U_6.3V_M_X5R_0603
    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402
    10U_6.3V_M_X5R_0402

    22U_6.3V_M_X5R_0603
    PC1029
    PGND1

    PGND2

    PGND3

    1000PC_50VC_KC_X7RC_0201 2 2
    B 2 B

    PC1061
    PC1060
    1 1 1 1 1 1 1

    PC1045
    PC1043

    PC1046
    PC1040

    PC1042
    PC1041

    PC1044
    5

    1 1
    Table EMC@
    1
    2 2 2 2 2 2 2
    PR1002
    SYNC (MODE_SEL) 1/4W_1_5%_0603

    @ @ @
    2

    High Normal Operation


    H.Z. Standby Mode
    Low Diode Emulation Mode

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    1 1 1 1 1 1 1 1 1 1

    PC1052

    PC1056

    PC1058
    PC1050

    PC1057
    PC1055
    PC1054
    PC1051

    PC1053

    PC1059
    2 2 2 2 2 2 2 2 2 2

    A A

    Vinafix.com Security Classification LC Future Center Secret Data Title


    Issued Date Deciphered Date DC/DC VCCGFXCORE_I (MP86901C)

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 110 of 120
    5 4 3 2 1
    5 4 3 2 1

    D D

    VSYS15 EMC@ For WHL VCCSA


    PL1101 7pcs 22uF+3pcs 10uF+7pcs 1uF
    MPZ1608S300AT_2P~D
    1 2 EMC@ EMC@ RF@

    22U_25V_M_B2_ESR100M_H1.9

    2200P_25V_K_X7R_0201
    10U_25V_M_X5R_0603

    10U_25V_M_X5R_0603

    1U_25V_K_X5R_0402

    100P_25V_J_NPO_0201
    1
    1 1 1 1 1 1 RF@
    VCCSA
    +

    PC1101

    PC1102

    PC1103

    PC1105

    PC1107
    PC1106
    PC1135
    2 2 2 2 2 2 2
    47P_25V_J_NPO_0201 VCCSA

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    TDC= 4A
    C 1 1 1 1 1 1 1 1 C

    PC1111

    PC1118
    PC1112
    PC1108

    PC1113

    PC1117
    PC1109

    PC1110
    VCC3M TABLE PL1102
    2 2 2 2 2 2 2 2

    PU1101
    VCCSA
    1

    6
    MP86901-AGQT-C669-Z_TQFN13_3X3 CYNTEC: CMLB042T-R47MS @ @ @

    VIN1

    VIN2
    PR1101 13 1
    TDK: SPM4020T-R47M-LR
    BST
    0_0402_SP
    1 2 12 PC1114
    VCC 1U_25V_K_X5R_0402
    2

    10U_6.3V_M_X5R_0402

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    10U_6.3V_M_X5R_0402

    10U_6.3V_M_X5R_0402
    1 2 PL1102
    SW1
    PC1115 0.47UH_CMLB042T-R47MS_7A_20%
    1UC_6.3VC_KC_X5RC_0402 3 1 2 1 1 1 1 1
    SW2

    PC1121

    PC1123
    PC1122
    PC1119

    PC1120
    2 11
    AGND
    2 2 2 2 2
    EMC@ EMC@

    2200P_25V_K_X7R_0201

    0.1U_6.3V_K_X5R_0201
    PWM_SA 7 9 TEMP_FAULT
    67 PWM_SA PWM VTEMP/FLT TEMP_FAULT 67,68,69
    MODE_SEL 8 10 CS_SA
    67,68,69 MODE_SEL SYNC CS CS_SA 67
    B 1 EMC_NS@ 2 2 B

    PC1133

    PC1134
    PGND1

    PGND2

    PC1116
    1000PC_50VC_KC_X7RC_0201
    2 1 1
    Table

    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402
    1UC_6.3VC_KC_X5RC_0402

    1UC_6.3VC_KC_X5RC_0402
    4

    SYNC (MODE_SEL) EMC_NS@ 1 1 1 1 1 1 1

    PC1131
    PC1129
    PC1127

    PC1130
    PC1128
    PC1126

    PC1132
    PR1102
    High Normal Operation 1/4W_2.2_5%_0603
    2 2 2 2 2 2 2
    H.Z. Standby Mode
    Low Diode Emulation Mode

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date Deciphered Date DC/DC VCCSA (MP86901A)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 111 of 120
    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    D D

    PJ1202
    2 1
    VCC1R2AP 2 1 VCC1R2A
    @ JUMP_43X118

    PJ1203
    2 1
    VCC1R2AP 2 1 VCC1R2A
    @ JUMP_43X118

    PJ1204
    2 1
    VCC0R6BP 2 1 VCC0R6B
    PJ1201
    2 1 EMC@ EMC@ RF_NS@ RF_NS@ @ JUMP_43X39
    VSYS15 2 1

    4700PC_25VC_KC_X7RC_0402
    10U_25V_K_X5R_0805_H1.25

    10U_25V_K_X5R_0805_H1.25
    10U_25V_K_X5R_0805_H1.25

    @ JUMP_43X79

    0.1UC_25VC_KC_X7RC_0402
    PJ1205
    2 1
    VCC2R5AP 2 1 VCC2R5A

    47P_25V_J_NPO_0201
    100P_25V_J_NPO_0201
    1 1 1 1 1
    PC1201

    PC1203

    PC1204

    PC1205
    PC1202

    2 2
    @ JUMP_43X39

    PC1226
    PC1225
    PR1201 PC1206
    0_0402_SP 0.22U_25V_KC_X5R_0402
    VCC1R2A
    2 2 2 2 2 1 2 1 2
    Table PL1201
    1 1 TDC= 7.8A
    @ CYNTEC CMLB053T-R68MS Max = 9A
    C
    VCC3M NEC-TOKIN: MPLCH0530LR68G C

    OCP = 11A

    10
    1
    PL1201

    VIN

    BST
    0.68UH_CMLB053T-R68MS_17A_20%
    PR1202 8 9 1R2A_SW 1 2 EMC@ EMC@
    VPPIN SW VCC1R2AP

    2200P_25V_K_X7R_0201
    1/16W_5.1_5%_0402

    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603

    0.1U_6.3V_K_X5R_0201
    1 2 3
    3V3
    2
    PR1203 PU1201 13 1 1 1 1 1 1 1 1 2 2
    FB

    PC1215
    PC1211

    PC1213
    PC1208

    PC1210

    PC1216
    PC1212

    PC1223
    PC1209

    PC1214
    PC1207 1/20W_100K_5%_0201 NB687GQ-C669-Z
    22U_6.3V_M_X5R_0603 1 2 +1.2V_PG 12
    1 PG
    6
    VDDQ 2 2 2 2 2 2 2 2 1 1
    PC1218 1 2 1UC_6.3VC_KC_X5RC_0402 AGND_1R2A @ PR1205 PC1217
    1/20W_0_5%_0201 220P_25V_K_X7R_0201
    DDR_VTT_PG_CTRL PR1204 1 2 0_0201_SP +1.2V_EN1 16 1 2 1 2 @ @
    DDR_VTT_PG_CTRL EN1
    5 1A
    VTT VCC0R6BP
    -PCH_SLP_S4 PR1206 1 2 0_0201_SP +1.2V_EN2 15
    <13,17,56,65> -PCH_SLP_S4 EN2 1 EMC_NS@

    VTTREF
    1A

    MODE

    1
    1
    AGND

    PGND
    11 2 PC1224
    VPP VCC2R5AP 1000PC_50VC_KC_X7RC_0201 PR1207 PR1208
    @ PR1209 1 2 1/20W_0_5%_0201 PC1219 2 1/20W_499_1%_0201 1/20W_102K_1%_0201
    <65> A_ON
    22U_6.3V_M_X5R_0603

    14
    4

    7
    2
    1

    2
    2
    EMC_NS@

    1
    0.22U_25V_KC_X5R_0402

    AGND_1R2A
    PR1213 PR1211
    22U_6.3V_M_X5R_0603 1/4W_2.2_5%_0603 1/20W_100K_1%_0201
    1

    2
    PC1220

    PR1212 PR1210

    2
    0_0402_SP 0_0201_SP 1 1
    B
    PC1221

    1 2 B
    1 PC1222
    2

    22U_6.3V_M_X5R_0603 AGND_1R2A
    2 2

    AGND_1R2A

    AGND_1R2A

    TABLE NB687GQ:EN1/EN2 TABLE NB687GQ:MODE


    State EN1 EN2 VDDQ VTTREF VTT VPP State USM Fs Resistor to GND
    S0 High High ON ON ON ON M1 NO 700KHz 0
    S3 Low High ON ON OFF(High-Z) ON M2 YES 700KHz 90K
    S4/S5 Low Low OFF OFF OFF OFF M3 NO 500KHz 150K
    A
    Others High Low OFF OFF OFF OFF M4 YES 500KHz >230K or Float A

    Security Classification LC Future Center Secret Data Title


    Issued Date Deciphered Date DC/DC VCC1R2A(NB687GQ)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.00
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. C
    Tuesday, December 18, 2018
    T490&T590
    Date: Sheet 112 of 125

    5 4 3 2 1
    5 4 3 2 1

    D D

    @ PJ1301
    JUMP_43X79
    VCC1R05_SUS
    1 2 EMC@ EMC@ RF_NS@ RF_NS@
    VSYS15 1 2 TDC = 7.82A
    10U_25V_K_X5R_0805_H1.25
    10U_25V_K_X5R_0805_H1.25
    10U_25V_K_X5R_0805_H1.25

    2200PC_50VC_KC_X7RC_0402
    0.1UC_25VC_KC_X5RC_0402

    68PC_50VC_JC_NPOC_0402

    47PC_50VC_JC_NPOC_0402

    1
    1 1 PR1301 TABLE PL1301

    PC1306

    PC1307
    1 1 1 1 1 1/20W_150K_5%_0201 PR1302
    PC1303
    PC1302

    PC1304
    PC1301

    PC1305
    0_0402_SP
    1 2 NEC-TOKIN: MPLCG0630L1R0

    2
    2 2
    2 2 2 2 2 CYNTEC : PCMC063T-1R0MN
    C
    1 VCC1R05_SUS C
    PC1310
    0.22U_25V_KC_X5R_0402
    2

    11

    10
    PL1301 @ PJ1302

    CLM

    BST
    1UH_MPLCG0630L1R0_16.8A_20% JUMP_43X118
    1R05_SUS_VIN 1 9 1R05_SUS_SW 1 2 EMC@ EMC@ 2 1
    VIN SW 2 1

    2200PC_50VC_KC_X7RC_0402
    0.1UC_6.3VC_KC_X7RC_0402
    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603

    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    PR1303
    0_0201_SP EMC_NS@ 1
    1 2 1R05_SUS_EN 15 PC1311 1 1 1 1 1 1 1 1
    <56> SUS_ON2 EN

    PC1317

    PC1318

    PC1319
    PC1314

    PC1316
    PC1315
    PC1313
    680PC_50VC_KC_X7RC_0402 PC1312
    1 13 220P_25V_K_X7R_0201
    FB 2
    PC1308 PU1301 PR1304 2 2 2 2 2 2 2 2

    1
    0.1UC_16VC_KC_X7RC_0402 NB693GQ-C669-Z_QFN16_3X3 1/20W_100K_5%_0201
    2 12 1 2 @ PR1308 PR1305
    PG VCC3M 1/20W_825K_1%_0201 1/20W_10_1%_0201 @
    1 2

    1
    PR1306

    2
    0_0201_SP PR1309
    1 2 14 16 1R05_SUS_VIN 1/10W_4.7_5%_0603
    MODE NC2
    PR1307 EMC_NS@

    1
    1/16W_5.1_5%_0402

    1
    1 2 3 8 1R05_SUS_SW PR1312
    VCC3M 3V3 NC1
    1/20W_499_1%_0201 PR1310
    1/20W_7.5K_1%_0201

    PGND1

    PGND3
    PGND2

    PGND4

    PGND5

    2
    1
    PC1309
    2

    5
    4

    7
    2.2UC_10VC_KC_X5RC_0603

    1
    2 PR1311
    1/20W_10K_1%_0201
    B B

    2
    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date Deciphered Date DC/DC VCC1R05_SUS(NB693)
    Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 113 of 125
    5 4 3 2 1
    5 4 3 2 1

    D D

    VCC1R0VIDEO
    @ PJ1401
    JUMP_43X79
    1 2 SWG_EMC@ Max = 0.3A
    VCC3M 1 2

    2200P_25V_K_X7R_0201
    1 1 1

    PC1409
    PC1401 PC1402 Table PL1401
    0.1U_6.3V_K_X5R_0201 10U_6.3V_M_X5R_0402
    SWG@
    SWG_EMC@ 2 2 2
    Murata :DFE252012F-0R47M=P2 VCC1R0VIDEO
    SWG@ Cyntec :HMLQ25201B-R47M
    PU1401
    BD9B304QWZE2_UMMP008AZ020-8-9 SWG@
    PC1403
    1 0.1U_6.3V_K_X5R_0201
    C VIN C
    3 1 2 SWG@
    BOOT
    PL1401 @ PJ1402
    2 0.47UH DFE252012F-R47M 5.8A_20% JUMP_43X79
    <97> 1R0VIDEO_EN EN
    4 1 2 SWG_EMC@ 1 2
    SW 1 2

    2200P_25V_K_X7R_0201
    22U_6.3V_M_X5R_0603
    22U_6.3V_M_X5R_0603
    1 8
    GND
    @ PC1404

    1
    0.1U_6.3V_K_X5R_0201 SWG@
    5 7 PR1401
    1
    PC1405 1 1 1 1
    SWG_EMC@
    2 MODE FB

    SWG@ PC1407
    SWG@ PC1406

    PC1410
    1/20W_75K_1%_0201 100P_25V_J_NPO_0201 PC1408

    E-PAD
    6 SWG@ 0.1U_6.3V_K_X5R_0201
    FREQ 2

    2
    2 2 2 2

    1
    PR1402
    1/20W_300K_1%_0201
    SWG@

    2
    B B

    VCC5M VCC1R0VIDEO
    1

    PR1403 PR1404
    1/16W_100K_5%_0402 1/10W_10_5%_0603
    SWG@ SWG@
    2

    2
    3

    D
    5 SWG@
    G PQ1401B
    6

    D UM6K33N_UMT6
    A 1R0VIDEO_EN 2 SWG@ S A
    4

    G PQ1401A
    UM6K33N_UMT6
    S
    Security Classification LC Future Center Secret Data Title
    1

    Issued Date Deciphered Date DC/DC VCC1R0VIDEO


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. T490&T590
    Date: Tuesday, December 18, 2018 Sheet 114 of 125
    5 4 3 2 1

    Vinafix.com
    5 4 3 2 1

    D D

    PR1514
    0_0201_SP
    1 2
    <72> GFXCORE_D_EN
    VCC1R8VIDEO_AON VCC1R8_SUS MLCCs must be placed
    symmetrically on Top and Bottom. SWG_EMC@
    PL1510

    1
    1
    SWG@ MPZ1608S300AT_2P~D
    PR1521 @ PR1551 SWG_EMC@ SWG_EMC@ 1 2
    VSYS15

    10U_25V_K_X5R_0805_H1.25

    10U_25V_K_X5R_0805_H1.25
    10U_25V_K_X5R_0805_H1.25
    1/20W_10K_1%_0201 1/20W_10K_1%_0201

    10U_25V_K_X5R_0805_H1.25
    1000PC_25VC_KC_X7RC_0402
    TABLE : PC1509 / PC1510

    2
    2

    1 1 1 1 1 1 1

    SWG@
    PC1504
    PC1502

    SWG@
    SWG@

    PC1505
    PC1503

    SWG@
    PC1506
    PR1523 PC1501 SWG@
    0_0201_SP UGATE1_VGA 0.1UC_25VC_KC_X5RC_0402 PC1556
    1 2 PSI_VGA 0.1UC_25VC_KC_X5RC_0402
    1st: 2R5TPE470M7 PANASONIC
    <72> VGA_CORE_PSI 2 2 2 2 2 2 2
    SWG@ SWG@ 2nd : T520V477M2R5ATE007 KEMET
    PR1502 PC1507
    1

    1 1/10W_1_1%_0603 0.22U_25V_KC_X5R_0402
    @ PR1550 1 2 1 2
    @ PC1539 1/20W_10K_1%_0201 PR1503
    0.1UC_25VC_KC_X5RC_0402 0_0201_SP SWG@ SWG@
    Table PL1501、PL1502
    2 1 2 PR1580 PQ1501

    BOOT1_VGA
    <72> VIDEO_PWM_VID
    2

    2
    3
    4
    8
    PHASE1_VGA 1/16W_1.5_1%_0402 SIZ980DT-T1-GE3 2N POWERPAIRR6X5-8 CYNTEC : CMLE063T-R15MS0R907
    UGATE1_VGA 1 2 1
    SWG@ SWG@
    PR1505 PL1501
    GFX_AGND 1/20W_20.5K_1%_0201 0.15UH_CMLE063T-R15MS0R907_38A_20%
    VREF_272 1 2 7 PHASE1_VGA 1 2 SWG_EMC@SWG_EMC@
    VCCGFXCORE_D

    0.1UC_25VC_KC_X7RC_0402
    SWG@ LGATE1_VGA LGATE1_VGA 6

    2200PC_50VC_KC_X7RC_0402
    @ PC1515 PR1506
    2 SWG_EMC_NS@

    470U_D2E_2.5VM_R7M
    470U_D2E_2.5VM_R7M

    10UC_6.3VC_MC_X5RC_0603
    10UC_6.3VC_MC_X5RC_0603
    10UC_6.3VC_MC_X5RC_0603

    10UC_6.3VC_MC_X5RC_0603
    C
    1 1 C
    2700PC_25VC_KC_X7RC_0201 1/20W_6.19K_1%_0201 PC1508 1 1
    1 2 + +

    PC1586
    1 2

    PC1585
    GFX_AGND 470PC_50VC_KC_X7RC_0201
    1

    VID_VGA

    PSI_VGA

    SWG@ PC1510
    SWG@ PC1509
    1 1 1 1

    VIDBUF

    5
    GFX_AGND 1

    PC1513
    PC1512
    PC1511

    PC1514
    2
    SWG@ 2 2 2 2
    PR1508 PR1504
    SWG@ SWG@ 1/20W_4.32K_1%_0201 2 2 2 2
    1/4W_2.2_5%_0603
    PR1509 PR1510
    SWG_EMC_NS@
    2

    2
    6

    SWG@
    SWG@
    SWG@
    1/20W_309_1%_0201

    SWG@
    1/20W_16.5K_1%_0201

    1
    1

    1 2 1 2

    PSI
    VID

    HG1
    VIDBUF

    EN

    BST1
    GFX_AGND
    PR1501
    1/20W_100_1%_0201 SWG@ TABLE : PQ1501,PQ1502
    SWG@ SWG@PC1516 1 2 4700PC_25VC_KC_X5RC_0201 REFIN_272 7 20 PC1518
    GFX_AGND REFIN PH1
    4.7UC_6.3VC_KC_X5RC_0603
    MLCCs must be placed
    2

    SWG@PC1517 1 2 0.01UC_25VC_KC_X7RC_0402 VREF_272 8 19 1 2


    GFX_AGND VREF LG1 Infineon : SIZ980DT
    PR1513 SWG@PR1512 1 2 1/20W_34K_1%_0201
    SWG@
    21 AOS : AON6982 symmetrically on Top and Bottom.
    GFX_AGND FS 9 PU1501
    0_0201_SP FS PAD
    NCP81278TMNTXG_QFN20_3X3
    1 2 FBRTN 10 18 MLCCs must be placed SWG_EMC@
    <69> GPU_GND_SENSE FBRTN PVCC VCC5M
    SWG@
    SWG@
    PC1526
    SWG@
    PR1515
    symmetrically on Top and Bottom. PL1511
    MPZ1608S300AT_2P~D
    SWG@ FB_VGA 11 17
    PC1525
    1
    47PC_50VC_JC_NPOC_0402 1/20W_49.9_1%_0201 PC1527
    FB LG2 SWG_EMC@SWG_EMC@ 1 2
    1 2 VSYS15

    10U_25V_K_X5R_0805_H1.25
    10U_25V_K_X5R_0805_H1.25
    1000PC_25VC_KC_X7RC_0402
    100P_25V_J_NPO_0201

    10U_25V_K_X5R_0805_H1.25
    1 2 FB1_VGA

    10U_25V_K_X5R_0805_H1.25
    1 2 COMP_VGA 12 16
    COMP/ILMT PH2
    PGOOD

    PR1516
    0_0201_SP 2 PR1517
    10PC_50VC_JC_NPOC_0402
    VCCGFXCORE_D
    BST2
    HG2

    1 2 1 2 1 2 FB2_VGA 1 2
    <69> GPU_VDD_SENSE 1 1 1 1 1 1 EDP-Cont = 30A

    SWG@
    PC1524
    PC1520

    SWG@
    PC1523
    SWG@
    PC1522
    SWG@
    PC1521
    SWG@ PC1519 1
    1/20W_10K_1%_0201 PC1528 PR1518 PR1520 0.1UC_25VC_KC_X5RC_0402 SWG@
    EDP-Peak= 60.1A
    14
    13

    15

    SWG@ 100PC_50VC_JC_NPOC_0402 1/20W_82K_1%_0201 1/10W_1_1%_0603 PC1557


    BOOT2_VGA 1 2 2 2 2 2 2 2 0.1UC_25VC_KC_X5RC_0402
    SWG@ SWG@ OCP = 87A
    1

    2
    1

    PR1552
    PR1511 1/16W_36K_1%_0402 UGATE2_VGA
    1/20W_100_1%_0201 SWG@ 1
    SWG@ SWG@
    2

    PC1529
    2

    0.22U_25V_KC_X5R_0402
    GFXCORE_D_PWRGD

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