Analog Electronics

Singnal and System
Analog Electronics
Analog Electronics
Chapter 1 – Diode Circuits ............................................................................................................................. 2
Solutions............................................................................................................................................................... 8
Chapter 2 – BJT ................................................................................................................................................ 24
Solutions............................................................................................................................................................. 31
Chapter 3 – MOSFET ...................................................................................................................................... 48
Solutions............................................................................................................................................................. 51
Chapter 4 – OP-AMP ..................................................................................................................................... 56

Solutions............................................................................................................................................................. 72
Chapter 5 – Feedback Amplifier ............................................................................................................. 111

Solutions.......................................................................................................................................................... 113
Scan this QR code to report an

1 http://www.examdost.com
Error in this Document
Analog Electronics
Chapter 1 – Diode Circuits
01. Figure shows an electric voltage regulator. The zener 06. The forward resistance of the diode shown in Figure is
diode may be assumed to require a minimum current of 25 5Ω and the remaining parameters are same as those of an
mA for satisfactory operations. The value of R required for ideal diode. The dc component of the source current is[2002]
atisfactory voltage regulation of the circuit is [1991]
Vm Vm
(a) (b)
50 50 2
Vm 2Vm
(c) (d)
02. The depletion region or space charge region or 100  2 50
transition in a semiconductor p-n junction diode has
[1996]
07. The cut-in voltage of both Zener diode DZ and diode
(a) Electrons and holes
(b) Positive ions and electrons D shown in Figure is 0.7 V, while break down voltage of DZ
(c) Positive ions and negative ions is 3.3 V and reverse breakdown voltage of D is 5V. The
other parameters can be assumed to be the same as those
(d) Negative ions and holes of an ideal diode. The values of the peak output voltage
(e) No ions, electrons or holes ( V0 ) are [2002]
03. The mobility of an electron in a conductor is expressed

in terms of [1999]
(a) cm / V − s
2
(b) cm / V − s
(c) cm2 / V (d) cm2 / s
04. As the temperature is increased, the voltage across a

diode carrying a diode carrying a constant current (a) 3.3 V in the positive half cycle and 1.4 V in the negative
[1999] half cycle
(a) Increases (b) 4 V in the positive half cycle and 5 V in the negative half
cycle
(b) Decreases (c) 3.3 V in both positive and negative half cycles
(c) Remains constant (d) 4 V in both positive and negative half cycles
(d) May increase or decrease depending upon the doping 08. A voltage signal 10 sint is applied to the circuit with
levels in the junction ideal diodes, as shown in Figure. The maximum and
05. A diode whose terminal characteristics are related as minimum values of the output waveform Vout of the
V
 
circuit are respectively 10k [2003]
iD = Is e
VT 
, where Is is the reverse saturation current and
VT is the thermal voltage ( = 25mV ) , is biased at
ID = 2mA . Its dynamic resistance is: [2000]

(a) 25 ohms (b) 12.5 ohms
(c) 50 ohms (d) 100 ohms

Analog Electronics
(a) +10 V and –10 V (b) +4 V and –4 V (a) 0 mA (b) 0.5 mA

(c) +7 V and –4 V (d) +4 V and –7 V (c) 1 mA (d) 2 mA
09. The current through the Zener diode in figure is

[2004] 13. What are the states of the three ideal diodes of the
circuit shown in figure? [2006]
(a) 33 Ma (b) 3.3 mA

(c) 2 mA (d) 0 mA
10. The circuit in figure shows a full-wave rectifier. The D 1 ON, D 2 OFF, D 3 OFF
(a)
input voltage is 230V (RMS) single-phase ac. The peak
reverse voltage across the diodes D1 and D2 is [2004] (b) D 1 OFF, D 2 ON, D 3 OFF
(c) D 1 ON, D 2 OFF, D 3 ON
(d) D 1 OFF, D 2 ON, D 3 ON
14. Assuming the diodes D1 and D2 of the circuit shown in

(a) 100 2 V (b) 100 V figure to be ideal ones, the transfer characteristics of the
(c) 50 2 V (d) 50 V circuit will be [2006]
11. Assuming that the diodes are ideal in figure, the current
in D1 is [2004]
(a) 8 mA (b) 5 mA
(c) 0 mA (d) −3mA
12. Assume that D 1 and D 2 in Figure are ideal diodes. The

value of current I is: [2005]
15. The equivalent circuits of a diode, during forward

biased and reverse biased conditions, are shown in the
figure. [2008]

Analog Electronics
(a) vc1 = 10V, vc2 = 5V

(b) vc1 = 10V, vc2 = −5V
(c) vc1 = 5V, vc2 = 10V
If such a diode is used in clipper circuit of figure given (d) vc1 = 5V, vc2 = −10V
above, the output voltage ( V0 ) of the circuit will be
17. The block diagrams of two types of half wave rectifiers

are shown in the figure. The transfer characteristics of the
rectifiers are also shown within the block. [2008]
It is desired to make full wave rectifier using above two

half-wave rectifiers. The resultant circuit will be
16. In the voltage doubler circuit shown in the figure, the

switch 'S' is closed at t=0. Assuming diodes D1, and D2, to
be ideal, load resistance to be infinite and initial capacitor
voltages to be zero, the steady state voltage across
capacitors C1, and C2, will be [2008]

Analog Electronics
18. Assuming that the diodes in the given circuit are ideal,
the voltage Vo is [2010]
20. The I-V characteristics of the diode in the circuit given

below are [2012]
 v − 0.7
 A, v  0.7V
i =  500
 0 A, v  0.7V

The current in the circuit is
(a) 4V (b) 5V (a) 10mA (b) 9.3mA
(c) 6.67mA (d) 6.2mA
(c) 7.5V (d) 12.12V
21. In the circuit shown below, the knee current of the ideal
19. A clipper circuit shown below. [2011] Zener diode is 10mA. To maintain 5 V across RL, in Ω and
the minimum power rating of the Zener diode in mW
respectively are [2013]
Assuming forward voltage drops of the diodes to be 0.7V,

the input-output transfer characteristics of the circuit is
(a) 125 and 125 (b) 125 and 250
(c) 250 and 125 (d) 250 and 250
22. The sinusoidal ac source in the figure has an RMS value

20
of V . Considering all possible values of R L , the
2
minimum value of RS in  to avoid burnout of the Zener
diode is __________. [2014-02]

Analog Electronics
26. Consider the diode circuit shown below. The diodes D,

obeys the current-voltage characteristic
  V  
ID = IS  exp  D  − 1 

  nVT  
where n>1, VT>0, VD is the voltage across the diode and ID
is the current through it. The circuit is biased so that
voltage, V > 0 and current, I<0, If you had to design this
circuit to transfer maximum power from the current source
23. Assuming the diodes to be ideal in the figure, for the (I1) to a resistive load (not shown) at the output, what
values R1 and R2 would you choose? [2020]
output to be clipped, the input voltage v i must be outside
the range [2014-02]
(a) -1V to -2V (b) -2V to -4V

(a) Small R1 and small R2
(c) +1V to -2V (d) +2V to -4V (b) Large R1 and large R2
(c) Small R1 and large R2
(d) Large R1 and small R2
24. In the following circuit, the input voltage Vin is 100
sin (100 t ) . For 100RC = 50 , the average voltage 27. A non-ideal diode is biased with a voltage of –0.03 V,
across R (in volts) under steady – state is nearest to and a diode current of I1 is measured. The thermal voltage
[2015-02] is 26 mV and the ideality factor for the diode is 15/13. The
voltage, in V, at which the measured current increases to
1.5I1 is closest to: [2020]
(a) –0.02 (b) –0.09
(c) –1.50 (d) –4.50
28. In the circuit shown, the input Vi is a sinusoidal AC

voltage having an RMS value of 230V±20%. The worst-case
(a) 100 (b) 31.8 peak-inverse voltage seen across any diode is _________ V.
(Round off to 2 decimal places.) [2021]
(c) 200 (d) 63.6
25. For the circuit shown in the figure below, assume that
diodes D1 ,D2 and D3 are ideal. [2017-01]
29. In the circuit shown, a 5V Zener diode is used to

regulate the voltage across load R0. The input is an
unregulated DC voltage with a minimum value of 6V and a
The DC components of voltages v1 and v 2 , respectively are maximum value of 8V. The value of Rs is 6Ω. The Zener
diode has a maximum rated power dissipation of 2.5 W,
(a) 0 V and 1 V (b) – 0.5 V and 0.5 V
Assuming the Zener diode to be ideal, the minimum value
(c) 1 V and 0.5 V (d) 1 V and 1 V
of R0 is ___________ Ω. [2021]

Analog Electronics
32. All the elements in the circuit shown in the following

figure are ideal. Which of the following statements is/are
true? [2023]
30. The waveform shown in solid line is obtained by

clipping a full-wave rectified sinusoid (shown dashed). The
ratio of the RMS value of the fullwave rectified waveform to (a) When switch S is ON, both D1 and D2 conducts and D3 is
the RMS value of the clipped waveform is _______. reverse biased.
(Round off to 2 decimal places.) [2021] (b) When switch S is ON, D1 conducts and both D2 and D3
are reverse biased.
(c) When switch S is OFF, D1 is reverse biased and both D2
and D3 conduct.
(d) When switch S is OFF, D1 conducts, D2 is reverse biased
and D3 conducts.
31. For the circuit shown below with ideal diodes the
output will be
(a) Vout =Vin for Vin > 0

(b) Vout=Vin for Vin < 0
(c) Vout =-Vin for Vin > 0
(d) Vout =-Vin for Vin < 0 [2022]

Analog Electronics
Solutions
01. Ans: (80)
Solution:
Minimum Zener Current, I Zmin = 25mA
20 − 10
I= = I Z + IL
R
Since Load Voltage is fixed at 10V.
10
IL = A = 100mA
100
Imin = IZmin + IL = 25 + 100 = 125mA
Hence, I  125mA
10
 125mA
R
10
R = 80
125mA
The value of R should be less or equal to 80
02. Ans: (c)

Solution:
The depletion region in p-n junction diodes has ionized acceptor and donor atoms. So, there are only positive (Donor) ions
and negative (acceptor) ions.
03. Ans: (a)

Solution:
We know Vd = E
Vd (Drift velocity) unit is cm/sec

E (Electric field) unit is V/cm
So  has unit = cm sec = cm2 volt − sec

V cm
04. Ans: (b)

Solution:
Diode current ID = IS exp  V0 
 
 V 
 T 
If temperature is increased, voltage across diodes drops. And the rate of drop = −2.5mV / 0 C
05. Ans: (b)

Solution:
V
Diode Characteristics, ID = IS e VT
ID IS  
= exp  V 
V VT  VT 
ID ID
=
V VT

Analog Electronics
1 VT
So, dynamic resistance rd = =
ID ID
V
25  10 V −3
So, rd = = 12.5
2  10 −3 A
06. Ans: (a)

Solution:
When the diode is forward biased the diode is replaced by a forward resistance as shown below,
When diode is Forward Biased ( V  0)

i
Vm sin t
I= A
50
When Diode is Reverse Biased ( V  0)
i
I = 0A
The current waveform is shown in adjoining figure.
The DC component of load current is given by average value of current.
Vm V
1 Vm sin t d ( t ) =

2 = m
2 0 50
Idc =
2  50 50
Vm
So, DC component of the source current =
50
07. Ans: (b)

Solution:
Determining the Thevenin Equivalent across the Diode and Zener Diode combination,
For Thevenin Voltage, using potential divider
1k V
VTh = Vi  = i = 5sin t
1k + 1k 2
1k  1k
R Th = = 500
1k + 1k
The Thevenin Equivalent of the system is shown below,

Analog Electronics
When Vth  0 , D Z will be reverse bias, so no current flow till D Z enters Breakdown region. Zener Diode will enter
breakdown region when the current through it can flow and for that the diode D must be forward biased and has voltage
drop of 0.7V across it.
Hence, Vth  3.3 + 0.7 = 4V
And D Z is in Breakdown, subsequently the output voltage =4V
V0 = 4V When Vth  4V
When Vth  0 D will be in Reverse Bias, so
No current flows till D enters Breakdown region
When diode enters breakdown region, then the Zener diode becomes forward biased and the voltage drop across it is
same as diode i.e. 0.7V. For this to happen, the Thevenin Voltage, Vth  5 + .7 = 5.7V
But Vth has peak negative voltage =-5V. So, Thevenin voltage cannot go below -5.7V and hence the diode will act as open
circuit and hence peak negative output voltage is same as peak negative input voltage is -5V.
08. Ans: (d)

Solution:
The given circuit is shown below,
During the positive half cycle, the diode D2 can get forward Biased and D1 will remain reverse biased.
D2 becomes forward biased and acts as short circuit if,
Vi  4V
In this case, V0 = 4V
If, 0  Vi  4V , then both diodes are reverse biased and no current flows through the circuit so, V0 = Vi
In the negative half cycle, the diode D1 can become forward biased as shown above and in that case the current through
diode D1 is,
ID1 =
(V + 4)
i
20k
The direction of this current is taken from cathode to anode of D 1.
The diode will be forward biased if ID1  0 or the current flows from anode to cathode terminal.
ID1 =
(V + 4)  0
i
20k

Analog Electronics
Vi  −4V
In this condition, the output voltage is, V0 = Vi −

( V + 4 )  10k =  V − 2  V
i i
 
20k 2 
For minimum voltage, we consider negative peak of input voltage i.e. Vi = −10V
 −10 
V0 =  − 2  V = −7V
 2 
Otherwise, −4V  Vi  0V , both diodes are reverse biased and V0 = Vi . So, the transfer characteristics are shown below,
Maximum Voltage = 4V and Minimum Voltage = -7V
09. Ans: (c)

Solution:
Since, the resistance and voltage of Zener diode is given, the Zener diode can be replaced by a voltage source and a
resistance as shown below,
Since, the voltage across Zener diode is 3.5V as shown in figure.

3.5 = 3.3 + I ZR Z
0.2
IZ = mA = 2mA
0.1
10. Ans: (a)

Solution:
The rating 50 – 0 - 50V on the secondary side implies that
Voltage across each half of the secondary winding is 50V.
Secondary R.M.S voltage= 50V, Secondary peak voltage = 50 2V

When D 1 is ON and D 2 is OFF, the circuit is shown below,

Analog Electronics
( )
So, PIV = 50 2 − −50 2 = 100 2 V
11. Ans: (c)

Solution:
Assume D 1 is OFF, D 2 is ON
The voltage at the anode terminal of diode can be determined
By Super-position Theorem.
If only 5V source is applied,
1
V1 = 5  = 2.5V [By Potential Divider]
1+1
If only 8V source is applied,
1
V1 = −8  = −4V [By Potential Divider]
1+1
V = V1 + V2 = 2.5 − 4 = −1.5V
So, D 1 will remain in Reverse Bias
Hence, assumption is justified. So, Current through D 1 is =0A
12. Ans: (a)

Solution:
Based on the current direction D1 should be ON and D2 is OFF.
As the diodes are ideal current will pass through diode from anode to cathode ( from p to n) here D 1
is in forward
biased D 2 is in Reverse Biased.
So, I = 0mA as D 2 will be Reverse Biased.
13. Ans: (a)

Solution:
The given circuit is,
Assume that the diode D1 is ON, the first loop gets completed.
Current through D1 is given by,
10
ID1 = = 10A
1
This current will flow from anode to cathode of the diode. Hence, the diode is forward biased. So, our assumption is
correct.
If the diode D3 is ON, the current through the current source will flow through the short circuit path provided by diode D 3
but in that case the direction of current is from top to bottom in the diode i.e. from Cathode to Anode but diode cannot
conduct in reverse direction and hence D3 is OFF.

Analog Electronics
If Diode D2 is ON, it short circuits the 1Ω resistor and the current through the current source tries to flow through the short
circuit path through D2. But in this case the current flows from cathode to anode of D 2 and so the assumption is incorrect
and D2 is OFF.
Hence D1 -> ON, D2 -> OFF, D3 -> OFF
14. Ans: (a)

Solution:
The given system is,
Case-1: Assume D 1 is ON and D 2 is OFF

Vi − 10
ID1 =
2
For D 1 to be ON ID1 has to be positive
ID1  0
Vi  10V
For this case V0 = Vi
Case-2: Assume D 1 is OFF and D 2 is also OFF
For Vi  10V
Vi − 10
ID1 = 0
2
D 1 is OFF.
In this case no current flows through R.
Hence, V0 = 10V
For this case D 2 is also OFF as its anode voltage is less than its cathode voltage.
So, the Transfer Characteristics are shown below,
15. Ans: (a)

Solution:
First we will determine Thevenin’s Equivalent across the Diode Branch,

Analog Electronics
By Potential Divider,
 R  Vi
Vth = Vi   =
R +R  2
 R R  R
R th =   = = 5k
R +R  2
The Thevenin’s Equivalent is shown above.
Case-1: When diode ‘D’ is ON

Vi 10sin t
Vth = = = 5sin t
2 2
Vth − 5.7
Now current through diode ID =
R d + 5k
But Vth  5.7 (for all t)
So, ID is negative this means
Our assumption us wrong and diode will remain in Reverse Bias all the time
So, V0 = Vth = 5sin t
16. Ans: (d)

Solution:
This is a voltage doubler circuit shown below.
During Positive Half Cycle, D1 is On and D2 is OFF.
Capacitor C 1 is charge through diode D 1 during

positive half of input voltage to the
maximum voltage, that is 5V
During negative half D 2 is short, D 1 is open and C 2 is charged by capacitor C 1 & input voltage source

Analog Electronics
So, C 2 will be charged Maximum up-to 10V

So, VC2 = −10V and VC1 = 5V
17. Ans: (b)

Solution:
The characteristics of the two rectifiers is shown below,
(P) (Q)
The working of Full Wave Rectifier is such that,

V , Vin  0

V0 =  in
−Vin , Vin  0

The characteristics of Full Wave Rectifier based on above function is shown below,
This transfer curve can be splitted into two parts
( when V  0 )
i ( when V  0 )
i
So, when Vi < 0, the curve is same as negative P
So, we need a difference amplifier which gives an output ‘Q’-‘P’
18. Ans: (b)

Solution:

Analog Electronics
Let us assume diode D 1 is ON and D 2 is off. Then the system looks like as shown below,
So, by potential divider

V0 = 10  1 =5V
2
The assumption is true as the cathode voltage of D 2 is 10V
And anode voltage is -15V so the diode D2 is Reverse Biased.
19. Ans: (c)

Solution:
Case-1:
When diode D is forward biased
V0 = (5 + 0.7 ) V = 5.7V
And Zener is in Reverse Bias but not in Breakdown
Region when Vi  5.7Volt then this case happens.
Case-2:
Diode D is Reverse Biased and Zener is also Reverse biased.
In this case V0 = Vi
This case happen only when - 0.7V  Vi  5.7V

Analog Electronics
Case-3:
Diode D is Reverse Biased and zener is Forward Biased
V0 = -0.7 Volt.
This case takes place when Vi  −0.7V Volt
So, the characteristics of the system are shown above.
Note: In none of the cases the Zener Diode is in breakdown region as whenever voltage is beyond 5.7V the diode at
output clamps the voltage to 5.7V and the voltage cannot exceed breakdown voltage of Zener diode.
20. Ans: (d)

Solution:
Based on the characteristic equation of the diode the diode in ON state can be considered as a series combination of 500Ω
and 0.7V voltage drop.
V − 0.7
So, current in the circuit i = A
500
10 − 0.7 9.3
i= A= mA = 6.2mA
1.5  10 3
1.5
Alternative Method,
10 − V
From circuit i =
1000
V − 0.7
Again i =
500
10 − V V − 0.7
=
1000 500
2V − 1.4 = 10 − V
3V = 11.4
V = 3.8
V − 0.7 3.8 − 0.7
So, i = = Amp = 6.2mA
500 500
21. Ans: (b)

Solution:
VZ = 5V
Minimum current through zener I Z (min) = I Z (knee) = 10mA

Analog Electronics
10 − 5
So, the current through 100 is I = = 50mA
100
Now, I = I Z + IRL
(
Maximum current through RL is IRL(max ) = 50 − 10 mA )
IRL(max ) = 40mA
VRL
So, = 40mA
RL(min)
5
RL(min) =
.04
RL(min) = 125
Maximum current that can through the Zener is I Z(max ) = 50mA and this will flow when the load resistance is infinite or
open circuited.
Maximum power rating or Maximum power dissipation in zener is
PZ(max ) = (50mA  5V ) = 250mW
22. Ans: (300)

Solution:
The voltage across the output of rectifier looks like as shown.
For limiting case, maximum current through zener diode will pass when,
RL = 
Vzener = 5V
Vmax = 20 V = Vzener + VR
S
By KVL, 20 = 5 + I × R S
P 1
To avoid burn out, Izener < = A
V 20
If RL =  , IR = Izener
S
1
15 =  R  RS = 300
20 S
23. Ans: (b)

Solution:
Voltage across diode branches if braches are open circuited
V
Vth = i
2
The waveform will be clipped if any of the diode conducts. In that case, output voltage will be a constant dc instead of
sinusoidal.
For diode connected to 1V source, it will conduct iff,
 Vi 
 + 1  0
2 
 
Vi  −2V
For diode connected to 2V source, it will conduct iff,

Analog Electronics
Vi
–2 – >0
2
 Vi 
 + 2  0
 2 
Vi < – 4V
So, Vi must lie outside (– 4, – 2) V range for output to be clipped.
24. Ans: (c)

Solution:
During positive half cycle,
D1 gets forward biased and C1 is charged to positive
peak of input.
VC1 = 100V
Similarly, during the negative half cycle capacitor C2 will
Negative peak of input.

VC2 = 100V
The RC time constant is much larger than time period of input so the discharging of capacitors will be negligible and we
can assume that the output voltage is constant at 200V.
25. Ans: (b)

Solution:
During positive half cycle, D 1 is forward biased

V1 = V2 = sin100t
2
During negative half cycle, D 2 and D 3 are forward biased

V1 =  sin100t
V2 = 0
DC component means average value

1   
2

1
V1(avg) =  sin ( t ) d ( t ) +   sin td ( t )  = 1  1  2 + 1 ( −2 )  = − V
2  0 2   2  2  2
1   
 2
V2(avg) =  sin ( t ) d ( t ) +  0sin td ( t )  = 1  1  2 = 1 V
2  0 2   2  2  2
26. Ans: (c)

Solution:
R1, low, R2 high
R2
VD = V 
R1 + R 2
If R2 is large Vd (high)
R1 is less VD=V
So for maximum power to deliver to load R1 is small and R2 is large.

Analog Electronics
27. Ans. (b)

Solution:
Diode current is given by the equation
ID = I0 e( VD / VT
−1)
 −0.03 0.026 
 I1 = I0  e15/13
 (
− 1 = I0 e−1 − 1
 )
 
 VD 0.026 
1.5I1 = I0  e15/13 − 1
 
 
Take ratio of both equations
 eVD / 0.03 − 1
1.5 =  
 e−1 − 1 
On solving, we obtain
VD = –0.088 volt
= – 0.09 volt
28. Ans: (390.32)

Solution:
This circuit is a full wave rectifier with a capacitive filter.
If we assume RC ≫T, capacitor charge to peak input voltage & does not discharge through R.
V0 = Vc = 2(230 + 20%) = 2  230  1.2 = 390.323 V
Peak Inverse voltage = Peak V0 = 390.32V
29. Ans: (30)

Solution:
To calculate R0min, we must find ILmax
Is min = I2min + ILmax
Vimin − Vz
= Iz min + IL
Rs max
For ideal zener diode, Iz min =0

Vimin − Vz
= IL max
Rs
6−5
= IL max
6
1
IL max = A
6
V 5
R0 min = z = = 30
lL max 1 / 6
30: Ans: (1.211)

Solution:
Period of wave form = 

Analog Electronics
 3
v(t) = Vmsint 0  t  &  t  
4 4
Vm  3
v(t) =  t 
2 4 4
RMS value of clipped waveform
  3 /4  V
2
1  /4 
Vrms =   0 /4
2
Vm sin2 td(t) + 
m
 d(t)
    2

1/2
  
3/4
2 2
+ Vm sin td(t) 
 
 1   /4 3 /4
Vrms = Vm  
 2 
0 (1 − cos2t)d( t) + /4 1 d( t)
1/2
  
+ 
3 /4
(1 − cos2t)d(t) 
 
1/2
   /4  
 1   sin2t    3   sin2 t   
Vrms = Vm   −   + +   −  − 
 2  4  2 0 2  4   2 3 /4  

1/2
 1  sin  / 2 sin3 / 2  
= Vm    − + 
 2  2 2  
Vrms = 0.5838 Vm
RMS value of rectified waveform
 Vm
Vrms =
2

Vrms
ratio = = 1.211
Vrms
31. Ans: (a)

Solution:
Positive half cycle

D1 and D2 will be ON.

Analog Electronics
For Negative half cycle

D1 and D2 will be OFF.
The output waveform
So.
V0 = Vin for Vin > 0
32. Ans. (𝒃, 𝒄)

Solution:
When S is ON, diode D3 gets reverse biased
Assume D1 is ON & D2 is OFF

Analog Electronics
I1 = 4A > 0 D1 is ON
VD2 = -20 V < 0 D2 is OFF
 Option (b) is correct
When S is OFF, D3 is ON due to 2A current source Assume D1 is OFF & D2 is ON
ID2 = 4A > 0  D2 is ON
VD1 = 20 – 40 = -20 < 0 D1 is OFF
 Option (c) is correct

Analog Electronics
Chapter 2 – BJT
01. Figure below shows a common emitter amplifier. The (d) Positive-current feedback
quiescent collector voltage of the circuit is approximately 04. In an RC-coupled Common Emitter amplifier, which of
[1991] the following is true? [1992]
(a) Coupling capacitance affects the high frequency
response and bypass capacitance affects the low frequency
response
(b) Both coupling and bypass capacitances affect the low
frequency response only
(c) Both coupling and bypass capacitances affect the high
frequency response only
(d) Coupling capacitance affects the low frequency
response and the bypass capacitance affects the high
frequency response
05. In the transistor circuit shown in figure, collector-to-

20
(a) V (b) 10 V ground voltage is +20V. Which of the following is the
3 probable cause of error? [1994]
(c) 14 V (d) 20 V
02. .Figure shows a common emitter amplifier [1991]
(a) Collector-emitter terminals shorted
(b) Emitter to ground connection open

(c) 10 kΩ resistor open
(d) Collector-base terminals shorted
06. In the transistor amplifier shown in figure, the ratio of

(a) Simplify the circuit by applying Thevenin’s theorem to small signal voltage gain, when the emitter resistor R1, is
the biasing network R1 ,R2 at the base of the transistor bypassed by the capacitor C1 to when it is not bypassed,
(assuming simplified approximate h-parameter model for
(b) Assuming Cs to be a short for the frequency range transistor), is [1996]
considered. Draw the small signal a.c. model of the circuit
obtained in (a) by using the simple model for the transistor
shown in figure.
V 
(c) Evaluate the small signal gain  0  of the amplifier.
V 
 1
03. In a Common Emitter amplifier, the un-bypassed

emitter resistance provides [1992]
(a) Voltage-shunt feedback
(b) Current-series feedback
(c) Negative-voltage feedback

Analog Electronics
(a) 1 (b) hfe
(c)
(1 + h ) R
fe e
(d) 1 +
(1 + h ) R
fe e
hie hfe
07. One of the applications of current mirror is: [1998]

(a) Output current limiting
(a) 0.0 micro amperes (b) 18.2 micro amperes
(b) Obtaining a very high current gain
(c) 26.7 micro amperes (d) 40.0 micro amperes
(c) Current feedback
(d) Temperature stabilized biasing
11. In the single-stage transistor amplifier circuit shown in
Fig., the capacitor CE is removed. Then the ac small-signal
08. A NPN, silicon transistor is meant for low-current audio
mid-band voltage gain of the amplifier. [2001]
amplification. Match its following characteristics against
their values: [1998]
Characteristics Values
(a) VEB ,max (P) 0.7V5
(b) VCB ,max (Q) 0.2V
(c) VCE ,sat (R) 6V

(S) 50V
09. For the small signal BJT amplifier shown in fig,

determine at 1 kHz, the following: [1999] (a) Increases (b) Decreases
Assume β = 100 (c) Is unaffected (d) Drops to zero
12. The transistor in the amplifier circuit shown in figure is

biased at IC = 1mA. Use
 kT 
VT =   = 26mV, 0 = 200, rb = 0, and r0 →  [2001]
 q
(a) Quiescent collector current, ICQ

v 
(b) Small signal voltage gain,  o 
 v 
 i  (a) Determine the ac small signal mid-band voltage gain
(c) Maximum possible swing of the collector current V0
of the circuit.
Vi
10. In the circuit of fig, the value of the base current
(b) Determine the required value of CE for the circuit to
IB will be [2000] have a lower cutoff frequency of 10 Hz.

Analog Electronics
16. Two perfectly matched silicon transistors are connected

13. For the circuit shown in Figure, IE = 1mA,  = 99 and
as shown in figure. The value of the current I is [2004]
VBE = 0.7V . Determine [2002]
(a) 0 mA (b) 2.3 mA
(c) 4.3 mA (d) 7.3 mA

(a) The current through R1 and RC .
17. The feedback used in the circuit shown in figure can be
(b) The output voltage V0 classified as [2004]
(c) The value of RF
14. In the circuit of Figure, assume that the transistor has

hFE = 99;VBE = 0.7V . The value of collector current I C of
the transistor is approximately [2003]
(a) Shunt-series feedback (b) Shunt-shunt feedback

(c) Series-shunt feedback (d) Series-series feedback
18. A bipolar junction transistor (BJT) is used as a power

control switch by biasing it in the cut-off region (OFF state)
or in the saturation region (ON state). In the ON state, for
(a) [3.3/3.3] Ma (b) [3.3/(3.3+ 0.33)] mA
the BJT [2004]
(c) [3.3/33] mA (d) [3.3/(33+3.3)] mA
(a) Both the base-emitter and base-collector junctions are
reverse biased
15. In the circuit shown in Figure, the current gain () of the
(b) The base-emitter junctions is reverse biased, and the
ideal transistor is 10. The operating point of the transistor
base-collector junction is forward biased
( VCE , IC ) is [2003]
(c) The base-emitter junction is forward biased, and the
base-collector junction is reverse biased
(d) Both the base-emitter and base-collector junctions are
forward biased
19. The trans-conductance gm of the transistor shown in

figure is 10mS. The value of the input resistance RIN is
[2004]
(a) (40V, 4A) (b) (40V, 5A)

(c) (0V, 4A) (d) (15V, 4A)

Analog Electronics
(a) 0 µA (b) 10 µA
(c) 100 µA (d) 1000 µA
22. Consider the circuit shown in figure. If the  of the

transistor is 39 and ICBO is 20nA and the input voltage is
+5V, then transistor would be operating in [2006]
(a) 10.0 k (b) 8.3 k

(c) 5.0 k (d) 2.5 k
20. In the Schmitt trigger circuit shown in figure, if

VCE(Sat ) = 0.1V , the output logic low level ( VOL ) is
(a) Saturation region (b) Active region
[2004] (c) Breakdown region (d) Cut-off region
23. The common emitter forward current gain of the

transistor shown is F = 100.
The transistor is operating in [2007]
(a) 1.25 V (b) 1.35 V

(c) 2.50 V (d) 5.00 V (a) Saturation region (b) Cutoff region
(c) Reverse active region (d) Forward active region
21. The common emitter amplifier shown in Figure is
biased using a 1mA ideal current source. The approximate
24. The three-terminal linear voltage regulator is
base current value is: [2005]
connected to a 10 load resistor as shown in the figure. If
Vin is 10 V, what is the power dissipated in the transistor?
[2007]

Analog Electronics
(a) 0.6 W (b) 2.4 W 28. The transistor circuit shown uses a silicon transistor
(c) 4.2 W (d) 5.4 W with VBE = 0.7V, I  I and a dc current gain of 100. The
C E
25. The input signal Vm shown in the figure is a 1 kHz value of V0 is [2010]
square wave voltage that alternates between +7V and −7V
with a 50% duty cycle. Both transistors have the same
current gain, which is large. The circuit delivers power to
the load resistor RL. What is the efficiency of this circuit for
the given input? Choose the closest answer. [2007]
(a) 4.65V (b) 5V

(c) 6.3V (d) 7.23V
29. The transistor used in the circuit shown below has a 
of 30 and ICBO is negligible. [2011]

(a) 46% (b) 55%
(c) 63% (d) 92%
26. Two perfectly matched silicon transistors are connected

as shown in the figure. Assuming the  of the transistors to
be very high and the forward voltage drop in diodes to be
0.7V, the value of current I is [2008]
If the forward voltage drop of diode is 0.7V, then the

current through collector will be
(a) 168mA (b) 108mA
(c) 20.54mA (d) 5.36mA
30. The voltage gain AV of the circuit shown below is

[2012]
(a) 0 mA (b) 3.6 mA
(c) 4.3 mA (d) 5.7 mA
27. Transformer and emitter follower can both be used for

impedance matching at the output of an audio amplifier.
The basic relationship between the input power Pin and
output power Pout, in both the cases is [2009]
(a) Pin = Pout for both transformer and emitter follower
(b) Pin > Pout for both transformer and emitter follower
(c) Pin < Pout for transformer and Pin = Pout for emitter
follower (a) A (b) A

 200  100
v v
(d) Pin = Pout for transformer Pin < Pout for emitter follower
(c) A  20 (d) A  10
v v

Analog Electronics
31. The magnitude of the mid – band voltage gain of the

circuit shown in figure is (assuming hfe of the transistor to
be 100) [2014-01]
35. When a bipolar junction transistor is operating in the

saturation mode, which one of the following statements is
TRUE about the state of its collector – base (CB) and the
base – emitter (BE) junctions? [2015-02]
(a) 1 (b) 10 (a) The CB junction is forward biased and the BE junction is
(c) 20 (d) 100 reverse biased.
(b) The CB junction is reverse biased and the BE junction is
32. The transistor in the given circuit should always be in forward biased.
active region. Take VCE(sat) = 0.2V, VBE = 0.7V. The maximum
(c) Both the CB and BE junctions are forward biased.
value of RC in  which can be used, is __________. [2014-02]
(d) Both the CB and BE junctions are reverse biased.
36. A transistor circuit is given below. The Zener diode

breakdown voltage is 5.3V as shown. Take base to emitter
voltage drop to be 0.6V. The value of the current gain  is
__________. [2016-01]
33. In the given circuit, the silicon transistor has  = 75

and a collector voltage VC = 9V. Then the ratio of RB and RC
is ____________. [2015-01]
37. The circuit shown in the figure uses matched transistors

with a thermal voltage VT = 25 mV. The base currents of
the transistors are negligible. The value of the resistance R
in k  that is required to provide 1 A bias current for
34. In the following circuit, the transistor is in active mode the differential amplifier block shown is __________ . (Give
and VC = 2V . To get VC = 4V , we replace RC withR'C . the answer up to one decimal place.) [2017-01]
Then the ratio R'C RC is _______________. [2015-02]

Analog Electronics
40. In the BJT circuit shown, beta of the PNP transistor is

100. Assume VBE = –0.7 V. R1 = 4.7kΩ.
The voltage across RC will be 5 V when R2 is ……… kΩ.
(Round off 2 decimal places). [2021]
38 For the circuit shown in the figure below, it is given that

VCC
VCE = . The transistor has  = 29 and VBE = 0.7 V
2
when the B-E junction is forward biased. [2017-02]
41. The Zener diode in circuit has a breakdown voltage of 5

V. The current gain β of the transistor in the active region in
99. Ignore base-emitter voltage drop VBE. The current
through the 20Ω resistance in milliamperes is _________.
(Round off to 2 decimal places). [2023]
RB
For this circuit, the value of is
R
(a) 43 (b) 92
(c) 121 (d) 129
39. In the circuit shown in the figure, the bipolar junction

transistor (BJT) has a current gain  = 100 . The base-
emitter voltage drop is a constant VBE = 0.7V . The value of
the Thevenin equivalent resistance R Th (in ) as shown in the
figure is ________(up to 2 decimal places). [2018]

Analog Electronics
Solutions
01. Ans: (c)
Solution:
For DC Analysis, the capacitor is open circuited and the DC Circuit is shown below,
Determining Thevenin equivalent at the base,

5
Vth = 20  = 20 V
10 + 5 3
10  5 10
rth = = k
15 3
Applying KVL in base emitter loop,
Vth − IBrth − 0.7 − 10  IE = 0
Vth − IBrth − 0.7 − 10  (  + 1 ) IB = 0

Here, IB , IE are in mA and all resistances are in kΩ
20 − 10  IB − 0.7 − 10  101  IB = 0
3 3
IB = 5.88mA
IC = IB = 100  5.88mA = 0.588A
VC = 20 − 10  0.588 = 14.11V  14V
02. Ans: ---

Solution:
The given system is shown below and for DC Analysis we need to apply Thevenin’s Theorem. The Thevenin Equivalent is
also shown below,

Analog Electronics
Capacitance C S acts as open circuit to D.C.
where R = R R = R1R 2
th 1 2
R1 + R 2
R2
Vth = VCC 
R1 + R 2
(b) Transistor Model of the circuit has been below ( C S Has been assumed to be short circuited)
(c) Here, V0 = −Ib  RL
Vbe = Ib (1 +  ) RE
Applying Thevenin’s Theorem to the above circuit

R1 R 2
Vth = Vi 
R S + R1 R 2
R th = R S R1 R 2
By KVL, Vbe = Vth − R th  Ib
So, Ib (1 +  ) RE + IbR th = Vth

 R1 R 2 
Vi  (
 = I R + (1 +  ) RE
 R S + R1 R 2  b th )
 
Vi =
(
Ib R th + (1 +  ) RE )
R1 R 2
(R S
+ R1 R 2 )
And, V0 = −IbRL
V0
−RL  R1 R 2( )
So,
Vi
=
(R + (1 + )R )(R
th E S
+ R1 R 2 )
Where R th = R1 R 2 R S
03. Ans: (b)

Solution:
The current through un-bypass R E is approximately equal to

Analog Electronics
output current that is the collector current.

So, this is current sampling at the output side
The voltage drop across R E reduces the effective
Input voltage = (V in
− REiE ) .
So at the input side it is voltage mixing.
So feedback is current-voltage or current-series.
04. Ans: (b)

Solution:
Coupling capacitance and bypass capacitance are responsible for low frequency response of a R.C. coupled amplifier
Higher frequency response is affected by stray or parasitic capacitance
05. Ans: (b)

Solution:
From the circuit diagram,
VE = 0V
Since, collector to ground voltage is 20V, VC = 20V
Current through 10kΩ resistor,
20 − 20
IC = = 0A
10k
So, IE = IB = 0
This is possible when emitter to ground connection is open. So, that there won’t be any base current and emitter current.
06. Ans: (d)

Solution:
zIn bypass case,
V01 = −hfe ibRC
Vin
Base current, ib =
hie
Vin
V01 = −hfe R
hie C
V01 −hfe R C
So, A V1 = =
Vin hie
In Non- bypass case, emitter resistance should also be included
V02 = −hfeib  RC
Now applying KVL

Vin − hieib − ib (hfe + 1 )  R e = 0
Vin = hie + (hfe + 1 ) R e  ib
V02 −hfe R C
A V2 = =
Vin hie + (hfe + 1 ) R e
A V1 hie + (hfe + 1 ) R e h +1

So, = = 1 +  fe  R e
A V2 hie  hie 

Analog Electronics
07. Ans: (d)

Solution:
Current mirrors are used as current source or sink to bias transistors and provide thermal stability
08. Ans: (a-P, b-R, c-Q)

Solution:
VEB Max = 0.7V (a − p)
VCB Max = 5V (b − R )
VCE Sat = 0.2V (c − Q )
09. Ans: (1mA, -7.874, 4.36mA)
Solution:
(a) While analyzing with DC only, capacitor act as open circuit
The input voltage is disconnected.
Applying KVL
5 − 420IB − VBE − 0.1 ( IE ) = 0 ---------(1)
IB & IE Are in mA and all resistances are in kΩ
IE = (  + 1 ) IB = 101 IB , VBE = 0.7V

From (1)
5 − 420IB − 0.7 − 0.1  101 ( IB ) = 0
IB = 9.9976A
IC = IB = 0.9997mA 1mA (Quiescent collector current)
VT 26  10−3
(b) r = = = 2.6k
IB 10−3
100
The small signal model is shown below,
Now, V0 = −gmV  103

V 
Current Through the 100Ω resistor =   + gm V 
r 
  
 V 
Vi = V +  + gm V   100
 r 

Analog Electronics
V0 gm  103 rgm  103 −  103

So, A V = = = =
Vi 1  r + (1 + rgm )  100 r + (1 +  )  100
1 +  + gm   100 
 r 
−100  103
AV = = −7.874
2.6  103 + 101  100
(c) Assume in saturation VCE = 0.2V
So, applying KVL
5 − IC  1 − 0.2 − 0.1IE = 0
Here, IC ,IE in mA and IC  IE
IC =
( 4.8 ) mA
= 4.364 mA
(1.1)
The collector current will swing about the point quiescent point.
Maximum swing of collector current will be 4.36 mA
10. Ans: (b)
Solution:
VE = 0 − 0.7 = −0.7V
−0.7 − ( −10 )
So, IE = = 1.476mA
6.3
IE
IB = = 18.2A
 +1
11. Ans: (b)

Solution:
If Bypass capacitor C E is removed, the effective negative feedback increases and subsequently the mid band gain falls.
12. Ans: (-6.623, 265.08μF)

Solution:
The small signal model for the given amplifier is shown below,
(a) V0 = −gmVRC
Vi = V + iRB
V
Input Current, i =
r
V
So, Vi = V + R
r B
V0 −gmVR C R C
So, gain = =−  = gmr 
Vi  RB  r + RB
 1 + r  V
  
Since, we are computing mid band gain, so C E is assumed to be shorted

Since, IC = 1mA
VT VT 200  26  10 −3
So, r = = = = 26  200
IB IC 10−3
V0 −200  103
So, A V = = =-6.623
Vi 26  200 + 25  103

Analog Electronics
(b) Lower cutoff frequency due to ‘CE’ is f = 1

L
2 R eq CE
Req is the resistance seen by C E
R eq =
(r + R ) R
 B
(Resistance seen by C E )
(1 +  ) E
 26  200 + 25  103 
R eq =  100    60.04
 201 
Since, fL = 10Hz
So, C = 1 1 = 265.08F
E
=
2f R eq 2  10  60.04
13. Ans: (a) 0.1mA, 1.1mA (b) 13.9V (c) 110.9kΩ)

Solution:
(a) As given in the question, IE = 1mA
1mA
IB = = 10−5 A
 +1
By KVL, VE = 1mA  1k = 1V
VB = VE + VBE = 1.7V
1.7V 1
So, current R 1 is IR1 = = mA = 0.1mA
17k 10
Collector Current, IC = IB = 99  10−5 = 0.99mA
By KCL, I1 = IR1 + IB = 0.1mA + 0.01mA = 0.11mA
Current through R C = I1 + IC = 0.11 + 0.99 = 1.1mA
(b) By KVL, V0 = 15 − 1.1  RC = 15 − 1.1  1 = 15 − 1.1 = 13.9V
VC − VB 13.9 − 1.7
(c) I1 = =
RF RF
RF =
(13.9 − 1.7 ) V = 110.9k
0.11mA
14. Ans: (b)

Solution:
Apply KVL,
4 − IBRB − VBE − (  + 1 ) IBRE = 0
4 − 33IB − 0.7 − 100  3.3IB = 0
Here, IB in mA
3.3
IB = mA
363
3.3  99 3.3 3.3
So, IC = IB =  = mA
363 3.63 3.3 + 0.33
15. Ans: (c)

Solution:
Assuming that the Transistor is biased in active region,

Analog Electronics
Given, IB = 0.5A
Ic = IB = 5A
Applying KVL in collector-emitter loop,
Vcc − 10Ic − VCE = 0
VCE = 40 − 10  5 = −10V
So, our assumption is incorrect. The transistor cannot be biased in active region rather it must be in saturation region
where, Ic  IB
VCE = VCE(sat)  0V
Vcc − VCE 40 − 0
Ic = = = 4A
10 10
Hence, the operating point is (0V, 4A)
16. Ans: (c)

Solution:
Due to high  we may neglect Base Current
This circuit is a current mirror circuit
So, current through 1 k Resistance =I
Now VB = −5 + 0.7 = −4.3V = VC
The voltage across 1kΩ, 0 − 4.3V = 4.3V

4.3
So, I = mA = 4.3mA
1
17. Ans: (b)

Solution:
Feedback resistance R F is the feedback element
Output voltage is being sampled
(as feedback element is directly connected

to output node) and input current is being
mixed. So, the feedback is voltage (output)
and current (input) or shunt (input)-shunt (output).
18. Ans: (d)

Solution:
‘ON’ state is the saturation region for BJT
In saturation – both Base Emitter and Base Collector are forward biased.
19. Ans: (d)

Solution:
For small signal analysis, DC supply is removed and capacitors are short circuited. The circuit and its small signal equivalent
is shown below,

Analog Electronics
 50
Now r = = = 5k
gm 10  10−3
(
So, input resistance Z in = 10k 10k 5k  ) = 2.5k
20. Ans: (b)

Solution:
If Vi = 0 , the base voltage of Q1, VB = 0V
By KVL, the emitter voltage is, VE = 1.25mA  1 k = 1.25V
Hence, VBE  0V . So Q 1 is in cutoff.
The current through the collector resistance of Q 1 drives Q2 into
saturation and output will be in low logic.
So, V0 = VCE ( sat ) + 1  1.25 = 1.25 + 0.1 = 1.35V

The output logic low level, V02 = 1.35V
21. Ans: (b)

Solution:
Since, a constant current source is connected at emitter terminal,
Ie = 1mA
Due to high current gain, Ic  Ie = 1mA
IC
Since,  =
Ib
10−3
So, Ib = = 10 −5 = 10A
100
22. Ans: (b)

Solution:
The given system is shown in the figure.
We have to determine the Thevenin Equivalent across Base-Emitter Junction.
The Thevenin Voltage can be determined by Superposition,

100 15
Vth = 5  − 12  = 2.78V
115 115
(
R th = 100 15 k = 13k )
The Thevenin Equivalent is shown in the figure below,

Analog Electronics
Assume that Q is in active mode

2.78 − 0.7
So IB = mA = 0.16mA
13
IC = IB = 30  0.16mA = 4.8mA
VCE = VCC − ICRC = 12 − 2.2  4.8 = 1.44V  VCE sat ( 0.2V )

So, the transistor is in active mode
23. Ans: (d)

Solution:
By KVL,
VB = 270IB ( IB is in mA)
Assuming that the Transistor is in forward active mode.
VE = VB + 0.7
10 − ( VE )
IE = mA
1
Since, IE = (  + 1 ) IB = 101  IB
101  IB = 10 − ( VB + 0.7 )
101  IB = 10 − ( 270IB + 0.7 )
371  IB = 9.3
IB = 0.0251mA
IC = IB = 100  0.0251 = 2.51mA
VC = IC  1k = 2.51V
VE = 270IB + 0.7 = 7.48V
VEC = ( 7.48 − 2.51 ) V = 4.97V  VECsat

So Transistor is in forward active mode.
24. Ans: (b)

Solution:
Since, the base of Transistor is connected to Zener Diode,
VB = 6.6V
Assuming that the Transistor is in Active Mode, VBE = 0.7V
VE = 6.6 − 0.7 = 5.9V
VBE VE 0.7V 5.9V

IE = − + =− + = −0.7mA + 590mA = 589.3mA
1k 10 1k 10
Assuming high current gain of Transistor,
IE  IC
VCE = Vin − VE = (10 − 5.9 ) V = 4.1V

Power dissipation in the transistor = VCE  IC = 4.1  589.3mA  2.4 W

Analog Electronics
25. Ans: (b)

Solution:
  Vp 
The given circuit is class-B amplifier whose efficiency,  =  
4  Vcc 
Vp = Peak voltage
Vcc = Supply voltage
 7 
=   = 54.98%
4  10 
  55%
26. Ans: (b)

Solution:
As  is assumed to be very high Base Current of
both the transistors can be neglected.
So, the configuration is working like a current Mirror and I = IC2 = IC1
Now base voltage of

Q1
Q2
is VB1 = VB2 = ( −5 + 0.7 ) V = −4.3V
Now drop across the resistance
V = 0 − ( −4.3 + 0.7 ) = 3.6V
Here 0.7V, is the voltage drop across the diode.
3.6V
So, I = = 3.6mA
1k
27. Ans: (d)

Solution:
For emitter follower (Buffer) voltage gain AV  1
But current gain A I is large
So, power gain AV AI which vary large for emitter follower
But for transformer
V2 n2 I n
= & 2 = 1
V1 n1 I1 n2
V2 I2 n1 n2
So, =  =1
V1 I1 n2 n1
So, power gain in transformer = 1
So, only for transformer Pin = Pout and for common collector or emitter follower Pout  Pin
28. Ans: (a)

Solution:
Applying KVL along the direction shown in figure,
10 − 10IB − VBE − 0.1  IE = 0
(Here IB , IE are in mA and all resistances are in kΩ)
Since, IE = (  + 1 ) 100IB
10 − 10IB − VBE − 0.1  100IB = 0

Analog Electronics
10 − 0.7 9.3
IB = = mA
20 20
IE  IC = 100  IB = 9.3  5mA = 46.5mA
So, V0 = 100IE = 46.5  10−3  100 = 4.65V
29. Ans: (d)

Solution:
VZ − VD − VBE
Base Current of the transistor IB = mA
1
5 − 0.7 − 0.7
IB = mA = 3.6mA
1
Collector current IC = IB = 30  3.6mA = 108mA
(Assuming that the transistor is in active region)
Now collector voltage VC = ( −2.2  108 ) = −237.6V
And VCE  0
So, the transistor is in saturation
And VCE = VCEsat = 0.2V
So, VC = ( −12 + 0.2 ) V = −11.8V

0 − ( −11.8 )
So, IC = mA = 5.3636mA
2.2
30. Ans: (d)

Solution:
For DC Analysis the capacitor will be open circuited and the AC Source will be removed as shown below,
VB = 0.7Volt & IC = 100IB
Applying KVL
13.7 − 12  ( IC + IB ) − 100  IB = 0.7
Here IC & IB are in mA
12  101IB + 100IB = 13
13
IB = mA  .01mA
10  101 + 100
IC = IB = 1mA
Small signal AC analysis,

Analog Electronics
IC
gm = = 38.46  10 −3
VT
r =  = 2600
gm
All resistances are in kΩ and all currents in mA and the conductance is in mS.
Applying Nodal analysis at the node having V potential

V V − Vi V − V0
+  + =0
2.6k 10k 100k
Vi V0
( 100 ) 10 100
V 1 +1 +1 = +
2.6 10
V  0.4946 = 0.1Vi + 0.01V0
V = 0.202Vi + 0.02021V0 -----------(1)
Applying Nodal analysis ‘ V0 ’ node
V0 V − V
+ gmV + 0 =0
12k 100k
V0 V − V
+ 38.46V + 0 =0
12 100k
0.0933V0 + 38.45V = 0
From Equation (1)
0.0933V0 + 38.45 0.202Vi + 0.02021V0  = 0
0.87037V0 + 7.7669Vi = 0
V0 7.7669
AV = = = 8.92
Vi 0.87037
So, close option will be A V  10

Note: We could have used Miller’s equivalent also.
Alternatively, for approximate analysis we can consider the circuit as Shunt-Shunt or negative feedback where,
Rf = 100k and R1 = 10k
The gain is then given by,
100
Av = − = −10
10
A v = 10
31. Ans: (d)

Solution:
For mid-band analysis,
We neglect dc-capacitances (short-circuit) and open circuit C & C
As no information about early effect or dc operating point is given, we neglect r & r0
Equivalent circuit based on h-model,

Analog Electronics
Vi
ib =
RS
Vi
V0 = −hfe ibR C = −hfe   RC
RS
V0 RC 10  103
= −hFE  = −100  = −100
Vi RS 10  103
V0
= 100
Vi
32. Ans: (22.32)

Solution:
By KVL in Base Emitter Loop,
VS = IBRS + VBE
5 = IB  (2k ) + 0.7
IB = 2.15 mA
Collector Current, IC = IB = 2.15 × 100 = 0.215 A
For limiting case in active region VCE = VCE (sat)
VCC = 5V = IC RC + VCE (sat)
5 = 0.215 R C + 0.2
RC = 22.32 Ω
33. Ans: (105.133)

Solution:
IC = IB = 75IB
By KVL,
15 = ( IC + IB ) R C + IBRB + VBE
14.3 = 76 (R CIB ) + IBRB
14.3 = IB ( 76R C + RB ) ------------(1)
15 − ( IC + IB ) R C = VC
Since Vc = 9V
(I C
+ IB ) R C = 6
76 ( IBR C ) = 6 ------------(2)
Divide (1) By (2),
14.3 76R C + RB
=
6 76R C
RB
= 1.3833
76R C
RB
= 105.133
RC
34. Ans: (0.75)

Solution:

Analog Electronics
By KVL:
10 − 0.7 9.3
IB = =
RB RB
10 − VC 10 − 2
I C =  IB = =
RC RC
If we replace RC by RC
IB is constant and hence I C is also constant
10 − 2 10 − 4
=
RC R 'C
R 'C 6 3
= = = 0.75
RC 8 4
35. Ans: (c)

Solution:
In saturation mode, both the Emitter-Base and Collector Base Junctions in a transistor are forward biased.
36. Ans: (19)

Solution:
VBE = 0.6V
VB = 5.3Volt (if zener is in Breakdown region)
VE = 5.3 − 0.6V =4.7 V
VE
IE = A = 10mA
470
10 − 5.3
Now I = mA = 1mA
4.7
So, IB = I − 0.5mA = 0.5mA
IE
+1 = = 20
IB
 =19
37. Ans: 172.7

Solution:
The current in second transistor is very small.
So it can be assumed to be in saturation
Is = 1A
Since the transistor are matched Is1 = 1A
 VBE1 V 
Ic1 = Is1  e T − 1 
 
 
 VBE1 
1mA = 1A  e 0.025 − 1 
 
VBE1
1001 = e 0.025
VBE1 = 0.1727V
The voltage drop across both transistor must be same & since IB  0 , VBE2  0 , IE2 = IC2 = 1A

Analog Electronics
IE2R = VBE1
0.1727
R= = 172.7k
1A
38. Ans: (d)
Solution:
By KVL
VCE = VCC − IE ( 4R + R ) = 10 − 5R  IE
5 = 10 − 5R IE
5 = 5R IE
IE R = 1 ………………………(i)
Applying KVL through base emitter junction
10 − 4R IE − RB IB − VBE − R IE = 0
IE
10 − 5R IE − RB  − 0.7 = 0
 +1
 R 
9.3 =  5R + B  IE …….(ii)
 30 
Divide (ii) by (i)
RB
5R +
30 = 9.3
R
RB
5+ = 9.3
30R
RB
= 4.3
30R
RB
= 30  4.3 = 129
R
39. Ans: (90.09)

Solution:
For open circuit
10.7 − ib 10 − 0.7 − 1(1 + )ib = 0
10 = 111 i
10
i =
11
10  101 1010
i = =
111 111
1010 1010
V0c = 1  =
111 111
For sc
10.7 − 10 ib − 0.7 = 0
ib = 1mA

Analog Electronics
Isc = ie = 101 mA
Voc 1010  1000
R th = = = 90.09
Isc 111  101
40. Ans: (17.06)

Solution:
5V
IC = = 1.515mA
3.3k
IE = 1.53 mA
IB = 0.0151 mA
-12 + 1.2 k × 1.53 m + 0.7 + VB = 0
VB = 9.464 V
12 − VB 12 − 9.464
Ix = = = 0.539mA
4.7k 4.7k
Ix + I B = I y
⇒ Iy = 0.5396 + 0.0151
Iy = 0.5546 mA
VB = 0.5546 m × R2 = 9.464
R2 = 17.06 kΩ
41. Ans. (250)

Solution:
Apply OC Test on Zener diode
Given VBE = 0
25 – 7000 IB – 0 – 10IE – 20IE = 0

Analog Electronics
IE I
IB = = E
1 +  100
25 = 100 IE IE = 0.25A = 250 mA
By KVL: -VD – 0 – IE × 10 = 0
VD = -2.5 V
Zener diode is reverse biased but does not operate in breakdown region & hence open.

Analog Electronics
Chapter 3 – MOSFET
01. An enhancement type n-channel MOSFET is (c) 1.4 mA (d) 1.0 mA

represented by the symbol [1999]
05. The value of R for which the PMOS transistor in figure
will be biased in linear region is [2004]
02. An n-channel JFET, having a pinch off voltage (Vp) of

−5V, shows a trans-conductance (gm) of 1mA/V when the (a) 220  (b) 470 
applied gate-to-source voltage (VGS) is -3V. Its maximum (c) 680  (d) 1200 
trans-conductance (in mA/V) is [2001]
(a) 1.5 (b) 2.0 06. Assume that the N-channel MOSFET shown in Figure is
(c) 2.5 (d) 3.0 ideal, and that its threshold voltage is +1.0V. The voltage
Vab between nodes a and b is: [2005]
03. The variation of drain current with gate-to-source
voltage (ID – VGS characteristic) of a MOSFET is shown in
Figure. The MOSFET is [2003]
(a) An n-channel depletion mode device

(b) An n-channel enhancement mode device
(c) A p-channel depletion mode device (a) 5V (b) 2V
(d) A p-channel enhancement mode device (c) 1V (d) 0V
04. For the n-channel enhancement MOSFET shown in 07. The charge distribution in a metal-dielectric-
Figure, the threshold voltage Vth = 2V. The drain current ID semiconductor specimen is shown in Figure. The negative
of the MOSFET is 4 mA when the drain resistance RD is 1 charge density decreases linearly in the semiconductor as
k. If the value of RD is increased to 4k, drain current ID shown. The electric field distribution is as shown in [2005]
will become [2003]
(a) 2.8 mA (b) 2.0 mA

Analog Electronics
08. The trans-conductance of the MOSFET is: [2005]

(a) 0.75mS (b) 1mS
(c) 2mS (d) 10mS
09. The voltage gain of the amplifier is: [2005]

(a) +5 (b) −7.5
(c) +10 (d) −10
10. Given Vgs is the gate-source voltage, Vds is the drain

source voltage, and Vth is the threshold voltage of an
enhancement type NMOS transistor, the conditions for
transistor to be biased in saturation are [2019]
(a) Vgs  Vth ; Vds  Vgs − Vth
(b) Vgs  Vth ; Vds  Vgs − Vth
(c) Vgs  Vth ; Vds  Vgs − Vth
(d) Vgs  Vth ; Vds  Vgs − Vth
11. The enhancement type MOSFET in the circuit below

operates according to the square law. nCox = 100 A/V 2 ,
the threshold voltage (V )
T is 500 mV. Ignore channel
Statement for Linked Answer Questions 8 & 9: length modulation. The output voltage Vout is [2019]
Assume that the threshold voltage of the N-channel
MOSFET shown in Figure is +0.75V. The output
characteristics of the MOSFET are also shown.
(a) 500 mV (b) 600 mV

(c) 2 V (d) 100 mV
12. A common-source amplifier with a drain resistance, RD

= 4.7 kΩ, is powered using a 10 V power supply. Assuming
that the transconductance, gm is 520 μA/V, the voltage
gain of the amplifier is closest to: [2020]
(a) 1.22 (b) –1.22
(c) 2.44 (d) –2.44,

Analog Electronics
13. The cross-section of a metal-oxide-semiconductor 14. For an ideal MOSFET biased in saturation, the
structure is shown schematically. Starting from an magnitude of the small signal current gain for a common
uncharged condition, a bias of +3 V is applied to the gate drain amplifier is [2022]
contact with respect to the body contact. The charge inside (a) 0 (b) 1
the silicon dioxide layer is then measured to be +Q. The (c) 100 (d) infinite
total charge contained within the dashed box shown, upon
application of bias, expressed as a multiple of Q (absolute
value in Coulombs, rounded off to the nearest integer) is
___________. [2020]

Analog Electronics
Solutions
01. Ans: (a)
Solution:
Enhancement types of channel MOSFET symbols are as follows
(1) (2)
(Body is not explicitly shown here body and source are shorted)
The broken line in the representation indicates that there is no channel at zero Gate Voltage and hence it is an
enhancement type device.
02. Ans: (c)

Solution:
2
 V 
For JFET ID = IDSS  1 − Gs 
 VP 

ID 2IDSS  VGs 
Trans-conductance, gm = =  1 − 
VGs VP  VP 
Now, gm = 10 −3 when VP = −5V , VGS = −3V
So, 10
−3
=
5
(
2IDSS
1− 3
5 )
10 −3 = 2 IDSS  2
5 5
IDSS = 6.25  10−3 A

2I
Now maximum trans-conductance g
m.max
= DSS
VP
( at V
GS
= 0)
2  6.25  10 −3
gm,max = A / V = 2.5 mA / V
5
03. Ans: (c)

Solution:
The drain current is non-zero at zero voltage which means the channel exists even at zero voltage. So, it is a depletion
mode device.
2
 V 
ID = IDSS  1 − GS 
 VP 
VP  0
VGS  0

Analog Electronics
Since, the pinch off voltage is positive, it is a p-channel device.

Similarly, for n channel depletion mode device the characteristics are shown below,
As can be seen the pinch off voltage is negative for n-channel device.
04. Ans: (c)

Solution:
In this configuration as the drain and gate terminals are connected,
VDS = VGS
So, VDS  VGS − Vt condition is satisfied. Hence, the transistor is in saturation mode
When ID = 4mA & RD = 1k then VG = VD = 10 − 4  1 = 6V
So, VGS = 6V
2
In Saturation Mode, Now, ID = k  V − Vt 
2  GS
2
So, 4  10 −3 = k 6 − 2 
2
2  10 −3
So, k = = 5  10 −4
4
When RD = 4k then VG = 10 − 4ID ( ID in mA )
5  10−4 2
So, 10  ID = 10 − 4ID − 2 (as ID in mA so 10−3 is multiplied)
−3
2
5  10 −4
 16 ( 2 − ID )
2
10 −3  ID =
2
(
10−3  ID = 4  10 −3 4 + ID 2 − 4ID )
4ID2 − 17ID + 16 = 0
ID = 2.84mA,1.4mA
If ID = 2.84mA
VGS = 10 − 4  2.84 = −1.36  Vt
But for saturation, VGS  Vt
Hence, ID = 1.4mA
05. Ans: (d)

Solution:
Here VS = 4V VG = 0V
So, VSG = 4V  Vt
Drain potential, VD = 10−3R

For linear region or triode region in PMOS,

Analog Electronics
VSD  VSG − Vt
4 − 10−3  R  4 − 1
10−3  R  1
R  103 
So, appropriate option be R = 1200
06. Ans: (d)

Solution:
Based on the system given,
Gate Voltage, VG = 2V
Source Voltage, VS = 0V
Hence, Gate to Source Voltage, VGS = 2V
Threshold Voltage, VTh = 1V
Saturation Voltage, VDs(sat) = VGS - VTh
Due to 10V supply, MOSFET is in saturation and acts as
Short circuit. Hence, Vab = 0V
07. Ans: (a)

Solution:
Electric Field inside a metal is 0 as the charge resides
on the surface of metal.
The dielectric acts as capacitor so the electric field
is constant in the dielectric.
In semi-conductor due to accumulation of
negative charge the charge enclosed in any Gaussian Surface reduces and the electric field decreases. Hence, the electric
field profile looks like as shown below,
08. Ans: (b)

Solution:
Trans-conductance of a MOSFET is given by,
ID ID
gm = =
VGS VGS VDS = Cons t
From output characteristics
gm =
(3 − 2) mA = 1mS
(3 − 2) V
So, Trans conductance =1mS
09. Ans: (d)

Solution:
For AC analysis drawing small signal equivalent

Analog Electronics
Vout
So, gain = = −gmR = −10 −3  10  103 = −10
Vin
So, voltage gain=-10
10. Ans: (c)

Solution:
For saturation, VGS  VTh & VDS  VGS − VTh
11. Ans: (b)

Solution:
Since, MOSFET is in saturation region,
n C 0  W
(V − VT )
2
ID = GS
2L
10A 100m
( V − 0.5 )
2
5A = 
2 10m GS
52 1
(V − 0.5 ) =
2
GS
= = 0.01
100 100
VGS − 0.5 = 0.1
VGS = 0.6
VG − VGS = 0.6 or V0 − 0 = 0.6
V0 = 0.6V = 600 mV
12. Ans: (d)

Solution:
Given data : RD = 4.7 kΩ, gm = 520 μA/V
Voltage gain of CS amplifier
= -gmRD
= -520 μAV × 4.7kΩ
= - 2.44
13. Ans: (0)

Solution:
+ + + + + + GATE + + + + + + + + Q
Silicon Dioxide
Si
BODY
The positive terminal of battery connected at gate delivers +Q charge to SiO2 layer through Gate.
At the same time negative terminal of battery delivers equal & opposite charge so, net charge = 0
Note: A battery always delivers equal & opposite charge

Analog Electronics
14: Ans : (d)

Solution:
For common drain amplifier,
Input current = Ig
Output current = Is
Due to SiO2 layer, Ig = 0
I
Current gain = s → 
Ig

Analog Electronics
Chapter 4 – OP-AMP
01. With ideal operational amplifiers, the circuit in figure

simulates the equation [1991] 05. In the following circuit (figure.), the output V follows an
equation of the form [1992]
d2 v dv
+a + bv = f ( t )
dt2 dt
Find a, b and f(t).
02. In figure shown, assume the Zener diode and the

operational amplifier to be ideal. [1991]
(a) Draw the equivalent circuit and evaluate the gain
( V0 vs Vi ) of the circuit for
06. An analog comparator is a high-gain amplifier whose

output is always either in positive or in negative saturation.
[1994]
07. Given figure shows a two-stage small signal transistor

(i) Vi  0 feedback amplifier. Match the defective component (listed
on the left hand side below) with its probable effect on the
(ii) 0  Vi  5V
circuit (listed on the right hand side below) [1994]
(iii) 5V  Vi
(b) Sketch the gain ( V0 vs V ) characteristics of the above
circuit and label the salient features
03. An ideal OPAMP is used to make an inverting amplifier.

The two input terminals of the OP-AMP are at the same
potential because [1992]
(a) The two input terminals are directly shorted internally
(b) The input impedance of the OPAMP is infinity
(c) The open loop gain of the OPAMP is infinity
(d) CMRR is infinity
(a) Capacitor C1 is open
(b) Capacitor C3 is open
04. The circuit shown in figure is excited by the input
(c) Capacitor C4 is open
shown in the figure. Sketch the waveform of the output
(d) RC2 is shorted
also indicating the salient values. Assume all components
to be ideal. [1992]
(P) All dc voltages normal, V0 increases marginally
(Q) Collector of TR2 is at VCC, V0 = 0
(R) All dc voltages normal, gain of 2nd stage increase V0
decrease
(S) All dc voltages normal, V0 = 0
(T) All dc voltages normal, overall gain of the amplifier

Analog Electronics
increases, V0 increases
(U) No change
08. Given figure, shows a non-inverting op-amp summer

with V1 = 2V and V2 = −1V . The output voltage V0 =
__________________ [1994]
12. A non-inverting Op-Amp amplifier is shown in figure.

The output voltage Vo is [1996]
09. The common mode voltage of a unity gain (voltage

follower) op-amp buffer in terms of its output voltage V0
is ______________ [1995]
(a) ( 3 / 2 ) sin (100t ) (b) 3sin (100t )

V0 ( s )
10. For the circuit shown in figure, determine and (c) 2 sin (100t ) (d) None of these
Vi ( s )
hence write the equations for the magnitude and phase 13. Let the magnitude of the gain in the inverting OP-Amp
response of 0 . If the value of R 1 is 100k Ohm and of R is
V amplifier circuit shown in be x with switch S1 open. When
Vi the switch S1 is closed the magnitude of gain becomes
10k Ohm, determine the value of C to obtain a phase shift [1996]
to 270° between V0 and Vi for an input frequency of

1000rad/s. [1995]
(a) x / 2 (b) –x
11. For the circuit shown in figure, determine the input
impedance Z. assume the op-amp to be an ideal one. (c) 2x (d) -2x
[1995]
14. A major advantage of active filters is that they can be
realized without using [1997]
(a) op-amps (b) inductors
(c) resistors (d) capacitors
15. A differentiator has transfer function whose

[1997]
(a) Phase increases linearly with frequency
(b) Amplitude remains constant

Analog Electronics
(c) Amplitude increases linearly with frequency

(d) Amplitude decreases linearly with frequency
16. The circuit shown in figure, acts as a… and for the given
inputs, its output voltage is… V [1997] (a) (P) High-pass filter
(b) (Q) Amplifier
17. For an input signal 4 sin 10t, the voltage across the
resistance R in the circuit shown in figure, is … V
[1997] (c) (R) Comparator
(S) Low-pass filter
20. In the circuit shown in fig Rs = 2k and, RL = 5 k. For

the op-amp, A = 105 , R1 = 100 k and R0 = 50. For V0
= 10V, calculate v s and

V0
and estimate the input
VS
resistance of the circuit [1998]
18. Determine the frequency of oscillation of the circuit
shown in figure. Assume the op-amp to be ideal
[1997]
21. Show that the circuit given in fig. 24 will work as an

1 R1 = 2R2
oscillator at f = , if [1998]
2RC
19. Match the column [1998]

Circuit

Analog Electronics
25. An active filter consisting of an op-amp, resistors

22. The input voltage v i in the circuit shown in fig is a 1
kHz sine wave of 1V amplitude. Assume ideal operational
R1 ,R2 ,R3 and two capacitors of value C each, has a
amplifiers with 15V DC supply. Sketch on a single transfer function [2000]
−s
diagram the waveforms of the voltages vi and v 1 shown,
T (s) =
(R 1 C )
indicating the peak value of v1 and the average value v0 2s 1
s2 + +
[1999] ( 3 )
R C RR(3
C2 )
Where R = R1 || R2
2
If R1 = 2k, R 2 = k, R 3 = 200k and C = 0.1F ,
3
determine the center frequency 0 , gain A 0 and the Q of
the filter.
23. The circuit shown is fig. uses an ideal op-amp working 26. An op-amp has an open-loop gain of 105 and an open-
loop upper cutoff frequency of 10 Hz. If this op-amp is
+5V and -5V power supplies. The output voltage V0 is connected as an amplifier with a closed gain of 100, then
equal to [2000] the new upper cutoff frequency is [2001]
(a) 10 Hz (b) 100 Hz
(c) 10 kHz (d) 100 kHz
27. For the oscillator circuit shown in figure, the expression

for the time period of oscillation can be given by (where 
= RC) [2001]
(a) +5V (b) -5V

(c) +1V (d) -1V
24. The feedback factor for the circuit shown in fig. is:
[2000]
(a)  ln 3 (b) 2 ln 3
(c)  ln 2 (d) 2 ln 2
28. An op-amp having a slew rate of 62.8 V/µsec, is

connected in a voltage follower configuration. If the
9 9 maximum amplitude of the input sinusoid is 10V, then the
(a) (b)
100 10 minimum frequency at which the slew rate limited
1 1 distortion would set in at the output is [2001]
(c) (d) (a) 1.0 MHz (b) 6.28 MHz
9 10
© 10.00 MHz (d) 62.8 MHz
29. For the op-amp circuit shown in figure, determine the

output voltage V0. Assume that the op-amps are ideal.
[2001]

Analog Electronics
 Vy 
33. Determine the transfer function   for the RC
 Vx 
 
network shown in Figure (a). This network is used as a
feedback circuit in an oscillator circuit shown in Figure (b)
to generate sinusoidal oscillations. Assuming that the
operational amplifier is ideal, determine RF for generating
these oscillations. Also, determine the oscillation frequency
if R = 10 k and C =100pF. [2002]
30. A simple active filter is shown in Figure. Assume ideal

V
op-amp. Derive the transfer function 0 of the circuit, and
Vi
state the type of the filter (i.e., high-pass, low-pass, band-
pass, or band-reject). Determine the required values of R1,
R2 and C in order for the filter to have a 3-dB frequency of
1 kHz, a high frequency input resistance of 100 k, and a
high frequency gain magnitude of 10. [2001]
31. A first order, low pass filter is given with R = 50 Ω and

C = 5 μF. What is the frequency at which the gain of the 34. For the circuit of Figure with an ideal operational
voltage transfer function of the filter is 0.25? [2002] amplifier, the maximum phase shift of the output Vout with
(a) 4.92 kHz (b) 0.49 kHz
(c) 2.46 kHz (d) 24.6 kHz reference to the input Vin is [2003]
32. The output voltage ( V ) of

0
the Schmitt trigger shown
in Figure swings between +15V and –15V. Assume that the
operational amplifier is ideal. The output will change from
+15V to –15V when the instantaneous value of the input
sine wave is [2002]
(a) 0° (b) −90°

(c) +90° (d) 180°
35. Assuming the operational amplifier to be ideal, the gain

Vout
for the circuit shown in Figure is [2003]
Vin
(a) 5 V in the positive slope only
(b) 5 V in the negative slope only
(c) 5 V in the positive and negative slopes
(d) 3 V in the positive and negative slopes

Analog Electronics
(a) −1 (b) −20

(c) −100 (d) −120 (a) Infinity (b) 1 M
(c) 100 M (d) 40 k
36. In the active filter circuit shown in figure, if Q=1, a pair
of poles will be realized with 0 equal to [2004] 39. In Figure if the input is a sinusoidal signal, the output
will appear as shown in [2005]
(a) 1000 rad/s (b) 100 rad/s

(c) 10 rad/s (d) 1 rad/s
 V 
37. The input resistance R IN  = x  of the circuit in figure
 i 
 x 
is [2004]
(a) +100k (b) −100k
(c) +1 M (d) – 1M
38. Consider the inverting amplifier, using an ideal

operational amplifier shown in Figure. The designer wishes
to realize the input resistance seen by the small signal
source to be as large as possible, while keeping the voltage
gain between –10 and –25, the upper limit on RF is 1 M.
The value of R1 should be [2005]

Analog Electronics
40. For a given sinusoidal input voltage, the voltage 42. A relaxation oscillator is made using OPAMP as shown
waveform at point P of the clamper circuit shown in figure in figure. The supply voltages of the OPAMP are 12V.
will be [2006] The voltage waveform at point P will be [2006]
41. The parameters of the circuit shown in the figure are

Ri = 1M,Ro = 10,A = 106 V / V . If Vi = 1V , then
output voltage, input impedance and output impedance
respectively are [2006]
43. The circuit shown in the figure is [2007]
(a) 1V, , 10 (b) 1V, 0, 10

(c) 1V, 0,  (d) 10V, , 10

Analog Electronics
(a) A voltage source with voltage rV

R1 || R 2
r || R 2
(b) A voltage source with voltage V
R1
r || R 2 V
(c) A current source with current .
R1 + R 2 r
R2 V
(d) A current source with current .
R1 + R 2 r
44. The switch S in the circuit of the figure is initially closed.

It is opened at time t = 0. You may neglect the Zener
diode forward voltage drops. What is the behavior of VOUT
for t > 0? [2007]
(a) It makes a transition from −5V to +5V at t = 12.98 µs

(b) It makes a transition from −5V to +5V at t = 2.57 µs
(c) It makes a transition from +5V to −5V at t = 12.98 µs
(d) It makes a transition from +5V to −5V at t = 2.57 µs
45. A waveform generator circuit using OPAMPs is shown

in the figure. It produces a triangular wave at point ‘P’ with
a peak to peak voltage of 5 V for Vi = 0V. [2008] Statement for Linked Answer Questions 46 and 47:
A general filter circuit is shown in the figure:
If voltage Vi is made +2.5V, the voltage waveform at point

‘P’ will become
46. If R1 = R2 = RA and R3 = R 4 = RB , the circuit acts as a
[2008]
(a) All pass filter

Analog Electronics
(b) Band pass filter

(c) High pass filter
(d) Low pass filter
47. The output of the filter in Q.80 is given to the circuit

shown in figure:
(a) 10mA leading by 90° (b) 20mA leading by 90°

The gain vs frequency characteristic of the output ( V0 ) will (c) 10mA leading by 90° (d) 10mA lagging by 90°
be [2008]
49. An ideal op-amp circuit and its input waveform are
shown in the figures. The output waveform of this circuit
will be [2009]
48. The following circuit has R = 10k, C = 10µF. The input

voltage is a sinusoid at 50Hz with an RMS value of 10V.
Under ideal conditions, the current iS from the source is[2009]

Analog Electronics
The correct transfer characteristics is
50. Given that the op-amp is ideal, the output voltage V0

is [2010]
(a) 4V (b) 6V
(c) 7.5V (d) 12.12V
51. A low-pass filter with a cut-off frequency of 30Hz is

cascaded with a high-pass filter with a cut-off frequency of
20Hz. The resultant system of filters will function as [2011]
(a) an all-pass filter
(b) an all-stop filter
(c) a band stop (band-reject) filter

(d) a band-pass filter
52. For the circuit shown below, [2011]
53. The circuit shown is a [2012]

Analog Electronics
56. Given that the op – amps in the figure are ideal, the
output voltage V is [2014-01]
o
(a) Low pass filter with f = 1

rad / s
3dB
(R 1
+ R2 ) C
(b) High pass filter with f3dB = 1 rad / s

R1 C
( 1 2)
(a) V − V (b) 2 V − V (1 2 )
1
(c) Low pass filter with f3dB = rad / s (c) ( V − V ) / 2 (
(d) V + V )
R1 C 1 2 1 2
(d) High pass filter with f = 1

rad / s 57. An oscillator circuit using ideal op-amp and diodes is
3dB
(R 1
+ R2 ) C shown in the figure. [2014-02]
54. In the circuit shown below what is the output voltage

( Vout ) in Volts if a silicon transistor Q and an ideal op-
amp are used? [2013]
The time duration for +ve part of the cycle is t1 and for
t1 −t2
–ve part is t2 . The value of e RC

will be ____________.
(a) -15 (b) -0.7
(c) +0.7 (d) +15 58. An operational-amplifier circuit is shown in the figure
[2014-03]
55. In the circuit shown below the op-amps are ideal. Then
V out in Volts is [2013]
The output of the circuit for a given input v i is

R   R 
(a) −  2  v i (b) −  1 + 2  v i
(a) 4 (b) 6 R   R1 
 1 
(c) 8 (d) 10
(d) +Vsat or − Vsat
 R 
(c)  1 + 2  v i
 R 
 1 

Analog Electronics
59. The transfer characteristics of the op-amp circuit shown a frequency of 50Hz, represented as a phasor with
in figure is [2014-03]
magnitude Vi and phase angle 0 radian as shown in the
figure. The output voltage is represented as a phasor with
magnitude V0 and phase angle  radian. What is the value
of the output phase angle  (in radian) relative to the
phase angle of the input voltage? [2015-01]
(a) 0 (b) 
(c)  (d) −
2 2
62. The op – amp shown in the figure has a finite gain A =

1000 and an infinite input resistance. A step voltage
Vi = 1mV is applied at the input at time t = 0 as shown.
Assuming that the operational amplifier is not saturated,
the time constant (in millisecond) of the output voltage V0
is [2015-01]
60. Of the four characteristics given below, which are the

major requirements for an instrumentation amplifier? (a) 1001 (b) 101
[2015-01] (c) 11 (d) 1
P. High common mode rejection ratio
Q. High input impedance. 63. The operational amplifier shown in the figure is ideal.
R. High linearity. The input voltage (in Volt) is Vi = 2 sin ( 2  2000t ) , The
S. High output impedance.
amplitude of the output voltage V0 (in Volt) is____________.
(a) P, Q and R only (b) P and R only
(c) P, Q and S only (d) Q, R and S only [2015-02]
61. Consider the circuit shown in the figure. In this circuit

R = 1k and C = 1F . The input voltage is sinusoidal with

Analog Electronics
64. The saturation voltage of the ideal op – amp shown

below is ±10V. The output voltage V0 of the following
circuit in the steady – state is [2015-02]
(a) Square wave of period 0.55ms

(b) Triangular wave of period 0.55ms.
(c) Square wave of period 0.25ms
(d) Triangular wave of period 0.25ms.

Analog Electronics
65. The circuit shown below is an example of a (b)

[2016-02]
(c)
(d)
(a) low pass filter (b) band pass filter

(c) high pass filter (d) notch filter.
66. For the circuit shown below, taking the opamp as ideal,
the output voltage Vout in terms of the input voltages V1 , 68. For the circuit shown below, assume that the OPAMP is
ideal [2017-02]
V3 and V3 is [2016-02]
(a) O = s (b) O = 1.5 s

(a) 1.8V1 + 7.2V2 − V3 (b) 2V1 + 8V2 − 9V3
(c) O = 2.5 s (d) O = 5 s
(c) 7.2V1 + 1.8V2 − V3 (d) 8V1 + 2V2 − 9V3
69. The op-amp shown in the figure is ideal. The input
67. The approximate transfer characteristic for the circuit V
impedance in is given by [2018]
shown below with an ideal operational amplifier and diode tin
will be [2017-01]
R1 R2
(a) Z (b) − Z
R2 R1
(a)
R1
(c) Z (d) −Z s
R1 + R 2

Analog Electronics
70. In the circuit below, the operational amplifier is ideal. If

V1 = 10 mV and V2 = 50 mV , the output voltage ( Vout )
is [2019]
(a)
(a) 600 mV (b) 100 mV

(c) 500 mV (d) 400 mV
(b)
71. A CMOS Schmitt-trigger inverter has a low output level
of 0 V and a high output level of 5 V. It has input
thresholds of 1.6 V and 2.4 V. The input capacitance and
output resistance of the Schmitt-trigger are negligible. The
frequency of the oscillator shown is ______________ Hz.
(Round off to 2 decimal places.) [2021] (c)
(d)
72. The steady State output (Vout) of the circuit shown

below, will [2022]
74. The current gain (Iout/Iin} in the circuit with an ideal

current amplifier given below is [2022]
(a) saturate to +VDD

(b) saturate to - VEE
(c) become equal to 0.1 V
(d) become equal to -0.1 V
73. The output impedance of a non-ideal operational

amplifier is denoted by Zout The variation in the magnitude
of Zout with increasing frequency, f, in the circuit shown
below, is best represented by [2022]

Analog Electronics
Cf −Cf (a) The maximum and minimum values of the output

(a) (b) voltage VO are +15 V and –10 V, respectively.
Cc Cc (b) The maximum and minimum values of the output
Cc −Cc voltage VO are +5 V and –15 V, respectively.
(c) (d) (c) The maximum and minimum values of the output
Cf Cf voltage VO are +10 V and –5 V, respectively.
(d) The maximum and minimum values of the output
75. Consider the OP AMP based circuit shown in the figure. voltage VO are +5 V and –10 V, respectively.
Ignore the conduction drops of diodes D1 and D2. All the
components are ideal and the breakdown voltage of the
Zener is 5 V. Which of the following statements is true?
[2023]

Analog Electronics
Solutions
01. Ans: ----
Solution:
The first Op-Amp acts as an integrator.

Output of the integrator,
1 1
V1 = −
RC  V1dt = −
10  100  10 −3 
V1dt = − V1dt 
The second Op-Amp acts as summer and its output is,
 R R R 
V0 = −  V1 f + V2 f + V3 f  = +2 V1dt − 4V2 − 5V3
R R R

 1 2 3 
02. Ans: ----

Solution:
(a) (i) When Vi < 0, zener diode becomes forward biased & since it is ideal, it acts as short circuit.
Equivalent source resistance = 0.5 kΩ

This acts as Inverting Amplifier
VO −R f
Gain = = = −1 = –2
Vi R1 0.5
(ii) When 0 < Vi < 5, zener diode becomes reverse biased & acts as open circuit
Source resistance = 1 kΩ
VO
Gain = = −1 =–1
Vi 1

Analog Electronics
(iii) When Vi > 5, zener diode operates in break down region.
By superposition
( 1 ) + V ( –1 1 ) = (5 - 2V )
VO = (Vi – 5) –1 i i
(b) The characteristics of the system are given below,
03. Ans: (c)

Solution:
V0 = ( V+ − V− ) A OL
AOL = Open loop gain
V0
Now V+ − V− =
AOL
V0 is always bound between +VSat − VSat (Supply voltages of OPAMP)
As AOL → 
V+ − V− = 0
V+ = V−
So, this is called as virtual ground phenomena and it is due to infinite open loop gain
04. Ans: -----

Solution:
Initially the capacitor was discharge so V0 = 0
Now when Vi  0 diode D 1 conducts
and capacitance gets charged
So, D 2 is OFF as its anode (P side) is at 0 volt and cathode side at positive voltage.

Analog Electronics
Up to for t=0.5sec, the capacitor charges up to 1V after that V− = 1V and V+  1V as the input voltage starts decreasing.
So the Op-amp output switches towards −VSat . This makes D 1 OFF and now capacitor has no path to discharge.
So, capacitor hold its charge at V0 = 1 V
05. Ans: ----

Solution:
The upper two Op-Amps are shown below,
Both the circuits are standard realization of Integrator,

For the 1st Op-Amp,
1
RC  1
V2 = − V dt
dV
V1 = −RC 2 -------- (1)
dt
Similarly, for 2nd Op-Amp,

dV
V2 = −RC -------- (2)
dt
The voltage of non-inverting terminal of Op-Amp can be determined by Superposition.

1
V+ = (
V + et
2 2
)
By Virtual Ground Concept,
1
V+ = V− = (V + et
2 2
)
Applying KCL at the Inverting Terminal,
d V
C
dt
( V+ − V1 ) = +
R
d
RC ( V+ − V1 ) = V+
dt
1 1
RC ( V1 − V+ ) =  V+dt = et +  V2dt
2 2

Analog Electronics
From (1) and (2)

dV2 dV
V1 = −RC = R 2C2
dt dt
 d V V +e  1 t 1
2 t
RC R 2C2 2 − 2  = e +  V2dt
 dt 2  2 2
d2 V 1 t 1  dV  1 t 1
2RC  2
R 2C2 − e −  −RC = e + V dt
dt 2
2 2 dt  2RC
1
RC  2
From (2), V dt = −V
d2 V 1 dV 1 t 1 t 1
R 2 C2 + RC − e = e − V
dt 2
2 dt 2 2RC 2
R 2C2
d2 V 1
+ RC
dt2 2
dV 1
dt 2
1
+ V = et 1 + 1
2 RC ( )
d2 V
dt 2
+
1 dV 1 1
+ 2 2 V = 2 2 et 1 + 1
2RC dt 2R C 2R C RC ( )
Comparing
a=
1
2RC
b=
1
2R 2C2
f (t) =
1
2R C
2 2 (
et 1 + 1
RC )
06. Ans: (True)
Solution:
If V+  V− then V0 = +VSat and if V+  V− then V0 = −VSat
So this is true.
07. Ans: (a-S, b-R, c-T, d-Q)

Solution:
(a) If coupling capacitor C 1 is open, the AC signal VS could have not been applied at all. So, V0 could have been ‘0’ but
DC analysis would not change (S ) .

(b) If C 3 is opened D.C. analysis would have been same. But due to analysis R C2 the gain of feedback would have
increased to decrease V0 (R ) .
(c) If C 4 is open D.C. voltage would have been same (at DC capacitors have as open circuit). But negative feedback via R F
would not be there. So, net increase in gain would have taken place would have V0 increased. (T)
(d) If R C2 is shorted D.C. voltage of collector of TR2 would be VCC and V0 = 0V [as during AC analysis DC source are
deactivated]. (Q )
08. Ans: (1V)
Solution:
The output can be determined by the use of Superposition.
The voltage of non-inverting terminal due to 2V supply is,
R
2 2
V+1 = 2  = V
R+R 3
2

Analog Electronics
R
2 1
V+2 = −1  =− V
R+R 3
2
2 1 1
Overall, V+ = − = V
3 3 3
 2R  1
V0 =  1 +   V+ = 3V+ = 3  3 = 1V
 R 
09. Ans: (V0)

Solution:
1
Common mode voltage ( V + V− ) = 12 ( Vi + V0 )
2 +
For Voltage Follower, Vi = V0
1
So, common mode voltage = ( V + V0 ) = V0
2 0
10. Ans: (0.1μF)

Solution:
The output can be determined by the use of Superposition,
Output due to Inverting Terminal Voltage,
 R
V01 = Vi  −  = −Vi
 R
Voltage of Non-Inverting Terminal by Potential Division,
 1 
 jC   1 
V+ = Vi    = Vi   1 + jRC 
1
 R + jC   
 
Output due to Non-Inverting Terminal Voltage,
 1  R  1 
V02 = Vi    1 +  = 2Vi  
 1 + jRC   R  1 + jRC 
Net Output Voltage,
 1   1 − jRC 
V0 = V01 + V02 = −Vi + 2Vi   = Vi  
 1 + j RC   1 + jRC 
The Phase Shift between input and output is,

 = −2tan−1 ( RC ) = 2700
RC = 1
1 1
C= = = 0.1F
R 1000  10 4

Analog Electronics
11. Ans: (R1)

Solution:
To determine the input impedance, we need to connect a supply at the input terminal and determine the current through
it,
Here we applied a test voltage Vt and current from it is I t

Now, V+ = Vt and V− = V0
The voltage of negative terminal is same as output voltage as no current flows through RL since the input current of an
Op-Amp is zero.
By Virtual Ground,
V0 = V+ = Vt
Now applying Node analysis at positive terminal,
Vt − 0 V − V0
− It + t =0
R1 R1
Now Vt = V0
Vt
So, − It = 0
R1
Vt
= R1
It
Vt
So, Z1 = = R1
It
12. Ans: (a)

Solution:
The voltage of Non-Inverting Terminal can be determined by Superposition Theorem and using Potential Divider,
R R 1
V+ = −2  + ( 2 + sin100t )  = sin100t
R +R R +R 2
V0 = 1 + 2R( R ) V+
= 3 sin100t
2
13. Ans: (a)

Solution:
The circuit configuration with both switch open and closed is shown below,

Analog Electronics
With switch open,

2R
Gain x = − = −2
R
Now when switch is closed
Gain x' = − R = −1
R
So, x ' = x
2
14. Ans: (b)

Solution:
Major advantage of active filter is that they can be realized without inductor. Inductor is implemented by linear circuit op-
amps.
15. Ans: (c)

Solution:
A differentiator has transfer function as T.F ( s ) = ks
T.F ( j) = jk
Phase = 900
So, for differentiator amplitude increases linearly with frequency.
16. Ans: (-3V)

Solution:
The circuit acts as an adder/ a summer
 R R   1 1
V0 = −  V1 f + V2 f  = −  1  + 2   = −3V
 R 1
R 2   1 1
So, output =-3V
17. Ans: ----

Solution:
The given circuit is shown in the figure below,
During positive half cycle of the input 4sin10t,
the voltage of inverting terminal of Op-Amp is
more than non-inverting terminal so the output will
be -Vsat.
The buffer at the output transmit the signal to FET
which will remain OFF due to negative voltage input.
Hence, no current flows through the reistance R and
the voltage across it is V = 0.
During negative half cycle, the voltage of inverting terminal is less than non-inverting terminal and hence the output will
be +Vsat. This will cause FET to turn ON and high current flows through it will negligible voltage drop between source and
drain and hence voltage across R is, V = 24V.
18. Ans: (33.863)

Solution:
1
This is a Wien – Bridge Oscillator with frequency =
2RC

Analog Electronics
1 1
f= = = 33.863 Hz
2  4.7  10 −6  103 2  4.7  10 −3
19. Ans: (a-R, b-S, c-P)

Solution:
(a)
No feedback is there, so it acts as comparator
(R)
(b) When =0 capacitor is open circuit
( ) −R R
So, gain at  = 0 = − f
When  =  capacitor acts as short circuit

V0 = 0
So gain (  =  ) =0
So this is a LPF ( S )
(c)
This is a HPF (P )
Check in the same way (  = 0 and  =  )
20. Ans: (10V, 1, 1010Ω)

Solution:
The system given is shown in figure,

Analog Electronics
Assuming the following VCVS model for the Op-amp as shown above,
Here, Ri = 100k , R0 = 50 , RL = 5k , RS = 2k
Vi = ( VS − IR
i S
− V0 ) = IR
i i
Applying nodal analysis at output node

V0 V0 − AVi
+ − Ii = 0
RL R0
And Vi = IiRi
V0 V0 − AIiR i
So, + − Ii = 0
RL R0
 1 1   AR i 
V0  +  = Ii  + 1 
R
 L R 0 
R
 0 
For V0 = 10V
 1 1   105  105 
10  +  = Ii  + 1
 5000 50   50 
So, Ii = 1.01  10−9 A

Again, VS − IiRS − V0 = IiRi
VS = Ii (R S + R i ) + V0
VS = 10.00010302  10V
Note: This can also be determined if we neglect the input current to Op-Amp then VS  V0 = 10V
V0 10
So, gain = =1
VS 10
(b)
Input Resistance,
V
Z in = in
Ii
Vi = Vin − V0 and Vi = IiRi
V0 V0 − AVi
Here, + − Ii = 0
RL R0
 1 1   AR i 
V0  +  =  + 1  Ii
 R L
R 0   R0 
Vin = Vi + V0 = IiRi + V0
 AR 
Ii  i + 1 
R
Vin = IiR i +  0 
1 1 
 + 
R
 L R 0 

Analog Electronics
 AR i   105  105 
 +1   +1
Vin R  100k +  50
Z in = = Ri +  0   1010  1010 
Ii  1 1   1 + 1 
+
 R R  
 5000 50 

 L 0 
So, Zin = 1010 
21. Ans: ----

Solution:
Here ZP is the parallel constitution of ‘R’ & ‘C’
And ZS is the series combination of ‘R’ & ‘C’
 R 
A = 1 + 1 
 R 2
Vf ZP 1
= = =
V0 ZP + Z S 1 + YP Z S
YP = jC + 1
R
ZS = R + 1
j C
1 1
= =
( 
1 + jC + 1  R + 1
R  ) 
jC 
3 + jCR −
j
CR
AB = 100 (Barkhausen criteria)
So,  should be real positive for phase of AB to be 00 ( AB = 0 )
Imaginary part of ( ) = 0
CR = 1
CR
1
=
CR
1
f=
2CR
1
At  = = 1
CR 3
So AB = 1
R1
A = 13 = 3  1 + =3
R2
R1 = 2R2
22. Ans: ----

Solution:
The given system is shown below,

Analog Electronics
Case-1: when the diode in off
This happens when anode voltage of Diode is less than its cathode voltage.
Here V01 = − Vi  5 = −5Vi
1
And V1 =0 V
So, Diode will remain in reverse bias when V01  V1
−5Vi  0
Vi  0
Case-2: Diode in ON
So, V01 =
(
− 5k 10k )  V = − 50
V = −3.33Vi
1k i
15 i
As diode is ON Vi < 0 so that output is positive and Diode is Forward Biased.
V1 = V01
The waveform for Vi and V1 is shown in the figure below,
23. Ans: (d)

Solution:
Va = V+ = 0V (Due to Virtual Ground)
Since, the current into the Op-Amp is 0A, the entire
Current passes through the 1kΩ resistor.
V0 = 0 − 1k  1mA = −1V

Analog Electronics
24. Ans: (d)

Solution:
Feedback Factor is ratio of feedback voltage to output voltage which can be determined by potential divider.
Vf 10 10
Feedback factor  = = = =1
V0 10 + 90 100 10
25. Ans: (103, -50, 100)

Solution:
− s
(R C )
Transfer Function, T s = () 2s 1
1
s +
2
+
R 3C RR 3C2 ( )
Comparing the denominator with second order general can equation = s2 + 20s + 02
1
Here, natural frequency 0 =
RR 3C2
2 2
Here R = R1 R 2 = 3 k = 0.5k
2+ 2
3
R3 = 200k
C = 0.1F
1 1 1 1
So, 0 = = = rad / sec = rad / sec = 103rad / sec
RR 3C 2
C RR 3 10 −7
200  0.5  10 6 10 −7  10 4
j
 −
R 1C 0 R −200  103
Now, A 0 = T ( j0 ) = =− 3 = = −50
2  0 j 2R1 2  2  103
6
(
10 − 10 +
6
R 3C
)
So, gain A0 = −50
1
Q=
2
Now 20 = 2
R 3C
1  R C 103  200  103  10 −6

Q= = 0 3 = = 100
2 2 2
So, 0 = 103 rad / sec

A0 = −50,Q = 100

Analog Electronics
26. Ans: (c)

Solution:
We know the gain bandwidth product of an op-amp is constant.
So, A1  fc1 = A2  fc2
10  105 = 100  fc2

106
fc2 = = 10kHz
102
Due to negative feedback gain decreases and bandwidth increases.
27. Ans: (b)

Solution:
The feedback voltage based on potential divider is,
R V
V+ = V0  = 0
R +R 2
Assume that initially the output is, V0 = −Vsat
V0 V
The capacitor would charge to a voltage V+ = = − sat
2 2
If capacitor voltage goes below this value the voltage of inverting terminal becomes less than non-inverting terminal and
output switches from −Vsat to + Vsat
VSat
V+ =
2
( )
, now capacitor is getting charged to the supply of VSat . So, VC  = VSat
V
But its initial voltage is VC ( 0 ) = − Sat
2
−t
So, VC ( t ) = VC (  ) +  VC ( 0 ) − VC (  )  e 
 
VSat 3 −t
VC ( t ) = − VSate 
2 2
VSat −t
= Vsat − 3 Vsate 
2 2
V
(When VC ( t ) = Sat the output again switches its state)
2
t =  ln3
So, total charging and discharging time = 2 ln3
28 Ans: (a)
Solution:
We know for avoiding distortion
 dV 
Slew Rate   0 
 dt max
Now if V0 is sinusoidal (V 0
= Vm sin t )
 dV0 
  = Vm
 dt max
So, 62.8  106  10  
62.8  106
f
2  10

Analog Electronics
f  106 Hz (For no distortion)

The minimum frequency that will be set in distortion due to slew rate is 106 Hz or 1MHz.
29. Ans: (0.4)

Solution:
For 1st Op-Amp applying superposition
( )
 2
V01 = V1  2 + 1 + 1   −  = V1  3 − 2 = 3V1 − 2
1  1
 1  V0
V1 = V0   = 4
1 + 3
For 2nd Op-Amp applying superposition
(
V0 = V01  − 3
4 ) + ( −1)  (1 + 8 4 ) = −2V 01
−3
V0
V01 = 3V1 − 2 = 3  − 2 = 3 V0 − 2
4 4
So, V0 = −2  3 V0 − 3 + 4
4
(
Or, 1 + 3
2 )V0
= −3 + 4
5 V =1
2 0
V0 = 2 = 0.4V
5
30. Ans: (100kΩ, 1MΩ, 1.5915nF)

Solution:
The given system is shown,
Apply nodal analysis at Inverting terminal
0 − V1 0 − V0
+ =0
1 R2
R1 +
sC
 
 R 
V0 = −V1   2

R + 1 
 1 
 sC 
V0 −R 2
T.F = =
V1  1 
 R1 + 
 Sc 
Here s = j A = V0 = R2
=
sCR 2
V1  1  1 + sCR1
 R1 + 
 sC 
− jCR 2
TF =
1 + jCR1
And when,  = 0 , A ( = 0) = 0

Analog Electronics
When  =  , A ( = ) = R 2
R1
So, this is High-Pass filter.
1
3dB cutoff frequency fC = = 103
2R1C
High frequency input resistance R1 = 100k
C is shorted at high frequency
1
So, = 103
2  105  C
1
C= = 1.5915 nF
2  108
R2 =10
gain = −
R1
So, R2 = 10R1 = 10  100k = 1M
So, R1 = 100k R2 = 1M C = 1.5915 nF
31. Ans: (c)

Solution:
RC Low Pass Filter with DC Gain of 1 has the Transfer Function,
1 1
TF = =
1 + sRC 1 + jRC
Gain =0 = 1 = DC Gain
Since, the Gain should be 0.25
1
0.25 =
1 + 2R 2C2
1 + 2R2C2 = 16
15
=
RC
15 15
Frequency, f = = = 2.46kHz
2RC 2  50  5  10 −6
32. Ans: (a)

Solution:
When output voltage =+15V
The voltage at non-inverting terminal of Op-Amp can be calculated by using superposition theorem,
3 10 45 + 20
Voltage potential at non inverting terminal = 15  + 2 = = 5V
13 13 13
So, VUTP = 5V
Similarly, when output voltage =-15V
3 25
VLTP = −15  + 2  10 =− V
13 13 13
So, the transfer curve of the Schmitt trigger will be as follows

Analog Electronics
The output will change from +15 V to -15V when

instantaneous value of input sine wave = VUTP = 5V
on positive slope.
Note: It can also be understood that the output will change from 15V to -15V when voltage of non-inverting terminal
goes above UTP i.e. 5V and to go above UTP it must be increasing i.e. positive slope.
33. Ans: (2kΩ, 159.15 kHz)

Solution:
The given RC network is shown below,
Applying Nodal Analysis at node of voltage ‘V’
V − VX V − VY V
+ + =0 -------(1)
R 1 1
sC sC
R sCR
VY = V  = V
1 1 + sCR
R+
sC
From (1)
V − VX
+ ( V − VY ) sC + VsC = 0
R
V (1 + 2sCR ) = VX + VY sCR
(1 + sCR )
sCR
(1 + 2sCR ) V Y
= VX + VY sCR
sCR VX = VY 1 + 2 ( sCR ) + 3sCR − ( sCR ) 

2 2
 
VY sCR
=
VX 1 + 3sCR + ( sCR )2
This is the Transfer Function of given RC Network.
Now, when this network is used as feedback to the Op-Amp then the input to this network is output voltage and the
output will be feedback voltage.
 
sCR
Vf = V0   
( )
 1 + 3sCR + sCR 2 
 
A = 100
Here A is the forward path gain and β is the feedback gain.

Analog Electronics
RF
A = 00 Here A =1+
1 (R F
in k )
jCR
 ( j ) =
1 + 3 jCR − 2C2R 2
So  has to be real, positive and for this 1 − 2c2R2 = 0
1
Or,  =
RC
= 1
3
This value is real as well as positive.
A = 1
A= 1 =3
1
3
So, 1 + R f = 3
R f = 2k
1 1
And frequency of oscillation f = = = 159.15kHz
2RC 2  10k  100pF
34. Ans: (d)

Solution:
The voltage of non-inverting terminal can be determined by potential division,
1
V+ = Vin  sC
1
R+
sC
Applying superposition theorem,
Vout = −Vin
R
R
(
+ V+  1 + R
R )
Vout = −Vin
R
R

+ Vin 
1 
(
  1 + RR
 1 + sCR 
)
 1
Vout = Vin 
 1 + sCR
(R

R )  2
1 + R − R  = Vin 
 1 + sCR
  1 − sCR 
− 1  = Vin 


 1 + sCR 
For determining phase shift, s=jω
 1 − jCR 
Vout = Vin  
 1 + jCR 
Phase shift of Vout with respect to Vin will be −2tan−1 CR
Maximum phase shift occurs at  →  or  → −
Maximum phase shift is 2  90 = 1800 0
35. Ans: (d)

Solution:
The voltage at inverting terminal is 0 by Virtual Ground Concept.
Applying KCL at the inverting terminal,
V− − Vi V− − Va
+ =0
1k 10k

Analog Electronics
Since, V− = 0V
−Vi Va
− =0
1k 10k
Va = −10Vi
Applying KCL at node ‘a’
Va − 0 Va Va − V0
+ + =0
10k 1k 10k
12Va = V0
V0 = −12  10Vi = −120Vi
V0
Hence, = −120
Vi
36. Ans: (a)

Solution:
The circuit given in the figure is a Bridge T-network whose Transfer Function is,
 1 1 1 1
s2 + s  +  +
C
 1 C R
2  1
C C RR
T(s) = 1 2 1 2
 1 1 1  1
s2 + s  + + +
 C1R1 C1R 2 C2R1  C1C2R1R 2
The pole polynomial will be given by numerator of the Transfer Function given above,
The numerator is of the form,
   1 1  1 1
s2 +  0  s + 02 = s2 + s  +  +
 Q  C
 1 C 2  1
R C C RR
1 2 1 2
0 C1 + C2
and  = Q  C1 + C2
 
Hence, = 
Q R1C1C2 0 R C C
 1 1 2 
10 −9  2
0 = = 1000 rad / sec
2000  103  10 −18
37. Ans: (b)

Solution:
VX − VY = 106  I X
This can be treated as a non-inverting amplifier,
 100k 
VY = VX  1 + 
 10 
VY = VX  11
So, VX − VX  11 = 106 IX
VX
= −105  = −100k
IX

Analog Electronics
38. Ans: (d)

Solution:
Vout R
Gain of the inverting amplifier = =− F
Vin R1
If gain = -25
1000
R1 = k = 40k
2.5
If gain =-10
1000
R1 = k = 100k
10
If RF  1M
R1  40k ( for gain = −25 )

R1  100k ( for gain = −10 )
So, R 1 should be 40k in order to have gain between -10 to -25
39. Ans: (d)

Solution:
When Vin  0 D 1 is forward biased and D 2 is in reversed biased as shown below,
So in this case V−  V+ and V0 = −Vsat (negative saturation)
When Vin  0 is in Reversed Biased, D 2 is in Forward Biased as shown below,
So, in this case V+  V− and V0 = +Vsat (positive saturation).

Hence, the output voltage waveform looks like as shown below,

Analog Electronics
40. Ans: (d)

Solution:
For this kind of problem first remove the feedback element that is diode and check the state of Diode.
When Vi  0 without feedback output voltage. Then the Op-Amp acts as a comparator and since, voltage of inverting
terminal is more than non-inverting terminal which is grounded. The output would have been VP = −12V ( − VSat ) .
This would have kept the diode off and no feedback would be present. So, V0 = −12V when Vi  0
When Vi  0 , the voltage of inverting terminal is less than non-inverting terminal which is grounded. So, without
feedback output voltage reaches towards positive saturation which turns the diode on and feedback path is activated.
So, VP = V− + 0.7 = 0 + 0.7 = 0.7V

Hence, the closest option would be D.
41. Ans: (a)

Solution:
If Vi = 1V
V0 = AVi = 106  10−6 V = 1V

Since, the input loop is open circuited.
Input impedance = 
Output impedance is calculated by deactivating the independent source,

Analog Electronics
So we make Vin = 0V
The voltage source in output loop is AVin = 0V
So, Rout = R0 = 10
42. Ans: (c)

Solution:
Here the Op-Amp acts as a comparator and so the
output can be Vsat i.e. 12V .
When the output is +Vsat = +12V , the diode D2 will
Turn ON and the feedback voltage at point P is,
10
VP1 = 12  = 6V
10 + 10
Then, the capacitor will charge as a RC circuit
through resistance R1 to a voltage 6V.
When voltage exceeds 6V the output becomes -12V.
When the output is −Vsat = −12V , the diode D1 will Turn ON and the feedback voltage at point P is,
10
VP2 = −12  = −10V
2 + 10
Then, the capacitor will charge as a RC circuit through resistance R 1 to a voltage -10V.
43. Ans: (d)

Solution:
Voltage of Non-Inverting Terminal of Op-Amp,

R2
V+ = V 
R1 + R 2
V−
Current through the load IL =
r
Now due to negative feedback V+ = V− (Virtual Ground)
V R2
So, IL =
r R1 + R 2
R2 V
So, this is a current source with Current
R1 + R 2 r

Analog Electronics
44. Ans: (c)

Solution:
At t0 the switch was closed so V− ( t  0 ) = −10V
But at t=0 the switch is opened and the capacitor starts getting charged
The Transient Equation for Capacitor Voltage is,
−t
VC ( t ) = VC (  ) +  VC ( 0 ) − VC (  )  e 
 = RC = 103  0.01  10−6 = 10−5 s

VC ( 0 ) = 0
As the voltage supply across RC circuit is 20V
VC (  ) = 20V
 − t −5 
VC ( t ) = 20  1 − e 10 
 
Now output oscillating between +5V and -5V due to zener diodes
100
So, V+ = 5 
100 + 10
( when Vout = +5V )
Now if V− exceeds V+ then output Vout switches from +5V to -5V as Op-Amp acts as a comparator.
(
V− ( t ) = 20 1 − e−10
5
t
) − 10
V− ( t ) = 10 − 20e−10 t
5
50
V+ = V
11
50 5
So, = 10 − 20e−10 t
11
t = 12.99s
So at 12.99μs the output will make a transition from +5V to -5V.
45. Ans: (a)

Solution:
There are two stages in this circuit first stage is a Schmitt trigger and next stage is an integrator.
When input voltage i.e. the reference voltage of integrator is 0V, the output of integrator is a triangular wave of peak to
peak voltage of 5V as shown below,

Analog Electronics
When Vi =2.5V, the integrator is a linear circuit so the output will shift upward by an amount equal to reference voltage
i.e. 2.5V as shown below,
46. Ans: (c)

Solution:
When =0 capacitor is open circuited ( as X C

→ )
Now R1 = R2 = R A and R3 = R 4 = RB
So, V = V  RB
 R   RA 
  1 + A  − Vi   
0 i
2RB  RA   RA 
V0 = Vi − Vi = 0V
When  =  capacitor is short-circuited ( as X C → 0 )

R1 V
V0 = Vi  = i ( when R 4 = R 3 )
R 4 + R3 2
So, this is a HPF as it passes high frequency and
disallows low frequencies.
For solving the next problem we need the Transfer Function of the filter shown above.
1
R2  R2
Z= sC =
1 1 + sCR 2
R2 +
sC
Voltage at non-inverting terminal of Op-Amp is,
R4 RB V
V+ = Vi  = Vi  = i
R 4 + R3 RB + RB 2
The system acts as differential amplifier whose Transfer Function is,
 Z V Z V Z V R 1 
V0 = Vi   −  + i  1 +  = i  1 −  = i  1 − 2  
 R1  2  R1  2  R1  2  R1 1 + sCR 2 
V  sCR A 
V0 = i  
2  1 + sCR A 

Analog Electronics
V0 1  sCR A 
=  
Vi 2  1 + sCR A 
This is the Transfer Function of High Pass Filter.
47. Ans: (d)

Solution:
The given filter is,
The Transfer Function of this filter is,
1
V0 sC 1
= =
Vi R A sCR A
+1
1+
2 sC 2
At Low Frequencies, the capacitor is open circuited and output is same as input.
At High Frequencies, capacitor is shorted so output voltage is zero.
This is a Low Pass Filter.
When it is cascaded with filter in previous question then overall Transfer Function is,
V0 1  sCR A  1
=  
Vi 2  1 + sCR A  sCR A
1+
2
This is Transfer Function of Band Pass Filter.
48. Ans: (d)

Solution:
VS − V0
iS =
R
By Virtual Ground Concept, the voltage at inverting terminal
of Op-Amp is Vs and it can be obtained from output voltage
by potential divider.
1
jC V0
VS = V0 =
R+ 1 1 + jCR
jC
V0 = VS (1 + jCR )
VS − VS (1 + jCR ) −VS jCR

iS = = = − jCVS
R R
( )
is = − j 2  50  10  10 −6  10 = − j10 mA = 10 mA − 90
0
So, iS is 10 mA lagging by 900
49. Ans: (d)

Solution:
This is an inverting Schmitt trigger circuit
VUTP = + Vsat  1 = 6 1 = 6 = 2V
2+1 2 +1 3
1
VLTP = −Vsat  = −1V
1+2

Analog Electronics
So the transfer curve is as shown below,
Based on the Transfer Curve, the output wave form can be plotted as shown above.
50. Ans: (b)

Solution:
The voltage at inverting terminal of Op-Amp is 2V by Virtual Ground Concept.
Applying Nodal analysis at the inverting terminal of op-amp
2 − 0 2 − V0
+ =0
R 2R
2  2 + 2 − V0 =0
V0 = 4 + 2 = 6 V
51. Ans: (d)

Solution:
The ideal frequency characteristics for LPF and HPF filter is shown below,
LPF HPF
When they are cascaded all the frequency ranging from 20Hz to 30Hz will exist at the output
So, this is a band pass filter.

Analog Electronics
52. Ans: (d)

Solution:
The given two stage amplifier is shown below,
Of this two stage cascaded op-amp connective, first stage is in differential amplifier. The output of Differential Amplifier is
given by (Superposition Theorem),
R  as Vi = V1 − V2 
( )
V01 = V2 − V1    = − Vi
R 
So, gain of differential amplifier is -1
Now the second stage is an Inverting Schmit trigger.
The triggering voltages for the Schmitt Trigger are,
 R 
VUTP = 12    = 6V
R +R 
 R 
VLTP = −12    = −6V
R +R 
The characteristics of Schmitt Trigger is shown below,
(V 0
vs. − Vi ) (V0
vs. Vi )
53. Ans: (b)

Solution:
To determine the nature of filter. We analyze the circuit at  =0 (capacitor is open circuited)

Analog Electronics
No current flow through the circuit so V0 = 0volt ( as V0 = V− = V+ )

At  =  (capacitor acts as short circuit)
R2
V0 = −Vi 
R1
So, the circuit is a High Pass Filter
Now finding out the transfer function,
Applying nodal analysis at inverting terminal after op-amp
0 − Vi 0 − V0
+ =0
R1 + 1 R2
sC
− Vi sC V0
=
(1 + sCR ) 1
R2
V0 sCR 2
So, =−
Vi 1 + sCR1
V0 1 R2
At  =  = 
3dB
Vi 2 R1
3dB2C2R 22 1 R 22
So, =
1 + 3dB C R1 2 2 2
2 R12
So, 3dB = 1 rad / sec

R 1C
54. Ans: (b)

Solution:
First of all we have to see where the transistor is in cutoff or not
Case-1:
Assume that the transistor Q is in cutoff so no feedback path will be present for the op-amp
In this case op-amp acts as comparator
So, Vout = −15V
(negative saturation as V −
= 5V & VP = 0V )
But for the transistor Q base potential ( V ) = 0 volt and emitter potential ( V ) = −15V
B E
This makes the Base-emitter junction of Q forward bias. So, our assumption is not justified so, Q cannot be in cutoff state.

Analog Electronics
Case-2:
Assumption that the transistor Q is in saturation,
So, now feedback path is connected and
virtual ground concept is also valid
VB = 0V VE = 0 − 0.7V = −0.7V
And VC = 0V (for virtual ground concept)
So, thus assumption is the and
Vout = ( 0 − 0.7 ) V = −0.7V
55. Ans: (c)

Solution:
The second Op-Amp acts as Non-Inverting Amplifier
 R 
(
Vout = Vin   1 + f  = V  1 + 1 = 2V
 R 1
1 )
Since, the current into the Op-Amp is 0.
V+ = +1V
Applying virtual ground concept
V− = +1 V
Applying nodal analysis at inverting terminal (V )

−
+1 − ( −2 ) 1−V
+ =0
1k 1k
1−V +3 = 0
V=4
So, Vout = 4  2 =8V
56. Ans: (b)

Solution:
Voltage at “-” terminals of Op-Amp is also V1 & V2 by virtual ground concept.
I=
( V1 − V2 )
2R
V− = V2 − IR
V− = V2 −
( V1 − V2 )  R = (3V2 − V1 )
2R 2
V+ = V1 + IR
V+ = V1 +
( V1 − V2 )  R = (3V1 − V2 )
2R 2

Analog Electronics
If only V+ is present,
V+ ( 3V1 − V2 )
Va = = [By Potential Divider]
2 4
 R
V0 =  1 +  Va =
(3V1 − V2 )
 R  2
If only V− is present,
R 
V0 = −    V− = −
(3V2 − V1 )
R
  2
V0 due to both V− & V+ ,
V0 =
(3V1 − V2 ) − (3V2 − V1 )
2 2
V0 = 2 ( V1 − V2 )
57. Ans: (0.8)

Solution:
During t1 (positive cycle),
V0 = +5V
D1 gets turned ON
 1 
V+ = V0    = 1.25 V
1 + 3
Capacitor starts getting charged
VC (  ) = 5V
VC ( 0 ) = ?
During t2 (negative cycle),
V0 = −5V
D2 gets turned ON
 1  V0
V+ = V0    = 2 = –2.5 V
1 +1
For positive cycle, VC ( 0 ) = –2.5 V
(
VC ( t1 ) = 1.25 = V (  ) + V ( 0 ) − V (  ) e ) −t1 /RC
1.25 = 5 + ( −2.5 − 5 ) e
−t1 /RC
−3.75 −t /RC 1

=e 1 =
−7.5 2
During negative cycle,
VC ( 0 ) = 1.25V ; V (  ) = −5V
(
VC ( t2 ) = −2.5 = V (  ) + V ( 0 ) − V (  ) e ) −t1 /RC
−2.5 −t /RC 2

6.25
=e 2 =
5
(
–2.5 = –5 + 1.25 – ( –5 ) ) e−t
2 /RC
−t2 /RC
e( 1 2 ) = e
t −t /RC
= 0.8
e−t1 /RC

Analog Electronics
58. Ans: (d)

Solution:
The given circuit is shown below,
The output of the first Op-Amp is either Vsat or -Vsat because it is operating under non linear region because of the positive
feedback. The second Op-Amp is a non-inverting amplifier.
For second Op-Amp,
 R
V0 = Vin  1 +  = 2Vin
 R
But, Vin = +Vsat or -Vsat
But since, output of any Op-Amp cannot exceed ± Vsat ,output of second stage will be ± Vsat .
59. Ans: (c)

Solution:
If Vi  0 , output of first op-amp is negative, then output diode is off & feedback diode is ON.
The voltage of negative terminal of op-amp is 0V.
Therefore input of second of op–amp is 0V and V0 = 0V
If Vi  0 , output of first op-amp is positive, then output diode is ON & feedback diode is off.
Output of 1st stage = −R V = − Vi

R i
Output of 2nd stage= −R  V01 = −V0i = Vi
R
 Vi , Vi  0
Therefore, V0 = 
0,
 Vi  0
So, the characteristics would be as shown below,

Analog Electronics
60. Ans: (a)

Solution:
Instrumentation amplifier should have low output impedance but rest of requirements are all correct.
61. Ans: (d)

Solution:
The output due to Inverting Input is,
 
−R 
V01 = V1  = − sCR V1
1 
 Cs 
The potential of non-inverting terminal is,
 
 R 
V+ = V2
R + 1 
 Cs 
The output due to non-inverting input is,
R
V02 = 1 + RCs  V = sCR V2
R + 1  1
 Cs
V0 = V01 + V02
V0 = −sCR  V1 − V2  = −sCR Vi  V 1 − V2 = Vi00 

 
C = 1F
R = 1k
For sinusoidal input,
s = j = j (100 )
V0 = 0.1Vi − 900
V0 = 0.1Vi ,  = −900
= −
2
62. Ans: (a)

Solution:
V =0
+
(
V0 = A V − V
+ − )
V0 = A (0 − V )
−
−V0
V =
− 1000
 V0 
 Vi + 
IR =
(V − V )
i −
=  1000 
= 10−3 Vi + 10−6 V0
R 1000
10−6 d dV0
IC = C
d
dt
( V−
− V0)
= C
d 
 −
V0
dt  1000
− V

0
= −
10 dt
3 ( )
1001V0  = − 1.001  10 −6
dt

Due to infinite input resistance,

Analog Electronics
IR = IC
dV0
(
10−3 Vi + 10 −6 V0 = − 1.001  10 −6 ) dt
Vi = 1mV
dV0
(
10−6 + 10 −6 V0 = − 1.001  10 −6 ) dt
dV0
1 + V0 + 1.001 =0
dt
dV0
1.001 + V0 = −1
dt
dV0
The differential equation of RC circuit is of the form, RC + V0 = Vs
dt
On comparing with the Differential Equation obtained,
Time constant,  = 1.001sec = 1001 msec
63. Ans: (1.245)

Solution:
1 1
Reactance of capacitor = = = 795.77
C 400  10 −6
Equivalent feedback impedance,
(R)( − jX C )
Z eq = = 622.67 − 51.4880 
R − jX C
 −Z eq  −622.67
Vo = Vin   = 2
 R  1000
 1 
Vo = 1.245V
64. Ans: (a)

Solution:
When Vo = 10 V
Vo  2
Voltage of positive terminal V1 = = 5V
4
This is UTP of Schmitt Trigger.
The RC circuit connected at the negative terminal has
V0 as the supply voltage.
Vc () = 10V
Vc (0) = −5V
Vc (t) = 10 + ( −5 − 10)e− t  = 10 − 15e− t 
At t = T1 ,
Vc (t) = 5V
5 = 10 − 15e− t 
−5 = −15e− t 
t = T1 =  ln3 = RCln3
T1 = 0.25ln3 = 0.275 ms

Analog Electronics
Duty cycle of the waveform is 50% due to symmetrical UTP & LTP
T = 2T1 = 0.55ms
65. Ans: (a)

Solution:
For determining the filter characteristics, we have check the circuit at = & =0
For =0 capacitor acts as open circuit
V0 R
So, =− 2
Vin R1
For = capacitor acts as short

So, V0 = V−
And due to virtual ground V− = 0Volt
So, V0 = 0Volt
So, this is an L.P.F
66. Ans: (d)

Solution:
Op-Amp is ideal, so input impedance = 
At node B:
Let V= voltage at node B
Applying KCL at node B:
V − V1 V − V2
+ =0
1 4
4V − 4V1 + V − V2 = 0
4V1 + V2
V=
5
By virtual grounding concept,
VA = VB = V
Applying KCL at node A:
V − V3 V − Vout
+ =0
1 9
9 (V − V ) + V − V
3 out
=0
 4V + V2 
Vout = 10V − 9V3 = 10  1  − 9V3
 5 
Vout = 8V1 + 2V2 − 9V3

Analog Electronics
67. Ans: (a)

Solution:
For positive input, V0  0 and diode becomes forward biased
The circuit then acts as voltage follower
V0 = Vin
For negative input, the output is negative

and diode is reverse biased so no current
flows through resistor & V0 = 0
68. Ans. (c)

Solution:
The given circuit can be redrawn as,
Apply Delta-Star Transformation
By voltage division, voltage at non-inverting terminal

2R V
V+ = Vs = s
2R + 2R 2
The resistance at inverting terminal does not play any role

 4R 
 R f  Vs  
3 
V0 = V+  1 +  =  1 +
 R1  2  R 
 
 3 

Analog Electronics
5
V0 = V = 2.5 Vs
2 s
69. Ans: (b)

Solution:
R
V+ = V0 = V− = Vin
R1 + R 2
R 
V0 = Vin  1 + 1 
R
 2 
R 
V0 = Vin  1 + 1 
R
 2 
By KVL
V0 = Vin − Iin Z
Vin − V0 VinR1
Iin = =−
Z R2Z
Vin R2
Z in = = −Z
Iin R1
70. Ans: (d)

Solution:
By voltage division
100 10
V+ = V2  = V
110 11 2
By using superposition,
 100   100  10
V0 = V+ 1 +  + V1  −  = ( ) (
V2 11 − 10V1 = 10 V2 − V1 = 400mV )
 10   10  11
71: Ans: 3150 to 3170

Solution:
Capacitor voltage would vary between the threshold levels
i.e. 1.6 V & 2.4 V
Assume V0 = 5 volt
Vc(0) = 1.6 V vc() = 5V
τ = RC = 470 μs
v c = v c ( ) +  v c (0) − v c ( ) e−t/ 
= 5 – 3.4 e-t/
at t = t1 vc = 2.4
2.4 = 5 – 3.4 e-t1/470
t1 = 126.08 μs
Assume V0 = 0V
& vc = 2.4 V
Cap. discharges towards 0V till it reaches lower threshold 1.6 V
Vc(0) = 2.4V vc() = 0V
Vc(t) = 2.4e-t/

Analog Electronics
At t = t2 = vc = 1.6
1.6 = 2.4e-t2/
 1.6 
t2 = − ln   = 190.57 sec
 2.4 
Time period = t1 + t2 = 316.65 μsec
Frequency of oscillations = 1/T = 3.16 kHz = 3158.06 Hz
72. Ans: (b)

Solution:
KCL at Node (i)

I1 + I 2 = 0
V1 − 0 d
R1
+ C1  ( V − 0) = 0
dt out
dVout V
=− i
dt R1C1
VA = 0
1
R1C1  1
Vout = − V dt
Vi = 0.1V
1 0.1
Vout = −
R1C1  0.1  dt = − R C
1
1 1
t
Vout = −k  t
73. Ans: (c)

Solution:

Analog Electronics
Analysis:
It is a voltage series feedback.
Voltage is a shunt connection,

Zout feedback,
Z0 Z
Zot = = 0 [Buffer, =1]
1+ A 1+ A
A = open loop gain
A = constant (low frequency)

ZO
Zof = [ Constant ]
1+ A
A = Decreasing
Zo
f → Zof =
1+ A 
A=0
Z
Zof = 0 = Z0
1+0

Analog Electronics
74. Ans: (c)

Solution:
1 I
Vx =
Ct  Iin  dt = in  t
Ct
dV1 d  Iin 
Iout = Cc  = Cc  
  t 
dt dt  Ct 
Iin
= Cc 
Ct
Iout C
= c
Iin Ct
75. Ans. (d)

Solution:
Applying open circuit test
Due to absence of feedback op-amp acts as comparator

V+ = 0 V- = VIN
during +ve half cycle VIN > 0 V- > V+
V0 = -VSAT
D1 & zener diode are forward biased & D2 is reverse biased
During -ve half cycle VIN < 0 V- < V+
V0 = VSAT = 15V
D2 is forward biased & D1 & Zener diode are reverse biased
Zener diode goes into BD.
During +ve half cycle

Analog Electronics
 −1K 
V0 = VIN   = −VIN
 1K 
 minimum value of V0 = -10V
During -ve half cycle
 Maximum value of V0 = 5Volt

Analog Electronics
Chapter 5 – Feedback Amplifier
01. A Wien bridge oscillator is shown in figure. Which of 05. A current amplifier has an input resistance of 10Ω, an
the following statements are true, if f is the frequency of output resistance of 10kΩ and a current gain of 1000. It is
oscillation. [1993] feed by a current source having a source resistance of 10k
Ω and its output is connected to a 10 Ω load resistance.
Find the voltage gain and the power gain. [2000]
06. The circuit of Figure shows a 555 Timer IC connected as

an Astable multi-vibrator. The value of the capacitor C is
10nF. The values of the resistors RA and RB for a frequency
of 10kHz and a duty cycle of 0.75 for the output voltage
waveform are [2003]
(a) For R = 1K
1
C= F, f = 1kHz
2
(b) For R = 3K
1
C= F,f = 3kHz
18
(c) The gain of the op amp stage should be less than two
for proper operation (a) R A =3.62 k, R B = 3.62 k
(d) The gain of the op amp stage should be three for (b) R A =3.62 k, R B = 7.25 k
proper operation
(c) R A = 7.25 k, R B = 3.62 k
02. A practical R-C sinusoidal oscillator is built using a (d) R A = 7.25 k, R B = 7.25 k
positive feedback amplifier with a closed loop-gain slightly
less than unity. [1994] 07. The typical frequency response of a two-stage direct
coupled voltage amplifier is as shown in [2005]
03. The voltage series feedback in a feedback amplifier
leads to [1996]
(a) Increase in band width, while the voltage gain becomes
less sensitive to variation in components and device
characteristics
(b) Decrease in overall gain, while the input resistance
decreases
(c) Increase in distortion, while the output resistance
decreases
(d) Decrease in input resistance, while the output resistance
increases
04. The type of power amplifier which exhibits crossover

distribution in its output is [2000]
(a) class A (b) class B
(c) class AB (d) class C

Analog Electronics
(a) Current - Current feedback

(b) Voltage - Voltage feedback
(c) Current - Voltage feedback
(d) Voltage - Current feedback
10. In the feedback network shown below, if the feedback
factor k is increased, then the [2013]
08. IC 555 in the adjacent figure is configured as an Astable

multi-vibrator. It is enabled to oscillate at t=0 by applying a
high input to pin 4. The pin description is: 1 and 8 − supply:
2-trigger; 4-reset; 6-threshold;
7-discharge. The waveform appearing across the capacitor
starting from t=0, as observed on a storage CRO is [2007]
(a) Input impedance increases and output impedance

decreases.
(b) Input impedance increases and output impedance also
increases.
(c) Input impedance decreases and output impedance also
decreases.
(d) Input impedance decreases and output impedance
increases.
11. A current controlled current source (CCCS) has an input

impedance of 10  and output impedance of 100 k .
When this CCCS is used in a negative feedback closed loop
with a loop gain of 9, the closed loop output impedance is
[2019]
(a) 100 k (b) 100 
(c) 10  (d) 1000 k
09. The nature of feedback in the op-amp circuit shown is

[2009]

Analog Electronics
Solutions
01. Ans: (3)
Solution:
1
Frequency of oscillator, f =
2RC
1
So, for R = 1k,C = F f = 1kHz
2
1
For R = 3k,C = F f = 3kHz
18
 R
Gain of the amplifier is A =  1 + 2 

 R1 
V ZP
= f =
V0 Z S + ZP
1
YP = + jC and ZS = R + 1
R jC
1 1 1
= = =
1 + YP Z S 1  1  1
1 +  + jC   R +  3 + jRC + jRC
R  jC 
1
=
 1 
3 + j  CR − 
 CR 
1
At  = = 1
RC 3
So, A = 100 (from Barkhausen Criteria)
1
So, A = =3

So, for proper operation gain of Op-Amp should be 3.
02. Ans: (False)

Solution:
According to Barkhausen criteria the closed loop gain ( A) should equal to 1 for sustained oscillator. If A <1 those won’t
be any sustained oscillation so the statement is false.
03. Ans: (a)

Solution:
Voltage (output)-series (input) or series (input) – shunt (output) feedback is used in case of voltage amplifier ( VCVS ) . This
reduces gain, increases Bandwidth, gain becomes less sensitive. Input resistance increases and output resistance decreases
04. Ans: (b)

Solution:
Class B amplifiers show cross over distortions

Analog Electronics
05. Ans: (1000, 1000, 106)

Solution:
The configuration of current amplifier is shown below,
10  10 4
Input voltage Vi = IS  = Ii  10
10 + 10 4
10  10 4
Output voltage V0 = 1000Ii 
10 + 10 4
105
1000 
V 10 + 104 1000
Voltage gain A V = 0 =
Vi 10
V0
Current gain Ai =
I0
=
RL V
= 0
(
10k 10 ) V0 10
 1000
IS Vi Vi 10 Vi 10
(
10k 10 )
P0 VI
Power gain = 00 1000  1000 = 106
Pi IS  Vi
06. Ans: (c)

Solution:
Charging time tC = (R A + RB ) Cln2

Discharging td = RBCln2
Since, f = 10kHz
The time period, T = tOFF + tON = 1 = 10 −4 s
f
t ON
Now Duty Cycle= = = 3
t OFF + tON 4
t ON = 3  10 −4
4
ln2 (R A + RB )  C = 3  10 −4
4
Since, C = 10nF
R A + RB = 10.82k
OFF time, toff = T − ton = 10 −4 − 3  10 −4 = 1  10 −4 s

4 4
ln2 RBC = 1  10 −4
4
RB = 3.606k
R A = (10.820 − 3.606 ) k = 7.214k

Analog Electronics
07. Ans: (b)

Solution:
In RC coupled amplifier low frequency roll off happens due to coupling capacitors and high frequency roll due to parasitic
capacitors as shown below,
In Direct Coupled amplifier there won’t be any coupling capacitors

So, subsequently there won’t be any low frequency roll off so the characteristics will be as follows.
08. Ans: (a)

Solution:
The given circuit and its developed view using internal construction of IC 555 timer is shown below.
Initially the S-R Flip Flop is set as S = 1 & R = 0 

So, Q = 1 and Q = 0
So, the transistor is off and the capacitor charges through R A = 10k and Diode ‘D’
Now, when the capacitor voltage (V )

C
VCC
surpasses then S becomes ‘0’ ad
3
Q continues to be at ‘1’ but VC further increases

Analog Electronics
2VCC
beyond
3
Then S=0 & R=1. So, now Q=1 and transistor turns on. So, capacitor C discharge through RB = 10k
So, the capacitor voltage curve is as shown above.
It can also be noticed that since charging and discharging resistances are equal so the charging and discharging time is
equal and since we have to plot the curve from t=0 so we have to show the transient in the response.
09. Ans: (b)

Solution:
Here the feedback element is the 2k resistance.
Now, we have to determine whether the output
signal is current or voltage. In this network, output
voltage is directly connected to feedback path
So feedback signal is voltage and output signal is
voltage/shunt.
Again, the input voltage is connected to non inverting
input and the feedback voltage is connected to inverting input,
So this voltage/series feedback (Mixing) at the input
So, the feedback is voltage output-voltage input or series input-shunt output.
10. Ans: (a)

Solution:
Here the feedback configuration is
series (input)-shunt (output)
In series feedback configuration, impedance increases
In shunt feedback configuration, impedance decreases
So, Here Input impedance will increase& output impedance will decrease
R if = R i (1 + A 0k )
R0
R of =
(1 + A0k )
11. Ans: (d)
Solution:
A current controlled current source must have low input impedance & high output impedance
Ri
R if =
1 + A
R 0f = R 0 (1 + A )
Given, A = 9
10
R if = =1 
1+ 9
R 0f = 100k (1 + 9 ) = 1000k

Singnal and System

Analog Electronics

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Analog Electronics

Uploaded by

Copyright:

Available Formats

Singnal and System

Chapter 1 – Diode Circuits ............................................................................................................................. 2

Chapter 4 – OP-AMP ..................................................................................................................................... 56

Chapter 5 – Feedback Amplifier ............................................................................................................. 111

Scan this QR code to report an

Chapter 1 – Diode Circuits

03. The mobility of an electron in a conductor is expressed

04. As the temperature is increased, the voltage across a

VT is the thermal voltage ( = 25mV ) , is biased at

ID = 2mA . Its dynamic resistance is: [2000]

Scan this QR code to report an

(a) +10 V and –10 V (b) +4 V and –4 V (a) 0 mA (b) 0.5 mA

09. The current through the Zener diode in figure is

(a) 33 Ma (b) 3.3 mA

14. Assuming the diodes D1 and D2 of the circuit shown in

12. Assume that D 1 and D 2 in Figure are ideal diodes. The

15. The equivalent circuits of a diode, during forward

Scan this QR code to report an

(a) vc1 = 10V, vc2 = 5V

17. The block diagrams of two types of half wave rectifiers

It is desired to make full wave rectifier using above two

16. In the voltage doubler circuit shown in the figure, the

Scan this QR code to report an

20. The I-V characteristics of the diode in the circuit given

Assuming forward voltage drops of the diodes to be 0.7V,

(a) 125 and 125 (b) 125 and 250

(c) 250 and 125 (d) 250 and 250

22. The sinusoidal ac source in the figure has an RMS value

Scan this QR code to report an

26. Consider the diode circuit shown below. The diodes D,

(a) -1V to -2V (b) -2V to -4V

28. In the circuit shown, the input Vi is a sinusoidal AC

29. In the circuit shown, a 5V Zener diode is used to

Scan this QR code to report an

32. All the elements in the circuit shown in the following

30. The waveform shown in solid line is obtained by

(a) Vout =Vin for Vin > 0

Scan this QR code to report an

02. Ans: (c)

03. Ans: (a)

Vd (Drift velocity) unit is cm/sec

So  has unit = cm sec = cm2 volt − sec

04. Ans: (b)

05. Ans: (b)

Scan this QR code to report an

06. Ans: (a)

When diode is Forward Biased ( V  0)

07. Ans: (b)

Scan this QR code to report an

08. Ans: (d)

Scan this QR code to report an

In this condition, the output voltage is, V0 = Vi −

Maximum Voltage = 4V and Minimum Voltage = -7V

09. Ans: (c)

Since, the voltage across Zener diode is 3.5V as shown in figure.

10. Ans: (a)

Secondary R.M.S voltage= 50V, Secondary peak voltage = 50 2V

Scan this QR code to report an

11. Ans: (c)

12. Ans: (a)

13. Ans: (a)

Scan this QR code to report an