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  • SR Latch Truth Table

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    karimyossef1001
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    The document contains a table with 8 columns and 64 rows that defines the states of 6 inputs (S1, S2, S3, R1, R2, R3) and the corresponding output values of 3 nodes (nset, nreset, Z) in a circuit. Each row represents a unique combination of the 6 input states and the corresponding output values of the 3 nodes.

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    SR latch truth table

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    The document contains a table with 8 columns and 64 rows that defines the states of 6 inputs (S1, S2, S3, R1, R2, R3) and the corresponding output values of 3 nodes (nset, nreset, Z) in a circuit. Each row represents a unique combination of the 6 input states and the corresponding output values of the 3 nodes.

    Copyright:

    © All Rights Reserved
    Download as XLSX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as xlsx, pdf, or txt
    7 views4 pages

    SR Latch Truth Table

    Uploaded by

    karimyossef1001
    The document contains a table with 8 columns and 64 rows that defines the states of 6 inputs (S1, S2, S3, R1, R2, R3) and the corresponding output values of 3 nodes (nset, nreset, Z) in a circuit. Each row represents a unique combination of the 6 input states and the corresponding output values of the 3 nodes.

    Copyright:

    © All Rights Reserved
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    of 4

    S1 S2 S3 R1 R2 R3 nset (N31) nreset(N18) Z

    0 0 0 0 0 0 x x x
    0 0 0 0 0 1 1 0 0
    0 0 0 0 1 0 1 0 0
    0 0 0 0 1 1 1 0 0
    0 0 0 1 0 0 1 0 0
    0 0 0 1 0 1 1 0 0
    0 0 0 1 1 0 1 0 0
    0 0 0 1 1 1 1 0 0
    0 0 1 0 0 0 0 1 1
    0 0 1 0 0 1 0 0 1
    0 0 1 0 1 0 0 0 1
    0 0 1 0 1 1 0 0 1
    0 0 1 1 0 0 0 0 1
    0 0 1 1 0 1 0 0 1
    0 0 1 1 1 0 0 0 1
    0 0 1 1 1 1 0 0 1
    0 1 0 0 0 0 0 1 1
    0 1 0 0 0 1 0 0 1
    0 1 0 0 1 0 0 0 1
    0 1 0 0 1 1 0 0 1
    0 1 0 1 0 0 0 0 1
    0 1 0 1 0 1 0 0 1
    0 1 0 1 1 0 0 0 1
    0 1 0 1 1 1 0 0 1
    0 1 1 0 0 0 0 1 1
    0 1 1 0 0 1 0 0 1
    0 1 1 0 1 0 0 0 1
    0 1 1 0 1 1 0 0 1
    0 1 1 1 0 0 0 0 1
    0 1 1 1 0 1 0 0 1
    0 1 1 1 1 0 0 0 1
    0 1 1 1 1 1 0 0 1
    1 0 0 0 0 0 0 1 1
    1 0 0 0 0 1 0 0 1
    1 0 0 0 1 0 0 0 1
    1 0 0 0 1 1 0 0 1
    1 0 0 1 0 0 0 0 1
    1 0 0 1 0 1 0 0 1
    1 0 0 1 1 0 0 0 1
    1 0 0 1 1 1 0 0 1
    1 0 1 0 0 0 0 1 1
    1 0 1 0 0 1 0 0 1
    1 0 1 0 1 0 0 0 1
    1 0 1 0 1 1 0 0 1
    1 0 1 1 0 0 0 0 1
    1 0 1 1 0 1 0 0 1
    1 0 1 1 1 0 0 0 1
    1 0 1 1 1 1 0 0 1
    1 1 0 0 0 0 0 1 1
    1 1 0 0 0 1 0 0 1
    1 1 0 0 1 0 0 0 1
    1 1 0 0 1 1 0 0 1
    1 1 0 1 0 0 0 0 1
    1 1 0 1 0 1 0 0 1
    1 1 0 1 1 0 0 0 1
    1 1 0 1 1 1 0 0 1
    1 1 1 0 0 0 0 1 1
    1 1 1 0 0 1 0 0 1
    1 1 1 0 1 0 0 0 1
    1 1 1 0 1 1 0 0 1
    1 1 1 1 0 0 0 0 1
    1 1 1 1 0 1 0 0 1
    1 1 1 1 1 1 0 0 1
    S3,S2,S1,R3,R2,R1 {s,r} Prev nset (N31) nreset(N18) Z
    000001 1 1 0 0
    000010 2 1 0 0
    000011 3 1 0 0
    000100 4 1 0 0
    000101 5 1 0 0
    000110 6 1 0 0
    000111 7 1 0 0
    001000 8 0 1 1
    001001 9 0 1 1
    001010 10 1 0 0
    001011 11 1 0 0
    001100 12 1 0 0
    001101 13 1 0 0
    001110 14 1 0 0
    001111 15 1 0 0
    010000 16 0 1 1
    010001 17 0 1 1
    010010 18 0 1 1
    010011 19 0 1 1
    010100 20 1 0 0
    010101 21 0 1 1
    010110 22 1 0 0
    010111 23 1 0 0
    011000 24 0 1 1
    011001 25 0 1 1
    011010 26 1 0 0
    011011 27 1 0 0
    011100 28 1 0 0
    011101 29 0 1 1
    011110 30 1 0 0
    011111 31 1 0 0
    100000 32 0 1 1
    100001 33 0 1 1
    100010 34 0 1 1
    100011 35 0 1 1
    100100 36 0 1 1
    100101 37 0 1 1
    100110 38 1 0 0
    100111 39 0 1 1
    101000 40 0 1 1
    101001 41 0 1 1
    101010 42 1 0 0
    101011 43 1 0 0
    101100 44 1 0 0
    101101 45 1 0 0
    101110 46 1 0 0
    101111 47 1 0 0
    110000 48 0 1 1
    110001 49 0 1 1
    110010 50 0 1 1
    110011 51 0 1 1
    110100 52 0 1 1
    110101 53 0 1 1
    110110 54 1 0 0
    110111 55 0 1 1
    111000 56 0 1 1
    111001 57 0 1 1
    111010 58 0 1 1
    111011 59 0 1 1
    111100 60 1 0 0
    111101 61 0 1 1
    111110 62 1 0 0
    111111 63 1 0 0

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