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Inofdn combusurs, WU ords tiers Ata bid the voripulls Haus Coll aiviey Orowwnd :~ provi indomnps rug uit Wore Ys mubauE ~Givt Orrbe Tag LMIDZp they aul evan te ovoid divi ovtifiu i1¥0 vy Wookiry Sport ary, O°) HoueluvOt AY 9:- pale Oars E Lecture Notes in Computer Architecture and Organization i a 4 a 9 4 9 Figure 10-10 4-bi by }-bit array euultiplier. ——____—_—_————— —— eee Oth a/9of:- a a, eee me d petior kp ub tractive opera 42, di AB, “nip pe “hy parol HE Mosnce ty = gn matteo ploa tue mollis Mom ae om cam be B ay gubyrouktd cantporsctscigoctn OMB) Og ce pag ade ra dikernuved por jada pun b rgnadlate aE cae of yee rraktad = tori b then Bs NO nae oD ie BuaD Gu ore “lyfe ed ithecoolestprofessor Cerne Lecture Notes in Computer Architecture and Organization Chapter 11 i Input-Output Organization Peripheral Devices Peripheral devices = input/output devices connected to a computer ‘American Standard Code for Information Interchange (ASCII) © 7-bit codes © 94 printable characters + 34 non-printable characters = 128 Memory-mapped input/output Memory and input/output devices share the same address space Asynchronous Data Transfer (2) Block diagram Data ‘Valid data ——>| Strobe (b) Timing diagram Figure 11-3 Source initiated strobe for data transfer. Data bus eer eee | (2) Block diagram | : Data ‘Valid data 4 | ee (6) Timing diagram Figure 11-4 Destination-initiated strobe for data transfer. ‘Hthecoolestprofessor : indeqact blw CPU & UP Rot & Re CORVODLOS) a1 ete t Data & Ay nduonet prams} Addi = Cod format - a - oy Sep ucts: i Grr of opuokrt BA es eee ae Ng f Conwroh h Cenkintabiatin) Wee tear wk : Nolaka H1° i ; ieee — wornman Jf, ‘adds i Pi, ca = da Insrrehions - —ycs rapped —> hs) c . at — Gas ai a nay | he aoe —all To IIs To "0 one Naan tes Keg} egal 7a Nayythor0 4s Comysiui carrion Ltafett'- BH eit ge a, =o ihe oe" Cerf Bee 4 hq ee ae = [a] fen Se Rye ives, Spiga Das vad \ ; \ / (oy Tammy dex Dec tes [eat | een a Ready for Se (@) Bat Gaga Beaty for dae neg Des vad Vaid do Desa bes (0) Teming Sagas w Lecture Notes in Computer Architecture and Organization Asynchronous Serial Data Transfer 1, When a character is not being sent, the line is kept in the ks 2, The initiation of a character transmission is detected from y, "8% which is always 0. “ath, 3. The character bits always follow the start bit, 4 After the last bit of the character is transmitted, a stop bit ig when the line returns to the I-state for at least one bit tine detec Baud rate is a measure of data transmitted in unit time Baud rate may be expressed in bits per second Input-Output Interface Transmitter Receiver Modem Brg LUctry vid S| Modes of Input-Output ans ee ae cag Programmed input/output selon rtlay Chainthy Interrupt-initiated input/output Puallel Prigc % Direct memory access (DMA) © Burst mode * Cycle stealing mode Input-Output Processor (10P) Supports multiple modes of input/output sthecoolestprofess™ Memory Mamagerauat tipterm (ee antl & wsog deen pes : Main Memory! hve ee pranft COS L_ « speeol ‘ra bent ered cache! MUL program rainy! Lb, canny, L proyracis “acetal al dase ross =paabielt prrogrante afr ————__» ———* —___ ,» — 19.2 Mane Meer —— gan S C seme ceomoluctor Gia Rom) REN SRAM | Sao T Pata toed HU pour cupply —— — Jexo ral Useeords ~ fp Hope brewuuters ee ors ~ hte stad yn Joxm y voltage — stored tn pom Of currins — No fuermory Mapping fike CONN) * =e =a chouackuti be access actin Aumiliony Macy: tN ee leapaciey] cot = putes wth novtry pacts requ asektine $0 pos'hin tee astm pack to a Cocatimn & tromju tim. Aeeletrhne > tram AM tes if computer Architecture and Organization no! ry on gram computer, Memory stores program and data wer ced-PPO eae ng actually @ collection of memory units of different types y jer OF Hierarchy wer cpu acer Rung speed Volatility Cost per byte Figure 12-1 Memory hierarchy in s computer system. Main Memory Random Access Memory (RAM) * 0s User programs Multiprogramming Multitasking / timesharing ftthecoolestprofessor Lecture Notes in Computer Architecture and Organization Read Only Memory (Rom) ° BIOS Bootstrap loader RAM and ROM share the memory space Cache Memory Associative memory / Content addressable memory Hit ratio = hits / (hits + misses) Hit ratio is 2PProximately 0.9 Writing into Cache memory o Wri e-through ° Write-back Secondary Memory Hard disk rock 1 Paging fit... irtual Memory : : Ge lly implemented using paging ae eae imber of pages >> number o} eae ¥ Ristersthicis p > number of bi . #thecoolestprofessor Lecture Notes in Computer Architecture and Organization @ Use a valid-invalid bit in Page table page fault "Page replacement _ Page replacement algorithms © FIFO LRU Locality of References Locality of references in code Locality of references in data Segmentation Types of segments * Code * Data Stack ‘Segment registers in 8086 . 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