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Powering Laser Diode Systems
Powering Laser Diode Systems
Powering Laser Diode Systems
Diode Systems
Gregoriy A. Trestman
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Tutorial Texts Series
. Powering Laser Diode Systems, Grigoriy A. Trestman, Vol. TT112
. Optics Using MATLAB®, Scott W. Teare, Vol. TT111
. Plasmonic Optics: Theory and Applications, Yongqian Li, Vol. TT110
. Design and Fabrication of Diffractive Optical Elements with MATLAB®, A. Vijayakumar and Shanti
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. Energy Harvesting for Low-Power Autonomous Devices and Systems, Jahangir Rastegar and Harbans S.
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. Practical Electronics for Optical Design and Engineering, Scott W. Teare, Vol. TT107
. Engineered Materials and Metamaterials: Design and Fabrication, Richard A. Dudley and Michael A.
Fiddy, Vol. TT106
. Design Technology Co-optimization in the Era of Sub-resolution IC Scaling, Lars W. Liebmann, Kaushik
Vaidyanathan, and Lawrence Pileggi, Vol. TT104
. Special Functions for Optical Science and Engineering, Vasudevan Lakshminarayanan and L. Srinivasa
Varadharajan, Vol. TT103
. Discrimination of Subsurface Unexploded Ordnance, Kevin A. O’Neill, Vol. TT102
. Introduction to Metrology Applications in IC Manufacturing, Bo Su, Eric Solecky, and Alok Vaid, Vol.
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. Introduction to Liquid Crystals for Optical Design and Engineering, Sergio Restaino and Scott Teare, Vol.
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. Ocean Sensing and Monitoring: Optics and Other Methods, Weilin Hou, Vol. TT98
. Digital Converters for Image Sensors, Kenton T. Veeder, Vol. TT97
. Laser Beam Quality Metrics, T. Sean Ross, Vol. TT96
. Military Displays: Technology and Applications, Daniel D. Desjardins, Vol. TT95
. Interferometry for Precision Measurement, Peter Langenbeck, Vol. TT94
. Aberration Theory Made Simple, Second Edition, Virendra N. Mahajan, Vol. TT93
. Modeling the Imaging Chain of Digital Cameras, Robert D. Fiete, Vol. TT92
. Bioluminescence and Fluorescence for In Vivo Imaging, Lubov Brovko, Vol. TT91
. Polarization of Light with Applications in Optical Fibers, Arun Kumar and Ajoy Ghatak, Vol. TT90
. Digital Fourier Optics: A MATLAB Tutorial, David G. Voeltz, Vol. TT89
. Optical Design of Microscopes, George Seward, Vol. TT88
. Analysis and Evaluation of Sampled Imaging Systems, Richard H. Vollmerhausen, Donald A. Reago, and
Ronald Driggers, Vol. TT87
. Nanotechnology: A Crash Course, Raúl J. Martin-Palma and Akhlesh Lakhtakia, Vol. TT86
. Direct Detection LADAR Systems, Richard Richmond and Stephen Cain, Vol. TT85
. Optical Design: Applying the Fundamentals, Max J. Riedl, Vol. TT84
. Infrared Optics and Zoom Lenses, Second Edition, Allen Mann, Vol. TT83
. Optical Engineering Fundamentals, Second Edition, Bruce H. Walker, Vol. TT82
. Fundamentals of Polarimetric Remote Sensing, John Schott, Vol. TT81
. The Design of Plastic Optical Systems, Michael P. Schaub, Vol. TT80
. Fundamentals of Photonics, Chandra Roychoudhuri, Vol. TT79
. Radiation Thermometry: Fundamentals and Applications in the Petrochemical Industry, Peter Saunders,
Vol. TT78
. Matrix Methods for Optical Layout, Gerhard Kloos, Vol. TT77
. Fundamentals of Infrared Detector Materials, Michael A. Kinch, Vol. TT76
. Practical Applications of Infrared Thermal Sensing and Imaging Equipment, Third Edition, Herbert
Kaplan, Vol. TT75
. Bioluminescence for Food and Environmental Microbiological Safety, Lubov Brovko, Vol. TT74
. Introduction to Image Stabilization, Scott W. Teare and Sergio R. Restaino, Vol. TT73
. Logic-based Nonlinear Image Processing, Stephen Marshall, Vol. TT72
. The Physics and Engineering of Solid State Lasers, Yehoshua Kalisky, Vol. TT71
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1 Introduction 1
1.1 Photonics Revolution and Power Electronics 1
1.2 Audience 2
1.3 Equation Derivation, Numerical Calculations, and Units 2
1.4 Schematic Plotting and Circuit Computer Simulation 4
1.5 Power-Supply Development 4
2 Power-Electronics Design Rules to Save Time and Avoid Frustration 7
2.1 Start with a Clearly Written Technical Specification 7
2.2 Attentively Study the Characteristics of the Load 8
2.3 Choose the PS Topology Carefully 9
2.4 Choose a Topology that Efficiently Uses the
Parasitic Elements of the Circuit Components 9
2.5 Use MathCad for Circuit Calculation and Mathematical Modeling 10
2.6 Perform a Computer Simulation of the Power-Electronics Circuits 10
2.7 Verify the Correctness of the Component Kit
and the Soldering Quality 11
2.8 Test Offline Power Sources Carefully 11
2.9 Offline Devices Not Connected to the AC Mains Do Not Work 12
2.10 Skillful Measurements Obtain the Required Results 12
2.11 LD-Driver Design Priorities 12
3 Similarities and Differences between LDs and LEDs 15
ix
x Contents
Index 111
Preface
In February 2015, SPIE Press offered Dr. Ilya Bystryak and me the
opportunity to write a book based on our professional development course
“Powering and Integration of Laser Diode Systems,” presented by both of
us at the Photonics West conference.1 The course material was the result
of our lengthy collaboration, initially in the Soviet Union, where we worked
for the same research laboratory for an extended period of time, and later in
the U.S.
Professional collaboration and the sharing of ideas are important factors
of our successful careers in the field of power electronics. Such communication
multiplies the engineering effectiveness of each other. The best-known
examples of similar fruitful cooperation are the joint work of Steve Jobs
and Steve Wozniak, Larry Page and Sergey Brin, and Bill Gates and Paul
Allen. Constant, critical face-to-face or telephonic discussions around ongoing
projects and emerging problems enables the fast and efficient resolution of
these challenges. This form of cooperation is rarely achieved by project formal
discussions at scheduled company meetings, design reviews, etc. Therefore,
I recommend to my young colleagues to find a partner and a formidable
opponent to cooperate with and to maintain this kind of professional
relationship throughout their career.
Because the book is based on an instructional course, I decided to present
it to a certain extent as a textbook; however, because strict technicalities are
often not very useful and boring to read, the material is not written in the
traditional textbook style. This Tutorial Text discusses the competent design
and skilled use of laser diode drivers (LDDs) and power supplies (PSs) for the
electrical components of laser diode systems. It is intended to help power-
electronic design engineers during the initial design stages: the choice of the
best PS topology, the calculation of parameters and components of the PS
circuit, and the computer simulation of the circuit. Readers who use laser
diode systems for research, production, and other purposes will also benefit.
The book will help readers avoid errors when creating laser systems from
ready-made blocks, as well as understand the nature of the “mystical failures”
of laser diodes (and possibly prevent them).
xiii
xiv Preface
xvii
Chapter 1
Introduction
1
2 Chapter 1
Mid- and high-power LDs are very expensive devices. The conversion
topologies offered in the book have an inherent current limit. This feature
provides the LD protection from any AC line instabilities or LDD
malfunctioning. Unlike LEDs, LDs are widely used in the pulsed mode and
thus require pulsed LDDs. Another goal of this book is to familiarize readers
with the effective pulsed LDDs.
The book also covers some other important aspects of power-electronics
design, such as soft switching in high-frequency (HF) switched-mode
converters, advantageous usage of parasitic elements of electrical circuit
components, paralleling conversion modules to increase power in industrial
LDDs, etc.
1.2 Audience
This book focuses on the powering of LD systems. It was written for two
categories of professionals: (a) power-electronics design engineers involved in
the development of LDDs and power supplies (PSs) for electrical components
of laser systems, and (b) professionals who build and/or operate laser systems.
Companies or organizations that build or use LD systems have two
alternatives when it comes to system creation. The first is to develop specific
LDDs and PSs. This case requires a significant investment of finances and
time, and it requires power-electronics-engineering resources experienced in
the development of current and power sources (which is not always possible).
The second alternative is to assemble the system from commercially available
components. In many cases, companies prefer the latter.
LDDs and PSs for LD subsystems are very important parts of LD systems
that directly affect the system’s general reliability and the expected lifetime of
the most expensive part of the system, i.e., the LD assembly. System
developers and users should understand how to choose the appropriate power
sources, which often involves compiling a list of questions for vendors and
knowing the limitations of the standard PSs on the market. These topics are
also discussed in the book.
The issue specific to LDs is their dangerous sensitivity to the slightest
current overloads in comparison to the other laser types. There is a joke
among laser specialists that “all LD system users can be divided into two
groups: those who already burned down an expensive LD and those who will
eventually.” I hope that this book will help readers avoid belonging to either
of these groups.
circuit examples. These formulas and examples can be copied from the book
and pasted into MathCad software for use with variations for calculations of
your circuits. Most graphics were also plotted using MathCad.
To interpret the formulas in the book correctly, it is necessary to mention
several MathCad specifics:
• To define a variable definition, use the symbol :¼. A variable can be set
either numerically or symbolically. For example,
x :¼ 2; y :¼ x2 1:
y ¼ 3:
dI load V
:¼ dc ▪.
T3 T2 Lf
for answers. The list of emerging issues and challenges is very long, including
ensuring PS safety, protecting against power surges in the AC mains,
preventing load failure when the PS malfunctions, etc.
It is possible to consider all of these issues, to find ways of solving them,
and learn how to design reliable PSs. However, digital-design engineers would
need to abandon their specialty for several years and completely immerse
themselves in power-conversion technology, namely the design of PSs.
Qualified experts in digital design who are not passionate about power
electronics would do better to focus on their field. (The exception is a PS with
microprocessor control. All a digital designer must do is develop the
microprocessor control and nothing more.)
Readers who are adamant about becoming a power-electronics engineer
will benefit from the useful rules and tips contained in this book. However,
this one text is not enough to become a professional power-electronics
designer. There are many other good books devoted to the subject matter,
which can be found online.4 Beginners should start with those light on
mathematics; the calculation of converters is rather simple and is based on
well-known mathematical formulations of electric-circuits laws.
Chapter 2
Power-Electronics Design
Rules to Save Time and Avoid
Frustration
So you have decided to specialize in power electronics (or you are working in
the field already), and you are tasked with developing a power source. The
following rules and recommendations will help you avoid unnecessary stress,
frustration, and undesirable consequences.
7
8 Chapter 2
characteristics are discussed later in this book. Due to the large variety of LD
assemblies on the market, power-electronics designers should carefully study the
specifics of each LD assembly and develop a corresponding LD driver; this
method ensures that a LDD would provide not only reliable LD operation but
also prevent failure of the driver itself during the warranty period.
lacked accuracy, and the experimental results were at odds with the simulated
results. A simulation run required additional circuit elements that were not
required in the real circuit, e.g., small resistors. Personal computers were slow,
and simulations required significant amounts of time to run. These issues were
irritating enough that many engineers refused to use simulation because it was
much faster to assemble and test the prototype circuits.
Most of these drawbacks no longer apply, and simulation has become a
powerful tool for the preliminary study of circuits. However, other hazards
remain. Some engineers omit calculation steps and attempt to solve design
problems by varying the component parameters in the simulation program.
This approach is rarely successful.
The next question asks to what extent a PS must be simulated. PSs are
devices of varying complexity. Some are simple devices powered by batteries
and have one converter with (or without) a simple feedback circuit. Others are
complex devices powered by AC mains and have several converters and
complex analog or digital feedback circuits. It may be unrealistic to simulate
the complete scheme of a complex PS.
A positive feature of simulation is its ability to quickly verify the quality of
the scheme calculation. If there was a significant difference between the
calculation and the results of the simulation, it is necessary to stop and try to
find the sources of these discrepancies.
LTspiceIV software by Linear Technology Inc. is one of the most convenient,
fast working, and accurate tools to simulate power converter circuits. This
software is free to download on the company’s website.3 It is very easy to master
and only requires a few hours to get comfortable with simulating circuits in it.
Also, Linear provides examples of circuit simulations for many of the chips they
manufacture. The case studies of Linear chips simulations are also beneficial.
(The author has no personal or financial ties to Linear Technology Inc.)
the AC line is cut off. High-quality capacitors can hold a charge for a long
time. An engineer might forget to disconnect the device from the AC line
before making changes to the scheme, which might be under the main voltage
(the presence of which is not evident).
It is advised to keep a voltmeter constantly connected to the rectified
mains voltage (bus voltage) to protect the laboratory staff and yourself. Check
the voltmeter to ensure that there is no voltage on the bus before attempting
anything with the circuit. A better option would shunt the input of the
voltmeter with a push-button contact connected in series with a several-
thousand-ohms two-watt resistor. Press the contact to discharge the
electrolytic capacitors before altering the circuit.
15
16 Chapter 3
17
18 Chapter 4
Figure 4.1 IVCs of ideal loads: (a) resistive load, (b) constant voltage load, and
(c) constant current load.
• Constant current load. The ideal load belonging to this class maintains a
constant current when the load voltage increases [Fig. 4.1(c)]. To this
load type belong energy-storage inductors and some electrical motors.
The characteristics of real loads are close to ideal with some degree of
approximation. They change with the operational temperature. Other factors,
such as humidity, electrical stress, and aging, also have an effect.
efficacy rapidly drops, and the lasing threshold and light frequency shift.
Effective cooling is necessary to keep the LD parameters stable. Although a
passive heatsink usually provides adequate cooling for low-power LDs, mid-
and high-power LDs require active cooling that uses thermoelectric (TE)
coolers or forced air or water.
Figure 4.3 IVCs of ideal electrical sources: (a) CVS, (b) CCS, and (c) CPS.
Laser Diodes: Electrical Loads and Driving Requirements 21
Figure 4.4 Powering a LD with (a)–(b) a CVS and (c) a CCS. (a) The LD temperature
increase during operation produces a large current increase (dI) in the LD. (b) Even a small
voltage ripple (dV) in the CVS leads to a significant current ripple (dI) in the LD. (c) The
LD temperature increase does not produce a large voltage decrease dV in the LD powered
by a CCS.
22 Chapter 4
23
24 Chapter 5
Figure 5.1 (a) Block diagram and (b) IVC of a real passive (unregulated) DC-voltage
source.
26 Chapter 5
Figure 5.2 (a) Block diagram and (b) output IVC of a real active CVS.
Primary and Secondary Sources of Electrical Energy 27
Figure 5.3 (a) Block diagram and (b) IVC of a real active CCS.
load curve of an unregulated CVS until at 0-V resistance it reaches 0 V and the
short-circuit current Isc.
An active CCS [Fig. 5.3(a)] is created by adding an active regulating
circuit to an unregulated CVS. An active regulating circuit includes a current
sense resistor Rs that converts the load current into a voltage form of the
current sense signal. The current sense signal is compared with the precision
signal from the voltage reference source with the differential signal-driving
active regulating element, which adjusts the load voltage to keep the output
current Ic constant. This active CCS can keep the constant output current Ic
close to ideal with the load resistance increase. It can reach the maximum
regulation voltage level Vreg max. At this point, the CCS becomes
unregulated, the output current starts to decrease, and the output voltage
still increases following the load curve of the CVS and reaches the open-circuit
voltage Voc at infinite load resistance.
An active CPS comprises an active regulating circuit and an unregulated
CVS, as depicted in Fig. 5.4(a). It includes a voltage divider R1, R2 to get
the voltage sense signal and a current sense resistor Rs to get the current
28 Chapter 5
Figure 5.4 (a) Block diagram and (b) IVC of a real active CPS.
sense signal. These signals are multiplied by a multiplier. The product of the
current-to-voltage signals is compared with the precision voltage reference
signal in a comparator, which drives the active regulating element and keeps
the output power constant.
An active CPS reaches the regulation limits with a load resistance decrease
as well as with a load resistance increase [Fig. 5.4(b)]. With the load resistance
decreases, it goes out of power control at the Ireg max, and the output voltage
follows the load curve of the CVS with a further resistance decrease, up to Isc.
When the load resistance increases and the output voltage reaches Vreg max,
the CPS goes out of power regulation, the output voltage increases more
slowly, and follows the load curve of the CVS with further resistance
increases, up to Voc.
Summarizing the explanations in this section,
• Depending on the conversion topology the load curve of unregulated
CVS could have a different shape.
• Different types of active secondary sources (PSs) can be made from
unregulated primary CVSs.
Primary and Secondary Sources of Electrical Energy 29
Figure 5.5 Load curve of an unregulated CVS and the regulation area. Depending on the
conversion topology, the load curve could have a different shape.
• Within the regulation area, an active control takes power over the
conversion topology specifics, and the PS behaves as a voltage, current,
or power source in the presence of the corresponding feedback.
• On the IVC graph, the PS regulation area is confined between the
voltage and current axis and the load curve of uncontrolled CVS
(shaded area in Fig. 5.5).
the power dissipates in the ballasting resistor. A resistor can also be used as
ballast when converting an AC CVS into an AC CCS (AC VtoI converter),
but in order to minimize power losses it is better to avoid resistive elements
and use instead reactive ballasting elements, e.g., inductors or capacitors.
Sinusoidal AC CVSs can use either an inductor or capacitor as a ballasting
element. However, as will be explained later in this chapter, a square-wave
AC CVS can only use an inductor.
Figure 5.7 (a) Schematic and (b) load curves of a passive DC VtoI converter.
Primary and Secondary Sources of Electrical Energy 31
Figure 5.8 IVCs of DC VtoI converters with different open-circuit voltages and ballasting
resistors.
closer the IVC of the VtoI converter is to the IVC of the ideal CCS, the larger
the voltage drop Voc2 – VLED and the power loss PRext in the ballasting resistor
Rext:
Prext :¼ ðV oc V LED ÞI LED ▪ . (5.3)
In order to calculate the current-limiting resistor Rext, the Voc of the CVS, the
load voltage VLED, and the load current ILED must be known. Based on
Eq. (5.2), the value of the ballasting resistor is
Figure 5.9 A passive AC VtoI converter with an inductor Lb as a ballasting element and a
resistive load Rload.
The voltage Voc of the CVS drops on the circuit impedance XZ:
V oc :¼ I load X Z ▪ , (5.5)
where the circuit impedance XZ is the square root of the sum of the squares of
the inductor impedance XLb and the load impedance Rload:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
X Z :¼ X 2Lb þ R2load ▪ , (5.6)
X Lb :¼ 2pF Lb ▪ , (5.7)
V oc
I load ðRload Þ :¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ▪, (5.8)
X 2Lb þ R2load
V oc
V load ðRload Þ :¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Rload ▪: (5.9)
X 2Lb þ R2load
Figure 5.10 Load curve of a sinusoidal AC VtoI converter with an inductive ballasting
element.
• Up to 20% of the Voc, the IVC is close to the characteristic of the ideal
current source. In this area, the CVS with a ballasting inductor acts as a
passive CCS.
• In applications where the proximity of the IVC to the ideal current
source characteristic is not critical, this circuit can be considered as a
VtoI converter up to 50% of the open-circuit voltage.
• From 0–50% of the load current, the circuit acts as a nonideal voltage
source (the load voltage drops from 100% to 88%).
• The area from 88% and 50% of the load voltage is a transition between a
CVS and CCS.
Disregarding any losses in the wires and core, an inductor can be
considered as a lossless ballasting element.
The formula for a ballasting inductor Lb can be derived by combining
Eqs. (5.6) and (5.7):
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi V 2oc V 2load
X 2Z R2load I 2load
Lb :¼ ▪ :¼ ▪: (5.10)
2pF 2pF
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
X Z :¼ X 2Cb þ R2load ▪, (5.12)
X Cb :¼ 1∕ð2pF C b Þ▪ , (5.13)
37
38 Chapter 6
Table 6.1 Initial data for a circuit calculation. The value of the output voltage
peak-to-peak ripple equals 1% of the nominal output voltage Vnom (dV :¼ 1).
CVS voltage Vdc :¼ 200
Acting HB voltage (Vin ¼ 0.5Vdc) Vin :¼ 100
Switching frequency Fsw :¼ 100 · 103
Switching period Tsw :¼ 1/Fsw ¼ 1 10–5
Nominal output power Pnom :¼ 100
Nominal output voltage Vnom :¼ 100
Nominal output current Inom :¼ Pnom/Vnom ¼ 1
Efficiency h :¼ 1
Turns ratio of transformer NTr :¼ W2/W1▪; NTr :¼ Vnom/Vin ¼ 1
40 Chapter 6
The first step calculates Isc, the value of the output current at the short-
circuit condition (Rload ¼ 0). An accurate calculation requires knowledge of the
converter IVC (load curve), but the derivation of an analytical expression for the
IVC in this case is impossible. The IVC for our numerical example (Fig. 6.2) was
obtained using computer simulation in LTspiceIV and verified experimentally.
Based on the load curve graph, the short-circuit current equals 1.135 of Inom:
The current in the inductor Lb has a triangular shape (Fig. 6.3), and the
peak current is
Figure 6.2 Load curve of a DC VtoV converter: Vdc ¼ 200 V, Vin ¼ 100 V, Fsw ¼ 100 Hz,
Lb ¼ 110 uH, Cr ¼ 8 nF, Cf ¼ 10 uF, Csn ¼ 0.6 nF, and W2/W1 ¼ 1.
Figure 6.3 Waveforms of one conversion cycle at the short-circuit output (Rload ¼ 0):
(a) voltage in the node A and (b) current in the inductor Lb.
High-Frequency Switch-Mode Passive DC-to-DC Converters in LD Systems 41
Figure 6.4 Waveforms of one conversion cycle at nominal output: (a) voltage at the node
A, (b) voltage across the resonant capacitor Cr, (c) current in the inductor Lb at Vo ¼ Vin,
(d) current in the inductor Lb at Vo . Vin, (e) current in the inductor Lb at Vo , Vin, and
(f) output voltage Vo with ripple voltage dV.
D3–D6 are not conducting during this time, the resonant tank is not loaded,
and the resonant oscillation happens. At T1, the current in the inductor
Lb reaches the maximum of IPKnom, which equals 2 Vin over the square root of
the characteristic impedance of the resonant tank:
2V in
I PKnom :¼ qffiffiffiffi ¼ 1.652: (6.10)
Lb
Cr
At moment T1, the diodes D4, D5 start to conduct, and they clamp the Cr
voltage to Vo. In the absence of a clamp, the Cr voltage can resonate up to 3Vo
(the dotted line in Fig. 6.4). During the voltage clamping time, the current in the
inductor Lb is flat until the moment T2, when the switch Q2 turns off. The current
that accumulated in the inductor Lb recharges the parasitic MOSFET drain-
source capacitors and snubber capacitor Csn (see Fig. 6.1). The inductor
Lb current then switches to D1 (moment T2) and flows into capacitors C1 and Co
(which are connected in series for this current). Because capacitors are large and
High-Frequency Switch-Mode Passive DC-to-DC Converters in LD Systems 43
Figure 6.5 Circuit diagrams for illustration switching losses in the power-switching device
MOSFET Q1: (a) without snubber components; (b) with current snubber components Lsn, D1,
R1; and (c) with voltage snubber components Csn, D2, R2.
High-Frequency Switch-Mode Passive DC-to-DC Converters in LD Systems 47
Figure 6.6 Voltage and current waveforms that illustrate hard- and soft-switching in a
MOSFET Q1 (the actual waveforms could look different).
In Fig. 6.6, the areas under the crossing trajectories of the voltage and
current (dark shaded areas) reflect energy loss in one switching cycle of Q1. The
fastest areas are turn-on and turn-off transitions, and the smaller ones are the
switching losses. The switching times of the MOSFET drain-source current
Ids and voltage Vds depend on the power of the MOSFET gate drive signal.
However, after reaching a certain level, the improvement of the gate drive
signal cannot hasten the MOSFET transitions any further. The transitions are
limited by the HF characteristics of the MOSFET: the standard switching times
are in tens of nanoseconds.
As mentioned earlier, another problem associated with fast voltage and
current transitions is the subsequent EMI generation. The faster the voltage
transition is, the broader the common-mode noise spectrum. Faster drain-
source current transitions mean a broader differential mode noise spectrum.
Broader noise spectrums are harder to suppress.
An important part of the switch-mode PS design process is the reduction
of the switching losses and the EMI generation. It is possible to reduce
switching losses and generate EMI simultaneously by slowing the speed of the
voltage or current transitions.
In order to slow the speed of the current rise in the switch Q1 at turn-on, it
is necessary to place an inductor Lsn in series [Fig. 6.5(b)]. As can be seen from
Fig. 6.6, Lsn slows the speed of the current rise and reduces turn-on losses
(lightly shaded area) in the switch.
Likewise, to reduce turn-off losses, a capacitor Csn (with additional diode
D2) is placed in parallel with Q1 [Fig. 6.5(c)]. The charging of the Csn slows the
speed of the Q1 Vds rise and reduces Q1 turn-off losses (lightly shaded area in
Fig. 6.6). The parasitic drain-source capacitance Cds of a MOSFET acts the
same way. Cds is sometimes enough for an acceptable level of Q1 turn-off losses.
The inductor Lsn with additional components D1 and R1 in Fig. 6.5(b), which is
used to remove energy from Lsn and prepare it for the next switching cycle, form
the so-called current snubber (also called a turn-on snubber). Similarly, the
capacitor Csn with additional components D2 and R2 in Fig. 6.5(c), which is used to
remove energy from Csn, form the voltage snubber (also called a turn-off snubber).
48 Chapter 6
These types of snubbers carry over switching losses from the semiconduc-
tor switching devices to the resistors, but losses still dissipate in the converter
circuit. The snubbers that move this energy to the load or return to the CVS are
called non-dissipative or lossless snubbers. Non-dissipative snubbers help to
increase the efficiency of the switching converters. Sections 6.6 and 8.2 show
how to design and calculate nondissipative snubbers in each particular case.
The slower the transition speed of the current or voltage is (which is
provided by the corresponding snubbers), the smaller the switching losses
and the EMI generation. However, if too much time is left for transitions, it
will limit the maximum frequency of the converter. The compromise is a
transition time ~5 times larger than the MOSFET switching time, indicated by
manufacturer specifications.
(with a switching period of 10 ms); the MOSFET turn-off fall time, i.e., the
current in the MOSFET drops to 0, is 20 ns. In the initial time T0, the gate
drive signal of the switch Q1 is high, and the switch is turned on. The current
from the capacitor C1 flows through Q1, Lb, and the primary winding W1 of
transformer T. The Q1 drain-source voltage (voltage across the snubber
capacitor Csn) is 0. At the moment T1, the Q1 gate-drive voltage goes to zero,
and the switch Q1 starts turning off. A 20-ns current in Q1 reduces to 0
(the moment T3).
What happens to the Q1 drain-source voltage while it turns off? As soon as
the gate-drive voltage falls to 0, Vds starts to increase and, in the absence of
a snubber capacitor Csn, reaches the Vdc level at the moment T2. Rise time
T1–T2 is defined by the value of the current in the inductor Lb and the sum of
Q1 and Q2 drain-source parasitic capacitances CdsQ1 and CdsQ2 (see Fig. 6.8)
because at turn-off they act in parallel (CdsQ1 is charging, and CdsQ2 is
discharging). If these capacitances are small, the Q1 drain voltage quickly rises
while Q1 current is still high. This situation produces high switching losses in Q1.
In this case, the addition of a snubber capacitor Csn reduces the voltage rise
and Q1 turn-off losses.
When choosing a snubber capacitor, follow a practical rule: to reduce
turn-off losses to an acceptable amount, the total capacitance (CdsQ1, CdsQ2,
and Csn) is such that the growth time of the MOSFET drain voltage is five
times greater than the spec value of the MOSFET current fall time. For
instance, if the spec value is 20 ns, then the growth time should be ~100 ns
(T1–T4 time).
50 Chapter 6
Figure 6.8 Schematic of a quasi-resonant VtoV converter with parasitic circuit elements:
leakage inductance Ls of transformer, secondary interwinding capacitance Csec, and body
diodes D1, D2 and drain-source capacitances CdsQ1, CdsQ2 of MOSFETs Q1 and Q2.
As soon as the voltage across capacitor Csn reaches Vdc [the moment T2 in
Fig. 6.4(c)], the body diode D2 of the MOSFET Q2 turns on, and the current
of the inductor Lb starts to flow through it into the capacitor C2, linearly
dropping to zero [moment of time T3 in Fig. 6.4(c)]. During any moment
when the diode D2 conducts current [period T2–T3 in Fig. 6.4(c)], the switch
Q2 can be turned on without losses (ZVS turn-on) because the voltage value
on it is the voltage of the directly biased Q2 body diode.
This process is shown in Fig. 6.7 for the switch Q1. At T5, the Q2 gate
drive signal drops to 0. The current of Lb recharges the capacitors CdsQ1,
CdsQ2, and Csn. The Q1 drain-source voltage linearly reduces to 0. At the
moment T6, Lb current switches to Q1 body diode. At the moment T7, the Q1
gate-drive signal turns on Q1. Because the current flows through Q1 body
diode at this moment, the Q1 turns on without losses (ZVS turn-on). After
that, the described operations are repeated for the next switching cycle.
In order to avoid cross-conduction in the power switches Q1 and Q2
(which could damage them), the following switch turn-on can be delayed by
the time required to recharge the snubber capacitor. The adjustable delay is a
built-in function in modern PWM controllers.
Consider which factors limit the conversion frequency. The first limiting
factor is the switching speed of the power circuit elements (MOSFETs and
output rectifier diodes). The second factor is the switching losses, and the third
factor is the parasitic parameters of the circuit components.
The last question to resolve is the relation of the converter switching
frequency Fsw and the resonant frequency Fr of the resonant tank, comprising
Lb and Cr. While the capacitor Cr [To–T1 in Fig. 6.4(c)] recharges, all rectifier
bridge diodes D3–D6 are off, and the current from the converter input does not
reach the output. Therefore, the closer the switching frequency Fsw is to the
resonant frequency Fr, the greater the RMS currents in the conductors and
the lower the converter efficiency. On the other hand, the large decrease in the
High-Frequency Switch-Mode Passive DC-to-DC Converters in LD Systems 51
stage of the conversion cycle, the energy accumulates not only in the
magnetizing inductance of the primary winding but also in the LI. This energy
is not transferred into the load; in order to prepare the converter for the next
conversion cycle, it must be either dissipated or returned to the primary source.
Both cases lead to energy losses and a reduction in the converter efficiency.
Flyback converter designers try to minimize LI. Flyback transformer
construction has two shortcomings: the difficulty in providing isolation
between the windings, and the large between-windings stray capacitance,
which provides the noise pass from the secondary to the primary side of the
converter. To reduce this capacitance, a Faraday shield (a single-turn, earth-
grounded piece of foil) is placed between the primary and secondary windings.
The necessity for a gap in the transformer core, improved isolation, and
Faraday shield complicates the transformer design.
The LI is useful in the HB VtoV converter presented in this section. It
depends on the configuration of the coupling windings and their respective
position. The LI between two windings can vary in the desirable range by
changing the number and distribution of winding turns and mutual
orientation. The LI does not depend on of the magnetic core parameters,
and it has good repetition from sample to sample. It makes the operation of
the power supply (utilizing the transformers with the LI) predictable and
usable in mass production.
Accurate calculation of LI is usually not possible because are too many
factors to consider. Much faster and efficient is the method of building a
transformer sample and measuring the LI. However, the calculation formulas
for the LI of several transformer configurations were developed; the most
significant ones for this book’s topic are discussed in this section.
The minimal LI is achieved in the transformer where the primary and
secondary are wound with bifilar wires and evenly distributed on the toroid
core. Formulas for toroidal transformer LI calculations can be found in
Ref. 9. The LI calculation methods for transformers made on an EE core and
pot core come from the Transformer and Inductor Design Handbook.10
Figure 6.10 shows the conventional transformer winding configuration where
the secondary winding is placed over the primary with tape insulation between
them. The formula of this type of LI transformer is
4pðMLTÞN p b1 þ b2
Ls :¼ cþ · 109▪ , (6.14)
a 3
where a is the winding length, b1 is the winding build of the primary, b2 is the
winding build of the secondary, c is the insulation thickness, MLT is the mean
length of the winding turns, and Np is the number of primary turns. The
dimensions are in centimeters, and inductance is in henrys.
Figure 6.11 shows the pot core sectionalized transformer where secondary
and primary windings are wound side by side. Compared to the conventional
54 Chapter 6
configuration, this transformer has excessive LI. Because the bobbin has an
insulation barrier, no tape is necessary between the secondary and primary
windings. The LI formula for this type is
4pðMLTÞN p a þ a2
Ls :¼ cþ 1 · 109▪ , (6.15)
b 3
where a1 is the primary winding length, a2 is the secondary winding length, b is
the winding build, c is the insulation barrier thickness, MLT is the mean
length of the winding turns, and Np is the number of primary turns. The
dimensions are in centimeters, and inductance is in henrys.
The maximum LI can be reached in a UU-core transformer with the
primary and secondary windings placed on the opposite legs of the core
(Fig. 6.12). To get the required LI, the turns of the primary winding can be
distributed: part of the primary is on one leg of the core, and the other part of
the other leg is under the secondary winding.
High-Frequency Switch-Mode Passive DC-to-DC Converters in LD Systems 55
57
58 Chapter 7
Figure 7.1 Schematic of a LD driver with an inductive output and direct LD current PW
modulator.
Figure 7.2 IVC of converter with inductive output, where Vdc ¼ 200 V, Vin ¼ 100 V, Fsw ¼
100 kHz, Lb ¼ 110 uH, Cr ¼ 8 nF, Lf ¼ 10 mH, and W2/W1 ¼ 1.
Figure 7.3 The static LDD load curve (Vdc ¼ 200 V, Vin ¼ 100 V, Fsw ¼ 100 kHz, Lb ¼ 100 uH,
Lf ¼ 10 mH, W2/W1 ¼ 2, Cr ¼ 2 nF) and the hypothetical LD string IVC. The graph also shows
the hypothetical LD-lasing-threshold current and the hypothetical destructive current level of the
LD string.
reference signal generator, and PWM control, as shown in Fig. 7.1. The
dependence of the load current on the duty ratio of the PWM signal is linear.
A switch Q3 connected in parallel with the LD string and driven by the
PWM signal generator is used for the direct PWM of the LD string current in
a broad range of frequencies and duty ratios. By using the MOSFET as a Q3
switch, very fast on and off transitions (in the range of tens of nanoseconds)
can be achieved. It is critical to install the MOSFET switch in the closest
proximity to the LD string when switching large currents. Very fast switching
of large currents causes significant voltage spikes even on the small
inductances of short wires. These spikes are dangerous for LDs. The parasitic
body diode D3 of the MOSFET Q3 shunts the LD string in the reversed
polarity and protects LDs from reverse voltage spikes.
Figure 7.4 Waveforms of the pulsing voltage Vrec at the output of rectifier bridge D4–D7
(node A) and the ripple of the load current ILoad.
61
62 Chapter 8
Figure 8.1 Boost converter for powering a passive LDD from a battery.
Figure 8.3 Waveforms of the rectified voltage and current of a one-phase rectifier: (a) the
voltage in the absence (dotted line) and in the presence (solid line) of an electrolytic
capacitor; and (b) the AC line current in the absence (bold line) and in the presence (thin
line) of the PFC circuit.
Powering Medium-Power LD Systems 63
reduction, a bigger Cf is better) is, the shorter the duration of the current
pulses [bold line in Fig. 8.3(b)]. The effect of these current pulses on the AC
line is negative: they distort the AC line voltage sinusoid (harmonic
distortion), generate significant differential mode noise, and lead to a low
power factor (PF).11
These adverse effects can be eliminated by a power factor correction
(PFC) circuit. Figure 8.4 depicts a block diagram of a LDD powered by a
one-phase AC line with a PFC circuit. The PFC circuit is usually an active
boost, switch-mode-type converter. The PFC circuit forces the AC line current
[thin line in Fig. 8.3(b)] to coincide in phase and shape with the AC line
voltage. It also produces very low harmonic distortion and a PF close to
100%. For the AC line, a LDD with a front-end PFC circuit looks like a
resistive load. However, the role of the PFC circuit is not limited just by these
functions. Additional advantages include the following:
• A PFC circuit produces a stable constant DC voltage that can be used at
the input of a passive LDD.
• Designing a PFC with an output voltage higher than the global highest
AC line peak voltage makes it possible to create a LDD with a
universal input, i.e., such a LDD could be plugged into any AC line
worldwide.
• A high-power laser system with a high PF saves significant money
because the customer pays the electrical company for the apparent
power. The apparent power of low PFs is much greater than the power
consumed by the load.
Because a PFC brings so many benefits for offline LDDs, there is no
reason to avoid it. PFC controllers for one-phase PSs are produced by many
companies. Their operational principles and circuit calculation are very well
Figure 8.5 Current in the inductor L1 during one half of the AC line period: (a) in a CCM
PFC converter and (b) in a DCM PFC converter.
Powering Medium-Power LD Systems 65
The circuitry of a DCM PFC is less complicated than the CCM version,
but conduction losses and differential-mode noise generation are larger.
An engineering compromise uses a DCM PFC circuit in PSs with a power less
than 300 W and a CCM PFC in PSs with higher power.
Consider the switching losses in the boost converter operating in CCM,
starting with the diode reverse recovery losses. In CCM, the energy stored in
L1 is not completely released into the load, and the current in L1 and diode D1
continues to flow before Q1 turns on. At this moment, the Q1 drain voltage is
Vout (minus the voltage drop on the forward-biased diode D1). When Q1 turns
on, the anode D1 voltage drops to zero while the cathode stays at the Vout
potential. Because the diode D1 stores the charge in the p-n junction, the
reverse polarity on its electrodes creates a reverse current that flows from the
cathode to the anode until the charge is removed completely (Fig. 8.6).
The faster the speed of the forward current drop is, the larger the peak of
the reverse current Irrpeak and the corresponding reverse recovery energy
losses. If the speed is limited only by the inductance of wires between Q1drain
and D1anode, then the reverse recovery losses are high. An additional inductor
Lsn can be used to reduce these losses (Fig. 8.7). As seen from the pulse shape
of the diode D1 current, this action leads to the reduction of the speed of
forward current drop. When the forward current reaches zero, the only small
charge left resides in the D1 p-n junction. This action of the Lsn dramatically
reduces the reverse recovery losses. The Lsn, with the components D2 and R2
that help discharge the current in the inductor and prepare it for the next
switching cycle, form the current snubber.
It is possible to use a silicon carbide (SiC) diode instead of a silicon
diode. It is a Shottky-type diode that does not have the reverse recovery
problem, and a current snubber does not seem necessary. However, the SiC
diode has a junction capacitance that is significantly larger than a silicon
Figure 8.6 Reverse recovery losses in diode D1 without and with current snubber.
66 Chapter 8
Figure 8.7 CCM PFC circuit with dissipative current and voltage snubbers.
diode that causes a problem similar to the reverse recovery issue. The
current snubber not only reduces the D1 reverse recovery losses but also
helps to reduce the turn-on losses in Q1 and the differential-mode noise
associated with the fast switching of the L1 current into Q1 (refer back to
Fig. 6.6).
Now consider what happens at Q1 turn-off. At the turn-off moment,
the transistor Q1 conducts the full L1 current. The speed of rising of the Q1
drain voltage is limited only by the Q1 drain-source parasitic capacitance Cds.
It leads to high turn-off losses and the generation of big common mode noise.
To reduce these losses and noise used the voltage snubber consisting of the
snubber capacitor Csn, diode D3, and resistor R3. The capacitor Csn charges
through diode D3 in parallel with Cds. The Csn capacitance reduces the speed
of the Q1 drain voltage rise and thereby decreases the turn-off losses in Q1 and
the common mode noise. During the next Q1 turn-on cycle, Csn discharges to
the resistor R3 and prepares Csn for the next turn-off cycle.
The current and voltage snubbers, described earlier, transfer the energy of
the switching losses from the semiconductor devices Q1 and D1 to the resistors
R2 and R3. However, this energy still dissipates in the PFC converter. To
increase the efficiency of the PFC, this energy should be utilized. Lossless
snubbers are described next.
The following equations calculate the power losses during turn-on and
turn-off and the component values of the current and voltage snubbers.
During one cycle of the AC line, the voltage and the pulse width in the
MOSFET Q1 change in a wide range. Thus, the accurate calculation of losses
in dissipative snubbers in a CCM PFC circuit is a difficult task. The
calculation is restricted to the estimate; the peak values of voltages and
currents in the snubbers were obtained by using LTspice simulation (Fig. 8.8).
Powering Medium-Power LD Systems 67
Figure 8.8 Waveforms in the circuit in Fig. 8.7 (from top to bottom): current in D1, Q1 drain-
source current, and Q1 drain-source voltage (V[n008]).
Initial data
AC line RMS voltage: Vline :¼ 120
PFC converter output voltage: Vout :¼ 400
PFC converter output voltage: Iout :¼ 1
PFC converter output power: Pout :¼ Vout · Iout ¼ 400
Converter switching frequency: Fsw :¼ 100 103
Switching period: Tsw :¼ 1/Fsw ¼ 1 10–5
Diode D1 reverse recovery time: Trr :¼ 50 10–9
MOSFET drain-source parasitic capacitance: Cds :¼ 0.1 10–9
PFC inductor: L1 :¼ 500 10–6
From circuit simulation waveforms (Fig. 8.8),
Peak current in D1 at Q1 turn-on: ID1pk :¼ 5
Peak current in Lsn at Q1 turn-on: ILsnpkon :¼ 6.3
Q1 drain-source peak voltage at turn-on: VQ1dspkon :¼ 400
Q1 drain-source peak current at turn-off: IQ1dspkoff :¼ 6.3
Q1 drain-source peak voltage at turn-off: VQ1dspkoff :¼ 600
Let the time of current reduction in the snubber inductor L2 equal 3Trr:
and the discharge time of inductor L2 on the resistor R2 equals 0.1 of the PFC
switching period:
Lsn ðI Lsnpkon Þ2
PR2 :¼ F sw ¼ 23.814:
2
When Q1 is on, a full output current Iout flows through it. When Q1 turns
off, this current charges the MOSFET drain-source capacitance Cds and
snubber capacitor Csn. It reduces Q1 dV/dT per the following formula:
Because the voltage on the MOSFET drain rises from zero to VQ1dspkoff,
dV Q1of f :¼ V Q1dspkof f :
Powering Medium-Power LD Systems 69
I Q1dspkof f · dT Q1of f
C sn :¼ C ds ¼ 6.875 1010 :
V Q1dspkof f
T Csndch :¼ C sn R3 ▪ :
T Csndch :¼ 0.1T sw :
C sn ðV Q1dspkof f Þ2
PR3 :¼ F sw ¼ 12.375:
2
The total power dissipating in the resistors of the current and voltage
snubbers is
Dissipative snubbers help to reduce the noise and losses in the switching
semiconductors by transferring losses in resistors. Lossless snubbers are used
to increase the efficiency of a PFC and other nonresonant PWM converters.
Figure 8.9 depicts a schematic of a CCM PFC with lossless current and
voltage snubbers. The addition of one capacitor C4 (for proper circuit
operation, the C4 value should be much larger than Csn) and one diode D4
helps to forward the energy accumulated in the capacitor Csn and in the
inductor Lsn to the output capacitor C2 and further to the load of the PFC.
References 12 and 13 are recommended for more details regarding lossless
snubber operation.
70 Chapter 8
Figure 8.9 CCM PFC circuit with a lossless current and voltage snubber.
71
72 Chapter 9
have a voltage drop of 1.8–2.0 V. For further power increases, the diode
bars are combined in stacks, i.e., the bars are electrically connected in series.
If 15 bars are connected in series, the total electrical power of the LDD will
be 6000 W.
There are two ways to build such a high-power driver for a LD stack. The
first way uses a single VtoI converter with powerful semiconductor devices, a
large transformer, inductors, and capacitors. The disadvantages of this
approach are as follows:
• Whenever new power requirements arise, a new LDD must be developed.
• High-power, slow semiconductor devices limit the maximum conversion
frequency, which leads to bad dynamic characteristics in the LDD.
• Due to the low conversion frequency, a large output filter is required.
• Moreover, one of the main drawbacks of a single converter is reliability.
A converter failure completely stops LDD system operation.
The only advantage of this approach is its minimal number of parts.
The second way to build a powerful LDD connects many relatively-
low-power, passive VtoI converter modules in parallel. Due to their current
intrinsic limitations, these converters can be connected in parallel directly. The
advantages of this approach are thus:
• Using pre-developed modules significantly decreases the design time of
the new, more-or-less powerful LDD.
• Redundant modules and replaced failed modules guarantee reliable
LDD operation.
• A very high effective-conversion frequency can be achieved by operating
the modules with a time shift; thus, a modular LDD has a very fast
dynamic response.
• A high effective-conversion frequency significantly reduces the require-
ments of the output-current filter.
• Inexpensive semiconductor devices and standard low-cost magnetic
cores can be used to lower the cost of a modular system compared to a
single converter LDD.
Figure 9.3 depicts a block diagram of a modular LDD. A modular LDD
is designed in such a way that N modules can handle the full power, and Nþ1
modules can support uninterruptable LDD operation if one module fails. The
inputs of all of the modules are connected to a DC voltage source Vdc
(rectified AC line) through individual fuses F1 – FNþ1, one of which
disconnects a failed module from the DC source. This topology allows for
“hot” replacement of failed modules.
Because each module has an intrinsic, passive current limit, the outputs of
all of the modules are connected directly in parallel. The current of a LD stack
can reach several hundred amps. A current transducer should be used with the
74 Chapter 9
Figure 9.3 Block diagram of a modular LDD containing Nþ1 passive VtoI converters
powering a single LD stack.
Hall effect when sensing such a large current. It converts the LD stack current
into an isolated voltage signal. In the comparator, this signal is compared
to the reference voltage. The signal from the comparator reaches the con-
troller, which contains the converter (voltage to PWM signal), the generator
of time-shifted signals (Fig. 9.4), and the signal distributor. These signals,
sent through FET drivers, control the MOSFETs of the corresponding
modules.
Figure 9.4 Time-shifted FET driver signals of parallel-connected passive VtoI converters.
Powering High-Power LD Systems 75
One solution to this problem forms the power switch with the parallel
connection of several MOSFETs. This arrangement reduces the on-resistance
of Q5 to an acceptable level. Another solution is illustrated in Fig. 9.5. At the
initial moment T0, all modules are disabled, and the gate drive signal of switch
Figure 9.5 Operational logic of the circuit shown in Fig. 9.2 to obtain high efficiency with a
low-duty-ratio pulsed mode.
76 Chapter 9
Q5 is low. At moment T1, the gate drive signal turns on the switch Q5.
However, because the modules are disabled, current does not flow in Q5. At
moment T2, the converter modules are enabled, and current starts to flow in
Q5. At moment T3, Q5 turns off, and the current switches to the LD stack.
Current flows in the LD stack up at the moment T4 when Q5 turns on again.
At moment T5, a signal disables the converter modules. After that, at moment
T6, the switch Q5 turns off and stays off until the start of the next cycle at
moment T7. Because power switch Q5 conducts current only during short
times (T2–T3 and T4–T5), the system has high efficiency in low-duty-ratio
operation mode. Due to the very fast MOSFET Q5 switching capability, the
circuit provides fast switching of the current in the LD stack.
Figure 9.6 Block diagram of a modular LDD for powering multiple LD strings.
power switches Q3–Q5 in parallel to each LED string (Fig. 9.8). These switches
provide LED light dimming by direct PWM of the LED.
The PWM dimming of LED light has advantages over analog dimming:
it does not create a color shift and has higher efficiency. At a PWM
frequency above several hundred hertz, light flicker is not visible. Due to the
very fast switching of MOSFETs, the duty ratio of the PWM can vary
practically from 0–100%, i.e., the LED light varies from full brightness to
complete darkness due to dimming. The light in each channel is controlled
by a programmable controller that provides dynamic color change. In both
cases, the galvanic isolation of the light-emitting strings from the AC line
through transformers is an important safety feature that also simplifies
control.
78 Chapter 9
Figure 9.9 Block diagram of a powerful, modular DC CVS based on Nþ1 passive
converters with intrinsic current limiting.
81
82 Chapter 10
Figure 10.2 Schematic of a buck converter with the additional circuitry required for LD
driving.
Figure 10.3 Buck converter with lossless voltage and current snubbers.
circuit breaker, which disconnects the buck converter from the CVS, is
necessary in order to prevent failures of the MOSFETs Q1 and Q2.
• When the CVS voltage Vdc is four or more times higher than the
nominal voltage of the LD string Vst, a buck converter becomes
inefficient because of the large pulsed currents in the circuit, which
create significant conduction losses and EMI. When powering a LDD
from the AC line, the rectified voltage Vdc is usually much higher than
Vst and better suited to the topology of the converter with a matching
transformer.
LD Drivers Based on Other Topologies 83
Initial data
DC supply voltage: Vdc :¼ 100
Lf current ILf :¼ 1
Maximum Lf peak-to-peak ripple
current is 5% of the Lf current: dI :¼ 0.05
LD string voltage: Vst :¼ 50
Converter switching frequency: Fsw :¼ 100 103
Converter switching period: Tsw :¼ 1/Fsw ¼ 1 105
To simplify calculations, this example uses PWM with a 50% duty ratio
(DC :¼ 0.5).
Calculation
When FET Q1 turns on, the voltage applied to Lf is
V Lf :¼ V dc –V st ¼ 50:
dT Lf :¼ T sw · DC ¼ 510–6 :
84 Chapter 10
Figure 10.4 Significant buck converter waveforms: (a) voltage in the node A (Fig. 10.1)
and (b) Lf current.
Figure 10.6 A switch-mode VtoV converter and linear current sink operating as a LDD for
powering a LD string. Vnom and Inom are the nominal voltage and current of the LD string,
respectively.
current sink in VtoI mode. The total circuit efficiency could be relatively high.
Figure 10.6 depicts the I-V characteristics of a switch-mode VtoV converter
and a linear current sink acting as a LDD for powering a LD string.
The described compound converter can also be used for LD pulsed
operation. In the pulsed mode, the PWM signal acts as a reference voltage
source (switch Sw1 in the bottom position). The peak voltage of the PWM
signal determines the level of current in the LD string during the Q1 on-time.
When the PWM signal drops to zero, Q1 disconnects the LD string from the
voltage source, and the current in the LD string stops.
The main shortcoming of this compound converter is the lack of an
intrinsic current limit. If the current feedback malfunctions due to noise in the
circuit, the current of the current sink is not restricted, and it can lead to a
catastrophic failure of the LD string.
Chapter 11
Passive Switch-Mode
Voltage-to-Power Converters
in Laser Systems
11.1 Passive VtoP Converter as a LDD
Some applications require a stabilized laser beam power. For this purpose,
many low-power LDs have a photodiode attached to the rear facet. Light
penetrates the rear facet mirror and is converted by the photodiode into a
signal proportional to the laser beam power. This signal is used to stabilize the
laser beam power, but in some LD systems it can be preferable to stabilize the
electrical power of the LD assembly.
Another application where a CPS is beneficial involves charging energy-
storing capacitors in pulsed laser systems. The advantage of a CPS-type
capacitor charger compared to a CCS type is that it provides a constant load
on the primary source of electrical energy during the charging cycle. Unlike
the CPS, a CCS-type capacitor charger increases the power consumption from
the primary source with an increased storage capacitor voltage.
The electrical power in a CPS can be stabilized by an active feedback loop
using the product of the LD current signal and the voltage signal according to
the block diagram depicted in Fig. 5.4(a). However, there is a passive means
(without feedback) of power stabilization. The working principal of this
converter is based on charging a capacitor with a constant frequency up to a
certain voltage and the subsequent discharge into the load.
If a voltage-to-power (VtoP) converter with a constant switching
frequency Fsw is powered by a CVS with output voltage Vdc, and the storage
capacitor value is C, the energy stored in the capacitor is
C · V 2dc
E c :¼ ▪,
2
87
88 Chapter 11
C · V 2dc
Pload :¼ F sw ▪:
2
Initial data
CVS voltage: Vdc :¼ 200
Converter switching frequency: Fsw :¼ 100 103
Converter switching period: Tsw :¼ 1/Fsw ¼ 1 10–5
Nominal LD string (load) voltage: Vload :¼ 50
Nominal LD string current: Iload :¼ Pload / Vload▪
The peak-to-peak load current ripple (the same ripple level in the filter
inductor Lf) is 5% of the nominal load current:
C 1 :¼ 10 10–9 ; C 2 :¼ 10 10–9 :
W 2 ∕W 1 :¼ 1▪ :
Calculation
The waveforms of voltage and current in Fig. 11.2 illustrate converter operation.
At the first moment T0, the voltage on the gate of the MOSFET Q1 is high; Q1 is
on, and the voltage of the node A is zero. Before the moment T1, the MOSFET
Q1 turns off; and at the moment T1, the MOSFET Q2 turns on. Capacitor
C2 discharges to zero, and the voltage on the capacitor C1 reaches Vdc.
During period T1–T2, the capacitors C1, C2 are recharging, and the energy
is delivered through the transformer T1, bridge rectifier D3–D6, and filter
inductor Lf to the load (LD string). This energy is
ðC 1 þ C 2 ÞV 2dc
E :¼ ¼ 4 104 : (11.1)
2
Due to the large Lf inductance and relatively small capacitance of C1 and
C2, the recharge current is constant, and during period T1–T2 the voltage rise
in the node A is linear.
In the moment T2, the voltage at the node A reaches Vdc and stays at this
level until the moment T3. During period T2–T3, energy is not delivered to the
load from the CVS, and the current in the load supported by the energy
accumulates in Lf and decreases.
The recharging process of the capacitors C1, C2 repeats during period
T3–T4 when Q2 turns off and Q1 turns on. Because capacitors recharge two
times during one converter switching cycle, the power delivered to the load is
The last item to calculate is the value of the filter inductor Lf. During time
T3–T2, Lf discharges on the LD string. Because the LD string is a constant
voltage load, the current drops linearly with speed:
dI load V
:¼ dc ▪, (11.3)
T3 T2 Lf
where
T 3 –T 2 :¼ ð1∕4ÞT sw ▪ : (11.4)
T sw · V dc
Lf :¼ ¼ 6.25 103 : (11.5)
4dI load
Passive Switch-Mode Voltage-to-Power Converters in Laser Systems 91
Equations (11.1) and (11.2) show that there are three ways to regulate the
converter output power Pload:
• Change the CVS voltage Vdc. In this case, Pload is proportional to the
square of Vdc.
• Change the switching frequency of the converter Fsw. In this case, Pload
is linearly proportional to Fsw.
• Use the corresponding capacitors C1, C2 for each project.
The dependence of the output power on the load voltage, presented in
Fig. 11.3, deserves further attention. The graphic data was obtained using
LTspice circuit simulation software.
The voltage drops in the MOSFETs, diodes D1, D2, and rectifier bridge
diodes D3–D6 were neglected while calculating the circuit using MathCad, so
the value of the power in the LTspice simulation is 3 W lower than calculated
(80 W). The graph shows that the power is fairly stable in the range of load
voltages from 40–88%. A passive VtoP converter will provide constant power
to LD strings with voltages in this range. Like their VtoI counterparts, passive
VtoP converters can be directly connected in parallel to increase the output
power.
Figure 11.3 Dependence of the VtoP converter output power on the load voltage.
92 Chapter 11
Figure 11.5 Output power and load voltage for one charging cycle in a VtoP capacitor
charger. The graph is based on a LTspice simulation of the circuit in Fig. 11.4 with the
following parameters: Vdc ¼ 200 V, C1 ¼ C2 ¼ 10 nF, Fsw ¼ 100 kHz, Cst ¼ 100 uF, W2/W1 ¼ 1,
and Lf ¼ 1 mH.
Figure 11.7 Output power and load voltage for one charging cycle in a passive VtoI
capacitor charger. The graph is based on a LTspice simulation of the circuit in Fig. 11.6 with
the following parameters: Vdc ¼ 200 V, C1 ¼ C2 ¼ 10 uF, Lb ¼ 155 uH, Cr ¼ 8 nF, Fsw ¼
100 kHz, Cst ¼ 100 uF, W2/W1 ¼ 0.85, and Lf ¼ 10 mH.
voltage does not drop below 30% of the nominal open circuit voltage, so the
next charging cycle starts in a constant power mode and stays in this mode
almost to the end of the charging cycle. This feature provides a constant
power load on the AC mains. As with a capacitor, upon reaching the nominal
battery voltage, the charging process stops, and the VtoP circuit maintains the
nominal voltage on the battery electrodes without additional control circuitry.
Poon, Pong, and Tse15 mentions that this circuit has “the inherent resistive
input characteristic that can be exploited for power factor correction[. . . ]when
the input is connected to AC mains.”
Chapter 12
Powering Other Components
of LD Systems
12.1 Thermoelectric Cooler
LDs need cooling to extend their life and maintain stable laser-beam char-
acteristics during operation. For low-power LDs, passive heatsinks are usually
sufficient. Medium- and high-power LD systems require forced cooling.
High-power lasers use a circulating liquid for cooling; however, liquid cooling
systems are beyond the scope of this book.
For mid-power LDs, thermoelectric coolers (TECs) offer a simple and
reliable solution. They are a kind of semiconductor diode that operates based
on the Peltier effect: the direct current flows through a p-n junction, which
forces one side of the junction to cool down and the other side heat up. The
cold side is used to cool designated objects, while the heat from other side is
removed with the help of heatsink.
The advantages of TE coolers in LD systems over other coolers include
• the absence of moving parts and associated mechanical vibration,
• precise temperature control (within fractions of a degree) by regulating
the TEC current,
• a wide variety of sizes and shapes,
• very long lifetime, and
• no liquid media or chlorofluorocarbons.
Diodes in TECs are mechanically placed in parallel between two ceramic
plates to form cold and hot plates. Electrically, the diodes are connected in
series, forming a diode string. Like a LD string, the TEC needs to be powered
by a PS with the characteristic of the current source, which is why the same
type of VtoI converter (Fig. 7.1) for powering TECs can be used. Temperature
control can be achieved by either an average current regulation (in this case, a
PWM of the inverter’s MOSFETs Q1 and Q2) or direct TEC current PWM by
using a switch Q3 parallel to the diode string. Temperature sensing should
involve a corresponding thermal sensor.
95
96 Chapter 12
D. Major developed the most accurate formulas for calculating the main
HV multiplier parameters, i.e., the regulation and the ripple of the output
voltage.17 The formula for regulation expresses the dependence of the
multiplier output voltage Vout on the multiplier parameters:
3
I out 2n n2 n
V out :¼ 2 ⋅ n ⋅ V secpk þ þ ▪, (12.1)
F sw C ac 3 2 3
where Vsecpk is the secondary peak voltage, Iout is the voltage multiplier output
current, Fsw is the converter switching frequency, Cac is the capacitance of AC
capacitors (all AC capacitors are equal), and n is the number of stages in the
voltage multiplier.
The first part on the right side of the equation is a multiplier output
voltage at no load condition (Iout ¼ 0). The second part is the regulation of the
multiplier output voltage (output voltage reduction due to load current Iout).
The regulation voltage increases linearly with the load current increase.
A second formula expresses the dependence of output peak-to-peak
voltage ripple Voutrip from multiplier parameters. The output voltage ripple is
also proportional to the output current:
I out nþ1
V outrip :¼ ·n ▪, (12.2)
F sw C dc 2
To simplify the design procedure, it is better to start with the values of the
DC capacitors Cdc equaling the AC capacitors Cac. If the output voltage
ripple exceeds the PS specification requirements, there are two alternatives to
reduce the ripple: either use larger DC capacitors or add a RC or LC filter.
Figure 12.2 shows a schematic with an output LC filter.
The specifics and practical limits of HV design are as follows:
• A HV between components and wires with different voltage potentials
causes a breakdown and a corona discharge, which destroy the HV PS.
• Adequate spacing is necessary between components and wires. The
spacing in the air (clearance distance) and along the surface (creepage
distance) should not exceed 3 kV/cm. This arrangement avoids the need
for an encapsulant or oil for isolation.
• Because the secondary winding of the HV transformer contains a vast
number of turns, its parasitic capacitance is significant. It acts in parallel
with the resonant capacitor Cr and can limit the maximum switching
frequency of the converter.
• The ability to use a transformer with a large LI simplifies the insulation
between the primary and secondary windings because they can be
placed on the opposite legs of a UU-core (Fig. 6.12).
• A high voltage across the secondary winding requires a safe creepage
distance between the first and the last layers. To ensure a safe distance
without an encapsulant, a universal-type winding is used for the
secondary. The rule states that the voltage across the secondary should
not exceed a 3-kV peak.
The following information can be used to calculate a HV converter for
powering a Pockels cell. Common HV PSs for Pockels cells have a voltage up
to 5 kV and a power up to 100 W, which will be applied to this example.
Initial data
Nominal output power: Pnom :¼ 100
Nominal output voltage: Vnom :¼ 5000
Nominal output current: Inom :¼ Pnom/Vnom ¼ 0.02
Switching frequency: Fsw :¼ 100 103
The output voltage regulation is 10% ofVnom: Vreg :¼ 0.1Vnom ¼ 500.
The output peak-to-peak voltage ripple is 1%
of Vnom: Vrip :¼ 0.01Vnom ¼ 50.
Calculation
Because the maximum secondary winding voltage should not exceed a 3000-V
peak, a one-stage voltage multiplier n ¼ 1 should be used to obtain 5000 V of
output voltage. The formula for the multiplier regulation voltage17 is
Powering Other Components of LD Systems 99
3
I nom 2n n2 n
V reg :¼ þ þ ▪:
F sw · C ac 3 2 3
To get a 5000-V nominal voltage for the multiplier output at the nominal
load, the peak voltage of the transformer secondary winding should be at least
V nom þ V reg
V sec :¼ ¼ 2750:
2n
C dc :¼ C ac ¼ 6 10–10 ,
I nom nþ1
V ripcalc :¼ ·n ¼ 333:
F sw · C dc 2
Because the calculated voltage ripple Vripcalc exceeds the spec ripple Vrip
by more than seven times, use DC capacitors that are ten times larger
(Cdc10 ¼ 10Cdc) and calculate ripple again:
I nom nþ1
V ripcalc :¼ ·n ¼ 33:
F sw · 10C dc 2
This voltage ripple meets the specified requirement.
Now we plot the load curve (IVC) of the multiplier using the MathCad
graph plotting tool. In the range of output current from 0–0.2 A, the output
current is stepped-up with the 0.01-A interval
I out :¼ 0,0.02,: : : ,0:2,
and according to Eq. (12.1),
3
I out 2n n2 n
V out ðI out Þ :¼ 2n · V secpk þ þ : (12.3)
F sw · C ac 3 2 3
Figure 12.3 depicts an IVC graph. As seen from the chart, by using a
voltage feedback loop with PWM of the inverter it is possible to obtain a
stable output voltage of 5000 V with an output current up to 40 mA. At the
nominal 20 mA current, the stable output voltage Vnom has a sufficient margin
to stay in regulation.
Appendix
LTspice Circuit-Simulation
Examples
101
102 Appendix
Figure A.1 VtoV converter circuit simulation. Waveforms from top to bottom: MOSFET Q1
and Q2 gate drive signals, Q1 drain voltage, Q1 drain current, current in inductor Lb, and
output voltage ripple. The waveforms are zoomed from 4.978 ms to 5.000 ms.
LTspice Circuit-Simulation Examples 103
Figure A.2 VtoV converter circuit simulation. Waveforms from top to bottom: Q1 drain
voltage, Q1 drain current, current in inductor Lb, and D1 current ripple. The waveforms are
zoomed from 4.978 ms to 5 ms.
104 Appendix
Figure A.4 VtoP converter circuit simulation. Waveforms from top to bottom: Q1 drain
voltage, node n009 voltage, and current in inductor Ls. The waveforms are zoomed from
4.978 ms to 5 ms.
LTspice Circuit-Simulation Examples 107
109
Index
A E
alternating current (AC), 23 electrical characteristics, 8
electromagnetic interference (EMI)
B filter, 37
ballasting capacitor, 35 electromagnetic interference (EMI)
ballasting inductor, 33 noise, 46
battery, 24 elevated temperature, 19
buck converter, 81, 82
bus voltage, 12, 43 F
Faraday shield, 53
C feedback loop, 25, 26, 100
circuit calculation, 10, 39 filter inductor, 59
compliance, 12 flyback converter, 52, 53
computer simulation, 10
conduction losses, 45 G
constant current load, 18 generator of time-shifted signals, 74
constant current source (CCS), 20
constant power source (CPS), 20 H
constant voltage load, 17 half-bridge (HB) inverter, 38
constant voltage source (CVS), 20
continuous conduction mode I
(CCM), 64 inverter, 70, 71
cross-conduction, 50
current ripple, 21 L
current–voltage characteristic laser diode (LD), 8
(IVC), 8 stack assembly, 19
string, 44, 57
D laser diode driver (LDD), 1
differential impedance, 19 design priorities, 12, 13
diode bar, 19, 72 modular, 73
direct current (DC), 23 leakage inductance (LI), 52
discontinuous conduction mode light-emitting diode (LED), 1, 15
(DCM), 64 LTspice, 4, 101
111
112 Index
M S
magnetic ballast, 25 Shottky-type diode, 65
MathCad, 2, 10 silicon carbide (SiC) diode, 65
modular DC voltage source, 79 snubber, 47, 48, 51, 66, 67
capacitor, 49
O dissipative, 69
open-circuit voltage, 24 lossless, 9, 69
specifications, 7
P switch-mode converter, 96
p-n junction, 65, 95 switching losses, 45–47, 65
parasitic elements, 51, 52
Peltier effect, 95 T
Pockels cell, 96, 98 thermoelectric cooler (TEC), 95
power factor correction (PFC) topology, 9, 51
circuit, 63–66 switch-mode convention, 9
power supply (PS), 23 total harmonic distortion
prototype, 11 (THD), 71
pulse width modulation
(PWM), 37 V
voltage-to-current (VtoI)
Q conversion, 29, 30, 34
quasi-resonant converter, 37 voltage-to-power (VtoP)
converter, 87
R voltage-to-voltage (VtoV)
reliability, 13 converter, 35
resistance, 9
resistive load, 17 Z
resonant tank, 41 zero-current switching (ZCS), 48
reverse recovery losses, 64, 65 zero-voltage switching (ZVS), 48
Grigoriy Trestman has over 40 years of experience in
developing switch-mode power supplies for gas discharge
lasers, electronic ballasts for fluorescent lamps, drivers for
laser diodes, and LEDs. He holds a Masters in Physics and a
Ph.D. in Photochemistry.
Trestman worked as a Senior Research Scientist in the
Department of Research and Development of Tajik State
University (USSR) for 20 years. After immigrating to the
United States, he worked as a Power-Electronics Design Engineer for several
U.S. companies (Glassman High Voltage Inc., Converter Power Inc., Philips
Color Kinetics Inc.) for another 20 years. For the past 13 years, he worked as
a Staff Engineer for Osram Sylvania Inc. He is currently a power-electronics
consultant.
Trestman is a co-author and instructor of several professional development
courses: “Powering and Integration of Laser Diode Systems;” “Electronic
Ballast Design;” “Electrical Ballasts for AC, DC, and Pulsed Loads;” and
“Powering Lasers and Laser Systems.” He holds eight U.S. patents and
14 patents in the former U.S.S.R. for various aspects of power conversion,
electrical supply of CW, and pulse devices.