Antenna Effects:

Modern wafer processing uses ‘Plasma etch’ (or ‘dry etch’).

Plasma is an ionized/reactive gas used to etch. It allows super
control of pattern (shaper edges / less undercut) and also allows
several chemical reactions that are not possible in traditional (wet)
etch. Apart from this, several unwanted things happen just because
of several plasma processing steps. One of them is the charging
damage.

Plasma charging damage refers to the unintended high-field

stressing of the gate-oxide in MOSFET during plasma processing.
The stress voltage that develops across the gate and substrate of a
MOSFET during plasma processing basically comes from three
sources.

• Non uniform distribution of plasma potential across

the wafer.
• Charging filtering (shading) due to microscopic
topography on the wafer.
• AC effects due to the nature of RF discharge that
sustain the plasma.

The stress voltages due to AC effects are quite small in most cases
and cannot cause damage by themselves. They do, however, add to
the magnitude of stress voltages developed by either non-uniform
plasma potential or topographic filtering of charge or the sum of
both.

The available charges are the net charges collected from the
plasma by the exposed conductor with connection to the gate or
substrate. Both electrons and positive ions from the plasma are
impinging on the exposed conductor during processing. Depending
on the charge balance condition, the electron flux might not equal
the ion flux, a net positive or negative charge collection rate exists.
The collected net charges are channeled to the gate as shown in fig.
1 where it is neutralized by the current tunneling across the gate-
oxide.

Clearly, the size of the conductor exposed to the plasma plays a

role in determining the magnitude of the net charge collection rate
and therefore the tunneling current. This is the so called “antenna
effect”. The area ratio of the conductor to the oxide under the gate
is the antenna ratio. The antenna ratio, in a rough sense, is a current
multiplier that amplifies the tunneling current density across the
gate-oxide. For a given antenna ratio, a larger tunneling current is
supported when the plasma density is higher. Higher tunneling
current means higher damage.

This antenna effect can be understood in a different way also. It

occurs during the manufacturing process and renders a die useless.
During metallization (when metal wires are laid across devices),
some wires connected to the polysilicon gates of transistors can be
left floating (unconnected) until the upper metal layers are
deposited. A long floating interconnect (without proper shielding
layer of oxide) can act as a temporary capacitor, collecting charges
during fabrication steps, such as plasma etching. If the energy built
up on the floating node is suddenly discharged, the logic gate
might suffer permanent damage due to transistor gate oxide
breakdown.
In other word the 'antenna' is an inter-connect, i.e., a
conductor like polysilicon or metal, that is not electrically
connected to silicon, i.e., not 'grounded', during the
processing steps of the wafer. The connection to silicon
would normally provide an electrical path to bleed-off any
accumulated charges. If the connection to silicon does not
exist, charges and may build up on the inter-connect to the
point at which rapid discharge does take place and
permanent physical damage results, e.g., to MOSFET gate
oxides. This destructive phenomenon is known as the
'antenna effect'.

Simplification:

• Charge builds up (DC) on the metal wires (antenna)

during the application of the plasma etch
• Because the gate of a MOSFET is like a capacitor
• If the potential on the gate reaches a certain value it
will ‘break down’
• ‘Punch through’ occurs
• The gate is damaged irreparably

The 'antenna ratio' of an inter-connect is used to predict if the

antenna effect will occur. 'Antenna ratio' is defined as the ratio
between the physical area of the conductors making up the antenna
to the total gate oxide area to which the antenna is electrically
connected. A higher ratio implies a greater propensity to fail due to
the antenna effect. This can result either from a relatively larger
area to collect charge or a reduced gate oxide area on which the
charge is concentrated.
Charge Build up is affected by:

• Diffusion path
o There is an NP diode to substrate at the
drain/source of any output pin
o During plasma-etch this diode is reverse biased
and at high temp
o This causes the diode to behave like a resistor
• Gate Area
o Larger gate_area == larger gate ‘capacitor’
o At fixed ‘charge’, voltage potential reduces as
cap size increases
o Reducing the voltage prevents ‘punch through’
• Diffusion Area
o Bigger diffusion == Smaller resistor
o Smaller R allows more current to pass
• Wire length
o Longer wires act as antennas to ‘pick up’ more
charge

The conditions that lead to antenna formation depend on the

technology used to fabricate the chip and must be determined
empirically for each process. Once they have been identified, they
can be used to define a set of antenna rules, similar to conventional
DRC rules, that can be coded. Factors these rules need to consider
is whether the antenna should be based on the "top" area of the
metal or on its "sidewall" area.

• In an aluminum-based process, charge accumulation

occurs during the ETCH step. The top of the metal is
protected by a resist during this step, so the antenna
rules for this process should be based on the metal
sidewall area.
• In copper-base technologies, charge accumulation
occurs during CMP (Chemical-Mechanical Polishing). In
this process, the sides of the metal are protected, so
the antenna rules need to be based on the metal's top
surface area.

A number of techniques can be utilized to minimize the antenna

effect. For example, the occurrences of antennas can be predicted
and their ratios calculated using design verification and layout
software known as 'design rule check' ('DRC') programs. Then by
adjusting the physical layout of the inter-connects, the antenna
ratios can be reduced to an acceptable level. In addition, processing
steps utilizing plasma can be optimized to reduce the build-up of
charges on any antennas that do exist on devices.

To avoid antenna problems, you must design all net topologies so

that no gate is vulnerable to a large amount of floating charge.
Antenna rules are commonly expressed as a ratio of wire area over
gate area (Aw/Ag) for each metal and cut (via) layer. This ratio
indirectly states how much floating charge a transistor gate can
handle by specifying how much wire can be connected to the input
of the logic gate before antenna problems occur.

Design Solution to reduce Antenna Effects:

• Router options
o Break signal wires and route to upper metal
layers by jumper insertion
 o All metal being etched is not connected to a gate
until the last metal layer is etched.
• Dummy transistors
o Addition of extra gates will reduce the
capacitance ratio.
o PFETs more susceptible than NFETs
o Problem of reverse Antenna Effects.
• Embedded Protection Diode
o Connect reverse biased diodes to the gate of
transistor (during normal circuit operation, the
diode does not affect functionality).
• Diode insertion after placement and route
o Connect diodes only to those layers with antenna
violations.
o One diode can be used to protect all input ports
that are connected to the same output ports.

Most important methods are jumper insertion and diode insertion

to remove antenna violation. We are discussing these two methods
here in detail.
Jumper techniques are the most effective method of avoiding
antenna-effect problems. Diode insertion can repair the remaining
antenna problems. However, it is costly in terms of cell area size
and it complicates the netlist verification process.

Jumper Insertion:

A jumper is a forced layer change from one metal layer to another,

and then back to the same layer. Jumper insertion breaks up a long
wire so that the wire connected to the gate input is shorter and less
capable of collecting charge, as shown in Figure. The advantage of
jumper insertion is that it is fully controlled by the routing tool.
The disadvantage is that it can potentially contribute to routing
congestion problems in upper metal layers. There are also
situations for which there are no valid jumper solutions.

Figure : Jumper Insertion Breaks Up a Long Wire

In most of the tools, jumper insertion is performed automatically

during the routing. After detailed routing, you can fix antenna
violations manually by inserting jumpers by using commands
corresponding to the tool you are using. When you execute those
commands, tool detects and fixes antenna violations using jumpers
and a tailored ripup and reroute strategy.

The Importance of Jumper Location in Repairing Antenna

Violations
Figure shows two nets with the same separation between the input
and output pins, but slightly different jumper locations. The first
one has an antenna violation, and the second one does not.

Figure: Impact of Jumper Location

The difference is that the first net has a long metal1 connection to
the input pin. The wire area as detected by the input pin of the first
net is significant, and, therefore, the antenna ratio is exceeded.

This example shows that antenna violations can be avoided

through the use of jumpers (also known as “bridges”). A jumper
directs the net to a higher metal layer before descending again. In
the process of metallization, the pin is connected to a small amount
of wire area, except on the highest layer, avoiding any antenna
problem below that layer.

Unfortunately, the use of jumpers might only defer the antenna

problem to the highest metal layer of the jumper, where antenna
violations might still occur because all geometries of the net are
physically connected to each other. For this reason, it is important
that the output pin have some ability to solve antenna violations.

Diode Insertion
Figure : Diode Inserted Near a Logic Gate Input
Pin

As shown in Figure, diode insertion near a logic gate input pin on a

net provides a discharge path to the substrate so that built-up
charges cannot damage the transistor gate.

Unfortunately, diode insertion increases cell area and slows timing

due to the increase of logic gate input load. Moreover, diode
insertion is not feasible in regions with very high placement
utilization.

In most of the tools, diode insertion is performed automatically

when you use the routing command. You can manually insert
diodes using the corresponding tool’s commands. There are two
points in the design flow where you can insert diodes to fix
antenna violations.

• Inserting Diodes Before Detailed Placement

Normally, the diode is added only to the pins that need it. The
antenna checker is called for each pin in question to decide first, if
the pin has antenna violations and second, if a jumper has failed in
the area of the pin because the area is blocked and a large enough
hole does not exist.

• Inserting Diodes After Detailed Placement

After detailed routing, the antenna violations can still exist for
various reasons. For example, there can be too much congestion to
insert a jumper or the diffusion strengths of the output pins are too
weak. In these cases, diode insertion is a viable choice.

The semiconductor manufacturer generally provides the gate area

or size, and the antenna checker calculates the appropriate wire
area using the wire (charge) accumulation method specified by the
manufacturer.

Design Rules for Some Current Technologies –TSMC 0.18um

• Metal antenna ratio is not cumulative.

• Maximum drawn ratio of field poly perimeter area to
the active poly gate area connected directly to it 200.
• When the protection diode is not used, the maximum
ratio of each metal (for M1 to M5) perimeter area to
the active Poly gate area 400.

• Antenna Ratio = 2[(L+W1)*t]/W2*l

L: floating metal length connected to gate

W1: floating metal width connected to gate
t: metal thickness
W2: connected transistor channel width
l: connected transistor channel length

Design Rules for Some Current Technologies –IBM 0.13um

• Antenna ratio is non-cumulative.

• Poly antennae larger than 100 are NOT ALLOWED
• Floating gate devices with metal antennae larger than
150 are NOT ALLOWED
• Every N-well is required to be tied down by a N+ diode

Antenna Rules:
In most cases, antenna rules are in the form of:

(antenna-area) / (gate-area) < (max-antenna-ratio)

• Gate-area
o Boolean AND of the ‘poly’ and the ‘diffusion’
layers
o Recognized as gate area of the transistors by
essentially all foundries
• Antenna-area
o Amount of metal area attached to the input pin
o Calculation method varies for different processes
• Max-antenna-ratio
o Represents max allowed ratio of antenna area to
gate area
o Calculation method varies for different processes

• There are 2 ways to calculate antenna area:

o Side-Wall Area = (W + L) * 2 * Thickness
o Polygon Area = W * L

Calibre antenna rules

M6_DIO = NET AREA SD >= 0.16

A.R.4_A.R.6.M6

{ @ (M6 area / gate area + ACCUMULATE ) > (600 in OD2,

5500 not in OD2) (without effective diode)

@ (M6 area / gate area)+ ACCUMULATE > Ratio (with effective

diode)

NET AREA RATIO M6 M6_DIO HV_GATE GATE > 0

ACCUMULATE ACC_M5

[
!!AREA(M6) * !!AREA(GATE) *

(!AREA(M6_DIO)*(!!
AREA(HV_GATE)*(AREA(M6)/AREA(GATE)-600) +

!AREA(HV_GATE)*(AREA(M6)/AREA(GATE)-5500)) +

!!AREA(M6_DIO)*(AREA(M6)/AREA(GATE)-
AREA(M6_DIO)*456-43000))

- (!AREA(M6)+!AREA(GATE)) * LargeNumber

ACC_M6 = NET AREA RATIO M6 GATE >= 0

ACCUMULATE ACC_M5

Magma antenna rules:

rule antenna ratio metal_rule $l -area_type area

-accumulation_type path \

-ratios {{{{0 600 0} {0.16e-12 43072.96 456e12}} {METAL6}}

Synopsys antenna rules:

define_antenna_rule -mode \

-diode_mode \

-metal_ratio \

-cut_ratio

define_antenna_layer_rule -mode \

-layer \
-ratio \

-diode_ratio <{v0 v1 v2 v3 [v4]}>

Summary:

During the IC manufacturing process, the metal layer is exposed to

conditions that lead to the build-up of an electrostatic charge. The
amount of charge that builds up depends on a number of factors;
the most important from an antenna standpoint is how much metal
is exposed. As more metal is exposed, the maximum charge that
accumulates on the net that the metal is part of also increases. The
substrate remains at ground since it is connected to the fabrication
device. As a result a voltage gradient develops across the gate
oxide. When this gradient becomes large enough, it is relieved via
an explosive discharge (i.e. "lightning"). The problem is more
significant at smaller technologies because the damage resulting
from the discharge is more likely to extend across the entire length
of the gate.

Antenna rule checking is different for every process technology

because the method for expressing antenna ratio is not
standardized.

Antenna repair is accomplished by inserting a reverse-bias diode

on the violating net as close to the gates being protected as
practical. During normal chip operation, the reverse bias prevents
electrons from flowing from the net through the diode and into the
chip's substrate. During fabrication, however, the charge on the net
can build to the point where the voltage drop across the diode
exceeds its break-down voltage. This voltage is greater than the
normal operating voltage, but less than the voltage at which an
electrostatic discharge at the gate can be expected. When this
happens, the diode allows electrons to flow from the net to the
substrate and thus limits how much charge can accumulate on the
net. The process is non-destructive, and it's possible that the net
could discharge through the diode several times during the
fabrication process.

The other way to repair is to "break up" the antenna by shifting

briefly to a different metal. When this metal layer is fabricated, the
long piece on one side is no longer electrically connected to the
gate and does not contribute to any antenna effects. When it is
eventually connected through the higher-level metal "bridge," it is
no longer exposed to the charge accumulation and again does not
contribute to an antenna violation.

Causes of antenna defects:

• Electrostatic charge collection on wires while the

metallization is being deposited. (This is usually
referred as ‘charge-collecting antenna problem’ or
simply antenna problem)

Most important ways to repair the antenna violation:

• Using jumpers to break up long wires connected to

gates (Jumpers are a short metal segment inserted
onto a long route of another metal layer).
• Using diodes to provide a discharge path to the
substrate by contact to a diffusion area.
 Antenna effect

The "antenna effect" is a common name for the effects of charge

accumulation in isolated nodes of an integrated circuit during its
processing. This effect is also sometimes called "Plasma Induced
Damage", "Process Induced Damage" (PID) or "charging effect".
In those cases that the discharging of the isolated nodes is done
through the thin gate oxide of the transistor, it might cause damage
to the transistors and degrade their performance.

This article will describe the degradation effects, the process steps
that might cause it, the existing design rules that should limit these
effects, their limitations and propose improvement solution for
these design rules.

PID degradation effects

If charge accumulates on an electrically isolated node of an IC

during processing, it can cause any number of problems, ranging
from easily-detected outright failure to more subtle and less
detectable problems. The PID may cause "hard" failure if the
energy of the accumulated charge is dissipated on a single spot of
the gate oxide. This will cause permanent failure of the transistor..
This is the extreme case, but most times the damage will appear
not as a hard failure, but as degraded performance. This
degradation can be due to any of the following effects:

 Increase of gate oxide leakage current.

 Increase of the threshold voltage of the transistors, and its
variance.
 Degradation of the gate oxide life time.
 Degradation of the transconductance of transistors.
 Increase of the noise generated by the devices.
 Increase of hot-electron effects.

While none of these effects would be welcome in digital circuits,

the major impact of PID is on the analog circuits that might suffer
from additional mis-match between devices, increase of intrinsic
noise, and lower amplification and bandwidth. In these cases the
effects of PID will appear not as a minor variation but as a failure
to meet specifications.

The causes of PID

There are several process steps during which charge can

accumulate on isolated nodes. Reasonably, these steps all involve
flooding the surface of the wafer with ions in one way or another.
The step which dominates the process in terms of potential damage
is the etching of metal and polysilicon, and especially the etch
process used with aluminum metallization. This is the step we will
study in more detail in the rest of the article. But it should be noted
that damage can also occur during photoresist ashing by plasma
after metal or polysilicon etch, during ion implantation while
forming the MOS devices, and during plasma-enhanced deposition
of dielectric on top of the conductors.

Prior to the etch process, the whole wafer is covered by a

conductive layer of metal that is shorting all the devices, and hence
no charge can accumulate in any one node. That is also the case
during the process of etching by ionized particles (Figure 1a), until
the etching has proceeded far enough into the metal so that patterns
have become isolated, enabling the accumulation of charge on each
node separately (Figure 1b). At this stage in the etching process,
the wide spaces are disconnected, while the narrow spaces are not
yet completely etched away. At this stage, named the "latent
stage", the residual metal at the bottom of the narrow spaces
absorbs the majority of the ion current, and consequently the
charge accumulation rate is high.
 Figure 1: Metal etching steps --
intermediate stage (a); 'latent stage' (b);
over-etching stage (c).

As the etch progresses, the etching of the narrow spaces is

completed. Now charge is accumulated at the sidewalls of the
metal patterns (Figure 1c). At this stage the charge accumulation
rate is much lower than during the latent stage. Figure 2 illustrates
the rate of charge accumulation versus time for a simplified etch
process.
 Figure 2: Charge accumulation rate during
the metal etch process.

Actually, the etching process is more complicated, and includes the

flooding of the surface of the wafer by electrons during the etch
process. The electron flooding should neutralize the positively-
charged ions used in the etching, and hence reduce the total
accumulation of charges. However, during the latent stage, there is
a "shadowing" effect in the narrow spaces that reduces the
effectiveness of the electron flooding. Hence there is still charge
accumulation in these narrow spaces.

Design rules related to PID

In order to prevent this residual accumulation from damaging

circuits, IC manufacturers have defined several types of design
rules. The most common rule is called "antenna ratio". This rule
applies to any metal pattern connected to a gate of a transistor. It
defines a limit for the ratio between the area (or the peripheral
length) of the metal and the area of the gate oxide of the gate to
which the metal is attached. If there is a diode connected to that
node, the restrictions on antenna ratio are relaxed. This rule tends
to limit the amount of charge that might stress the victim gate
oxide. Most of the EDA tools that are currently used to check
topological design rules can check antenna ratio rules as well.
There has been considerable question, however, about the
effectiveness of these rules. Several leading manufacturers have
performed and published experiments on PID, measured on
structures similar to those described in Figure 3. The most
remarkable of these experiments has been published by Srikanth
Krishnan et al. from Texas Instruments.

Figure 3: Three topologies used for monitoring

PID that presented similar sensitivities.

Pattern 3a has the shape of a comb with narrow spaces between its
fingers--generating a large area and peripheral length for antenna
effects. It is connected to a small gate structure of an MOS
transistor. In pattern 3b the fingers of the comb are separated,
causing the "antenna ratio" to be much smaller. In pattern 3c the
comb structure is separated completely from the victim transistor
with narrow metal gaps with minimum space. Again, the
calculated antenna ratio would be very small, as hardly anything is
directly connected to the gate.

But actual measurements showed very little difference in PID

between these structures, although there is difference of orders of
magnitude in the "antenna ratio" between the structures.

The reason for this phenomenon is probably related to the

"shadowing" effect during the "latent stage" of the metal etches.
During the later stages of the etch, the narrow spaces between the
metal islands in patterns 3b and 3c act like fuses. That is, they
remain conducting bridges that accumulate charge, and they are
disconnected only at the end of the latent stage, after the majority
of the charge has already been accumulated.

Hence even though these metal structures are, by the end of the
etch process, isolated from each other and from the gate, it is
incorrect to treat them as isolated during antenna rule analysis. The
experiments demonstrate that the existing design rules do not
consider those cases where a cluster of adjacent patterns are
separated from the other patterns by wide spaces.

Implications for design

Figure 4 presents a common pattern that can be generated by any

automatic routing S/W, where metal conductors are randomly
placed in the same routing direction. The gray lines are the metal
patterns, and the green lines are the narrow spaces that are
shadowed during the latent stage of the metal etch. Such clusters of
shadowed areas can be selected by a dedicated set of DRC (Design
Rule Checking) commands. The effective area of such structures
for antenna analysis is the sum of all the shadowed areas for each
cluster, and the effective gate area is the sum of all the gates
connected to that cluster. If there are diodes connected to any of
these clusters, they should be considered as well. The new "latent
antenna ratio", is the ratio between the shadowed spaces and the
sum of gate areas for each cluster. This ratio represents the real
situation better than the common antenna ratio.
 Figure 4: Description of clusters of shadowed
spaces that should be used for calculating
the 'latent antenna ratio'.

Is it really important to include this level of estimation in antenna

effect rule checking? Unfortunately, not just experiments such as
the one cited here, but also actual design experience indicate that it
is. Antenna effect has already caused several failures in
development of new products, including designs by some of the
leading IC vendors. Some of these failures affected products that
passed all the checks of the existing design rules. Indeed the
probability of failure due to latent effects is low, but the bigger the
die the higher the risk. Beside, why should we take a risk that can
be avoided?

In fact there is reason to believe that as we move to denser and

higher-frequency circuits, the problem will get worse. One of the
specific implementations that might aggravate the latent effect is
the addition of shielding traces parallel to noise-sensitive signals.
Such topology may reduce the noise, but it creates exactly the sorts
of structures that are vulnerable to this latent-stage effect. Hence,
using shielding traces without augmenting the design rules might
enhance the PID effects, leading for instance to an increase in
offset voltage of amplifiers on the very signals that the designer set
out to protect in the first place.

Summary

The PID is one of the process factors that can degrade the
performance, reliability and yield of ICs. There are several
topological design rules that tend to limit these effects. However,
the existing design rules does not address one of the key issues,
and thus do not provide complete elimination of PID. The key
issue is the shadowing effects during the latent stage of the metal
etch. Additional design rules, such as proposed here, are necessary
to eliminate this effect completely.