1

STANDARD SEQUENTIAL MODULES

• REGISTERS

• SHIFT REGISTERS

• SYNCHRONOUS COUNTERS

• FOR EACH MODULE WE SHOW:

• SPECIFICATION
• IMPLEMENTATION WITH FFs AND GATES
• BASIC USES
• HOW TO IMPLEMENT LARGER MODULES

Introduction to Digital Systems 11 – Standard Sequential Modules

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REGISTERS

Data input x

Control inputs n
LD (Load)
CLK REGISTER
CLR (Clear)
n

Data output z
Figure 11.1: n-BIT REGISTER MODULE

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REGISTER: HIGH-LEVEL SPECIFICATION

INPUTS: x = (xn−1, . . . , x0), xi ∈ {0, 1}

LD, CLR ∈ {0, 1}
OUTPUTS: z = (zn−1, . . . , z0), zi ∈ {0, 1}
STATE: s = (sn−1, . . . , s0), si ∈ {0, 1}

FUNCTION: STATE TRANSITION AND OUTPUT FUNCTIONS








x(t) if LD(t) = 1 and CLR(t) = 0
s(t + 1) =  s(t) if LD(t) = 0 and CLR(t) = 0


 (0 . . . 0) if CLR(t) = 1




z(t) = s(t)

Introduction to Digital Systems 11 – Standard Sequential Modules

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IMPLEMENTATION OF 4-BIT REGISTER

x3 x2 x1 x0

1 0 1 0 1 0 1 0
MUX MUX MUX MUX
LD
CLK
CLR
D D D D
Q’ Q Q’ Q Q’ Q Q’ Q

z3 z2 z1 z0
Figure 11.2: IMPLEMENTATION OF 4-BIT REGISTER.

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TIME-BEHAVIOR OF REGISTER

Clock CLK

tsu setup time

Load LD

Input x

Output z

tp propagation delay

Figure 11.3: TIME-BEHAVIOR OF REGISTER.

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USES OF REGISTERS: Example 11.1

INPUT: x ∈ {0, 1}
OUTPUT: (z1, z0), zi ∈ {0, 1}
STATE: (s1, s0), si ∈ {0, 1}
INITIAL STATE: (s1, s0) = (0, 0)

FUNCTION: STATE TRANSITION AND OUTPUT FUNCTIONS:

PS Input
x=0 x=1
00 00 01
01 01 11
11 11 10
10 10 00
NS

z(t) = s(t)

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CANONICAL IMPLEMENTATION

Y 1 = y 1 x0 y 0 x Y0 = y0x0 y10 x

x x’ y 1 y’1

y1
x’
D flip-flops
y0 Y1
x y1
Y0
y0
y0
x’
y’1 CLK
x
(a)
Figure 11.4: NETWORKS FOR Example 11.1: a) NETWORK WITH STATE CELLS;

Introduction to Digital Systems 11 – Standard Sequential Modules

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IMPLEMENTATION WITH REGISTER

Y1 = y 0 Y0 = y10 LD = x

Y1 LD
y1

Y0 Register y0
CLR
CLK

(b) 0
Figure 11.4: NETWORKS for Example 11.1: b) NETWORK WITH STANDARD REGISTER MODULE

Introduction to Digital Systems 11 – Standard Sequential Modules

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SHIFT REGISTERS

Parallel data input x

Serial data input Serial data input

n
(right shift) (left shift)
xr xl
CLK SHIFT REGISTER
CTRL
2
n

Parallel data output z

Figure 11.5: SHIFT REGISTER

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PARALLEL-IN/PARALLEL-OUT BIDIRECTIONAL SHIFT REGISTER

x n-1 x n-2 x0

xr xl
CLK n-1 n-2 0

CTRL
2
z n-1 z n-2 z0
Figure 11.6: PARALLEL-IN/PARALLEL-OUT BIDIRECTIONAL SHIFT REGISTER

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HIGH-LEVEL SPECIFICATION

INPUTS: x = (xn−1, . . . , x0), xi ∈ {0, 1}

xl , xr ∈ {0, 1}
CT RL ∈ {LOAD, LEF T, RIGHT, N ON E}
STATE: s = (sn−1, . . . , so), si ∈ {0, 1}
OUTPUT: z = (zn−1, . . . , z0), zi ∈ {0, 1}

FUNCTIONS: STATE TRANSITION AND OUTPUT FUNCTIONS:








s(t) if CT RL = N ON E
x(t) if CT RL = LOAD




s(t + 1) = 






(sn−2, . . . , s0, xl ) if CT RL = LEF T
 (x , s
r n−1 , . . . , s1 ) if CT RL = RIGHT




z=s

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SHIFT REGISTER CONTROL

Control s(t + 1) = z(t + 1)

N ON E 0101
LOAD 1110
LEF T xl = 0 1010
LEF T xl = 1 1011
RIGHT xr = 0 0010
RIGHT xr = 1 1010

CT RL c1 c0
N ON E 0 0
LEF T 0 1
RIGHT 1 0
LOAD 1 1

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4-BIT BIDIRECTIONAL SHIFT-REGISTER

x3 x2 x1 x0
xl
xr

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

MUX MUX MUX MUX

c
c10

D D D D
Q Q Q Q

CK

z3 z2 z1 z0

Figure 11.7: IMPLEMENTATION OF A 4-BIT BIDIRECTIONAL SHIFT REGISTER WITH D FLIP-FLOPS.

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SERIAL-IN/SERIAL-OUT UNIDIRECTIONAL SHIFT REGISTER

z(t) = x(t − n)

xr
CLK n-1 n-2 0

CTRL
z
(a)
Figure 11.8: COMMON UNIDIRECTIONAL SHIFT REGISTERS: a) SERIAL-IN/SERIAL-OUT

Introduction to Digital Systems 11 – Standard Sequential Modules

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PARALLEL-IN/SERIAL-OUT UNIDIRECTIONAL SHIFT REGISTER

x n-1 x n-2 x0

CLK n-1 n-2 0

CTRL
2
z
(b)
Figure 11.8: COMMON UNIDIRECTIONAL SHIFT REGISTERS: b) PARALLEL-IN/SERIAL-OUT

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SERIAL-IN/PARALLEL-OUT UNIDIRECTIONAL SHIFT REGISTER

xr
CLK n-1 n-2 0
CTRL
z n-1 z n-2 z0

(c)
Figure 11.8: COMMON UNIDIRECTIONAL SHIFT REGISTERS: c) SERIAL-IN/PARALLEL-OUT

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SUMMARY OF SHIFT-REGISTER TYPES

xr
CLK n-1 n-2 0

CTRL
(a) z

x n-1 x n-2 x0

CLK n-1 n-2 0

CTRL
2
z
(b)

xr
CLK n-1 n-2 0
CTRL
z n-1 z n-2 z0
(c)

Figure 11.8: COMMON UNIDIRECTIONAL SHIFT REGISTERS: a) SERIAL-IN/SERIAL-OUT; b) PARALLEL-IN/SERIAL-OUT; c)

SERIAL-IN/PARALLEL-OUT

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USES OF SHIFT REGISTERS

• SERIAL INTERCONNECTION OF SYSTEMS

System A System B
x n-1 x n-2 x0
xr

CLK n-1 n-2 0 CLK n-1 n-2 0

CTRL CTRL
2 z
z n-1 z n-2 z0

Figure 11.9: SERIAL INTERCONNECTION OF SYSTEMS USING SHIFT REGISTERS

• BIT-SERIAL OPERATIONS

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x 31 x 30 x0

CLK 31 30 0 Operand X
Clock
CTRL Action
2 Cycle

y 31 y 30 y0 1 Load,
clear carry FF

2-33 Add and shift

CLK 31 30 0 Operand Y

carry-in

FA
Result Z
carry-out sum
Q D 31 30 0
CLK
Q’ CTRL
z 31 z 30 z0

CLR

Figure 11.10: BIT-SERIAL ADDER.

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USES OF SHIFT REGISTERS: STATE REGISTER

sn−1(t + 1) = x(t)
si(t + 1) = si+1(t) for i = n − 2, . . . , 0

• FINITE-MEMORY SEQUENTIAL SYSTEM

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Example 11.2: SHIFT REGISTER AS STATE REGISTER

s7(t + 1) = x(t)
si(t + 1) = si+1(t) for i = 6, . . . , 0
z(t) = x(t)s0(t)

z(t)

x(t) x(t-8)
CTRL 8-bit SHIFT REGISTER

CLK
Figure 11.11: IMPLEMENTATION OF NETWORK IN Example 11.2

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Example 11.3: SHIFT REGISTER AS STATE REGISTER



 1 if s(t) = 01101110 and x(t) = 1
z(t) = 


0 otherwise

x
CTRL 8-BIT SHIFT REGISTER
CLK

z
Figure 11.12: IMPLEMENTATION OF NETWORK IN Example 11.3

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NETWORKS OF SHIFT REGISTERS

CTRL

CLK serial-in
8-BIT SHIFT 8-BIT SHIFT 8-BIT SHIFT 8-BIT SHIFT (left shift)
serial-in REGISTER REGISTER REGISTER REGISTER
(right shift) 7 0 7 0 7 0 7 0

serial-out serial-out
(left shift) (right shift)

Figure 11.13: NETWORK OF SERIAL-INPUT/SERIAL-OUTPUT SHIFT REGISTER MODULES

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COUNTERS

• MODULO-p COUNTER
s(t + 1) = (s(t) + x) mod p

(state/output) 1/1
s/z

1/0 1/0 1/0 p-1

0/0 1/1 2/2
/p-1

x/TC = 0/0 0/0 0/0 0/0

(input/terminal count)

Figure 11.14: STATE DIAGRAM OF A MODULO-p COUNTER

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A HIGH-LEVEL DESCRIPTION OF A MODULO-p COUNTER

INPUT: x ∈ {0, 1}
OUTPUTS: z ∈ {0, 1, . . . , p − 1}
T C ∈ {0, 1}
STATE: s ∈ {0, 1, . . . , p − 1}

FUNCTION: STATE TRANSITION AND OUTPUT FUNCTIONS

s(t + 1) = (s(t) + x) mod p

z(t) = s(t)

 1 if s(t) = p − 1 and x(t) = 1


T C(t) = 
0 otherwise

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TYPES OF COUNTERS

• UP or DOWN COUNTERS

State Binary BCD Excess-3 Gray Ring Twisted Tail

0 000 0000 0011 000 00000001 0000
1 001 0001 0100 001 00000010 0001
2 010 0010 0101 011 00000100 0011
3 011 0011 0110 010 00001000 0111
4 100 0100 0111 110 00010000 1111
5 101 0101 1000 111 00100000 1110
6 110 0110 1001 101 01000000 1100
7 111 0111 1010 100 10000000 1000
8 1000 1011
9 1001 1100

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RING and TWISTED-TAIL COUNTERS

0 0 0 1

CLK xl
3 2 1 0
LOAD
x
(COUNT)
0 1 0 0 State = 2

(a) z3 z2 z1 z0
0 0 0 0

xl
CLK
3 2 1 0
LOAD
x
(COUNT)
0 0 1 1 State = 2
(b) z3 z2 z1 z0

Figure 11.15: a) MODULO-4 RING COUNTER; b) MODULO-8 TWISTED-TAIL COUNTER

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BINARY COUNTER WITH PARALLEL INPUT

INPUTS: I = (I3, . . . , I0), Ij ∈ {0, 1}, I ∈ {0, 1..., 15}

CLR, LD, CN T ∈ {0, 1}
STATE: s = (s3, . . . , s0), sj ∈ {0, 1}, s ∈ {0, 1, ..., 15}
OUTPUT: s = (s3, . . . , s0), sj ∈ {0, 1}, s ∈ {0, 1, ..., 15}
T C ∈ {0, 1}

FUNCTION: STATE-TRANSITION AND OUTPUT FUNCTIONS


0






if CLR = 1
I if LD = 1




s(t + 1) = 






(s(t) + 1) mod 16 if CN T = 1 and LD = 0
 s(t) otherwise






 1 if s(t) = 15 and CN T = 1
T C = 


0 otherwise

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MODULO-16 COUNTER

Outputs
Clear

Terminal
S3 S2 S1 S0 CLR
count
Count enable
TC MODULO-16 CNT
COUNTER
CLK
I3 I2 I1 I0 LD

Load inputs

Inputs
Figure 11.16: A MODULO-16 BINARY COUNTER WITH PARALLEL INPUT

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MODULO-k COUNTER (1 ≤ k ≤ 16)

CN T = x


 1 if (s = k − 1) and (x = 1)
LD =


 0 otherwise



I = 0

T C = LD

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MODULO-k COUNTER (1 ≤ k ≤ 16)(cont.)

0/0

1/0
1/0 1/0
0 1 k-1 k 14 15

0/0 0/0 0/0 0/0 0/0 0/0

1/1
(a)

clear

S3 S2 S1 S0 CLR
CLK
MODULO-16 CNT x
State 9 10 11 0 1
COUNTER
CLK
I3 I2 I1 I0 LD LD(TC)
s0
s1
s3
0 0 0 0
TC (b)

Figure 11.17: a) STATE DIAGRAM OF MODULO-k COUNTER (1 ≤ k ≤ 16); b) MODULO-12 COUNTER AND ITS TIME
BEHAVIOR (x = 1)

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a-to-b COUNTER (0 ≤ a, b ≤ 15)

CN T = x


 1 if (s = b) and (x = 1)
LD =


 0 otherwise



I = a

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1/0

1/0 1/0 1/0 1/0

0 a a+1 b b+1 14 15

0/0 0/0 0/0 0/0 0/0 0/0 0/0

1/1
(a)

clear

S3 S2 S1 S0 CLR

MODULO-16 CNT x (b)

COUNTER
CLK
I3 I2 I1 I0 LD

s2
s3
0 0 0 1
TC

Figure 11.18: a) STATE DIAGRAM OF a-to-b COUNTER; b) A 1-to-12 COUNTER

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MODULO-k FREQUENCY DIVIDER (1 ≤ k ≤ 16)

CN T = x


 1 if T C = 1
LD =


 0 otherwise



I = 16 − k

z = TC

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1/0 1/0 1/0 clear

0 16-k 14 15
S3 S2 S1 S0 CLR

z TC MODULO-16 CNT x
0/0 0/0 0/0 0/0 COUNTER
1/1 CLK
I3 I2 I1 I0 LD

(a)

0 1 1 1

CLK

State 13 14 15 7 8 13 14 15 7

z(TC)

(b)

Figure 11.19: a) STATE DIAGRAM OF MODULO-k FREQUENCY DIVIDER; b) MODULO-9 FREQUENCY DIVIDER AND ITS
TIME BEHAVIOR (x = 1)

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USES OF COUNTERS

• COUNT THE NUMBER OF TIMES THAT A CERTAIN EVENT TAKES

PLACE;

• CONTROL A FIXED SEQUENCE OF ACTIONS

• GENERATE TIMING SIGNALS

• GENERATE CLOCKS OF DIFFERENT FREQUENCIES

• STATE REGISTER

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ENTRANCE
SENSOR UP
CLK COUNTER
EXIT DOWN
SENSOR MAX NUMBER
OF SPACES

COMPARATOR
> <

LOT FULL FREE SPACE

(a)

Sequence of actions:
CLEAR
0
0: CLEAR ALL REGISTERS 1 INPUT A

DECODER
COUNTER
modulo-6

BINARY
1: INPUT A 2 INPUT B
2: INPUT B
3
3: COMPUTE COMPUTE
4
4: COMPUTE
CLK 5 OUTPUT C
5: OUTPUT C

(b)

Figure 11.20: a) EXAMPLE OF EVENT COUNTER; b) EXAMPLE OF CONTROLLER.

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USES OF COUNTERS (cont.)

S Q TS0

0 R Q’ CLK0

Binary Counter
1 S0

BINARY DECODER

Modulo-4
CLK2
Binary Counter
S0 2
TS1
Modulo-8

S Q
S1 3 S1
CLK4
4
S2 R Q’
5
6
CLK
7 S Q TS2

CLK
R Q’
CLK CLK0

7 0 1 2 3 4 5 6 7 0
State CLK2

TS0 CLK4

TS1
(b)

TS2
(a)

Figure 11.21: EXAMPLES OF NETWORKS FOR GENERATING a) TIMING SIGNALS; b) CLOCKS WITH DIFFERENT FREQUEN-
CIES.

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COUNTER AS STATE REGISTER

Counting s(t + 1) = (s(t) + 1) mod p

No change s(t + 1) = s(t)
Arbitrary s(t + 1) 6= (s(t) + 1) mod p and s(t + 1) 6= s(t)

Output
Combinational z
Network

s
n
CLK
n
Modulo- 2
Combinational
CNT Counter
Network for
x CNT(Count)
LD
n I

Combinational Combinational
Network for Network for
LD(Load) Parallel Inputs

Figure 11.22: IMPLEMENTATION OF SEQUENTIAL SYSTEM WITH COUNTER AND COMBINATIONAL NETWORKS.

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COUNTER AS STATE REGISTER (cont.)



 1 if s(t + 1) = (s(t) + 1) mod p and x = 1
CN T =


 0 otherwise




1 if s(t + 1) 6= s(t) and






LD =  s(t + 1) 6= (s(t) + 1) mod p and x = 1


 0 otherwise






 s(t + 1) if LD = 1
I =


 − otherwise



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Example 11.4

a’/0

S0

a/0 b/0

S1 S6
b’/0

-/0 -/0

S2 c/0 S5

-/0
c’/0

b’/1 S3 S4
b/0

Figure 11.23: STATE DIAGRAM for Example 11.4

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Example 11.4 (cont.)

CN T = S0a S1 S2 S3b S4c0 S5

0
LD = CN T
0






(0, 0, 0, 0) if S 0 a S6 b
(I3, I2, I1, I0) =  (0, 0, 0, 1) if S4c S6b0



 (0, 0, 1, 1) if S 3 b0




SWITCHING EXPRESSIONS FOR PARALLEL INPUTS

I3 = 0
I2 = 0
I1 = Q0
I0 = Q0 Q2Q01 Q2b0

OUTPUT z
z = Q 1 Q0 b0

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Q Q Q Q
3 2 1 0
a 0

1 1

1 2 CK
Modulo- 16
b 3 CNT Counter
MUX
c’ 4
LD I I I I
1 5 3 2 1 0

0 6
0 0
d.c. 7
2 1 0

Q Q Q
2 1 0

Q
1
Q z
0
b’
Q b’ Q Q’
0 2 1

Figure 11.24: SEQUENTIAL NETWORK FOR Example 11.4

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NETWORKS OF COUNTERS

• CASCADE COUNTERS


 1 if (s = p − 1) and (CN T = 1)
T C = 


0 otherwise

• FOR THE i-th MODULE

1 if (s(j) = p − 1) and (x = 1)







CN T i =  ( for all j < i)




 0 otherwise




where s(j) is the state of counter j.

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CASCADE COUNTERS (cont.)

TC Q CNT TC Q CNT TC Q CNT x

k-1 k-2 0
I LD I LD I LD

CLK
LOAD

Figure 11.26: CASCADE IMPLEMENTATION OF A MODULO-pk COUNTER

• THE WORST-CASE DELAY

Tworst−case = (k − 1)ttc + tsu + tp

• THE MAXIMUM CLOCK FREQUENCY POSSIBLE

fmax = 1/[(k − 1)ttc + tsu + tp]

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Example 11.5

tsu = 4.5[ns] (including the delay of the gates used

to produce the inputs to the cells)
tp = 2[ns]
ttc = 3.5[ns]

MIN CLOCK PERIOD:

with one module T = 6.5[ns] (153[M Hz])
with 8 modules T = 31[ns] (32[M Hz])

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FASTER COUNTERS

• INTRODUCE CEF (Count Enable First)



 (s(t) + 1) mod p if CEF = 1 and CN T = 1
s(t + 1) = 


s(t) otherwise

• T C SIGNAL NOT INFLUENCED BY CEF ,



 1 if (s(t) = p − 1) and (CN T = 1)
T C = 


0 otherwise

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FASTER CASCADE COUNTER

Q CEF Q CEF Q CEF Q CEF 1

k-1 CNT TC k-2 CNT TC 1 CNT TC 0 CNT x
I LD I LD I LD I LD
"1"
LOAD
CLK

Figure 11.27: A FASTER VERSION OF A CASCADE COUNTER

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WORST-CASE DELAY

Tworst−case = (k − 2)ttc + tsu + tp

⇒ SMALL REDUCTION IN THE DELAY

* Note: propagation of T C can span several clock cycles

CONSEQUENTLY, IF T IS THE CLOCK PERIOD,

pT ≥ (k − 2)ttc + tsu + tp

T ≥ ttc + tsu + tp
COMBINING
T ≥ max(ttc + tsu + tp, ((k − 2)ttc + tsu + tp)/p)

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p-2 p-1 0 1
Q (0)

p-1 0
Q (1)

p-1 0
Q (k-2)

TC (0)
tp

CNT (k-1)
Time available to propagate TC t su

r r+1
Q (k-1)

(a)

p-2 p-1 0 1 2 p-2 p-1 0 1 2

Q (0)

p-2 p-1 0
Q (1)

TC (0)
= CEF

TC (1)

CNT (k-1)
tp t su

Time available to propagate TC

r r+1
Q (k-1)

(b)

Figure 11.28: TIMING RELATIONS: a) Without CEF ; b) With CEF

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PARALLEL COUNTERS

Modulo-504 counter: 7 × 8 × 9 states

000, 111, 222, 333, 444, 555, 666, 077, 108, 210, 321, 432, ...

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PARALLEL MODULO-(7 × 8 × 9) COUNTER

x CNT
Modulo-7
Modulo-(7x8x9)
COUNTER COUNTER

CNT
Modulo-8
COUNTER
CLK

CNT
Modulo-9
COUNTER

Figure 11.29: PARALLEL IMPLEMENTATION OF MODULO-(7 × 8 × 9) COUNTER.

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MULTIMODULE SYSTEMS

• Complex sequential system ⇒ several interacting sequential subsystems

Example 11.6: BLOCK PATTERN RECOGNIZER

• INPUT SEQUENCE: blocks of k symbols

• FUNCTION: check for pattern P in each block
• IMPLEMENTATION: counter + recognizer
• OUTPUT OF THE COUNTER:


 1 if t mod k = k − 1 and check = 1
T C(t) = 


0 otherwise
• OUTPUT OF THE SYSTEM: z(t) = p(t) · T C(t)

Introduction to Digital Systems 11 – Standard Sequential Modules

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INITIALIZE

MODULO - k TC
check
COUNTER

z(t)

PATTERN
x(t)
RECOGNIZER p

CLK

(a)

Figure 11.30: BLOCK PATTERN RECOGNIZER

Introduction to Digital Systems 11 – Standard Sequential Modules

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Example 11.6: ILLUSTRATION

t 0 1 2 3 4 5 6 7 8 9 10 11
x 5 3 7 4 1 0 3 7 4 3 7 4
TC 0 0 1 0 0 1 0 0 1 0 0 1
p 0 0 0 1 0 0 0 0 1 0 0 1
z 0 0 0 0 0 0 0 0 1 0 0 1

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Example 11.7

• count the number of instances of pattern P in blocks of k symbols

INITIALIZE

MODULO - k TC
check
COUNTER

z(t) MODULO - N
COUNTER

PATTERN
x(t)
RECOGNIZER p
Count
of instances of P

CLK
(b)

Figure 11.30: BLOCK PATTERN RECOGNIZER.

Introduction to Digital Systems 11 – Standard Sequential Modules