SREE VIDYANIKETHAN ENGINEERING COLLEGE

(AUTONOMOUS)
Sree Sainath Nagar, Tirupati- 517 102

AssignmentProblems/Questions
Course Code: : 20BT70409
Course Name: : LOW POWER CMOS VLSI DESIGN
Year & Semester : IV B.Tech I Semester
Branch & Section : ECE - A, B, C & D Sections
Regulations (SVEC-19/SVEC-20) : SVEC-20
Academic Year : 2023-24
Faculty member(s) : Dr.N.Ashokkumar,Professor, ECE

Max. Marks/Assignment: 10
Blooms
Group Q. Problem/Question Description Marks POs
Level
No.
Briefly outline the need of low power VLSI chips in developing real electronics
1. 5 L2 PO6
2. Interpret the Data Correlation Analysis in evaluating the performance of DSP 5 PO4
L4
I systems
1. Organize, how scaling is affected by technology PO4
5 L1
2. Explain the effect of VDD and VT on CMOS power where VDD is the supply PO6
5 L4
voltage and VT is the threshold voltage
II
1 Inspect the interesting characteristic of short circuit current variation with output load L1 PO6
5
III
also explain the effects of increasing output load capacitance.
2 Criticize single edge triggered flip-flop and double edge triggered flip-flop and bring PO4
5 L4
out the various advantages and disadvantages of each with the help of neat diagrams
and equations.
1 Justify how guarded Evaluation technique is used to reduce the switching activities 5 PO4
IV L4
and multiplexing to reduce hardware resources.
2 Elaborate the impact of transistor sizing, gate oxide thickness and technology scaling 5 PO6
L1
on low power electronics.
1 Identify the technology and device innovations for novel high speed low power VLSI 5 L4 PO6

V
devices.

2 Derive the statistical estimation of mean with its normal distribution curve in Monte 5 L2 PO4
Carlo power simulation.
1 Asses the techniques to reduce hardware resources in digital systems. 5 L3 PO6
VI

2 Analyze the technique of Adiabatic model of Quantum computation. 5 L3 PO4

VII 1 Estimate the importance of Low Power Figure of Merits. 5 L1 PO6

2 Evaluate the Effects of data correlation on bit switching frequency in dual bit type 5 L4 PO4
model and Datapath Module Characterization of Power Analysis
VIII 1 Briefly, discuss in detail about the following terms 5 L1 PO6
(i) SPICE Basics
(ii) Hardware Emulation

2 Derive an expression for short circuit power dissipation in a CMOS inverter and 5 L1 PO4
Discuss the techniques to minimize the power dissipation.

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 Details of Students/Questions to submit the Assignment
Section A
Q.
No. No. of
Register Nos of Students
Students
1.
20121A0401-408 08

2. 20121A0409-416
08

3. 20121A0417-424
08

4. 20121A0425-432
08

5. 20121A0433-440
08

6. 20121A0441-449
09

7. 20121A0450-459
10

8. 20121A0460-470
10

Section B
Q. No.
No. of
Register Nos of Students
Students

1. 20121A0471-478 08

2. 20121A0479-486 08

3. 20121A0487-494 08

4. 20121A0495-4A2 08

5. 20121A04A3-4B1 09

6. 20121A04B3-4C2 09

7. 20121A04C3-4D3 10

8. 20121A04D4-4E5 10