Bandgap modulated phosphorene based gate drain underlap double-gate TFET

Md. Abdullah-Al-Kaiser, Dip Joti Paul, and Quazi D. M. Khosru

Citation: AIP Advances 8, 095121 (2018); doi: 10.1063/1.5049611

View online: https://doi.org/10.1063/1.5049611
View Table of Contents: http://aip.scitation.org/toc/adv/8/9
Published by the American Institute of Physics
 AIP ADVANCES 8, 095121 (2018)

Bandgap modulated phosphorene based gate drain

underlap double-gate TFET
Md. Abdullah-Al-Kaiser,a Dip Joti Paul, and Quazi D. M. Khosru
Department of Electrical and Electronic Engineering, Bangladesh University of Engineering
and Technology, Dhaka 1205, Bangladesh
(Received 24 July 2018; accepted 18 September 2018; published online 27 September 2018)

In this work, a novel bandgap modulated gate drain underlap (BM-GDU) structure
of tunnel-FET exhibiting suppressed ambipolar characteristics and steep SS is pro-
posed by applying layer dependent bandgap and electron affinity property of 2-D
material Phosphorene. An artificial hetero-junction between the source and chan-
nel region is composed of trilayer and bi-layer Phosphorene respectively without
any lattice mismatch. BM-GDU TFET exhibits ON-current ∼100 µA/µm, on-off
ratio greater than 109 and average subthreshold swing 28.6 mV/decade for a chan-
nel length of 20 nm at V DD of 0.4 V due to its low bandgap at source region than
the channel region, larger tunneling window and lower carrier effective mass. Gate
drain underlap structure yields ∼10 decades ambipolar suppression than conven-
tional homojunction DG TFET. Performance parameters of our BM-GDU TFET by
varying channel length are also studied using our developed self-consistent quantum
mechanical transport simulator. © 2018 Author(s). All article content, except where
otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license
(http://creativecommons.org/licenses/by/4.0/). https://doi.org/10.1063/1.5049611

I. INTRODUCTION
Fundamental physical limits for conventional CMOS technology in power efficiency, sup-
ply voltage scaling, leakage power dissipation and shrinking channel length have already been
reached. Moreover, Boltzmann subthreshold swing limit (60 mV/decade) of traditional CMOS forces
researchers to find out the best alternative of CMOS technology for low-power nano-electronics. In this
regard, tunnel field effect transistor (TFET) has already demonstrated SS lower than 60 mV/decade
and low leakage due to its carrier injection mechanism which is different from conventional CMOS.1–3
Lower SS and low leakage of TFET offer reduction in static and dynamic power dissipation. More-
over, TFET facilitates further supply voltage reduction as well as channel length scaling for ultra
low-power ICs. The main differences of TFET from conventional CMOS technology are carrier
injection mechanism and doping type. In conventional nTFET, source, channel and drain regions are
degenerately p-type, lightly n-type and degenerately n-type doped, respectively. Carrier tunnels from
source valence band to channel conduction band which can be enabled or disabled by controlling gate
voltage. Tunneling current mainly depends on the band-to-band tunneling charge which is smaller
compared to the charge produced by conventional thermionic carrier injection mechanism at iso-
V GS . As a result, TFET suffers from low ON-current problem which is one of the major drawbacks of
TFET. To boost the ON-current, electric field and band-to-band tunneling charge generation should
be large significantly. Different structural modifications like p-n-p-n TFET structure,4,5 dual material
gate structure,6–8 gate dielectric engineered structure,9,10 vertical TFET structure,11 and heterostruc-
ture12,13 have already been reported in quest of finding a solution to improve ON-current in TFET.
Moreover, in recent years 2-D channel materials have drawn quite a lot attention than 3-D channel
material for nano devices. 2-D channel materials manifest excellent gate control at lower dimension

a
Electronic mail: fahim.kaiser.epsilon@gmail.com

2158-3226/2018/8(9)/095121/9 8, 095121-1 © Author(s) 2018

095121-2 Abdullah-Al-Kaiser, Paul, and Khosru AIP Advances 8, 095121 (2018)

due to their atomically thin layer thickness, direct bandgap, lower carrier effective mass, high density
of states and high carrier mobility. 2-D material based TFETs surpass conventional 3-D material
based TFET in both ON-current and SS.1,14–17
Besides low ON-current, TFET experiences another intrinsic ambipolar conduction problem
which makes it an inappropriate choice for digital logic based applications. Ambipolar conduction
happens at high negative gate bias due to the lowering of barrier width between the channel valence
band and drain conduction band which leads to the degradation of output voltage in digital logic
circuits. As a result, at logic high, the output voltage cannot reach V DD and the output voltage level
remains above 0 V at logic low.18,19 This ambipolar conduction cannot be suppressed fully but it
can be reduced by certain orders of magnitude by various structural modifications like heterogeneous
gate dielectric structure,20 gate underlap spacer structure,21,22 gate overlap structure and dual material
gate structure.23,24
Heterostructure TFET can enhance the ON-current, keeping OFF-current lower by utilizing
low bandgap source with high bandgap channel region. Among different types of heterostructure
TFET, Ge-Si based heterojunction TFET,25,26 III-V materials based heterojunction TFET27,28 and
2D material based heterojunction TFET29,30 have already been reported. But large lattice mismatch
poses a strong hindrance for forming effective heterojunction. Hence, to utilize the advantage of
heterojunction by preventing lattice mismatch problem, layer or thickness dependent bandgap and
electron affinity property of a single material can be the best solution. DFT simulation study of bilayer
and monolayer Phosphorene junction using Vienna ab initio simulation package (VSAP) for both
stacking order and direction has been analyzed.31 Moreover, atomistic quantum transport simulation
of similar type of heterojunction based on bilayer Phosphorene at source and monolayer Phosphorene
at channel for TFET has been investigated.32 Besides, Phosphorene trilayer and monolayer junction
based TFET structure has also been reported so far.33
The aim of our work is to find out a solution of two major problems in TFET by applying both
structural modification and material optimization. In this regard, we propose a novel structure by
applying the layer dependent bandgap and electron affinity property of 2-D material Phosphorene.
To make the ON-current larger, lower source bandgap than channel is required for greater tunneling
probability. The bandgap of Phosphorene is related inversely with the number of layers. So, in source
region higher number of layers of Phosphorene than channel have to be used. But increasing the
number of layers in the source region will decrease the bandgap significantly, as a result, OFF-
current will also be increased as well as the ON-current and SS will be deteriorated greatly. So, for
optimum performance we have used trilayer Phosphorene as source material and bilayer Phosphorene
as channel material to compose a heterostructure without having any lattice mismatch. Moreover,
gate underlap spacer structure performs better in ambipolar suppression by introducing higher barrier
width than conventional DG structure in our proposed scheme. So bandgap modulated gate drain
underlap (BM-GDU) DG TFET can be the best solution in boosting ON-current as well as suppressing
ambipolar conduction.
The remainder of the manuscript is organized as follows: In Sec. II, our proposed device structure
and material parameters have been described. Then current modeling of TFET using our quan-
tum mechanical simulator and validation of this simulator are explained in Sec. III. Finally, device
operation of our proposed structure and different performance parameters have been reported in
Sec. IV.

II. DEVICE STRUCTURE AND PARAMETERS

The 2-D cross-sectional schematic view of our proposed n-channel BM-GDU TFET is illus-
trated in Fig. 1. The source, channel and drain lengths are considered to be 10 nm, 20 nm and 10
nm, respectively. Source and drain regions are degenerately p-type and n-type doped with doping
concentration 5 × 1013 cm−2 and 1 × 1013 cm−2 respectively and channel region is lightly n-type doped
with doping concentration 1 × 1010 cm−2 . The source, channel and drain regions are composed of
trilayer, bilayer and bilayer Phosphorene. Phosphorene exhibits honeycomb puckered layer structure
and each sheet consists of an atomic double layer. Each Phosphorous atom in this sheet is cova-
lently connected with another three atoms within this puckered layer structure. The bond lengths for
095121-3 Abdullah-Al-Kaiser, Paul, and Khosru AIP Advances 8, 095121 (2018)

FIG. 1. Schematic representation of bandgap modulated gate-drain underlap (BM-GDU) structure of TFET.

puckered structure are considered 2.283 Å, and 2.243 Å.34 For bilayer and trilayer Phosphorene, the
adjacent puckered layers are stacked according to AA and ACA stacking order with weak Van der
Waals forces respectively. The intermediate layer to layer distances are considered 3.50 Å for bilayer
and 3.68 Å, 3.69 Å for trilayer Phosphorene.35 Doping junctions are considered to be abrupt in our
simulation. The energy bandgaps (E g ) of trilayer and bilayer Phosphorene are obtained as 0.57 eV and
0.93 eV, respectively from the band structure calculation through density functional theory (DFT)
using HSE06.16,33,35
In our simulation, electron affinity of bilayer and trilayer Phosphorene are used as 4.19 eV
and 4.02 eV. respectively.33 The source, channel and drain thickness are 1.8 nm, 1.2 nm and 1.2 nm
respectively depending on layers of Phosphorene.36 The electron effective mass (me∗ ) and hole effective
mass (mh∗ ) of bilayer Phosphorene are 0.115× me and 0.12 × me , respectively.16 The gate dielectric
is divided into two parts-the dielectric near source is high-k HfO2 ( r = 25) and the spacer dielectric
near drain is low-k SiO2 ( r = 3.9). The gate dielectric thickness (t ox ) is 3 nm in our simulation. The
gate length (L G = 10 nm) is considered as half of the total channel length (L ch = 20 nm) for better
ambipolar suppression characteristics. Flat-band voltage is considered 0.15 V and the top and bottom
gates are tied together to feed the same gate bias.

III. SIMULATION METHOD AND VALIDATION

A self-consistent quantum mechanical transport simulator is developed to calculate the band-to-
band tunneling current in TFET. Local electric field method was first introduced by Kane to calculate
BTBT current in tunneling diode by considering average constant electric field along the tunnel path.37
But to investigate tunneling phenomena more precisely, spatial variation of electric field along the
tunneling region should be considered.38,39 So, band to band tunneling carrier generation rate is given
by
!
−B
GBTBT (x, y) = A|ξ(x)| E(x, y) exp
D−1
(1)
ξ(x)
here A, B, and D are Kane’s parameters which depend on material’s bandgap, thickness and reduced
effective mass. Local electric field E(x,y) can be extracted by solving Poisson’s equation and
Schrödinger’s equation iteratively until the convergence of solution. 2D Poisson’s equation along
and perpendicular to channel direction and 1D Schrödinger’s equation along the confinement direc-
tion are solved for our structure using COMSOL Multiphysics. To incorporate quantum phenomena,
open boundary condition is considered in channel-dielectric interfaces in Schrodinger’s equation to
calculate Eigen energy and wave function. Average electric field ξ(x) depends on the effective tun-
neling distance (ltunnel ) of the carrier. In our analysis, tunneling is dominant in lateral direction, so,
we can write ltunnel = x 2 − x 1 . At x = x 1 , the channel conduction band reaches to the source Fermi
level and at x = x 2 the channel conduction band flattens and the tunneling of carrier stops, shown in
095121-4 Abdullah-Al-Kaiser, Paul, and Khosru AIP Advances 8, 095121 (2018)

Fig. 2(a). So average electric field can be expressed as follows

Eg
|ξ(x)| = (2)
qltunnel
Moreover, carrier occupancy in source and channel region is of paramount importance in cal-
culating BTBT current. Gate voltage mainly controls the tunneling window for BTBT current and
drain bias affects the occupancy by modulating the drain Fermi level.40,41 So, we can express the
band-to-band tunneling charge generation rate as follows which is proportional to the difference of
occupancy of carrier in the source and channel region
 Emax
GBTBT ∝ ( fs (E) − fch (E)) dE (3)
Emin

where E max is the maximum energy of source valance band, E min is the minimum energy of channel
conduction band and electron energy E is within the tunneling energy window (E min <E<E max ). The
electron occupation probability in the source valence band and channel conduction band can be
expressed as Eq. (4) and Eq. (5).
  E − EFs   −1
fs (E) = 1 + exp (4)
kB T
  E − EFch   −1
fch (E) = 1 + exp (5)
kB T
where E Fs and E Fch are the Fermi energy level in the source and channel region. Substituting these
values in Eq. (3) and integrating it within the limit, we get
  !
1 + exp(E1 ) 1 + exp(E2 )
GBTBT ∝ ln    (6)
1 + exp(E3 ) 1 + exp(E4 )

where E 1 , E 2 , E 3 and E 4 can be expressed as:

Emax − EFch Emin − EFs
E1 = E2 =
KB T KB T

Emax − EFs Emin − EFch

E3 = E4 = (7)
KB T KB T

FIG. 2. (a) Tunneling window for drain current computation from ON-state energy band diagram (b) Validation of our
simulator by benchmarking the transfer characteristics of Chang et al.16
095121-5 Abdullah-Al-Kaiser, Paul, and Khosru AIP Advances 8, 095121 (2018)

Both spatial electric field and carrier occupancy probability play a vital role in generating band-
to-band tunneling charge. By incorporating both effect, we can write the modified expression for
band-to-band generation rate as Eq. (8).
!   !
−B 1 + exp(E1 ) 1 + exp(E2 )
GBTBT (x, y) = A|ξ(x)| E(x, y) exp
D−1
× ln  (8)
ξ(x)
 
1 + exp(E3 ) 1 + exp(E4 )
Finally, drain current I DS per unit width is calculated by integrating the band to band tunneling
generation rate throughout the device structure
 x=x2 y=tch
IDS = q GBTBT (x, y) dydx (A/µm) (9)
x=x1 y=0

Since experimental data for our proposed structure is not available, so to validate our simulator
we have compared our simulation result for n-channel DG TFET of exact same structure with the
atomistic transport simulations by Chang et al.16 which shows a good accuracy of our simulator
(Fig. 2(b)).

IV. RESULTS AND DISCUSSIONS

Fig. 3(a) compares the transfer characteristics (I D − V GS ) of BM-GDU TFET and BM-DG
TFET with conventional bilayer Phosphorene DG TFET. It is observed that our proposed structure

FIG. 3. (a) Transfer characteristics (I D − V GS ) comparison (b) ON-state energy band diagram comparison of proposed
TFET with BM-DG TFET and conventional bi-layer Phosphorene DG TFET at V GS = 0.6 V and V DS = 0.4 V (c) Band-to-
band tunneling charge generation rate comparison of BM-DG TFET with conventional bi-layer Phosphorene DG TFET at
V GS = 0.6 V and V DS = 0.4 V (d) Source to channel minimum tunneling distance comparison of proposed BM-GDU TFET
with BM-DG TFET and conventional bi-layer Phosphorene DG TFET at V GS = 0.6 V and V DS = 0.4 V.
095121-6 Abdullah-Al-Kaiser, Paul, and Khosru AIP Advances 8, 095121 (2018)

outperforms by ∼2 decades higher ON-current than the conventional DG TFET based on the same
channel material and structural parameters. At V GS = 0.6 V with 20 nm channel length, BM-DG and
BM-GDU TFET exhibits same ON-current (I ON ) of 99.29 µA/µm when V DS = 0.4 V. The ON-current
of BM-DG and BM-GDU TFET is same as material optimization of source and channel is similar
in both structures. The main difference between these two structures lies at the channel-drain region
in dielectric material and gate biasing condition. BM-GDU offers ∼10 decades ambipolar current
(I AMB ) suppression than BM-DG and conventional DG TFET at negative gate bias (V GS = −0.6 V).
Moreover, BM-GDU TFET reports subthreshold swing (SS) of 28.64 mV/decade which is lower
than BM-DG TFET (SS = 40.62 mV/decade). The better SS in BM-GDU TFET is achieved due to
the lower value of minimum current (I MIN ), which is ∼4 decades smaller than BM-DG TFET. The
OFF-current at V GS = 0 V is alike in both BM-DG and BM-GDU structure, as a result same on-off
ratio (1 × 109 ) is obtained for both structures.
A comparison among the energy band diagram of DG, BM-DG and BM-GDU TFET at
V GS = 0.6 V is illustrated in Fig. 3(b). Trilayer Phosphorene and bi-layer Phosphorene combina-
tion creates straddling type heterojunction at the source-channel interface. The conduction band
bending in channel region is similar for both conventional DG TFET and BM-DG TFET at particular
gate bias since same channel and dielectric material are present at the tunneling junction. But due
to the electron affinity and bandgap difference in the source region of BM-DG TFET, valence band
lies 0.19 eV higher from DG TFET. As a result, effective tunneling distance is lowered and tunneling
window becomes larger. Enlarged tunneling region ensures greater band-to-band tunneling charge
density hence ON-current is improved. Comparison of BTBT generation charge per nm2 for DG
TFET and BM-DG TFET is shown in Fig. 3(c). It is observed that at V GS = 0.6 V, BTBT charge is ∼2
decades larger in BM-DG TFET than DG TFET. Moreover, comparison of the shortest tunneling dis-
tance from source valence band to channel conduction band for both structures is visible in Fig. 3(d).
It is apparent from Fig. 3(d) that the source-channel heterojunction offset enables lower tunneling
distance in bandgap modulated artificial heterojunction TFET than conventional homojunction DG
TFET. The energy band diagram near source-channel interface and the shortest tunneling distance
characteristics overlaps for both BM-DG and BM-GDU TFET due to having same material and
structural parameters at the source-channel junction.
Fig. 4(a) shows the energy band diagram of three structures at V GS = −0.6 V from which
ambipolar suppression behavior of BM-GDU can be explained. In conventional DG and BM-
DG TFET, material and structural parameters near channel-drain junction are same. As a result,
both structures experience higher ambipolar conduction at negative gate bias. But in BM-GDU
TFET structure, low-k spacer oxide with shorter gate at channel-drain junction enables lower band
bending by lessening the effective voltage. So, the shortest tunneling barrier width from channel
valence band to drain conduction band becomes ∼3 times higher in BM-GDU TFET than BM-
DG and conventional DG TFET. Lower effective voltage also causes lower electric field at the

FIG. 4. Ambipolar state (a) energy band diagram and (b) electric field comparison of proposed BM-GDU TFET with BM-DG
TFET and conventional bi-layer Phosphorene DG TFET at V GS = −0.6 V and V DS = 0.4 V.
095121-7 Abdullah-Al-Kaiser, Paul, and Khosru AIP Advances 8, 095121 (2018)

FIG. 5. Transfer characteristics (I D − V GS ) of our proposed BM-GDU TFET at V DS = 0.4 V by varying channel length.

channel-drain junction, hence lower ambipolar tunneling occurs. Surface electric field along the chan-
nel at V GS = −0.6 V is illustrated in Fig. 4(b). The channel-drain junction electric field for BM-DG
and BM-GDU TFET are 4.583 MV/cm and 2.399 MV/cm, respectively. Due to the same channel-
drain junction characteristics, BM-DG TFET and conventional DG TFET shows same energy band
diagram and electric field along the channel. On the other hand, higher tunneling distance and lower
electric field enables lower BTBT charge generation, hence ensures lower ambipolar conduction at
higher negative gate bias in BM-GDU TFET.
The transfer characteristics of BM-GDU TFET by varying channel length is illustrated in Fig. 5.
It is observed that scaling of channel length increases leakage current. At the off state, source to
channel tunneling barrier width is higher. As a result, tunneling carrier probability from source to
channel is very low. But due to the shrinking of channel length, the channel-drain junction barrier
width becomes lower. In this phase, ambipolar conduction becomes significant, hence, off current
increases with the decrease of channel length. Moreover, shrinking the channel length also affects the
ambipolar current. At lower channel length, drain-channel barrier width is lower at lower negative
bias than the higher channel length device. As a result, both the ambipolar current and minimum
current increase. Minimum current and ambipolar current at V GS = −0.6 V for different channel
length is shown in Fig. 6(a).
The subthreshold swing comparison of our proposed BM-GDU TFET with conventional DG
TFET is illustrated in Fig. 6(b). From the figure it is observed that SS value is lower for any channel

FIG. 6. (a) Ambipolar current (V GS = −0.6 V) and minimum current of proposed BM-GDU TFET at V DS = 0.4 V for
different channel length (b) Subthreshold swing comparison of proposed BM-GDU TFET with conventional DG TFET at
V DS = 0.4 V for different channel length.
095121-8 Abdullah-Al-Kaiser, Paul, and Khosru AIP Advances 8, 095121 (2018)

length in BM-GDU TFET than DG TFET. Improved SS performance is achieved in our structure due
to the effects of increasing ON-current and decreasing minimum current at the same time. SS value
is found lower than 60 mV/decade upto 13 nm of channel length in BM-GDU TFET. So, at lower
channel length BM-GDU TFET also exhibits better SS than conventional DG TFET.

V. CONCLUSIONS
In summary, our proposed BM-GDU TFET addresses the solution for both the ON-current
and ambipolar problem of TFET. Formation of an artificial heterostructure enables us to utilize the
benefits of electron affinity difference by enlarging the tunneling window hence tunneling current
increases. Gate underlap spacer widens the barrier width to lessen the ambipolar conduction of TFET.
The energy band diagram, electric field along the channel direction, barrier width and band-to-band
tunneling generation charge analysis are demonstrated elaborately to explain the structural behaviors
in both ON- and ambipolar-state of TFET. Moreover, performance parameters by channel length
variation of our device are also studied. Artificial heterostructure with underlap structure can be the
best representative of TFET in the ultra low power nano devices.

ACKNOWLEDGMENTS
The authors thankfully acknowledges the support and facilities obtained from the Department of
Electrical and Electronic Engineering (EEE), Bangladesh University of Engineering and Technology
(BUET) during the course of this research work.
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