Welcome to the

Course-Digital System Design

Code-BECE102L
Dr Arun Dev Dhar Dwivedi
Associate Professor, Department of Micro and Nano Electronics
School of Electronics Engineering (SENSE)
Email: arundevdhar.dwivedi@vit.ac.in, adddwivedi@gmail.com
Phone: 8209517661, 9450547267 (WhatsApp)
Cabin-SJT313A11A

Module-5: Design of Sequential

Logic Circuits 1

Design of Counters

Dr. Arun Dev Dhar Dwivedi

Associate Professor (Sr.)
School of Electronics Engineering
Vellore Institute of Technology
 Counters

 A register that goes through a prescribed sequence of states upon the application of
input pulses (clock pulse) is called a counter.

 Two main types of counters

 Ripple (asynchronous) counters

 Synchronous counters

 Ripple counters - Flip flop output serves as a source for triggering other flip flops

 Synchronous counters - All flip flops triggered by a clock signal

 Synchronous counters are more widely used in industry.

Digital Logic Design

Counters
 Counters can be designed to generate any desired sequence of states.
 A divide‐by‐ N counter (mod ‐ N counter) is a counter that goes through a repeated
sequence of N states.
 The sequence may follow the binary count or may be any other arbitrary sequence.
 Counters can also be constructed by means of shift registers.

Applications
 Perform timing functions as in digital watches
 Create time delays
 Generate pulse trains
 Generate timing signals to control the sequence of operations in a digital
system.

Digital Logic Design 4

 Design of synchronous counters

 Number of Flip flops required

 State diagram
 Choice of flip flops & Excitation Table
 Minimal expression
 Logic (circuit) diagram

Digital Logic Design 15-10-2023 5

Seven steps to design a counter (state machine).

• The first step in the design of a state machine (counter) is to

create a state diagram.
• A state diagram shows the progression of states through which the
counter advances when it is clocked.

Digital Logic Design 15-10-2023 6

 Characteristic Table of JK

Step 4. Excitation table of JK

Jo Ko J1 K1 J2 K2

1 X 0 x 0 x

X 0 1 x 0 x

X 1 x 0 0 x

0 X x 0 1 x

1 X x 0 x 0

X 0 x 1 x 0
Digital Logic Design 7 0 x x 0
X 1
0 X 0 x x 1

Step 5:

Digital Logic Design 15-10-2023 8

Step 6:

Step 7:

Digital Logic Design 15-10-2023 9

Synchronous (Parallel) Counters

 Synchronous (parallel) counters: the flip-flops are clocked at the same time by a common clock
pulse.
 Example: 2-bit synchronous binary counter

State Diagram Excitation table

Present Next Flip-flop

state state inputs
00 01 A1 A0 A1+ A0+ TA1 TA0
0 0 0 1 0 1
0 1 1 0 1 1
11 10
1 0 1 1 0 1
1 1 0 0 1 1
 Synchronous (Parallel) Counters
Minimal Expression
Present Next Flip-flop
state state inputs
A1 A0 A1+ A0+ TA1 TA0 TA1 = A0
0 0 0 1 0 1 TA0 = 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1

A0 J A1
J Q Q
C C
Q' K Q'
K

CLK

Synchronous (Parallel) Counters

 Example: 3-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical
J, K inputs).

Present Next Flip-flop

000 state state inputs
111 001 A2 A1 A0 A2+ A1+ A0+ TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
110 010 0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
101 011 0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
100 1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
A1 A1 A1

1 1 1 1 1 1 1
A2 1 A2 1 1 A2 1 1 1 1

A0 A0 A0
TA2 = A1.A0 TA1 = A0 TA0 = 1
Synchronous (Parallel) Counters
 Example: 3-bit synchronous binary counter (cont’d).
TA2 = A1.A0 TA1 = A0 TA0 = 1

001  010  101  111

Digital Logic Design 15-10-2023 14

Step 4. Excitation table of D

D2 D1 D0
0 1 0
1 0 1
1 1 1
0 0 1

Digital Logic Design 15-10-2023 15

Step 5: Step 6:

Step 7:

Digital Logic Design 15-10-2023 16

 Digital Logic Design 15-10-2023 17

Synchronous Up/Down counters

 Up/Down Counter can either count up
or down on each clock cycle

 Up counter counts from 0000 to 1111

and then changes back to 0000

 Down counter counts from 1111 to

0000 and then back to 1111

 Counter counts up or down each clock

cycle

 Output changes occur on clock rising

edge
Digital Logic Design 18
Designing Synchronous Counters
A 3-bit Gray code counter (using JK flip-flops). 000
100 001

101 011

111 010
110
Present Next Flip-flop
state state inputs
Q2 Q1 Q0 Q2+ Q1+ Q0+ JQ2 KQ2 JQ1 KQ1 JQ0 KQ0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 1 0 X 1 X X 0
0 1 0 1 1 0 1 X X 0 0 X
0 1 1 0 1 0 0 X X 0 X 1
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 1 0 0 X 0 0 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 1 X 0 X 1 X 0

Designing Synchronous Counters

 3-bit Gray code counter: flip-flop inputs.

Q 1Q 0 Q 1Q 0 Q 1Q 0
Q2 00 01 11 10 Q2 00 01 11 10 Q2 00 01 11 10
0 0 1 X X 0 1 X X
1
1 X X X X 1 X X 1 X X 1

JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = Q2.Q1 + Q2'.Q1'

= (Q2  Q1)'

Q 1Q 0 Q 1Q 0 Q 1Q 0
Q2 00 01 11 10 Q2 00 01 11 10 Q2 00 01 11 10
0 X X X X 0 X X 0 X 1 X
1 1 1 X X 1 1 X 1 X

KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2.Q1' + Q2'.Q1

= Q2  Q 1
 Designing Synchronous Counters
 3-bit Gray code counter: logic diagram.
JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = (Q2  Q1)'
KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2  Q1

Q0 Q1 Q2
J Q J Q J Q
C C C
Q 1' Q 2'
K Q' K Q' K Q'
Q 0'

CLK

Ring Counter
 It is the special application of Shift register(circular shift register)
 The output of the last FF is given as the input of the first FF.

Digital Logic Design 22

Johnson Counter
 Johnson counter is similar to the ring counter.
 The only difference is the complemented output of the last FF is given as
the input of the first FF

Digital Logic Design 23

Verilog HDL – Up/Down Counter

module up_down_counter(clk,clr,load, up, down, q);
input clk,clr,load, up, down;
output [3:0]q;
reg [3:0]q;

always@(posedge clk)
begin
if(clr)
q <= 4‘b0;
else if (load)
q <= 4‘b0001;
else if(up)
q <= q + 4’b1;
else if(down)
q <= q – 4’b1;
end
endmodule

Digital Logic Design 24

Verilog HDL – Ring Counter
module ringcounter(clk,clr,load, q);
input clk,clr,load;
output [3:0]q;
reg [3:0]q;

always@(posedge clk)
begin
if(clr)
q <= 4'd0;
else
begin
if (load)
q <= 4'd8;
else
q <= {q[0], q[3:1]};
end
end
endmodule

Digital Logic Design 25

Verilog HDL – Johnson Counter

module johnson_counter(clk,clr,load, q);
input clk,clr,load;
output [3:0]q;
reg [3:0]q;

always@(posedge clk)
begin
if(clr)
q <= 4'd0;
else
begin
if (load)
q <= 4'd8;
else
q <= {!q[0], q[3:1]};
end
end
endmodule

Digital Logic Design 26

Thank You!!