A One Zener Diode, One Memristor Crossbar
Architecture for a Write-Time-Based PUF
Timothy Potteiger and William H. Robinson
Security and Fault Tolerance (SAF-T) Research Group
Department of Electrical Engineering and Computer Science
Vanderbilt University, Nashville, TN, USA
Abstract - With the rise of emerging technologies,
nanoelectronics are seen as potential solutions for
various security primitives. Memristors are of interest,
as they are believed to offer benefits for use as a Physical
Unclonable Function (PUF), since their non-linear
behavior is inefficient to model in large quantities. A
write-time-based PUF has been suggested in the form of
a memristor array to avoid the sneak path problem. To
amend this approach, a one Zener diode, one memristor
crossbar architecture may be used. Such an architecture
can virtually eliminate sneak paths in crossbars up to a
size that is limited by the saturation current of the Zener
diode. This approach allows uniformity and uniqueness
among the crossbar, similar to a SRAM-based PUF,
where the uniformity in the response is derived from the
uniformity of the memory cells. Ultimately, this
approach is meant as a beneficial contribution to the
novel and relatively new technique of creating a random
bit distribution among an array of memristors, as it
allows the same technique to be used on a crossbar to
offer an improvement in terms of bits per area.
I. INTRODUCTION
Physical unclonable functions (PUFs) can depend
strongly on the impurities of the components that comprise
them to generate a random bit distribution among the
response bits that is unpredictable [1]. In the case of one
specific SRAM PUF, the impurities of the SRAM are used
to generate a random bit distribution among the memory
cells. A challenge is applied to the SRAM in the form of
memory locations, and the response comprises the values at
those locations [2]. The idea is that if there is a random
distribution among the values in the memory cells, then
using those values as bits in the response will form a
random distribution. In this work, a write-time-based
algorithm is used to generate a random distribution among a
one Zener diode, one memristor (1ZD1M) crossbar
architecture (CBA) to create a PUF synonymous to the
SRAM PUF.
PUFs must exhibit three primary traits. Those traits are
uniformity, uniqueness, and reliability [3]. The need for a
one diode, one memristor crossbar architecture arises
because of a phenomonen noted as a sneak path that occurs
in memristor crossbars. The sneak path reduces the ability to
perform accurate reads and can compromise the essential
trait of uniformity, which is defined as a random bit
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distribution in the response. For this reason, a 1ZD1M CBA
can be used as a solution, since it can allow for accurate
reads from memory cells to ensure uniformity in the
response values. Such an approach has been motivated by
the use of a 1ZD1M CBA for ReRAM devices [4], [5]. This
method is believed to be practical; the Zener diode and the
memristor simulated in this work have a feature size on the
order of tens of nanometers, which would allow for a
1ZD1M CBA to be on the same order of magnitude for size
compared to a memristor crossbar. As for feasibility, the
Zener diode is inorganic. For fabrication, inorganic Zener
diodes can be created using simple means, such as vapor
deposition and printing, that would allow for both mass
production and incorporation into memristor crossbars [6].
The paper is organized as follows. Section II discusses
memristor technology and its use as physically unclonable
functions. Section III discusses the write-time-based
algorithm. Section IV provides the simulation methodology.
Results are discussed in Section V. Finally, Section VI
summarizes the paper.
II. MEMRISTORS AS A PHYSICAL UNCLONABLE FUNCTION
Memristors are one of the core nanotechnologies being
studied for the advancement of secure and efficient systems.
This potential stems from a large set of traits that are
desirable for such purposes that include non-volatility,
power efficiency, and scalability [7]. The basic principle of
the memristor is its memory resistance, or the ability for its
instantaneous resistance at any moment in time to be
dependent on the previous history of the applied voltage.
Thus, if an electric potential is removed from the memristor,
then it will maintain its instantaneous resistance because its
voltage history will remain the same. This is from where the
non-volatile characteristic emerges and allows the concept
of states to be established [7].
With memristors, there are at least two prominent states.
These are: (1) a high resistive state (HRS) and (2) a low
resistive state (LRS). The HRS occurs when the memristor
is off, and a positive pulse is applied to the device for a
required amount of time. The memristance in this state is
classified as Moff. The LRS occurs when the memristor is on,
and a negative pulse is applied to the device for a required
amount of time. The memristance in this state is classified
as Mon [7].
The core memristor-based security primitive is the
physical unclonable function. PUFs can operate as a means
of authentication [8]. With a memristive PUF, there may be
a crossbar of memristors or a single array of memristors. For
a crossbar memristor PUF, there are nano-arrays of
memristors. A challenge is applied to the nano-arrays, and a
response is generated in a repeatable manner. In other
words, there are unique challenge response pairs [8].
The challenge-response mapping has to satisfy three
important constraints. It has to satisfy uniqueness,
reliability, and uniformity [3]. Uniqueness implies that the
challenge-response mapping is unique to each PUF.
Reliability implies that the challenge-response pairs can be
generated in a repeatable manner. Lastly, uniformity implies
that there should ideally be 50 percent ones and 50 percent
zeros in the response string.
III. A WRITE-TIME-BASED ALGORITHM FOR A CROSSBAR
ARCHITECTURE
For the purposes of this paper, the PUF model will
encompass a write-time-based algorithm in order to achieve
a random bit distribution among the memristor cells. This
method works by first setting all of the memristors to a HRS
through the application of a voltage (Vw) of negative polarity
with a greater magnitude than a threshold voltage (Vth). This
is necessary in order for the memristors to change their
resistive values. Otherwise, the memristance will remain
stagnant, and the memristor will act as a linear resistor.
The next step is done by applying a voltage (Vw) of
positive polarity with a greater magnitude than a threshold
voltage (Vth) across all of the memristors for a minimum
write-time. The minimum write-time is the amount of time
needed for a memristor of the expected diameter to
transition from the HRS to the LRS. Choosing this
particular write-time leads to half of the memristors
transitioning to a LRS. The remaining memristors will be in
a near HRS.
The write-time-based algorithm can be successful at
generating a random bit distribution within the memristor
crossbar so long as the columns are grounded. It is during
the read operation that sneak paths appear as a problem.
When sneak paths occur during the read operation, the
randomness is reduced because of false reads. The result is
that the uniformity of the PUF is compromised.
The sneak path problem is defined as the occurance of
the current branhing off of from the desired path. This
phenomenon is inherent to memristor crossbars. For this
reason, the original write-time-based memristor PUF
algorithm was comprised of an array of memristors as
opposed to a crossbar [9]. To allow for accurate reads and
ensure uniformity with a crossbar, the use of a one Zener
diode, one memristor cell layout is proposed. A Zener diode
is used as opposed to a traditional diode; it allows for a
current of either a positive or negative polarity to flow,
which can allow for a transition to a LRS from a HRS and
vice versa during a write operation. For a read operation, a
1ZD1M CBA virtually eliminates sneak paths provided that
the read voltage exceeds the turn-on voltage of the Zener
diode and is less than three times the turn-on voltage of the
2
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Zener diode. This is because the shortest sneak path consists
of three memory cells. When the read voltage exceeds three
times the turn-on voltage of the Zener diode, a sneak path
may be enabled. When the adequate conditions of the read
voltage are satisfied, each sneak path then becomes
equivalent to the Zener diode’s reverse saturation current.
IV. SIMULATION METHODOLOGY
In order to ensure that the analysis led to realistic results,
parameters are chosen that were used in previous literature.
Note that a majority of the following parameters apply to a
write operation via the memristor state transition expression
in Equation 1. The following parameters are chosen: a LRS
of 121 kOhms, a HRS of 121 MOhms, a mean diameter of
50 nm, a diameter variance of 5 percent and 10 percent, Vth
of 1.2 V, and a E0 of 25 MV/m [10]. A reasonable µ is
calculated using the equation including the mobility for
small electric fields [11]. The frequency of escape attempt is
1013 Hz, while a periodicity of 2.068 nm and activation
energy of 0.778 eV are assumed. These values are used to
calculate the mobility for small electric fields [12].
The next matter of importance is to identify just how
prominent the sneak path problem is during a read operation
and how large a memristor crossbar has to be for this
problem to emerge. During a read operation, a voltage is
applied to the row of the memory cell of interest, and a load
resistor is connected to the column of the memory cell of
interest. In this case, the read voltage and load resistance
used are 1 V and 1 kOhm respectively. When the memory
cell of interest is in a HRS, the voltage across the load
resistor is supposed to be smaller than it would be if the
memory cell of interest is in a LRS. This is the mechanism
for distinguishing a logic 0 and vice versa. A read operation
may be compromised when a worst-case scenario for
reading a cell with a HRS leads to a larger load voltage than
a worst-case scenario for reading a cell with a LRS.
A worst-case scenario for a crossbar would usually be
where every cell besides the cell of interest is in the opposite
state of the cell of interest. Yet, it is known that this is not a
possible scenario, as the write operation leads to a high bit
entropy. Hence, the worst-case scenario would occur when
all of the cells in the same row and same column are in the
opposite state of the cell of interest. The remaining cells are
in appropriate states to ensure a 50% bit ratio.
Following the evaluation of a read operation in a
memristive crossbar, the next step is to evaluate the read
functionality for the 1ZD1M CBA. The read function is
performed the same way as with the memristor crossbar.
The only difference is the number of elements in each cell
and the sneak path. A read from a cell is modeled using the
circuit model in Figure 1, where Iread goes to a load resistor.
Vread is 1 V, Rline is 3.356 ohms, and Ron is 500 ohms. The
load across the resistor determines the bit value.

Figure 1: Schematic of a memory cell during read, where N is the number
of rows [4]
For the write simulation, the write voltage is 2 V, and the
read voltage is 1 V. The memristor’s response during the
write operation is calculated using Equations 1 and 2 along
with the parameters in order to arrive at a differential
equation for the voltage across the memristor (Equation 3).
( ) √ ( ( )) (
( ) ∫ (2)
( ∫
( ) ( ) (( ) √
( ∫ ( ) ( )
( √
The memristance itself is the term that is multiplied by
(Vw-Vth). For the Zener diode, the linear model of the Zener
diode is used with a size of 10 nm, a Vth of 0.5 V, Ron of 500
ohm and a saturation current of 1 nA [4]. Also, a line
resistance of 3.356 ohms is used. Various size crossbars are
tested for 1000 iterations at each size to observe the mean
and variance of the percentage of each bit. In addition, the
uniqueness and uniformity are calculated using Equations 4
and 5 at each of the sizes to ensure there is a convergence to
the ideal value of 0.5 for each. In Equation 4, k is the
number of responses taken into account, R is a response, n is
the number of bits per response, and HD is the Hamming
distance. In Equation 5, n is the number of bits in a response
and r is a bit in a response.
( )
∑ ∑
( )
∑ (5)
V. RESULTS AND DISCUSSION
The sneak path problem exhibits signs of possible bit
aliasing during the read operation for crossbars as small as
25 cells (Figure 2). Note that the limiting scenario on the
size of the crossbar appears to be the case of attempting to
read a memory cell that is in a HRS while the memory cells
in the same column and same row are in a LRS.
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Load Voltage to Represent Logic Value (mV)
Worst Case Load Voltage During Read to
Represent Logic Low and High in
Memory Cell of Interest With Respect to Crossbar Size
20
15
10
0
0 10 20 30 40 50 60
Number of Cells in Crossbar
Worst case load voltage to represent logic high
Worst case load voltage to represent logic low
Fit curve for logic low load voltage (R squared = .9927)
Fit curve for logic high load voltage (R squared = .9820)
Figure 2: Graph of the voltage across load resistor while reading from a cell
with a memristor is a LRS (solid) and HRS (dashed). These are worst-case
) (1) scenarios where all of the points under the blue curve represent a 0 and all
of the points under the black curve represent a 1. After a size of 25, there is
a region of intersection for assigning a 1 bit and a 0 bit that could lead to
aliasing.
Equation 6 is used to calculate the current through the
( ) ( ) )
) load resistor using Figure 1. The equation was modeled in
Simulink for a read operation. The Simulink read operation
) simulation successfully showed that a cell in a HRS was
) (3) read as a logic 0, and a cell in a LRS was read as a logic 1.
( ( ) ( ) ( )
( ) ) (6)
From Equation 6, the voltage across the load resistor
while reading from either a HRS cell or a LRS cell can be
computed for various crossbar sizes. Both situations are
graphed in Figure 3, showing that the voltage across the
load resistor during a read operation for either reading a
logic 1 or reading a logic 0 begin to converge when the
scale of the crossbar is about 10,000 cells. This is the point
where distinguishing between a logic 1 and a logic 0
becomes difficult. This point of convergence has been
shown to be related to the Zener diode saturation current,
and a larger-sized crossbar has been shown to be possible
with a smaller saturation current [4].
(4)
3

Figure 3: Graph of the voltage across load resistor while reading from a cell
with a memristor is a LRS (solid) and HRS (dashed). The points on the
blue curve represent a logic 1, and the points on the green curve represent a
logic 0. The convergence can cause difficulty in distinguishing between a
logic 0 and a logic 1.
The write operation is shown in Figure 4 that enables the
memristor to transition from a HRS to a LRS. The dramatic
rate of change towards the end of the transition is an
important trait when considering the write-time-based
algorithm. It ensures that if a memristor is not in a LRS,
then there will be a high chance that the memristor will
exhibit a resistance that is on the same order of magnitude
as its HRS.
In Figure 5, the uniformity is shown to converge to the
optimal value of 50%. In addition, uniqueness is also shown
to be approximately the optimal value of 50%.
Figure 4: Memristor transition from a HRS to a LRS
Uniformity and Uniqueness
51.5
Uniformity Percent
51.0 Uniqueness Percent
50.5
Percent
previous work, a crossbar of diodes has led to a read out of
about 100 bits/s [13]. A PUF greater than 10,000 bits in
such a case would not be ideal with that time constraint. In
summary, the write-time-based PUF on the 1ZD1M CBA
can be used to create uniformity and uniqueness among the
crossbar, which does allow it to be used in a PUF
synonymous to the SRAM based PUF, provided that the
challenge-response pairs can be generated in a repeatable
manner.
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Number of Cells in Crossbar

Figure 5: Graph of uniformity (solid) and uniqueness (dashed) in relation to

the number of cells in the crossbar

VI. SUMMARY
The 1ZD1M CBA is shown via simulation to be
functional. During the write function, the memristor still
exhibits a necessary drop-off closer to a LRS, and the read
function can accurately distinguish between a cell that is in
a HRS and LRS in a crossbar of the size of 10,000 memory
cells. This is fitting as the diode may be a limiting
component in terms of scalability during read operations. In

4
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