This paper describes objective technical results and analysis.

Any subjective views or opinions that might be expressed

in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

SAND2020-10083C

Heterogeneous Integration of Silicon Electronics

and Compound Semiconductor Optoelectronics
for Miniature RF Photonic Transceivers

PRiME

li
1ES IC, .po

FreqUenCy(H,

Christopher D. Nordquist*, Erik J. Skogen, Seth A. Fortuna, ttctober 7 2020

Andrew E. Hollowell, Caroline S. Hemmady, Justine M. Saugen,
Travis Forbes, Michael G. Wood, Matthew B. Jordan, Jaime L.
H01-1833
McClain, Henry Dallo, Stefan M. Lepkowski, Charles R. Alford,
Gregory M. Peake, Andrew T. Pomerene, Christopher M. Long,
Darwin K. Serkland, and Kenneth A. Dean
OENEilGy
Sandia National Laboratories, Albuquerque, NM USA Supported by the Laboratory Directed Research
and Development program at Sandia National
Laboratories, a multimission laboratory
managed and operated by National Technology
Et Engineering Solutions of Sandia, LLC, a wholly
owned subsidiary of Honeywell International
Inc., for the U.S. Department of Energy's
National Nuclear Security Administration under
*cdnordq@sandia.gov contract DE-NA0003525. SAND2020-
 2 Introduction and Outline 4X1 MMI

• What is Heterogeneous Integration (HI)?

SLC capacitors
40s
• Why HI? 4)
os,
,S•ro etc'
5_ELTI
-psi
s'epl

• RF Photonics & Technologies RFIN1

RECEIVER
FIN3
EAM
• HI Approaches Driverl EAM EAM Modulators
Drive 4:1 MMI Combiner

• Lessons Learned SLC capacitors

RFOUT2
• Summary TRANSMITTER
RFIN2
RFOUT4

RFIN4

Ring Filters
RFOUT1
and PDs
RFOUT3
3
What Is Heterogeneous Integration (HI)?

From https://www.semi.org/en/heterogeneous-integration-roadmap
"Integration of separately manufactured parts into a higher assembly (SiP) that, in the
aggregate, provides enhanced functionality and improved operating characteristics."
HI Defines the Space Between Microfabrication and Packaging
Smaller than packaging, but coarser than microelectronics.
Allows integration of different optimized microtechnologies. • gstt,„
•.1 -
HI Challenges in Context of R&D/Prototyping. N./7,.#..
Minimal influence on component supply chain: little opportunity for customization.
High non-recurring costs of process development and dedicated fabrication runs.
Short time scales do not allow for in-depth process development.
R&D sponsors pay for results, not integration.

Objective: Develop HI Processes and Techniques Suitable for a Variety of COTS, Custom, and RaD
Technologies Without Requiring Substantial Development for Each Iteration.
4 HI @ Sandia's MESA Complex
MESA= Microsystems Engineering,Science and Applications

Co-jointed Fab Facility

Silicon Fab
Compound Semiconductor Fab

Non-Profit FFRDC Charter:

Design, develop,fabricate, qualify,
and produce at low-volume for
USG applications
Conduct leading edge research

Currently dozens of products:

ASICs, III-V SSICs, MEMS,FPAs,
RFICs, Optoelectronics
Co-located R&D and Production
https://www.sandia.gov/mesa/

HI Provides the Ability to Integrate Externally-Sourced a Internally Fabricated Technologies

5 Sandia's National Security Photonic Center
www.sandia.gov/
Silicon Fab: Microfab: mstc/nspc
Silicon Photonics Compound Semiconductor
Photonics A member of
wig IN Pr+ ra..1
'
MESA 111111
(Microsystems and Engineering Sciences Application).-
A-11,ii VA
- ptiotorlics

notechnnogy F.

PDK and Center for Integrated NanotechnDlogies (CIN Custom Epitaxial Growth & III-V Devices
8" Multi-Project Wafers (GaAs, InP, GaSb, GaN)
\\ ,/ 60+ Photonics Staff PDK and Multi-Project Wafers (InP)
Device Design, Modeling, Simulation
Semiconductor Device Fabrication
Microsystem Fabrication
Testing, Rad Effects, Cryo
Reliability

Microsystems and Heterogeneous Integration

(Flip Chip Bonding, micro-optics, assembly, packaging)

t-
Si Photonic circuits Photonic circuits Et Lasers
Si Photonics Platform w/ LiNb03 + InP
 6 Outline 4X1 MMI

• What is Heterogeneous Integration (HI)?

SLC capacitors
Zos
• Why HI? 4)
os,
,S•ro etc'
5_ELTI
-psi
s'epl

• RF Photonics & Technologies RFIN1

RECEIVER
FIN3
EAM
• HI Approaches Driverl EAM EAM Modulators
Drive 4:1 MMI Combiner

• Lessons Learned SLC capacitors

RFOUT2
• Summary TRANSMITTER
RFIN2
RFOUT4

RFIN4

Ring Filters
RFOUT1
and PDs
RFOUT3
 Why HI? Electrically Short Interconnect
7

Source/Load Terminated Electrical Link Unterminated Electrical Link

50
Z0=50 0
Long Length
r Must be electrically short

50 Ltrace
*—AAAt—*
i *-1\AAI—* ,fYYL.
1

4110
..1.. ,
I

.1
, 10
50

1
Cload

1Cload

• Typically Used for RF Signaling. • Typically Used for Low-Speed Signals.

• Controlled impedance for arbitrary length
• Less sensitive to parasitic impedance
• But load resistor lowers efficiency and gain.
• Load voltage is half of source voltage
• Continual power consumption at load
r
• Load voltage equals source voltage
• Minimal low-frequency power consumption
• Link is resonant at longer lengths.
• Power consumption increases
• Output voltage drops beyond resonance

Intimate integration from HI can allow high-frequency signaling across unterminated chip-to-chip
electrically short interconnect.
 HI For Electrically Short Interconnect: RF
10 Simulation
8 ••.
oo
.
1 mm wirebond •• ,•
.7 . .•

Interconnect Power (mW)

• Unterminated links should be run below resonance 8 25 pm bump .:
• •
•

V
•
*

• Unterminated bump has lower power consumption A` ••

• 0•o.
at ••
••
•
•
•6

than terminated bump through -20 GHz 6

terminated ...-•:
•Air
••
•.
.
_, . 1, - w w oft. ,----"A.A. oovosoomov . e
• Unterminated bump has higher output voltage than .
o
4 w
1
•
terminated bump through -80 GHz 4
e
•
V
6
li
a
•
a
di a
* al.
2 • ••
•
Terminated Unterminated ..
nterminated 01
..
I
u
..•.-.0 ,f
Structure Wirebond Bump Wirebond Bump 0
1E8 1E9 1E10 1 11
3 dB Freq 17 GHz 85 GHz 20 GHz 30 GHz 5

Interconnect Output Voltage (dB)

Freq(P=5 mW) - - 9 GHz 18 GHz 1 unterminated
0 ......
....
- terminated •........
-5
.. .........
-
-10

__ 1 mm wirebond
-15
25 pm bump

-20
1E8 1E9 1E10 1E11

Frequency (Hz)
HI Enables Low-Power Chip-to-Chip GHz Signaling
 HI For Electrically Short Interconnect: Eye Diagram Models
9 1
5 Gbps 20 Gbps 40 Gbps
0.6 0.13 0.6

0.4 0A

0.2 0.2

0.0
0.0 .t 0.0

-a2 -0.2

1.5 1.5
Wirebond Unteii mated

10 10 10

05- 0.5 05

Wirebond U
00 .2 a0 00

415
0.5 0.6 0.6

Bump Terminated

Bump Terminated
Bu•lip Terminated

04 1) 4

0.2 9.2 02

ao 00 00

-a2 -0.2

1.0 1.5 1.6

Bump Lialerminated
Bump Unteirnmaied

Bump Unlerminated
to_ 1,0
0.5-
0.5- 0.5-
.0
0.0 0.0

-0.5 T - 1. r I 1 FIIFFT[lirli .a5 -0.5

1
!ill !Ili

0 20 40 60 86 100 120 140 160 180 ND 0 10 20 30 5 10 15

Time (psec) lime (psec) Trne (psec)

HI Enables Low-Power Chip-to-Chip Gbps Digital Signaling

 HI For Electrically Short Interconnect: Eye Diagram Models
10 k
5 Gbps 20 Gb 40 Gbps
0.5 0.6

0.4 0.4

0.2 0.2

0.0 0.0

1.5 1.5
Wirebond Un1e i mated

1.0 10

0_5 05

Wirebond U
00
A AL 00

.0.5
Unterminated wirebonds
0.5 barely support 5 Gbps 0.6

Bump Terrnmaled
Bu•lip Terminated

04 4

0.2 02

aa
-a2 • 00

-02

to 1.5

Bump Unlerminated
Bump Unterrnmated

1,0
a5—

-0.5 T r I 1 Ilr r T[lir I

0 20 40 60 80. 100 120 140 160 180 21:10 0 10 20 30 5 10 15 20 25

Time (psec) lime (psec) Trne lpsec)

HI Enables Low-Power Chip-to-Chip Gbps Digital Signaling

 HI For Electrically Short Interconnect: Eye Diagram Models
11 k
5 Gbps 20 Gbps 40 Gbps
0.5 0.6 0.6

0.4 2 a4 0.4

43 0 2
1-
0.2 02

2
0.0 0.0 0.0
Terminated wirebonds—m"

1
-a2 -a2 -0.2

1.5 1.5 Mastruggle w/ 20 Gbps 1.5

Wirebond Unieu iiriziled

42
• ---z...%7--.argamp--
1.0 1.0

11.V
A _
dirr-

Wirebond U
111110
"-.
0.0 2 oo
Unterminated wirebonds Unterminated wirebonds
0.5 barely support 5 Gbps a5
worse ® 20 Gbps 06

ump Terminated

Bump Terminated
Bu•rip ler-minuted

04 04 0 4-

0.2 9.2 02-

aa 00 00

■
-a2 Terminated Et Unterminated -0.2

1.6 1.5
Bumps Good ® 20 Gbps
Bump Untem-imated

Bump Unlerminated
Bump Linierminated

to
a5—
a5— 05-
a
a0 00

-0.5 T 111. 1- 2. [ liri 1 I -0 5 !ill ill !Ill 12

26 40 60 86 100 120 140 160 1E10 ND 10 20 30 5 10 15 20 25

Time (psec) Tme (psec) Trne lpsec)

HI Enables Low-Power Chip-to-Chip Gbps Digital Signaling

 HI For Electrically Short Interconnect: Eye Diagram Models
12 k
5 Gbps 20 Gbps 40 Gbps
0.6 0.6 0.6

0.4 2 0.4 0A

0.2 I— 0.2 02
-2
0.0
.4elibi
1
0.0 .t 0.0

-a2 -a2
Terminated wirebonds—m" -0.2

1.5 1.5 Mastruggle w/ 20 Gbps 1.5

Wirebond Un1e i iiriziled

Wirebond Unlei.iimated
11
1 11 .
1
.
1.0 1.0 1.0

11.V
A 0.5
door- 0.5

0.0 2 oo 00

Unterminated wirebonds Unterminated wirebonds

0.5 barely support 5 Gbps a5
worse ® 20 Gbps 06

Bump Terminated
Bu•lip Terminated

04 04 04
2
9.2 f
0.2 02

aa 00 A, E 00

-a2 • Terminated a Unterminated Terminated Et Unterminated

to
Bumps Good ® 20 Gbps Bumps OK ® 40 Gbps
Bump Linierminated
Bump Unterrnmated

Bump Unlerminated
10
0.5—
0.5- 05
a
0.0 — 00

-0 5 T I 05
0 20 40 60 86 100 120 140 160 180 ND 10 20 30

Time (psec) Tme (psec)

HI Enables Low-Power Chip-to-Chip Gbps Digital Signaling

13 Why HI? Integrated Photonics
Intimately combine electronic and optoelectronic technologies for:
Reduced Size/Weight/Power
Improved electrical/optical performance and interconnect density
Separate Optimization of Electronics and Photonics
Different materials and processes
Monolithic integration requires compromise, even within the same material system

Silicon: high integration, large wafers
• Full suite of passive devices Et modulators
Photonics • Tight dimensional control a high density
• But: No light emitters; requires compounds
• -101° transistors
Low entry cost with multi-project-wafers
Electronics
• Little opportunity for customization
• Limited drive voltage
Silicon Electronics + Silicon Photonics: great
if you have control over both technologies
and/or large development resources
III-V: moderate integration, faster turn
• Full suite of active a passive devices
• Materials Et bandgap engineering
• Planar and vertical light emitters (lasers)
• -104 transistors
• Higher Performance Materials
• Limited digital capability
• Higher drive voltage
'0'
III-V Electronics + III-V Photonics: somewhat
lower cost of infrastructure, but moderate
levels of integration
14 Why HI For Photonics? Combine The Best Technologies
Use HI to combine the best devices from each quadrant

131111111; 1:11: It' t t.“

Itii;1 glIllmuu .1
1 I
Silicon: high integration, large wafers Ill-V: moderate integration, faster turn
Lasers, gain, bandgap engineering
Very high density filters Et gratings
Photonics Higher performance materials
Minature high-impedance modulators
High-efficiency Photovoltaics

Single-chip digital, analog, RF, signal processing High-power voltage RF/optical drivers
Electronics i Direct interface with FPGA/memory/processor High-voltage point-of-load power conditioning 1

And don't forget:

RF Passives
AIN modulator platform
MEMS: RF, Optical, Sensors, Actuators
LiNb03 and other unique optical and electrical materials & devices
15
HI Starting Point: III-V Photonics + Si CMOS
Develop HI approaches with two technologies for demonstration

Silicon III-V
InGattsP/InP Photonic Integrated Circuit
Custom SNL Fabrication
Lasers
Modulators
Photonics Future Expansion
Combiners
Drop Filters
Photodiodes
Couplers

180 nm Silicon CMOS RF Integrated Cir uits

Accessible through MPW foundry
Capable through S-band
Electronics Potential for digital Et logic capability Future Expansion
Scalable to smaller nodes Et higher frequency
1.8V / 3.3V interface voltage
16 Outline 4X1 MMI

• What is Heterogeneous Integration (HI)?

SLC capacitors
Zos
• Why HI? 4)
os,
,S•ro etc'
5_ELTI
-psi
s'epl

• RF Photonics & Technologies RFIN1

RECEIVER
FIN3
EAM
• HI Approaches Driverl EAM EAM Modulators
Drive 4:1 MMI Combiner

• Lessons Learned SLC capacitors

RFOUT2
• Summary TRANSMITTER
RFIN2
RFOUT4

RFIN4

Ring Filters
RFOUT1
and PDs
RFOUT3
 1 RF Photonic Application: Multiplexed Radio-Over-Fiber
17
Modulator
Driver
Channelizing Filter

Through
Antenna
Elements 1.- - Drop

0
Driver NJ
Amplifiers 1.55 1.551 1.552 1.553 1.554 1.555
n Wavelength(pm)
RF1 RF2 RF3 RFN Optical
A1 RF1
Fiber
RECEIVER
A.2 RF2
Drop Filters
Lasers A.3 RF3
=N
Optical
xi„ Optical Combiner. IÀn RF
Modulators A.N RFN
Photodiodes
TRANSMITTER Transimpedance
Amplifiers

RF Beamforming and
Receiver Electronics
Laser
Photodiode
Rear Mirror Front Mirror
Phase Electroabsorption Modulator
18 InGaAsP/InP Multi-Wavelength Photonic Integrated Circuits
• Fabricated with multiple epitaxial growths & re-growths on InP substrate
• -1550 nm wavelength
• State-of-the-art discrete photonic component performance from a single chip
• Light generation, modulation, amplification, routing, switching, detection

SOA PD CAP CAP

Active Devices Passive Devices

DBR Laser Waveguide

output
—> SOA Turning mirror
NOTE
PDO8X EAM MMI
EA3X27
PD DBR mirror
input DBR Laser EAM Resistor
WG Resistor

High-Psat SOA, MZM Capacitor

Passive WG
ti Phase modulator

411111111111ivol

DBR Laser EAM High-gain SOA

 19 Multi-Project-Wafer (MPW) CMOS Electronics
• MPW runs have made CMOS electronics
accessible for a low cost of entry...
• MPW run: —$5Ok
• Dedicated run: —$300k+ 1
• Custom process: —$M's
• But minimal customization...
• No full wafers: only get —mm-square chips
• Al-based bondpads are optimized for
wirebonding: solder doesn't wet Al
• Forget about adding steps or processes
n

1
25
20
15
10
5
0
-Gain (dB)
-Retum Loss(dB)
25
20
15
10
it

..,•••••:••••:. • •
'c''-.'t'7.7•• •

• u 1
o
5 T, Driver
10
15
20
Zload = 100 // 200 fF
-25 25
0 0.5 1 1.5 2 2.5 3 3 5 4 45 5
Frequency(GHz) 2 mm
20 Outline 4X1 MMI

• What is Heterogeneous Integration (HI)?

SLC capacitors
Zos
• Why HI? 4)
os,
,S•ro etc'
5_ELTI
-psi
s'epl

• RF Photonics & Technologies RFIN1

RECEIVER
FIN3
EAM
• HI Approaches Driverl EAM EAM Modulators
Drive 4:1 MMI Combiner

• Lessons Learned SLC capacitors

RFOUT2
• Summary TRANSMITTER
RFIN2
RFOUT4

RFIN4

Ring Filters
RFOUT1
and PDs
RFOUT3
21
Flip-Chip Interconnect Scaling
MPW Chips Are
"Sweet Spot" Currently Limited
Diminishing Move MPW chips towards
-50 pm pitch bumps fine-pitch flip chip to Wirebonding
returns for this
1
application at
very fine pitch,
but good for FPAs 411lie / ‘/
Et stacked ASICs
.41M.
tki!
✓
S4890 3.0kV K3.00k SE(M)

"KO IS .1 Sp SE LiSql.1. No"

SUN 3 C.D. •S • ON SE

Interconnect Pitch
DBI Bonding Indium Bumps Cu and Au pillars Solder Bumps Et Wirebonds

10 pm 25 pm 100 pm All images courtesy of

Sandia MESA teams
 22
ENIG/ENEPIG Deposition for Underbump Metal
3. A temporary epoxy mounting compound (EMC) used for
1. As received MPW die with AICu bond pads batch level under bump metallurgy(UBM)deposition
Temporary Die Bonding
Polyimide
Nitride AICu Bond Pad „, .m•FlEmo,

Oxide I 1

Epoxy Mounting Compound (EMC)

Die alignment marks

Exposed S' disrupts ENIG/ENEPIG electroless Carrier Wafer
deposition and must be passivated

4. Electroless UBM deposition.

2. Flip die upside down onto carrier wafer and ENEPIG = electroless Ni, electroless Pd, immersion Au.
deposit 1 pm CVD TEOS to passivate exposed Si
ENEPIG
Zincate AICu AICu Pads Zn + Ni
•••
followed by
ENEPIG UBM
i
l1=M___,
q. —. — _ —

Carrier Wafer EPOxy Illauralno Comm.:1(0.K)

earner, Wafer

ilr

AICu Bond Pad

5. Solvent release die from EMC and die are ready for flip
7
Oxide —I* =
11 1- chip bonding using thermocompression, pillars, or solder
Gold

• 10% thickness coverage on sidewall Palladium

Nickel
• No temporary bonding media necessary
• Potentially compatible with non-Si technologies Zincated AICu

(e.g. AIGaN, GaN, GaAs)

Hollowell, et al, "Die Level Microbumping and Flip Chip Bonding for MPW Die, SAND2019-3599C
https://www.osti.gov/biblio/1639613-die-level-microbumping-flip-chip-bonding-mpw-die
 23
Flip-Chip Bonding of MPW Die
• After Underbump Metal is Deposited, Different Flip-Chip Approaches May Be Used
Bond to solder-capped copper Approaches plannedfor this integration
1
or gold pillar on interposer
Thermocompression Bond Bond with jetted solder balls 1 1
MPW Die ENIG UBM
to gold bump on interposer
1 or carrier
SnAg solder HDI
==j

Interposer -

Cu Pillar Solder
Ball

Interposer

S4800 10 OkV x1 80k SE(U) 30 u 11

MPW Die

10 pm
AICu
ECD SnAg
Passivation
30 pm
ECD Cu Pillar ENEPIG UBM

S3400 15.0kV 11.8mm x1 50k SE 3/15/2019 30.0um ECD Au bump

S4800 10.0kV x9.00k SE(U, n
Hollowell, et al, "Die Level Microbumping and Flip Chip Bonding for MPW Die, SAND2019-3599C
https://www.osti.gov/biblio/1639613-die-level-microbumping-flip-chip-bonding-mpw-die
24
Flip-Chip Bonding: Test Structures 0

• Test structures to evaluate 80 gm ball, 160 gm pitch

density and yield of solder balls & 50 p.m ball, 701..tm pitch
pillars in the context of MPW die
assembly

11111111P 411
• • •

• • • .
• • • • • • . • • •

• • • • • • • • • • • •

RF Test Structures
RFIC Flip-Chip Landing Structures 111111111111
 25
I What About Passives?
• Passives are required for de-
coupling, matching, and power
supplies.
• Good passives (Resistors,
Capacitors, Inductors) are hard
to integrate on-chip, so they go
on the PCB.
• State-of-the-art SMT
components are large but
difficult to assemble and
integrate.
• Possible Solutions:
• Integrate onto interposer
• Flip-chip integration onto die
• Wirebond in thin-film
components
Wirebonded Single-Channel Optical Transmitter
A single capacitor takes up
almost as much area as an
entire integrated circuit
1 - 1
The inductor is even bigger
1
.The Microelectronics are here.
1
1,The rest of the board area is
spent on R, L, C's
I
The actual useful active
electronics & photonics only
take up these small areas
8 mm
 26
Miniature Four-Channel WDM RF Photonic Link
• HI Approaches will allow a four-channel RF photonic link within the same volume as the single-
channel wirebonded transmitter.
• Integration platform is the InP photonic substrate: all optical interfaces are on-chip.
• Passives are either moved on-chip, eliminated with close interconnect, or wirebonded.
SLC capacitors
zes Four-Channel RF Photonic
los (4".7 Transmitter/Receiver Link
zos
zoss,0,5? et.?
Single-channel Driver + EAM (to scale) RECEIVER
RFIN1
A/
A,FIN3

Driverl EAM EAM Modulators

Driver3 4:1 MMI Combiner
SLC capacitors

RFOUT2
► TRANSMITTER RFOUT4
RF1N2
1044,
RF1N4 .1111110
!V,
*(t

RFOun
Ring Filters
and PDs
RFouT3
27 Outline 4X1 MMI

• What is Heterogeneous Integration (HI)?

SLC capacitors
Zos
• Why HI? 4)
os,
,S•ro etc'
5_ELTI
-psi
s'epl

• RF Photonics & Technologies RFIN1

RECEIVER
FIN3
EAM
• HI Approaches Driverl EAM EAM Modulators
Drive 4:1 MMI Combiner

• Lessons Learned SLC capacitors

RFOUT2
• Summary TRANSMITTER
RFIN2
RFOUT4

RFIN4

Ring Filters
RFOUT1
and PDs
RFOUT3
 28
HI: Lessons Learned
• There are a lot of things to coordinate, all with different schedules.
• Different teams (+ vendors) w/ different expertise, cultures, and design/fab/test cycles & schedules.
• Mitigate risk & reduce "serial" dependencies with modeling, test structures, pre-development, etc.
• Pay attention to early co-design of the physical and electrical interfaces.
• CMOS & optoelectronics make different assumptions: clarify the interfaces early.
• Negative voltages, unusual impedances, device model compatibility, biasing, etc.
• Don't forget about connectors and interfaces for electrical/optical power/signals
• 10x as many chips - 10x as many connections
• Must have passives for biasing, tuning, de-coupling, etc.
• HI has less appeal if the inductor/capacitor is as big as the integrated circuit.
• Affordable & accessible multi-layer high-density interposers are an R&D gap.
• HI needs -10 pm; PCBs struggle for -100 pm; vias make it worse.
• Most capability is focused on high-volume commercial product.
• Don't make things harder than they need to be...
• Only shrinking to 50 pm: avoid challenges of very high density flip-chip.
• Optical interfaces are on InP chip: avoid -dB losses and precision alignment.
• Separate device process flows: avoid multiplying yield fallout & adding cycle times & long ($) development.
 29
Conclusions

• SNL is developing an ecosystem that allows intimate integration of COTS and foundry technologies.
• Electronics: Existing Si/GaAs/GaN die from vendors, Custom Si/GaAs/GaN MPW die from foundries.
• Photonics: III-V surface-normal or planar optoelectronics, Integrated Si photonics.
• Passives: SMT components, integrated passive die, magnetics, antennas, sensors, etc.
• Emerging Technologies: MEMS, NEMS, nanotechnologies, phase-change, multi-ferroics, etc.
• For R&D prototyping, MPW die-level bumping and handling is required.
• Move from mm-length bondwires and —100 pm pitch to smaller pads and bumps.
• —50 pm-pitch bumps can support unterminated interconnect to 80 Gbps.
• HI has the potential to enable order-of-magnitude SWaP improvement for integrated photonics.
• Reduce size from "book-sized" to "matchbox-sized".
• Open more application and insertion opportunities
 Heterogeneous Integration of Silicon Electronics
and Compound Semiconductor Optoelectronics
for Miniature RF Photonic Transceivers

PRiME

li
1ES IC, .po

FreqUenCy(H,

Christopher D. Nordquist*, Erik J. Skogen, Seth A. Fortuna, ttctober 7 2020

Andrew E. Hollowell, Caroline S. Hemmady, Justine M. Saugen,
Travis Forbes, Michael G. Wood, Matthew B. Jordan, Jaime L.
H01-1833
McClain, Henry Dallo, Stefan M. Lepkowski, Charles R. Alford,
Gregory M. Peake, Andrew T. Pomerene, Christopher M. Long,
Darwin K. Serkland, and Kenneth A. Dean
OENEilGy
Sandia National Laboratories, Albuquerque, NM USA Supported by the Laboratory Directed Research
and Development program at Sandia National
Laboratories, a multimission laboratory
managed and operated by National Technology
Et Engineering Solutions of Sandia, LLC, a wholly
owned subsidiary of Honeywell International
Inc., for the U.S. Department of Energy's
National Nuclear Security Administration under
*cdnordq@sandia.gov contract DE-NA0003525. SAND2020-