Module EA 234

CADENCE LAB

Design of an LC oscillator
In a 350nm CMOS Technology

T. Taris, N. Deltimple
Bx-INP, Talence, France
 LC Oscillator Design

NOTES

Bring your Lab Booklet from the last year: EA116, Formation
Cadence, Projet CAN with Mme Deltimple or Mr Taris

2
 LC Oscillator Design

INTRODUCTION

This Lab is dedicated to the design and the characterization of an

LC cross-coupled oscillator in a 350nm CMOS Technology with
Cadence Virtuoso according the schematic proposed below.
A “step by step” design flow is proposed for the implementation
of the LC oscillator combing hand writing derivations and circuit
simulations to address the targeted specifications reported in the
table.
Vdd
L L

out+ out-

Vdd
M1a M1b

Ibias

Ibias

M2 M3

Targeted Specifications
VDD (V) 3.3
Vout_pp (V) 4
Phase Noise (dBc/Hz) -110@1MHz
Current consumption (mA) 5
Frequency (MHz) 433

3
 LC Oscillator Design

NOTES

-Real Inductor-
Any real inductor features some losses limiting its quality factor (QL). The
inductor losses are modeled by a serie resistance rL. The quality factor is
conventionally defined as:
|#!$|
𝑄! = %!

-LC resonator basics-

In an LC-based oscillator, the resonant frequency of the LC tank defines
the oscillator frequency.
Due to the low-quality factor of silicon integrated inductors, the losses of
the tank are dominated by the inductor losses. At the resonant frequency (f0),
the losses of the tank (RT) are defined as:

𝑅& = 𝑄! . |𝑗𝐿𝜔' |

-Device Choice-
Passive Devices
Library Analog Lib >> ind, cap
Generators & Sources
Library Analog Lib >> psin

-Simulations-
S-param (“sp”) analysis : select the “port” and the “frequency range”
for simulation
 LC Oscillator Design

I.RESONNATOR STUDY

rL QL>>1
inductor RT L Ztank
L C C

1/ Evaluate the inductor losses rL for the following case: L=10nH & QL = 20

2/ Determine the value of the capacitor C to resonate the tank at the targeted
frequency:

3/ Determine the tank losses RT at the targeted frequency:

4/ Simulate the resonnator according the proposed schematic and compare

the theoretical results with your estimations
Z11

L C

5
 LC Oscillator Design

NOTES

-NMOS transistor in Saturation-

*
𝐼() = 𝐾) . (𝑉+, − 𝑉&) )-
!
-.0"# *
𝑔.) = = 2. 𝐾) . (𝑉+, − 𝑉&) )
(2$% 32&# ) !

-Technology Parameters-

Technology Parameters
350nm CMOS Process
VDD 3.3V
Lmin 350nm
KN 55 uA/V2
KP 24 uA/V2
lN (SI) 0.12 V-1(0,27)
lP (SI) 0.20 V-1 (0,50)

-Device Choice-
Active Devices in Library: PRIMLIB >> nmos4
Passive Devices in Library: Analog Lib >>ind, res, cap
Generators & Sources in Library: Analog Lib >> vdc,idc

-Simulations-
- Tran analysis: field time must cover at least 20 periods (at least) of
oscillation to account for oscillator start up and settling time
- PSS analysis: the fields “beat frequency” and “number of harmonics”
must verify
“beat frequency” x “number of harmonic” = fosc x N
with N an integer (typ. 4, 5…,10)
- If your oscillator does not start:
ADE window>>Simulation>>Convergence Aids>>Initial Conditions
Select an Output node in the schematic window

6
 LC Oscillator Design

II.LC OSCILLATOR STUDY

Vdd
L L

C
Ztank at f0

out+ out-

Zc-c at f0
Vdd
M1a M1b

Ibias

Ibias

M2 M3

1/ Determine the theoretical transconductance (gmstart) of M1 to start the

oscillator.

In practice the gm1 is set to twice the gmstart to compensate for additional losses
and to ensure oscillation start up.
2/ Define Ibias as a function of gm1 and (VGS-VTN).
àEstimate Ibias if (VGS-VTN)»300mV

3/ Estimate W1, W2 and W3 if L1=L2=L3=Lmin=350nm

7
 LC Oscillator Design

NOTES

-Differential Output Amplitude-

For low to moderate output amplitude Mai behaves as a current source.
Hence Ibias current is equally splitted between Ma1 and Ma2. The peak-to-peak
output amplitude is given by:

4 I<:=>
V567_9:;; = 2. . . (Q ? . ω5>@ . L)
π 2

-Phase Noise-
The phase noise of an LC oscillator can be estimated in the thermal noise
region by:
<latexit sha1_base64="DBX7pTkpOTWUGZMCZYtN+aAGs1Q=">AAADUnicjVFNb9QwFHzZ8FFCoQucEJeoK6TdA1GyIOCCVFQOHBDaSt22UtNGTtbZWuvEUeIgVZZ/Av8OCfEP4MyNE8+uixYqBI6SjOfNjP3svOGsk3H8xRv4167fuLlxK7i9eefu1vDe/YNO9G1B54Xgoj3KSUc5q+lcMsnpUdNSUuWcHuarXVM//EDbjol6X5439KQiy5qVrCASqWz4cfZ+rNI3lEuSioouiZ68ClSgnq72dZAKtAbqdaYWrCyfiF7q02k03sveRRfiTImu0NFupiSpV3qiA43mlNNSYuqa5FfW+lKulLZseSYnp9NAZ8NRHMV2hFdB4sAI3JiJ4WdIYQECCuihAgo1SMQcCHT4HEMCMTTInYBCrkXEbJ2ChgC9PaooKgiyK/wucXbs2BrnJrOz7gJX4fi26AzhMXoE6lrEZrXQ1nubbNi/ZSubafZ2jv/cZVXISjhD9l++S+X/+kwvEkp4aXtg2FNjGdNd4VJ6eypm5+FaVxITGuQMXmC9RVxY5+U5h9bT2d7N2RJb/2qVhjXzwml7+GZ2iRec/HmdV8HBNEqeR8nes9FO7K56Ax7BNozxPl/ADryFGcwx+7v30Nv2RoNPgx++5/sX0oHnPA/gt+Fv/gRyasHd</latexit>

✓ ◆2
3kT !osc
P N ( !) =
A2dif f out .(QL .!osc .Ctank ) !osc

-Simulations-
- noise analysis (“pnoise”): see Annex 2 to fill in the fields

8
 LC Oscillator Design

III.OSCILLATOR PERFORMANCE
1/ Estimate the theoretical (differential) output amplitude of the oscillator
à Compare with a transient or PSS simulation

2/ Estimate the Phase Noise (PN) at 1MHz

à Compare with a PSS simulation
3/ Complete the table

@433MHz Specification Theory Simulations

VDD V 3.3

Vout_pp V 4

PN @ 100kHz dBc/Hz -110

Ibias mA 5

L nH -

C pF -

RT Ohm -

9
 LC Oscillator Design

Annex 1: “PSS” Analysis Set Up

10
 LC Oscillator Design

Annex 2: “pnoise” Analysis Set Up

11