Universidad Autónoma de Nuevo León

Facultad de Ingeniería Mecánica y Eléctrica

Laboratorio de Microcontroladores
Hoja de especificaciones MC

Practica N°1

Prof: Ing. Efren Ivan Tinoco Vazquez

Luis Eliezer González Cano 1618200

Mierocles – N2

7/9/22
Freescale MC9S12T64

The HCS12 CPU is a high-speed, 16-bit processing unit. It has full 16-bit data paths and wider
internal registers (up to 20 bits) for high-speed extended math instructions. The instruction set is a
proper superset of the M68HC11instruction set. The HCS12 CPU allows instructions with odd byte
counts, including many single-byte instructions. This provides efficient use of ROM space. An
instruction pipe buffers program information so the CPU always has immediate access to at least
three bytes of machine code at the start of every instruction. The HCS12 CPU also offers an
extensive set of indexed addressing capabilities

 CPU
The Core CPU12 programming model, shown in Figure 2, is the same as that of the 68HC12
and 68HC11. The register set and data types used in the model are covered in the
subsections that follow.

General-purpose 8-bit accumulators A and B hold operands and results of operations.

Some instructions use the combined 8-bit accumulators, A:B, as a 16-bit double
accumulator, D, with the most significant byte in A
Most operations can use accumulator A or B interchangeably. However, there are a few
exceptions. Add, subtract, and compare instructions involving both A and B (ABA, SBA, and
CBA) only operate in one direction, so it is important to verify that the correct operand is
in the correct accumulator. The decimal adjust accumulator A (DAA) instruction is used
after binary-coded decimal (BCD) arithmetic operations. There is no equivalent instruction
to adjust accumulator B.

16-bit index registers X and Y are used for indexed addressing. In indexed addressing, the
contents of an index register are added to a 5-bit, 9-bit, or 16-bit constant or to the
contents of an accumulator to form the effective address of the instruction operand.
 Having two index registers is especially useful for moves and in cases where operands
from two separate tables are used in a calculation

 Memoria
This section describes the Flash EEPROM module which is a 64k byte Flash (Non-Volatile)
Memory. The Flash array is organized as 2 blocks of 32k bytes. Each block is organized as
512 rows of 64 bytes. The Flash block’s erase sector size is 8 rows (512 bytes). The Flash
memory may be read as either bytes, aligned words or misaligned words. Read access
time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words.
Program and erase functions are controlled by a command driven interface. Both sector
erase and mass erase of the entire 64k byte Flash block are supported. An erased bit reads
‘1’ and a programmed bit reads ‘0’. The high voltage required to program and erase is
generated internally by on-chip charge pumps. All Flash blocks can be programmed or
erased at the same time, however it is not possible to read from a Flash block while it is
being erased or programmed. The Flash is ideal for program and data storage for single-
supply applications allowing for field reprogramming without requiring external
programming voltage sources
 Interfaces
The MEBI sub-block of the Core serves to provide access and/or visibility to internal Core
data manipulation operations including timing reference information at the external
boundary of the Core and/or system. Depending upon the system operating mode and the
state of bits within the control registers of the MEBI, the internal 16-bit read and write
data operations will be represented in 8-bit or 16-bit accesses externally. Using control
information from other blocks within the system, the MEBI will determine the appropriate
type of data access to be generated.

The Serial Peripheral Interface module allows a duplex, synchronous, serial

communication between the MCU and peripheral devices. Software can poll the SPI status
flags or the SPI operation can be interrupt driven

The Serial Peripheral Interface includes these distinctive features:

• Master mode and slave mode
• Bi-directional mode
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Double-buffered operation
• Serial clock with programmable polarity and phase
• Control of SPI operation during wait mod

 Puertos
The Port Integration Module establishes the interface between the peripheral modules
and the I/O pins for all ports except A, B, E and K. Ports A, B, E and K are handled by the
HC12 multiplexed bus interface, due to their tight link with the external bus interface and
special modes. The 8-bit port associated with the ATD is included in the ATD module due
to their sensitivity to electrical noise, requiring special care on routing and design. This
section covers port T connected to the timer module, the serial port S associated with 2
SCI and 1 SPI module and port P connected to the PWM. Each I/O pin is associated with a
set of registers which configure items like input/output selection, drive strength reduction,
and pull resistors enable and selection.

The port integration module is device dependant which is reflected in its naming.

A standard port has the following minimum features:

• Input/output selection
• 5V output drive with two selectable drive strength
• 5V digital and analog input
• Input with selectable pull-up or pull-down device Optional features:
• Open drain for wired-or connections
 Convertidores
The ATD module is an 8-channel, 10-bit, multiplexed input successive approximation
analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. The
block is designed to be upwards compatible with the 68HC11 standard 8-bit A/D
converter. In addition, there are new operating modes that are unique to the HC12 design.
There is software programmable selection between performing single or continuous
conversion on a single channel or multiple channels. The conversion modes for the ATD
module are defined by the settings of three control bits and three control values. The
control bits are ETRIGE in ATDCTL2, and MULT, SCAN in ATDCTL5. In brief, ETRIGE controls
whether an external trigger is used to start a conversion sequence. MULT controls
whether the sequence examines a single analog input channel or scans a number of
different channels. SCAN determines if sequences are performed continuously. The
control values are bits CC/CB/CA in ATDCTL5 which define the input channels to be
examined; S8C/S4C/S2C/S1C in ATDCTL3 define the number of conversions in a sequence;
SMP0/SMP1 in ATDCTL4 define the length of the sample time.
PIC PIC18F2455/2550/4455/4550

 CPU
PIC18F2455/2550/4455/4550 devices include several features intended to maximize
reliability and minimize cost through elimination of external components. These are: •
Oscillator Selection • Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator
Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Fail-
Safe Clock Monitor • Two-Speed Start-up • Code Protection • ID Locations • In-Circuit
Serial Programming The oscillator can be configured for the application depending on
frequency, power, accuracy and cost.

In addition to their Power-up and Oscillator Start-up Timers provided for Resets,
PIC18F2455/2550/4455/4550 devices have a Watchdog Timer, which is either
permanently enabled via the Configuration bits or software controlled (if configured as
disabled). The inclusion of an internal RC oscillator also provides the additional benefits of
a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background
monitoring of the peripheral clock and automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed almost immediately on start-up, while
the primary clock source completes its start-up delays. All of these features are enabled
and configured by setting the appropriate Configuration register bits.

 Memoria
The Flash program memory is readable, writable and erasable, during normal operation
over the entire VDD range. A read from program memory is executed on one byte at a
time. A write to program memory is executed on blocks of 32 bytes at a time. Program
memory is erased in blocks of 64 bytes at a time. A Bulk Erase operation may not be issued
from user code. Writing or erasing program memory will cease instruction fetches until
the operation is complete. The program memory cannot be accessed during the write or
erase, therefore, code cannot execute. An internal programming timer terminates
program memory writes and erases. A value written to program memory does not need to
be a valid instruction. Executing a program memory location that forms an invalid
instruction results in a nop.

In order to read and write program memory, there are two operations that allow the
processor to move bytes between the program memory space and the data RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)
The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table
reads and table writes move data between these two memory spaces through an 8-bit
register (TABLAT).

Table read operations retrieve data from program memory and place it into the data RAM
space. Figure 6-1 shows the operation of a table read with program memory and data
RAM.

Table write operations store data from the data memory space into holding registers in
program memory. The procedure to write the contents of the holding registers into
program memory is detailed.

Table operations work with byte entities. A table block containing data, rather than
program instructions, is not required to be word-aligned. Therefore, a table block can start
and end at any byte address. If a table write is being used to write executable code into
program memory, program instructions will need to be word-aligned.
 Interfaces

 Puertos
Depending on the device selected and features enabled, there are up to five ports
available. Some pins of the I/O ports are multiplexed with an alternate function from the
peripheral features on the device. In general, when a peripheral is enabled, that pin may
not be used as a general purpose I/O pin.

Each port has three registers for its operation. These registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the device)
• LAT register (output latch) The Data Latch register (LATA) is useful for readmodify-write
operations on the value driven by the I/O pins.

A simplified model of a generic I/O port, without the interfaces to other peripherals.
 Convertidores
The Analog-to-Digital (A/D) converter module has 10 inputs for the 28-pin devices and 13
for the 40/44-pin devices. This module allows conversion of an analog input signal to a
corresponding 10-bit digital number.

The module has five registers:

• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)

The ADCON0 register, shown in Register 21-1, controls the operation of the A/D module.
The ADCON1 register, shown in Register 21-2, configures the functions of the port pins.
The ADCON2 register, shown in Register 21-3, configures the A/D clock source,
programmed acquisition time and justification.

 Aplicaciones

Control de pantallas alfanuméricas LCD

Los microcontroladores son especialmente útiles para controlar con muchísima facilidad
los displays de cristal liquido LCD.

Control de teclados
En muchas aplicaciones se requieren teclados especiales que se adapten exactamente a
ciertas necesidades. Los PicMicro se puedan utilizar para realizar secuencias de rastreo y
así saber que tecla se ha oprimido

Control de temperatura
Gracias a que los PIC incluyen convertidores Analógico / Digitales el control de variables
como Temperatura, Presión Flujo puede realizarse con circuitos sumamente simples. Con
unas cuantas resistencias y un buen sensor de temperatura se puede hacer un Termostato
o un controlador de Flujo.
LPC

LPC2458

 CPU
NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2458 has 512 kB of on-chip high-speed flash memory. This flash
memory includes a special 128-bit wide memory interface and accelerator architecture
that enables the CPU to execute sequential instructions from flash memory at the
maximum 72 MHz system clock rate. This feature is available only on the LPC2000 ARM
microcontroller family of products. The LPC2458 can execute both 32-bit ARM and 16-bit
Thumb instructions. Support for the two instruction sets means engineers can choose to
optimize their application for either performance or code size at the sub-routine level.
When the core executes instructions in Thumb state it can reduce code size by more than
30 % with only a small loss in performance while executing instructions in ARM state
maximizes core performance.

The LPC2458 microcontroller is ideal for multi-purpose communication applications. It

incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed
Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two Controller Area
Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I2C
interfaces, and an I2S interface. Supporting this collection of serial communications
interfaces are the following feature components; an on-chip 4 MHz internal precision
oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for Ethernet,
16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an External
Memory Controller (EMC). These features make this device optimally suited for
communication gateways and protocol converters. Complementing the many serial
communication controllers, versatile clocking capabilities, and memory features are
various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external
interrupt pins, and up to 136 fast GPIO lines. The LPC2458 connects 64 of the GPIO pins to
the hardware based Vector Interrupt Controller (VIC) that means these external inputs can
generate edge-triggered interrupts. All of these features make the LPC2458 particularly
suitable for industrial control and medical systems.

 Memoria
The LPC2458 incorporates 512 kB flash memory system. This memory may be used for
both code and data storage. Programming of the flash memory may be accomplished in
several ways. It may be programmed In System via the serial port (UART0). The application
program may also erase and/or program the flash while the application is running,
allowing a great degree of flexibility for data storage field and firmware upgrades.

The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to
allow it to operate at speeds of 72 MHz.

The LPC2458 includes a SRAM memory of 64 kB reserved for the ARM processor exclusive
use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16
bits, and 32 bits.

A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM
associated with the second AHB can be used both for data and code storage. The 2 kB RTC
SRAM can be used for data storage only. The RTC SRAM is battery powered and retains the
content in the absence of the main power supply.

The LPC2458 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the
ARM7 local bus for closely coupled, high-speed access to the majority of on-chip memory,
the AMBA AHB interfacing to high-speed on-chip peripherals and external memory, and
the AMBA APB for connection to other on-chip peripheral functions. The microcontroller
permanently configures the ARM7TDMI-S processor for little-endian byte order. The
LPC2458 implements two AHB in order to allow the Ethernet block to operate without
interference caused by other system activity. The primary AHB, referred to as AHB1,
includes the VIC, GPDMA controller, and EMC.

The second AHB, referred to as AHB2, includes only the Ethernet block and an associated
16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a
bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or
unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function,
and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2
are the ARM7 and the Ethernet block.

AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB ARM
memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB
address space. Lower speed peripheral functions are connected to the APB. The AHB to
APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a 2 MB range
of addresses, beginning at the 3.5 GB address point. Each APB peripheral is allocated a 16
kB address space within the APB address space

The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed complex
 instruction set computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory

 Interfaces
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The Host Controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
Host Controller.

 Puertos
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers.
Pins may be dynamically configured as inputs or outputs. Separate registers allow setting
or clearing any number of outputs simultaneously.

The value of the output register may be read back as well as the current state of the port
pins. LPC2458 use accelerated GPIO functions:
• GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing
can be achieved.
• Mask registers allow treating sets of port bits as a group, leaving other bits unchanged.
 • All GPIO registers are byte and half-word addressable.
• Entire port value can be written in one instruction.

Additionally, any pin on port 0 and port 2 (total of 64 pins) that is not configured as an
analog input/output can be programmed to generate an interrupt on a rising edge, a
falling edge, or both. The edge detection is asynchronous, so it may operate when clocks
are not present such as during Power-down mode. Each enabled interrupt can be used to
wake the chip up from Power-down mode.

 Aplicaciones

o Industrial control
o Medical systems
o Protocol converter
o Communications