Unit 4: Design Vision First Tutorial

Carlos Jesús Jiménez Fernández

Instituto de Microelectrónica de Sevilla / Universidad de Sevilla
October 2023. Versión 3.0

Outline:

In this tutorial, we see the most basic aspects of Design Compiler, as reading, synthesizing and
optimizing a simple design. We impose different restrictions and we see the results.

We use some basic UNIX commands, so it is important to have basic knowledge of this operating
system.

The steps to follow are:

•1 Run Design Compiler.

•2 Reading a design.
•3 Setting optimization restrictions.
•4 Analysis of the results.
•5 Save the design.
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I. INITIALIZATION AND STARTING.

A. Before begin.

It is always important to create a good directory hierarchy for the data and the files. In your
account must be a directory called MHCAD. In this directory, create another directory called “tema4”.
This can be done with the unix commands:

% mkdir MHCAD
% cd MHCAD
% mkdir tema4

Go into this directory and create a subdirectory where the source files must be placed:

% mkdir src

Copy the HDL Verilog file to the source subdirectory:

% cp /mnt/cnm/master/MHCAD/tema4/accumulator.v src

Create another subdirectory where run the Design Compiler tool. Go to this directory and get a
Synopsys initialized xterm:

% mkdir design_vision
% cd design_vision
% tools

In the window that it opens select:

Synopsys -> Version 2012.09 -> Front End and Verification Tools

Before run Synopsys, you have to copy the Design Vision configuration file (.synopsys_dc.setup)
to the working directory:

% cp /mnt/cnm/master/MHCAD/tema4/.synopsys_dc.setup

This hidden file can be seen with the option “-a” in the “ls” command: ls -a

Explore the contents of this file (without modifying it). There are several UNIX commands to
do this, but a useful one is “more”:

% more .synopsys_dc.setup

Run the Design Compiler tools with the command “design_analyzer” in the xterm:

% design_vision

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II. READING AND OPTIMIZATION OF THE DESIGN.

The first step is reading the design copied to the src directory:

File -> Read ...

You have to search in the src directory and select the accumulator.v file.

Once the design is read, its name appears in the “Logical Hierarchy” section of the “Hier.1”
window. We can create the schematic by right-clicking on the name of design in this section and
selecting “Schematic View.” In the right part of the “Hier.1” window we can list the components, nets,
etc. of the circuit. As it is not yet optimized, the components are not cells of the technological library.
You can change to the symbol view pressing the symbol icon.

A minimum period of 20 ns clock will be imposed as synthesis restriction. To do this, in the

“Hier.1” window, select the design “accumulator” in the Logical Hierarchy area, and in the area on
the right select “Pins / Ports”.

(I) Select the (II) Select the

design Pins/Ports

Select the clock signal (clk), and execute:

Attributes -> Specify Clock...

Put the name of the clock signal (clk), set the value 20 in the period, 0 in rising and 10 in falling.
Note that the clock waveform is displayed at the bottom. Press “Ok”. This period is too high for this
circuit, so the synthesis tool must obtain an implementation with the least possible area.

Optimize the design. Select the accumulator and execute:

Design -> Compile Design...

Do not change any option and press “OK”.

Now, the design is implemented with the cells of the target library. Look again the schematic
and check the changes. Observe that now there is a design hierarchy. There are two circuits, because
Design Vision introduce additional hierarchy levels when there are arithmetic operators. Look the
adder type that Design Vision has introduced.

III. REPORTS.

The information for the optimized design is available from two menus: the “Design” menu and

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 Design Vision, first tutorial

the “Timing” menu.

In the Design menu, we can see the area and the cells of the design:

Design -> Report Area... (Write down the Total Area value)

Design -> Report Cell...

To see whether it have met the time constraints, we can run in the bottom of the screen, the
command:

Design vision> report_timing

We can also see a histogram with the biggest delay paths. To do this run the command:

Timing -> Path Slack...

We leave the default options and press OK. A window with a bar diagram with the largest delay
paths is opened. We can see a description of each of the paths, the corresponding path in the schematic,
etc. You can also change the options for changing the number of bars, the number of paths shown, etc.

IV. IMPOSING NEW RESTRICTIONS.

Following the same procedure explained above, and using the optimized design, change the
maximum clock period impose for the clock to 5 ns. Make a new optimization and get an area and
timing report.

Compare the results with the previously obtained. View the adder schematic and see the
differences with the previously obtained.

Repeat the steps but with a clock restriction of 2.5 ns. Examine again the area results. As it can
be observed, that if we want higher operation frequencies, the obtained design has more area.

V. SAVE THE DESIGN

Finally, save the design in the Synopsys database format (ddc):

File -> Save As...

Put the name “accumulator_5ns” and choose “ddc” as format.