KONERU LAKSHMAIAH EDUCATION FOUNDATION

(Deemed to be University estd, u/s, 3 of the UGC Act, 1956)

(NAAC Accredited “A++” Grade University)

Green Fields, Guntur District, A.P., India – 522502

Department of Electronics and Communication Engineering

(DST - FIST Sponsored Department)

B.Tech. III ECE PROGRAM

A.Y.2023-24 ODD, Semester-I
21EC3061 Analog VLSI Design
CO2

Session 8: Cascode Current Mirror

1. Course Description (Description about the subject)

Analog VLSI Design is a course offered to create students who are academically and
practically skilled in designing analog circuits which are required as building blocks for the
real time applications. During this course, the students will learn about the process of
analyzing the different parameters of a circuit by varying different loads and different
configurations. This course provides insights to amplifiers, Op-amps and mixer circuits.

2. Aim

To learn the basics of cascode current mirror and analyze their behavior in analog circuits
when used as a load.

3. Instructional Objectives (Course Objectives)

 Apply the fundamentals of MOS transistors for the design of single stage amplifiers.
To learn CMOS process technology.
 Realize the active & passive current Mirrors and analyze the differential amplifiers
with qualitative and quantitative approaches.
 Analyze the CMOS Op Amps, and various types of Op Amps with qualitative and
quantitative approaches.
 Analyze the high frequency response of CS, CG and CD amplifiers and noise analysis
of various amplifiers and mixers.
 Design and analysis of various MOS analog circuits using Cadence/ LT-SPICE/
QSIM environment for real time applications
4. Learning Outcomes (Course Outcome)
CO2: Realize the active & passive current Mirrors and analyze the differential amplifiers
with qualitative and quantitative approaches.

5. Module Description (CO-2 Description)

Realize the active & passive current Mirrors and analyze the differential amplifiers with
qualitative and quantitative approaches.

6. Session Introduction:
• So far, Channel length modulation is neglected.
• If minimum length transistors are used then neglecting channel length modulation
results significant error in copying current.
• Small length transistors are used so as to minimize the width and hence output
capacitance of the current source.
For simple Current Mirror

(1)

(2)

(3)

From circuit, VDS1 = VGS1 = VGS2

while VGS2 may not equal to VDS2 because of
circuitry fed by M2.
Fig. 1. Current processing using aspect ratio
Example (VDS can be different)

Fig. 2. Unequal Vp and Vx in the design due to amplifier load

Let VX = VDS1 and VP = VDS2
V
GS,in1 = Vin,CM – VP = Vin,CM – VDS2 VDS2 = Vin,CM – VGS,in1 ≠ VDS1 (4)
Therefore, potential at node P is determined by input common mode level and gate-source
voltage of Min,1 or Min,2 and it may not equal VX.

7. Session Description:
Modification in circuit (to suppress the effect of channel length modulation)
Cascode current source
Channel length modulation effect can be reduced by cascoding
Vb is chosen such that voltage at Y must be equal to X
Iout will closely track IREF
Effect of voltage VP is very less on VY due to cascoding of M3.
The cascoding of M3 will shields the M2 from VP variation by

Fig. 3. Cascode Current Source

(5)

Accuracy is obtained at the cost of voltage headroom consumed by M3

Generation of Vb (such that VY = VX)
As VGS3 = Vb – VY this implies Vb = VGS3 + VY
Therefore,
Vb = VGS3 + VX (to get VY = VX) (6)
Vb must be biased such that VX should add to one G-S voltage.

Further modification in circuit

To get Vb = VGS3 + VX,
A MOSFET must be added above ‘X’ so to get one extra VGS
Therefore, VN = VGS0 + VX

Biasing Vb (VN = Vb)

Connect node N to the gate of M3. Thus VGS0 + VX = VGS3 + VY
Hence proper choice of the dimension of M0 with respect to M3
yields VGS0 = VGS3 which cause VY = VX

Fig. 4. Circuit modification forming Vx=Vy

Condition to ensure VGS0 = VGS3 (so that VY = VX)

(7)

(8)

(9)

Fig. 5. Circuit modification forming Vx=Vy

(10)

If VGS0 = VGS3 then VY = VX. Put this in equation

(11)

Thus above condition must be satisfied to get VGS0 = VGS3 cause VY = VX

Note: Result holds good even if M0 and M3 suffer from body effect.

Example:
Sketch VX and VY as a function of IREF. If IREF requires 0.5 V to operate as a current source,
What is its maximum value?
Solution:
VY = VX (M2 and M3 are properly ratioed with respect to M2 and M3)
 (11)

Comparison b/w Cascode Mirror and Cascode current Source

Fig. 6. Cascode current mirror

VN is chosen such that VY = VX

Minimum allowed voltage at VP
V
P,min = VN – VTH3 = (VGS0 + VGS1) – VTH3
Let all transistor are identical (i.e. VTH same)
V
P,min = (VGS0 – VTH) + (VGS1 – VTH) + VTH (12)
In Cascode Mirror, VN should be such that min. allowable voltage at VP is 2-over drive
voltage plus one threshold voltage. (1 extra VTH waste because VDS2 = VGS2)
Hence Iout tracks IREF accurately
Vb is chosen arbitrarily, so VY ≠ VX
Minimum allowed voltage at VP
Assume all transistors are identical
Fig. 7. Cascode current source
V
P,min GS3 TH GS2 TH)
= (V –V ) + (V –V
(13)
In Cascode Current Source, Vb could be so low that the min. allowable voltage at P is merely
2-over drive voltage.
Hence Iout will not tracks IREF because M1 and Mka2r *su* stain unequal drain-source volt1a6ge

Modified Cascode Circuit (to eliminate accuracy-headroom trade-off)

Previously studied that for higher copying accuracy i.e. I out = IREF, one extra threshold voltage
is required which cause more voltage headroom. A modified cascode circuit is used to
eliminate accuracy-headroom trade-off.
Modified Circuit Task:
New circuit should have low voltage headroom but also IREF should be copied accurately.
1) Like Cascode Mirror there should be cascoding and proper ratioing of the transistors
(which cause VX = VY), so IREF can be copied accurately.
2) Gate Voltage Vb should be lower than VN, therefore consume less headroom.
(Cascode Mirror VN = VGS0 + VGS1 while in Cascode Current Source Vb = VGS2 –
VTH2 + VGS0)
Consider this circuit

Fig. 8. Circuit to determine

limits of Vb

M1 and M2 must remain in saturation

Condition
For M1: VGS1 – VTH1 ≤ VA (= Vb – VGS2) → (VGS1 – VTH1) + VGS2 ≤ Vb (14)
For M2: Vb – VTH2 ≤ VX (= VGS1) → Vb ≤ VGS1 + VTH2 Thus, (VGS1 – VTH1) + VGS2 ≤ Vb ≤ VGS1 +
VTH2 (15)

(16)
Therefore size M2 such that its overdrive voltage remains less than one threshold voltage

Fig. 9. Low voltage cascode

All transistors are in saturation. Proper ratioing ensures VGS2 = VGS4 (and VA = VB)
For min. voltage headroom, Vb must be minimum
(For min. headroom, VP should be low and VP = Vb – VTH4)
V
b,min = (VGS1 – VTH1) + VGS2 (16)
As VGS1 = VGS3 → Vb,min = (VGS3 – VTH3) + VGS4
Therefore, VP,min = Vb,min – VTH4 = (VGS3 – VTH3) + (VGS4 – VTH4)
Cascode current source M3 – M4 consume minimum headroom (overdrive voltage of M3 plus
that of M4) without trading with copying of IREF.
(M1 and M3 sustain equal drain-source voltage, allow accurate copying of IREF)
In Cascode Mirror one extra threshold voltage is wasted in headroom to copy exact IREF.
Generation of Vb = (VGS1 – VTH1) + VGS2
 Fig. 10.
From previous circuit, VGS1 – VTH1 ≤ VA (= Vb – VGS2) [for M1 and M3 to be in saturation]
Therefore, Vb ≥ (VGS1 – VTH1) + VGS2
(Vb must equal or slightly greater than VGS1 – VTH1 + VGS2 so M3 can remain in saturation)
From circuit, Vb = VGS5 + VDS6 (where VDS6 = VGS6 – I1.Rb) VGS5 ≈ VGS2 and VDS6 = VGS6 – I1.Rb ≈
V
GS1 – VTH1
Note: Some inaccuracy nevertheless arises because M5 does not suffer from body effect
whereas M2 does. Also magnitude of RbI1 is not controlled.
Replace Resistance (Rb) with Diode connected load (M 7) such that M7 has high (W/L) so that
VGS7 (= VDS7) ≈ VTH7. Therefore VDS6 = VGS6 – VDS7 = VGS6 – VTH7
Hence, Vb = VGS5 + VGS6 – VTH7 (circuit require no resistance but still affect from body effect)

Low-Voltage Cascode using Source follower level shifter

Fig. 11. Low-Voltage Cascode using

Source follower level shifter

Idea is to shift the gate voltage of M3 down with respect to VN by interposing a source
follower. MS is biased at very low current density [i.e. ID/(W/L)], therefore it’s VGS ≈ VTH
VGS = VN – VN’ ≈ VTH . This implies VN’ ≈ VN – VTH. Gate voltage of M3 is down by one VTH
with respect to VN. Hence source follower can be used to bias Low voltage Cascode Mirror.
Disadvantage
 • VB = VGS1 + VGS0 – VTH3 – VGS3 = VGS1 – VTH3 [where VNN’ (= VGSS) ≈ VTH3] This value of
Vb implies that M2 is at edge of triode region
• VDS2 ≠ VDS1, introduce substantial mismatch
• If body effect for M0, MS, and M3 is considered, it is difficult to guarantee that M 2
operate in saturation
Note: Cascode structure reduce the mismatch in current due channel length modulation and
also provide high output impedance.

8. Activities/ Case studies/related to the session

1. In a particular cascaded current mirror, such as that shown at the right, all transistors have
Vt=0.6V, µnCox=160 L=1µm, and VA=10V . Widths W1=W4=4µm, and W2=W3=40µm.
The reference current IREF is 20µA. What The output current results? What are the voltages at
the gates of Q2 and Q3? What is the lowest voltage at the output for which current source
operation is possible? What are the values of gm and ro of Q2 and Q3? What is the output
resistance of the mirror.

2. Modify the circuit with corresponding analytical modeling so that VY can be made
independent of VP to have perfect copy of IREF through M2.

3. Assume all transistors are identical. Sketch IX and VB v/s VX, as VX drops from a large
positive value.
Solution:
• VX ≥ VN – VTH3 → M2 and M3 in saturation → IX = IREF and VB = VA (constant),
where VA = VN -VGS0
• VX < VN – VTH3 → M3 enters in triode (VX < VN – VTH3).
Decrease in V will decrease V rapidly (M is in triode, requiring a greater gate-source
X B 3
overdrive to carry same current) and now V ≠ V while M can still be in saturation because
B A 2
V >V –V
B A TH2
As M is in saturation but V (V ) ≠ V (V ) → I decreases slightly with V
2 DS2 B DS1 A X X
• VX < VA – VTH2 + VDS3 → As VX decreases further, VB also decreases rapidly which
cause VB < VA – VTH2. Therefore, M2 enters in triode region → IX drops sharply with

9. Examples & contemporary extracts of articles/ practices to convey the idea of the
session

Article: "Design and Analysis of High-Precision Cascode Current Mirror for Analog
Integrated Circuits"

This article discusses the design and analysis of a cascode current mirror circuit for high-
precision analog integrated circuits. It provides insights into the benefits of using a cascode
configuration and highlights the considerations for achieving high accuracy and stability in
current mirroring.

10. SAQ's-Self Assessment Questions

1. A cascode current mirror is a circuit configuration that combines:

a) Two current mirrors in parallel

 b) A current mirror and a differential amplifier

c) A common-source amplifier and a common-gate amplifier

d) A common-source amplifier and a common-drain amplifier

2. The primary advantage of a cascode current mirror over a simple current mirror is:

a) Higher output resistance

b) Lower output resistance

c) Higher voltage gain

d) Lower voltage gain

3. The cascode configuration in a cascode current mirror is formed by:

a) Two MOSFETs in series with their gates connected

b) Two MOSFETs in parallel with their gates connected

c) Two MOSFETs in series with their sources connected

d) Two MOSFETs in parallel with their sources connected

4. The cascode current mirror provides better output resistance by:

a) Increasing the transconductance of the output stage

b) Decreasing the transconductance of the output stage

c) Increasing the output impedance of the input stage

d) Decreasing the output impedance of the input stage

5. The cascode current mirror offers improved performance in terms of:

a) Input resistance

b) Output resistance

c) Gain bandwidth product

d) Power supply rejection ratio

6. The cascode current mirror is commonly used in applications that require:

a) High voltage gain

b) Low power consumption

 c) High output current

d) Low output impedance

7. The purpose of the cascode transistor in a cascode current mirror is to:

a) Increase the output impedance

b) Decrease the output impedance

c) Increase the gain

d) Decrease the gain

8. The cascode configuration helps to minimize the effect of:

a) Channel-length modulation

b) Threshold voltage variations

c) Substrate biasing

d) Body effect

9. The cascode current mirror is particularly useful in:

a) High-frequency applications

b) Low-power applications

c) Low-gain applications

d) High-voltage applications

10. The voltage drop across the cascode transistor in a cascode current mirror is typically:

a) Equal to the supply voltage

b) Equal to zero

c) Less than the supply voltage

d) Greater than the supply voltage

11. The cascode current mirror offers improved voltage headroom by:

a) Increasing the voltage swing

b) Decreasing the voltage swing

c) Increasing the common-mode voltage range

 d) Decreasing the common-mode voltage range

12. The cascode current mirror is less sensitive to variations in:

a) Supply voltage

b) Temperature

c) Input voltage

d) Output current

13. The input resistance of a cascode current mirror is primarily determined by the:

a) Source resistor of the input transistor

b) Drain resistor of the input transistor

c) Source resistor of the cascode transistor

d) Drain resistor of the cascode transistor

14. The output resistance of a cascode current mirror is primarily determined by the:

a) Drain resistor of the input transistor

b) Source resistor of the input transistor

c) Drain resistor of the cascode transistor

d) Source resistor of the cascode transistor

15. The cascode current mirror configuration is useful for minimizing:

a) Voltage gain

b) Power consumption

c) Output current

d) Output voltage swing

16. The cascode current mirror can be considered as a combination of:

a) Common-source and common-gate amplifiers

b) Common-source and common-drain amplifiers

c) Common-gate and common-drain amplifiers

d) Common-emitter and common-base amplifiers

17. The cascode current mirror provides better linearity due to:

a) Reduced voltage swing

b) Increased voltage swing

c) Reduced distortion

d) Increased distortion

18. The output current of a cascode current mirror is primarily determined by the:

a) Ratio of the transconductances of the input and cascode transistors

b) Ratio of the drain resistances of the input and cascode transistors

c) Ratio of the drain currents of the input and cascode transistors

d) Ratio of the source resistances of the input and cascode transistors

19. The cascode current mirror is commonly used in:

a) Operational amplifiers

b) Voltage regulators

c) Data converters

d) Audio amplifiers

20. The cascode current mirror offers better thermal stability due to:

a) Reduced power dissipation

b) Increased power dissipation

c) Reduced temperature dependence of threshold voltage

d) Increased temperature dependence of threshold voltage

11. Summary

Design and analysis of cascode current mirrors are discussed along with optimization of the
designs to mitigate short channel effects and improve current copying mechanism.

12. Terminal Questions

1. What is a cascode current mirror?

2. What are the advantages of using a cascode current mirror?

3. How is the output impedance improved in a cascode current mirror?

4. What is the purpose of the cascode transistor in a cascode current mirror?

5. How do you select the transistor sizes in a cascode current mirror?

6. How can you optimize the performance of a cascode current mirror?

7. What are the trade-offs in cascode current mirror design?

8. How can you improve the linearity of a cascode current mirror?

9. Can you briefly explain the concept of gain boosting in a cascode current mirror?

10. What are some applications of cascode current mirrors?

11. How can we design a modified cascode current mirror which can reduce the problem of
voltage headroom without trading with copying of Iref.

12. Explain how second order effects in mosfets hamper current copying mechanism in
cascode current mirrors

13. Design a low voltage current mirror circuit by interposing source follower circuit. How
does it help to reduce effect of body bias on current copying mechanism?

13. Case studies:

1. Case Study: Designing a Temperature-Independent Voltage Reference Circuit

Objective: To design a voltage reference circuit that provides a stable output voltage
regardless of temperature variations.

Description: In this case study, students are tasked with designing a temperature-independent
voltage reference circuit using MOSFETs. They need to analyze different biasing techniques
such as PTAT (Proportional to Absolute Temperature) current generation and constant-Gm
biasing to generate a reference voltage that is insensitive to temperature changes. The
students select appropriate MOSFET sizes, resistor values, and biasing currents to achieve the
desired temperature stability. They simulate the circuit and evaluate its performance across a
range of temperatures to assess its temperature-independent characteristics.

2. Case Study: Analysis of Cascode Current Mirror

Objective: To analyze the performance of a cascode current mirror circuit and understand its
advantages over a basic current mirror.

Description: In this case study, students compare the performance of a basic current mirror
with a cascode current mirror. They are provided with the circuit schematics and component
values for both configurations. The students analyze the voltage and current characteristics of
each circuit and calculate parameters such as output impedance, voltage gain, and linearity.
They investigate the advantages of the cascode current mirror in terms of improved output
impedance and reduced sensitivity to variations in transistor parameters. The students
simulate the circuits and compare their performance to validate their analysis.

3. Case Study: Designing a Temperature-Compensated Differential Pair

Objective: To design a differential pair amplifier with MOS loads and active current mirrors
that maintains high performance over a wide temperature range.

Description: In this case study, students are given the task of designing a temperature-
compensated differential pair amplifier for an audio application. They need to select
appropriate biasing techniques, such as active current mirrors, to ensure stable operation and
minimize temperature-induced variations in performance. The students analyze the small-
signal characteristics, gain, and linearity of the amplifier. They simulate the circuit and
evaluate its performance across different temperature ranges to verify the effectiveness of the
temperature compensation techniques.

14. Answers:

1. c) A common-source amplifier and a common-gate amplifier

2. a) Higher output resistance

3. a) Two MOSFETs in series with their gates connected

4. a) Increasing the transconductance of the output stage

5. b) Output resistance

6. a) High voltage gain

7. a) Increase the output impedance

8. b) Threshold voltage variations

9. a) High-frequency applications

10. c) Less than the supply voltage

11. a) Increasing the voltage swing

12. b) Temperature

13. c) Source resistor of the cascode transistor

14. c) Drain resistor of the cascode transistor

15. d) Output voltage swing

16. b) Common-source and common-drain amplifiers

17. c) Reduced distortion

18. a) Ratio of the transconductances of the input and cascode transistors

19. a) Operational amplifiers

20. c) Reduced temperature dependence of threshold voltage

15. Glossary

Cascode Current Mirror: A cascode Current Mirror is a circuit designed to copy current
from a reference current source to other parts of the circuit considering channel length
modulation (CLM).
Small Signal: A small-signal model is an AC equivalent circuit in which the nonlinear circuit
elements are replaced by linear elements whose values are given by the first-order (linear)
approximation of their characteristic curve near the bias point.
Cascode current source: Similar to its bipolar counterpart, MOS cascode can be thought of
as stacking a transistor on top of a current source reducing CLM.

16. References of books, sites, links

Text Books:

1) BehzadRazavi, “Design of Analog CMOS Integrated Circuits”, Tata Mc Graw Hill, (2005)

2) Jacob Baker, “CMOS Mixed Signal Circuit Design”, John Wiley, (2008)

Reference Books:

1) Neil H. E. Weste and David. Harris Ayan Banerjee, “CMOS VLSI Design” – Pearson
Education, 1999.

2) Gray& Mayer, “Analysis & Design of Analog Integrated Circuits”, 4th edition, Wiley,
(2001).17. Keywords

Sites and Web links:

1. https://inst.eecs.berkeley.edu/~ee105/sp07/lectures/SP07-Lecture7-
Cascode&CurrenMirrors.pdf
2. https://wiki.eecs.yorku.ca/course_archive/2016-17/W/3611/_media/
eecs3611_lecture3.pdf
3. https://people.engr.tamu.edu/spalermo/ecen326/
lecture04_ee326_cascode_current_mirrors.pdf
4. https://www.youtube.com/watch?v=x9xt9ChSiow

17. Keywords

Cascode current mirror, Current replication, Biasing, Transistor matching, Load impedance,
Differential pair, MOSFET cascode, BJT cascode, Linearity, Output impedance