CHAPTER 3 JySTRUCTION Set Or 8085 ee PROCESSOR CYCLES 3.1 The sequence of operations tha a processor has to carry out while executing the instruction _aed insulin Cycle. Each instruction eyele of a processor in tun consists of a number of isa cycles. The machine cycles are the basic operations performed by the processor. To mati tinstrction, the processor executes ne or more machine cycles ina particular sequence oe Yeles of a processor are also called Processor Cycles. The manufacturers of ‘The machine Cy rr oorecessors define the timings and status of various signals during the processor cycles. In general, the instruction cycle of an instruction can be divided into two sub-cycles: Fetch cyele and Execute cycle. The fetch cycle is executed to fetch the opcode from the memory or the execute cycle is executed to decode the instruction and to perform the work specified by the instruction. 3.2 MACHINE CYCLES OF 8085 The 8085 microprocessor has seven basic machine cycles. These are: LAC Opcode fetch cycle (AT or BT) ‘Je Memory read cycle (3T) 3° Memory write cycle (37) 4, 10 read cycle (37) 5. lOwrite cyclé (37) 6. Interrupt acknowledge cycle (GT or 12T) 7. Busidle cycle (2T or 3T) Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when the 8085 processor executes an instructién, it will execute some of the machine cycles in a specific order, The processor takes a definite time to execute the machine cycles. The time taken by the Processor to execute a machine cycle is expressed in T states. One T-state is equal to the time Period of the internal clock signal of the processor. The T-state starts at the falling edge of a clock. Fig. 3.1 : Clock Signal.ct ach machine cycle are mentig,, processor to execute © i he 8085, uired by the ie The T states req css st of machine cycles given 4 within brackets in the Ti 3.2.1 Timing Diagram The timing diagram provides infor De ae Is whi ta high impedance state) of the s : ni ase a sa 3 suy spied by the manufacturer of the imicroprocess r The timing eee are esseng, Fi ree eee ner, only from the knowledge of the timing diagrams, the matched periph, etc., can be selected to form a system with a microprocessor as Cp, 1 the various conditions (high state ory, ‘a machine cycle is executed. The tiny for a system designer. devices like memories, ports, Opcode Fetch Machine Cycle of 8085 Each instruction of the processor has ET HET ET an one byte opcode. The opcodes are stored CLK in the memory. The opcode fetch machine My] a cycle is executed by the processor to fetch Co _[onfsie Toa asia)“ Cakes") the opcode from memory. Hence, every AP.-AP_{A Ades emo instruction starts with an opcode fetch machine cycle. Inigh Bye] . actin aw ae --t The time taken by the processor to execute the opcode fetch cycle is either 4T or eX | 6T. In this time, the first 3 states are used ALE - for fetching the opcode from the memory and. RD | a \ | emaining T states are used for internal operations by the processor. The timings of the various signals during the opcode fetch 10%%,8,8, [Xomt-o] s,=1 | S.=1 cycle are shown in Fig. 3.2. 1. Atthe falling edge of the first T-state (T,), the WR will be high ; READY is tied high either microprocessor outputs the ow byte address permanently or temporarily in the system) onAD,AD, ines andhigh byte address on, Fig. 3.2 : Opcode fetch machine cycle of 80 10, ies, ALEis asserted high to enable the Goths S121 externa adress latch. The othe control signals eae are asserted as follows: \Oiti-0, S, = 1,, ~ 1. (Oils asserted low to indicate memory access.) 2. At the middle ofT,, the ALEis asserted Ic i i low and this enables the external i address and keep onits output lines. ee 3. : i tineedtame wa “ mana requested for read by asserting read line low. When read is ss#* i, led for placing the opcod it eiechun tore na 7 ne St " ‘on the data bus. The time allowed for memory to output 4, Inthe third. gnali i pele et 4 ae a). i read signal ‘s asserted high. On the rising edge of the read signal, the opcodeis| latche ens OF. ther control signals remain in the same state until the next machine cycle. ). e +s is ‘ eee a i ual ha tw ent a internal operations to decode the instruction and encode , ipleting the task specified by -byte i ic ing this : th adress andthe data buswllbeinhighimpedaneestate the T-byte instruction, During this stye cH ead Machine ele of 8085 T, ‘us memory Rea es cux lat ‘rhe memory read machine eyele is executed by ‘a data byte from memory. The The memory write machine cycle is executed by crx aenen 3 sTauer! lon Set Or 8085 7, sor to read toexccute this cycle. The timings Ap,- AD ae A 3). (Dharam Memory Ache [XP ute flingedgeo!T, thmiraprocessor ouput the low ace pyteadéress on AD, AD, nes and high byte adress onA,- A, lines. ALEis asserted high to: ‘enable the external address fac The othe contol signals are assorted as follows: ALE 7D ‘ioiMi-0.S, = 0,5, = 1.(l0/Mis asserted low to indicate memory access) Yio =o tthe middle of , the ALEis asserted low and thisenables ox, s,s, the external address latch to take low byte of address and keep onits output lines. Inthe second T-state (T), the memory is requested for read (WR will be high ; READY is tied high either permanently or temporarily in the system.) Sting the read signal low. When the read signal is Be oaaar eal raid Fig. 3.3 : Memory read machine cycle of an 8085. asserted low, the memory is enabled for placing the data on the d bus. The time allowed for memory to output the datais the time during which read remains low. Atthe end of T, the read signalis asserted high. the microprocessor. Other control signals remal Write Machine Cycle of 8085 43 the processor to write a data byte in a memory location. The processor takes 3T states to execute this machine cycle. The timings of various signals during ap, ap, S On the rising edge of the read signal, the data is latched into the in the same state until the next machine cycle. Nissuek) (a ata from kroprocess: memory write cycle are shown in Fig. 3.4. 1 At the falling edge of T,, the microprocessor outputs the =, 4, x High Byre| Address lowbyte address on AD, - AD, lines and high byte address an A, to A,g lines, ALE is asserted high to enable the extemal adress latch. The other control signals are asserted as follows: l0ifi~0,5, = 1,8, = 0.(10/Mis asserted low toindicate = WR ‘memory access.) At the middle of T,, the ALE is asserted low and this enables the external address latch for latching the low byte '”™ S» S. Kosi adéressintoits output nes. Inthe fling edge of T, the races: RD y the processor outputs data on AD, (RD will be high ; READY is tied high either Q AD, lines and then, request memary for write operation y asserting the write control signal WR to low. cycle of an 8085. Sotl ys permanently or temporarily in the system.) Fig. 3.4 : Memory write machine 20rr iow Ser Or 8085 curren 3 Instauert a K-19 Tye cK— FA OF Tah Dfia ron av.-ap._[XauetX—Phesar_[)~ aaw [Pints \ ALE WR de 10M, Sw S, iow sn) | 5-0 ed high either (RD will be high ; READY he system.) permanently or temporarily Fig. 3.6 : 1O write machine cycle of an 8085. This enables the 10 port to latch the data intoit. The 10 port should in which write control signal remains low. Other control 4, Attheendof T,, the processor asserts wR prepareitsel to accept the data within the time duration it signals remain in the same state until the next machine cycle. Interrupt Acknowledge Machine Cycle of 8085 The interrupt acknowledge machine cycle is executed by the processor to service an interrupt, when an interrupt request is made through the INTR pin of the processor. errupt at the second T-state of the last machine cycle of every instruction. If there is a valid interrupt request and if INTR is enabled, then the processor .d then executes an interrupt acknowledge machine completes the current instruction execution an cycle. The interrupt acknowledge machine cycle is executed to get either an RST n instruction fromthe interrupting device orto get a CALL instruction with the CALL adress from the interrupting device. It also stores the content of the program counter (return address) in the stack. u The timings of various signals during interrupt acknowledge cycle of 8085 when RST n struction is supplied by the interrupting device are shown in Fig. 3.7. 1. ‘ F eae ae of interrupt acknowledge cycle, the address is placed on the AD, - AD, andA,-A,, and ALE is asserted high. But the address is not used i Sona ised to read from memory. The other control signals are 1OIM=1, 8, = 1 and, = 1. In the mic is ic zfs _ ofT,, ALE s assorted low. The INTR signal can remain high or it can go low once the interrupt is 2 nthe see INTA ond T-state (T,),INTA is asserted I i ing devi BT cistern cearapee low, and this enables the interrupting device to place the opcode of The 8085 processor checks for an intRO, fom laced ct. RG is atchedinto the pr et ae which NTA remains oy, Me, a jerations. The internal Operations ety Saad Wi paneratin ol th Vector Att y ighante RST vast neo a | internal used far chine cyl INTAis asserter Atthe end of T, the INTAis rf aa forthe extenal harder tr ss wes ttre T states TT a he ding thinsttin and ead Gocoding Memory Write Memory Wing RST nintorpt. wo {| get =o eC (sP)- i] >} 5. S,=0 19-87: Inlerupt Acknowledge Sycle with RST n opcode. The T states TT, and, are used to sta 8 the high by in the stack sin” fate the Stab Paiter Pas adgeng minset the Program Counter FC) that In, the content of isd ’ tow lath he wen time laced on AD,AD, ang ArA\ lines. ALEis asserted hae S,=Tands, = 0, ‘he external atch The status signals are asserted 25 InT,,thebigh byte of the Pe 1 faite wit pee op fae eee 2nd Wis asserted tow toenable the stat™ The T states T,,, 1); mr, ATE Used to, Store the. low b igh, InT,, the content of SPig again te Of the Program counter into the stack. i) "eel VAD, and A, A. tines. ALEIS aeae quarter 3_InstaueriON SerOr 8085 oe a7 and then low, tlatch the aw byte of adress into theexteral latch, The status signals are asserted as liMi=0, g,- lands, ~ 0. a InT,, the ow byte of PCs placed on AD, AAD, lines and WR is asserted low to enable the stack memory for the write operation. At the end of T,,, WRis asserted high. nterrupt acknowledge machine cycle, the Program Counter (PC) will have the truction and so, the processor starts servicing the interrupt by execut- After the in ; address of RST n ins! vice subroutine stored at this address. vector ing the interrupt set cycle of 8085, with CALL instruction This cycle is executed by the machine to service an interrupt, when an interrupt request is throveih the 8259 (Interrupt Controller) to the INTR pin of the 8085. The INTEL 8259 can rat aerrupt requests and allow one by one to the INTR pin of the 8085 processor. It also ae CALL opcode and CALL address, when it receives INTA signal from the processor. supplies Interrupt acknowledge The processor checks for an interrupt at the second T-state of the last machine cycle of rrupt request and if INTR is enabled, then the processor every instruction. If there is a valid inter : completes the current instruction execution and then executes an interrupt acknowledge machine cycle. ‘The timings of various signals during interrupt acknowledge cycle when CALL instruction is supplied by the interrupting device are shown in Fig. 3.8. 1. Atthe felling edge of T, the address is placed on AD, - AD, and A, A,, lines and ALE is asserted high. But the address is not used to read from memory. The other control signals are asserted as 10/M=1, S, - 1 and 8,-1. Inthe middle of T, the ALEis asserted low. The INTR signal can remain high orit can go low once the interrupt is accepted by executing acknowledge cycle. 2. InT,,INTAis asserted low and this enables the interrupt controler 8269 to place @ CALL opcode on the data bus. 3. Atthe end of T,, the INTA is asserted high and the CALL opcode is latched into the processor. 4, The T states T,, T, and T, are used for internal operations. The internal operations performed are decoding the opcade and encoding into various machine cycles. 5. The Tstates T,, T, and T, are used to fetch the low byte of cal address from 8259. In T,, the content of the Program Counter (PC)s placed on the address bus but not used for memory operation. In T, the INTA is asserted ‘ow and this enables the interrupt controller 8259 to place the low byte of call address on the data bus. At the end Of T, the INTA is asserted high and the low byte call address on the data bus is latched into the processor. 8 The states, T,, and, are used to fetch the high byte of call address from the 8259. In T, the content of Cis placed onthe address bus, but snot used for memory operation. In, the INTA is asserted low and the 8259 a for placing the high byte of call address on the data bus. At the end of T.,, the INTA is asserted high and high byte call address on the data busis latched into the processor. TheT states, T,, andT,, are sed to store the high byte of the program counter inthe stack memory. i ere i to Sak Pointer (SP)is decremented by one and placed on the address bus. ALEis asserted asi0ii-0,$, 1 latch the low byte of address into the external latch. The other control signals are asserted arable then tS: 0. nT te high byte of PCs placed on AD, - AD nes and WRis asserted low to ‘he stack memory for write operation. At the end of T,., Wis asserted high.a 2 Mecho, * Micnopnocessons A, tT 3.8 epeede TIVO wim e149 ebpe\mouyoe JANOWI ? BE “Bia ; (ee | {|_| etapebeh tpt TALIA j—+ | +— ‘YINI vou) Xi us| oa Yi cas) fra ‘oa eeequarteny _ The T states Ty Tanda used to store the ow byte ofthe program counter nthe stack memory. nT the content of SPis again SEAR tah the fw byte of adress inc the external ath. The other contol signals are aserted as 1 =0, 8. s,71 ands, = 0. at thelow byte of PCis placed onthe AD, -AD;tines and WR is asserted ow to enable the stack memory for InTyy a the end of T,, WRis assertod high. write operation. At ledge machine cycle, the PC will have the call address and so the ‘After the interrupt acknow! by executing the interrupt service subroutine stored at this processor starts servicing the interrupt address. us Idle Machine Cycle “The bus idle machine cycle is executed when extra time or more time js needed for an inremal operation of the processor. During this cycle, the status signals S, and S, are asserted tow. The data, address and control pins are driven to high impedance state. The READY signal wall not be sampled by the processor during this cycle. Machine Cycle With Wait States Machine Cycle YOo——er Wait states can be introduced in any machine cycle except bus idle cycle between T, and T,. The wait states are introduced in the machine cycle if READY pin is tied low at the second T-state of a machine cycle. The processor samples (or check) the READY signal at the second T-state of every machine cycle. If READY is tied low at this time then the processor keeps on introducing wait state until the READY is again tied high. This facility is used by the slow memories, IO devices and peripherals to get extra time for read or write operations. In the system when the peripheral timings are matched with the processor timings, then the READY pin is permanently tied high. If the system peripherals requires more time for read or write he then using additional hardware the READY pin should be tied low for the required number of T states, The circuit shown in Fig. 3.9 can be used to introduce one wait state in the machine cycles. ‘The working of the circuit shown in Fig. 3.9 can be explained as follows: (logic 1) +5-V FF2 D-Flip Flop ‘To READY Clock Out PRESET Pin of 8085 from 8085: (The values shown at the input and output of the flip-flops are initial cor Fig, 3, es ions) Circuit to introduce one wait state in an 8085 machine cycle.= ta oF FY Microprocessors Anp Michocontnou., AS Initially Q, ~ O.and 0,1. Theinput Dis permanently tied they are clocked (recognizes the clock) at the falling edges. Inthe beginning of every machine cycle (except bus idle), AL ALE, FF1 is clocked and its output Q, changes to 1. Also, high. The tiptlops are negative-edge Sensitive ang By Eis asserted high and then tow. At the falling ed, the input to FF2, D, changes to 1, — 1 and RESET ~ 1, Now D, =1,0,=1,0,~1,0,~0,d, Atthe fling edge beginning) of T,, FF2is clocked and soits output Q, changes to 1 and O, changes to Now, D, =1,0,~ 1, D,~ 1,0, =1,0,~ 0 and RESET ~ 0. Since O, is connected to the READY pin of an 8085, the READY willbe tied low. The 0, is also and so when O, goes to 0, the FF1is reset or cleared. Now 0, = O and since Q, = , Now, D, =1,0,= 0, D, ~ 0,0, = 1,0; 0 and RESET - 0. At the falling edge of thenext T-state Now, D sd to reset fy the D, is also equal to inwait state) again FFs clocked and so the output of F2 ican 0, = 0, D, = 0,0, = 0,0,= 1 and RESET ~ 1. Since Q,- 1, again READY is tied high. When the processor checks the READY at th falling edge of the next cycle (T,), it will be high and it will continue the machine cycle. Thus, the hardware shown in Fig. 3.9 introduces one wait state in the machine cycles, machine cycle with one wait state is shown in Fig. 3.10. Truth Table of D-flip flop Preset and reset/clear facility in D-flip flop Input | Output PRESET | RESET Q Q Clock D Qo 0 T T 0 0 1 4 it 0 1 Oo i 1 1 Clock and D input 8 9 1 decide the output 0 0 Should not occur Time | D, | Q| P| @ leo O | Or ie | 1 CLK (CLK ow | Cee el ot ort! of 8085) : ec rtaiftaftardo 0 | ALE. i | o {0 | if ilo io | READY | w [Fi | o | 0 (of) yt : ile fol o.| ojet |! hy j ‘Note: T= wait state| Gel ole | 0. at Fig. 3.10 : Machine cycle with one wait state.3 Instucrion Set OF 8085. . 3.1 cuaete® INSTRUCTION FORMAT OF 8085 structions and 246 total instructions. The instruction set of 8085 is Tne 8085 has 74 basic ned by ne manufacturer INTEL Corporation, Each instruction of 8085 has one byte opcode. wih p256 ail binary codes. In this, 246 codes have been pe (085 instructions. peodes of 8 ize of 8085 instruction can be one byte, sed £0" ‘Thes hasan opcode ‘ a via, The dhree byte instruction three byte instruction in the memory, ofaddress or data and then high byte of two byte or three byte. The one byte instruction and the two byte instruction has an opcode followed by an cight bit address 1 has an opcode followed by a 16-bit address or d: While the sequence of storage is, opcode first followed address or data. The format of 8085 instructions alone or storing the tl pylow byte are shown in Fig. 3.11. 16543210 One byte instruction: opcode 16543210 76543210 Two byte instruction — = ‘opcode bit datladess 76543210 76543210 76543210 Tow byte data/address | [ high byte data/address ‘Three byte instruction opeode : Format of 8085 instructions. Fig. 3.1 3.4 ADDRESSING MODES Every instruction of a program has to operate on a data. The method of specifying the essing. The 8085 supports the following five data to be operated by the instruction is called Addi addressing modes. 1. Immediate Addressing 2. Direct Addressing 3, Register Addressing 4, Register Indirect Addressing 5. Implied Addressing Ininmedite addressing mode, th dat is specified inthe instruction tse The data willbe apart ofthe progrem instructon. Example: MVI B, 3E, a Move the data 3E,, given inthe instruction to B-ragister eet Addressing In dire ir sky ahaa rel ‘mode, the address of the data is specified in the instruction, The data will be in memory In this the program instructions and data can be stored in different memory blocks. i Example : LDA 1050, Load th data available in memory location 1050, in accumulstor.ote lable. " +h the data is avaliable Register Addressing ‘ame of the register jn. which the C= fi In register adoressing mode, the instruction specifies te 6 MOV A,B Example : ‘Move the content of B-registor toA-registar, = [ Move the content of Bvepisior 2° Register Indirect Addressing : ie In register indirect addressing mode, the instruction species a 7 available, Here the dete will be in memory and the address Wi register pait Example: MOV A,M The memory deta addressed by he HLpair is moved to the A-register eqisterin which the address ofthe dats ava t Implied Addressing si In implied addressing mode, the jnstruction itself specifies the data to be operated. Example: CMA Complements the content of the accumulator 3.5 | INSTRUCTION SET The 8085 instructions can be classified into the following five functional groups: gh- Group I - DATA TRANSFER INSTRUCTIONS: Includes the instructions that moves, (copies) data between registers or between memory location and the re In all data transfer operations, the content of the source register/memory is not altered. Hence, the data transfer is a copying operation. oD Group - ARITHMETIC INSTRUCTIONS: Includes the instructions which perform addition, subtraction, increment or de rement operations. The flag conditions are altered after execution of an instruction in this group. \ Group - LOGICAL. INSTRUCTIONS: The instructions which perform the logical. ns ike AND, OR, EXCLUSIVE-OR, complement, compare and rotate instructions are grouped under this headin Th onditi in A se le after execution of an instruction in this ae ne ae Group IV a & Group BRANCHING INSTRUCTIONS: The instructions that are used to transfet the program control from one mey er ‘mory location i are grouped under this heading," “° ®0ther memory location 5 GroupV c 5 Group MACHINE CONTROL INSTRUCTIONS, Includes the instructions related {o interrupts and the instruction used 40 halt pro; relate The 74 basic instructions of 8085 are listed j ie ey Table-3, , size, machine cycles, number of T states and the total number % [The opcode of each instruction instruc shown in Table-3.1. The instructions affecting the status flag are list, ot in each type are als? ed in Table-3,2.