Digital Electronics

EEE211
Lecture 8

Dr Atiqur Rahman
Dept. of Electrical and Computer Engineering
North South University
 Other Gate Types
• Why?
– Low cost implementation
– Useful in implementing Boolean functions
– Convenient conceptual representation
• Gate classifications
– Primitive gate - a gate that can be described using a
single primitive operation type (AND or OR) plus
optional inversion(s).
– Complex gate - a gate that requires more than one
primitive operation type for its description
• Primitive gates will be covered first
 NAND Gate
• The basic NAND gate has the following symbol and
truth table:
– AND-Invert (NAND) Symbol: X Y NAND
0 0 1
0 1 1
X
X·Y 1 0 1
Y 1 1 0
• NAND represents NOT AND. The small “bubble”
circle represents the invert function
• The NAND gate is implemented efficiently in CMOS
technology in terms of chip area and speed
 NAND Gate: Invert-OR Symbol
• Applying DeMorgan's Law: Invert-OR = NAND
X
X + Y = X · Y = NAND
Y
• This NAND symbol is called Invert-OR
– Since inputs are inverted and then ORed together
• AND-Invert & Invert-OR both represent NAND gate
– Having both makes visualization of circuit function easier
• Unlike AND, the NAND operation is NOT associative
(X NAND Y) NAND Z ≠ X NAND (Y NAND Z)
 The NAND Gate is Universal
• NAND gates can implement any Boolean function
• NAND gates can be used as inverters, or to
implement AND / OR operations
• A NAND gate with one input is an inverter
• AND is equivalent to NAND with inverted output
X X·Y X X·Y X·Y
≡
Y Y

• OR is equivalent to NAND with inverted inputs

X+Y X X X · Y= X+Y
X ≡
Y Y
Y
 NOR Gate
• The basic NOR gate has the following symbol and
truth table:
X Y NOR
– OR-Invert (NOR) Symbol:
0 0 1
X 0 1 0
X+Y 1 0 0
Y 1 1 0

• NOR represents NOT OR. The small “bubble” circle

represents the invert function.
• The NOR gate is also implemented efficiently in
CMOS technology in terms of chip area and speed
 NOR Gate: Invert-AND Symbol
• The Invert-AND symbol is also used for NOR
X
X · Y = X + Y = NOR
Y

• This NOR symbol is called Invert-AND, since inputs are

inverted and then ANDed together
• OR-Invert & Invert-AND both represent NOR gate
– Having both makes visualization of circuit function easier

• Unlike OR, the NOR operation is NOT associative

(X NOR Y) NOR Z ≠ X NOR (Y NOR Z)
 The NOR Gate is also Universal
• NOR gates can implement any Boolean function
• NOR gates can be used as inverters, or to implement
AND / OR operations
• A NOR gate with one input is an inverter
• OR is equivalent to NOR with inverted output
X X+Y X X+Y X+Y
≡
Y Y

• AND is equivalent to NOR with inverted inputs

X·Y X X X + Y= X · Y
X ≡
Y Y
Y
 NAND–NAND Implementation

• Consider the Following SOP Expression:

F  XZ  WY Z
• A 2-level AND-OR circuit can be converted easily
to a NAND-NAND implementation
X X
Z Z
F F
W W
Y Y
Z Z Two successive bubbles
X
on the same line cancel
Z
F each other
W
Y
Z
 NOR–NOR Implementation
• Consider the Following POS Expression:
F  ( X  Z )(W  Y  Z )
• A 2-level OR-AND circuit can be converted easily
to a NOR-NOR implementation
X X
Z Z
F F
W W
Y Y
Z Z Two successive bubbles
X on the same line cancel
Z each other
F
W
Y
Z
 Other Types of 2-Level Circuits
• Other useful types of 2-level circuits:
– AND-NOR and NAND-AND
– OR-NAND and NOR-OR
• AND-NOR Function: F  XY  W X Z
AND-NOR NAND-AND
X X X
Y Y Y
F F F
W W W
X X X
Z Z Z

• Similarly, OR-NAND circuits can be converted to NOR-OR

 Exclusive OR / Exclusive NOR
• The eXclusive-OR (XOR) function is an important
Boolean function used extensively in logic circuits
• The XOR function may be:
– Implemented directly as an electronic circuit (true gate)
– Implemented by interconnecting other gate types (XOR is
used as a convenient representation)

• The eXclusive-NOR (XNOR) function is the

complement of the XOR function
• XOR and XNOR gates are complex gates
 XOR / XNOR Tables and Symbols
XOR XNOR
X Y XY X Y XY
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1

XOR Symbol XNOR Symbol

• The XNOR is also denoted as equivalence

 Uses for XOR / XNOR
• SOP Expressions for XOR/XNOR:
– The XOR function is: XY  XYXY
– The eXclusive NOR (XNOR) function, know also as
equivalence is: XY  XYXY
• Uses for the XOR and XNORs gate include:
– Adders/subtractors/multipliers
– Counters/incrementers/decrementers
– Parity generators/checkers
• Strictly speaking, XOR and XNOR gates do not
exist for more that two inputs. Instead, they are
replaced by odd and even functions.
 XOR Implementations

SOP implementation NAND only

for XOR: implementation
XY=XY+XY for XOR:

X X

X Y X Y

Y Y
 XOR / XNOR Identities

X0  X X 1  X
XX 0 XX 1

XY  YX

XY  XY= X Y

( X  Y)  Z  X  ( Y  Z ) = X  Y  Z

( X  Y)  Z  X  ( Y  Z ) = X  Y  Z

• XOR and XNOR are associative operations

 Odd Function
• The XOR function can be extended to 3 or more variables
• For 3 or more variables, XOR is called an odd function
– The function is 1 if the total number of 1’s in the inputs is odd

X  Y Z  XYZ XYZ XYZ XYZ

YZ YZ
00 01 11 10 00 01 11 10
X WX
0 1 1 00 1 1
1 1 1 01 1 1

XYZ 11 1 1
10 1 1
WXYZ
 Odd and Even Functions

• The 1s of an odd function correspond to inputs with

an odd number of 1s

• The complement of an odd function is called an even

function

• The 1s of an even function correspond to inputs with

an even number of 1s

• Implementation of odd and even functions use trees

made up of 2-input XOR or XNOR gates
 Odd/Even Function Implementation
• Design a 3-input odd function with 2-input XOR:
• 3-input odd function:
X
F = (X  Y)  Z Y
F
Z

• Design a 4-input even function with 2-input XOR and

XNOR gates:
W
• 4-input even function: X
F
F = (W  X)  (Y  Z) Y
Z
 Parity Generators and Checkers
• A parity bit added to n-bit code produces (n+1)-bit
code with an odd (or even) count of 1s
• Odd Parity bit: count of 1s in (n+1)-bit code is odd
– So use an even function to generate the odd parity bit
• Even Parity bit: count of 1s in (n+1)-bit code is even
– So use an odd function to generate the even parity bit
• To check for odd parity
– Use an even function to check the (n+1)-bit code
• To check for even parity
– Use an odd function to check the (n+1)-bit code
 Parity Generator & Checkers

n-bit code Parity (n+1)-bit code Parity

Error
Generator Checker
Sender Receiver
• Design an even parity generator and checker for 3-bit codes
• Solution: Use 3-bit odd function X
to generate even parity bit Y
P
• Use 4-bit odd function to check Z
for errors in even parity codes X
• Operation: (X,Y,Z) = (0,0,1) gives Y
E
(X,Y,Z,P) = (0,0,1,1) and E = 0 Z
• If Y changes from 0 to 1 between P
generator and checker, then E = 1 indicates an error
 Buffer

• A buffer is a gate with the function F = X

X F
X F
0 0
• In terms of Boolean function, 1 1
a buffer is the same as a connection!
• So why use it?
– A buffer is used to amplify an input signal
– Permits more gates to be attached to output
– Also, increases the speed of circuit operation
 Hi-Impedance Output
• Logic gates introduced thus far …
– Have 1 and 0 output values
– Cannot have their outputs connected together
• Three-state logic adds a third logic value:
– Hi-Impedance output: Hi-Z
• What is Hi-Impedance output?
– The output appears to be disconnected from the input
– Behaves as an open circuit between gate input & output
• Hi-Z state makes a gate output behave differently:
– Three output values: 1, 0, and Hi-Z
– Hi-impedance gates can connect their outputs together
 The 3-State Buffer
• IN = data input Symbol
• EN = Enable control input
IN OUT
• OUT = data output
• If EN = 0 then OUT = HI-Z EN
– Regardless of the value on IN
– Output disconnected from input Truth Table
• If EN = 1, then OUT =IN EN IN OUT
– Output follows the input value
0 X Hi-Z
• Variations: 1 0 0
– EN can be inverted
1 1 1
– OUT can be inverted
– By addition of bubbles to signals
Wired Output: Resolving Output Value
• The output of 3-state buffers can be wired together
• At most one 3-state buffer can be enabled. Resolved output is
equal to the output of the enabled 3-state buffer
• If multiple 3-state buffers are enabled at the same time then
conflicting outputs will burn the circuit
EN0
O0 Resolution Table
IN0
O0 O1 O2 OUT
EN1 0 or 1 Hi-Z Hi-Z O0
O1 OUT Hi-Z 0 or 1 Hi-Z O1
IN1
Hi-Z Hi-Z 0 or 1 O2
EN2 Hi-Z Hi-Z Hi-Z Hi-Z
O2 0 or 1 0 or 1 0 or 1 Burn
IN2
 Data Selection Circuit
• Performing data selection with 3-state buffers:
– If S = 0 then OUT = IN0 else OUT = IN1
EN0
S EN0 EN1 IN0 IN1 OUT S

0 1 0 0 X 0 IN0

0 1 0 1 X 1 OUT
EN1
1 0 1 X 0 0
IN1
1 0 1 X 1 1

• The outputs of the 3-state buffers are wired together

• Since EN0 = S and EN1 = S, one of the two buffer outputs is
always Hi-Z
 Implementing a XOR Gate
• We can use 3-state buffers A
X
to implement a XOR gate as
shown F = AB
B
• B = 0 will enable the 3-state Y
buffer with output X (F = X
= A) Truth Table
• B = 1 will enable the 3-state A B X Y F
buffer with output Y (F = Y 0 0 0 Hi-Z 0
= A) 0 1 Hi-Z 1 1
• Therefore, F = A  B 1 0 1 Hi-Z 1
1 1 Hi-Z 0 0