Analog Signal Processing

Assignment – 2
Name- Santanu Samanta
Roll no.- 23EE64R01
Possible configurations of realizing a capacitor using
NMOS
We can realise a Capacitor using NMOS by using the parasitic capacitances. We can use the
following three parasitic capacitances in an NMOS:
• Gate to Substrate capacitance (Cgb)
• Gate to Source capacitance (Cgs)
• Gate to Drain capacitance (Cgd)
The value of the all the above mentioned parasitic capacitances have different values at different
regions of operation of the NMOS.
So, for considering all the possible configurations we should not only consider the parasitic
capacitances but, also the regions of operation of the NMOS.
Values of parasitic capactiances in different regions of
operations:

Parasitic capacitance Cutoff Linear Saturation

Gate to Substrate Cox.W.L 0 0

capacitance (Cgb)

Gate to Source Cox.W.LD Cox.W.LD + Cox.W.L/2 Cox.W.LD + (2/3)Cox.W.L

capacitance (Cgs)

Gate to Drain capacitance Cox.W.LD Cox.W.LD + Cox.W.L/2 Cox.W.LD

(Cgd)
The possible configurations of realizing a 1pF capacitance
using the parasitic capacitances are:
1. In the cutoff region we can use the Gate to Body capacitance (Cgb).
2. In the cutoff region we can use the Gate to Source (Cgs) or the Gate to Drain capacitance (Cgd).
Both the configurations will give same value as the overlap of the gate region with the drain
and source is same.
3. In linear region we can use both the Gate to Drain or Gate to Source capacitances as both of
them will give us the same value.
4. In saturation region we can use the Gate to Source capacitance.
Specifications of the NMOS to be used for realizing a
1pF capacitance using the previously mentioned
configurations of parasitic capacitances:

Minimum Channel length (L) = 65nm

Threshold voltage (Vtn) = 0.3V
Oxide capacitance per unit area (Cox) = 12 fF/um^2
Overlap of Gate over drain and souce regions (LD) = 3.25nm
Configuration 1 – Gate to Body capacitance in cutoff
region
To realise a 1pF capacitance using Gate to Body parasitic capacitance in cutoff region we can use the
following relation :
Cox.W.L = 1pF …....(i)
where, W is the width of the NMOS transistor considered. From the previous consideration of the NMOS
specifications we have ,
Cox = 12fF/um^2 and L = 65nm
Using these values is equation (i) we can determine the width of the trnasistor required.
W = 1pF/(Cox.L) => W = 1pF/(12fF/um^2 * 65nm)
=> W = 1282.05 um
This value of W represents the required width to realise 1pF capacitance. We can also comment on the
area required to make this capacitor on a chip. The area is given by;
A = W * L = 1282.05 um * 65 nm = 83.33 um^2.
The amount of area required for this configuration is high. So, the density will be less.
Configuration 2 – Gate to Source capacitance in cutoff
region
In cutoff region we can either use the Gate to Souce (Cgs) or Gate to Drain (Cgd) parasitic
capacitance for realising our 1pF target capacitance. Both configurations will give the same value
due to the symmetric structure of our NMOS transistor. We can use the following relation to use the
realise 1pF capacitance using Cgs capacitance in cutoff region:
Cox.W.LD = 1pF …........(ii)
Here, W is the required width of the NMOS transistor. Putting the values into equation (ii) from
our NMOS specifications we get;
W = 1pf / (12fF/um^2 * 3.25 nm)
=> W = 25641.02 um
This is the required width for realising a 1pF capacitance using Cgs at cutoff region.
We can determine the area on chip required for this configuration. For this we have to take the
width and the length of the MOS device (L).
Area = W * L = 25641.02 um * 65 nm = 1666.67 um^2
Compared to the Configuration 1 we can see that the area usage has significantly increased. So,
density will be significantly lesser as compared to Configuration 1.
Configuration 3- Gate to source capacitance in Linear
region
In Linear region of the NMOS we can use the Gate to Source (Cgs) or Gate to Drain (Cgd) parasitic
capacitances to realise 1pF capacitance. Both will provide the same relation due to the symmetric
design of the NMOS device. We can use the following relation to use the realise 1pF capacitance
using Cgs capacitance in Linear region:
(½).Cox.W.L + Cox.W.LD = 1pF …............(iii)
Here, W is the required width of the NMOS transistor for this configuration. Putting the values of
our NMOS device in equation (iii) we get;
W = 1pF / [(0.5*L + LD)*Cox]
=> W = 1pF / [(0.5*65nm + 3.25nm)*12fF/um^2]
=> W = 2331.002 um
This is the required width for realising a 1pF capacitance using Cgs at Linear region. With this we can
determine the Area required on the chip for realising 1pF capacitance in this configuration.
Area = W * L = 2331.002 um * 65 nm = 151.51 um^2
Compared to configuration 1 the area usage is higher and compared to configuration 2 the area
usage is significantly less. So, density of this configuration will be more than configuration2 but,
lesser than configuration 1.
Configuration 4 – Gate to Source capacitance in
saturation region
In saturation region of the NMOS we can use the Gate to Source (Cgs) capacitance to realise the 1pF
capacitance. The relation between the target capacitance (1pF) and the Gate to Source capacitance
parametres in saturation region is given by;
(2/3).Cox.W.L + Cox.W.LD = 1pF ….............(iv)
Here, W is the required width of the NMOS transistor for this configuration. Putting the values of our
NMOS device in equation (iv) we get;
W = 1pF / [Cox.(0.667*L + LD)]
=> W = 1pF / [12fF/um^2 * (0.667*65nm + 3.25nm)]
=> W = 1788.07 um
This is the required width for realising a 1pF capacitance using Cgs at Saturation region. With this we
can determine the Area required on the chip for realising 1pF capacitance in this configuration.
Area = W * L = 1788.07um * 65nm = 116.22 um^2
Compared to configuration 1 the area usage is higher and compared to configuration 2 and 3 the
area usage is less. So, density of this configuration will be more than configuration2 and 3 but, lesser
than configuration 1.
Variation of capacitances with frequency for different
configurations

This above plot shows the variation of MOS capacitance mainly the parasitic capacitance between
Gate and Body (Cgb) with change in Gate voltage VG for different frequency bands. One thing we
can observe from this plot is that the value of Cgb decreases with increase in frequency.
Now, with this we have to find how the capacitances in the previous four configurations will vary
as frequency is varied from 1MHz to 1GHz which is from Medium frequency band to Ultra High
Frequency band.
Configuration 1 – Gate to Body parasitic capacitance in Cutoff region
So, when in Cutoff region the VG value lies in the Depletion region just before the weak inversion
region. From the C-V characteristics we can see that the value of the MOS capacitance for different
frequency bands mentioned is not changing in depletion region. But, there can be slight ecrease
but, the change in the capacitance for this configuration in cutoff region will not be much signficant.
Conclusion: The value of the capacitance in this configuration will not deviate much from the 1pF
value with increase in frequency.

Configuration 2 – Gate to Source Capacitance in Cutoff region

The value of Cgs in cutoff region doesn't depend on the value of Cgb (Gate to Body) capacitance due
to the presence of depletion region between source and drain. So, the value of the capacitance will
only depend on the width, length of Gate-Oxide overlap and Cox value of the NMOS and not the
frequency of operation. These parametres remian constant for realizing 1pF capacitance.
Conlusion: The value of capacitance in this configuration will remain constant with increase in
frequency from 1MHz to 1GHz.
Configuration 3 – Gate to Source capacitance in Linear region
In Linear region the value of VG is greater than Vtn. So, according to the C-V curve we can say that
the MOS device will be in inversion region. Also, the value of the MOS capacitance varies with
respect to change in frequency. The Gate to Source capacitance in Linear region depends on both
the capacitance due to the Gate-Oxide overlap with the source region and also the MOS
capacitance. Due to this dependency, the capacitance of this configuration will vary with change in
frequency.
Conclusion: In inversion region the value of capacitance decreases with increase in frequency. So, as
we vary the frequency from 1MHz to 1GHz the value of the capacitance will decrease from 1pF.

Configuration 4 – Gate to Source capacitance in Saturation region

In Saturation region, the value of Gate to source parasitic capacitance also depends on the MOS
capacitance value as the MOS device operates in inversion region. Due to this dependency, the
capacitance of this configuration will also vary with change in frequency.
Conclusion: The value of capacitance in this configuration will also decrease as we increase the
frequency of operation from 1MHz to 1GHz.
Variation of Threshold Voltage (Vtn) of NMOS with
respect to temperature
The threshold voltage is given by;

In the above equation, the first term represents the metal

semi conductor work function. The metal work function is
fixed with respect to temperature but the semiconductor
work function is a function of temperature.
The semiconductor work function directly depends on Efi – Efp
value (the energy gap between Intrinsic and extrinsic fermi
level of the P type substrate). Efi – Efp = KT*ln(p/ni) where,
K = Boltzmann constant
T = Temperature in Kelvin
Figure - Plot of Vtn vs Temperature
P = Acceptor concentration
Ni = Intrinsic carrier concentration
So, Vtn will be directly proportional to (–)KT*ln(p/ni). Vtn will
decrease linearly with respect to increase in temperature.
Variation of Threshold voltage (Vtn) of NMOS with
increase in channel length:

The above plot shows the variation of Vth with increase in Channel length. For short channel lengths
we can see that the increase in Threshold voltage for small increase in channel length is high. As we
increase the channel length from Lmin to 10*Lmin the increase in Threshold voltage almost
saturates to some maximum value.
Variation of Threshold voltage (Vtn) of NMOS
with increase in channel width:

The above plot shows the variation of Vth with increase in Channel Width. For small value of
channel width we can see that the increase in Threshold voltage for small increase in channel width
is high. As we increase the channel width from min_W to 10*min_W the increase in Threshold
voltage almost saturates to some maximum value.