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Thermal Performance of 3D IC Package with Embedded TSVs

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Journal of Microelectronics and Electronic Packaging (2012) 9, 1-7
Copyright © International Microelectronics And Packaging Society
ISSN: 1551-4897
Thermal Performance of 3D IC Integration
with Through-Silicon Via (TSV)
Heng-Chieh Chien, John H. Lau, Yu-Lin Chao, Ra-Min Tain, Ming-Ji Dai, Sheng-Tsai Wu,
Wei-Chung Lo, and Ming-Jer Kao
Abstract
Thermal performance of 3D IC integration is inves-
tigated in this study. Emphasis is placed on the determination of
a set of equivalent thermal conductivity equations for Cu-filled
TSVs with various TSV diameters, TSV pitches, TSV thicknesses,
passivation thicknesses, and microbump pads. Also, the thermal
behavior of a TSV cell is examined. Furthermore, 3D heat trans-
fer simulations are adopted to verify the accuracy of the equiva-
lent equations. Finally, the feasibility of these equivalent equations
is demonstrated through a simple 3D IC integration structure.
Keywords
3D IC integration, equivalent thermal conductivities
of Cu-filled TSVs, SiO2, through silicon via (TSV)
INTRODUCTION
hermal management is one of the critical issues of 3D IC
T integration [1-19]. This is because [9-19]: (1) the heat flux
generated by stacked multifunctional chips in miniature pack-
ages is extremely high; (2) 3D circuits increase the total power
generated per unit surface area; (3) chips in the 3D stack may
be overheated if cooling is not properly and adequately pro-
vided; (4) the space between the 3D stack may be too small for
cooling channels (i.e., no gap for fluid flow); and (5) thin chips
may create extreme conditions for on-chip hot spots. Thus,
effective thermal management design methods, tools, guide-
lines, and solutions are desperately needed for widespread use
of 3D IC integration.
Even with the most advanced software and high-speed hard-
ware, it is very time-consuming to model all the TSVs in a 3D
IC integration system-in-package (SiP). In [10, 15, 16], empir-
ical equations for the equivalent thermal conductivities of TSV
chips/interposers with various copper (Cu)-filled TSV diame-
ters, pitches, and aspect ratios have been determined. Unfortu-
nately, the passivation layer (SiO2) was not considered.
In this study, empirical equations for the equivalent thermal
conductivities of Cu-filled TSV chips/interposers with various
passivation thicknesses, TSV diameters, TSV pitches, TSV
thicknesses, and microbump pads, are determined. Also, the
thermal behavior of a Cu-filled TSV cell with a SiO2 layer is
examined. Furthermore, 3D heat transfer simulations are per-
formed to verify the accuracy of the equivalent equations.
Manuscript received September 2011 and accepted April 2012
Electronics and Optoelectronics Research Laboratories Industrial Technol-
ogy Research Institute (ITRI), Chutung, Hsinchu, Taiwan
*Corresponding author; email: Jack_Chien@itri.org.tw
doi:10.4071/imaps.309 1551-4897 © 2012 International Microelectronics And Packaging Society
Finally, the feasibility of these equivalent equations is demon-
strated through a simple 3D IC integration SiP.
CU-FILLED TSV EQUIVALENT THERMAL
CONDUCTIVITY EXTRACTION
A. Simulated Model Establishment
Fig. 1 shows and defines a TSV cell for extracting its equiv- F1
alent thermal conductivities, and Table I shows the parameter T1
matrix for simulations. In the figure and table, DTSV is the
diameter of the TSV (from 10-50 mm); H is the chip thickness
(from 10-200 mm; the thinner chips are meant for stacked
memories, while the thicker chips are for active/passive inter-
posers); P denotes the TSV pitch; and tSiO2 denotes the thick-
ness (from 0.2-1.0 mm) of the deposited SiO2.
The equivalent thermal conductivities to be extracted
include kxy and kz. The subscripts xy and z mean, respectively,
the in-plane direction and cross-plane direction of the chip/
interposer. For Cu-filled TSV in-plane equivalent thermal con-
ductivity (kxy), we apply a positive heat flux (Qin00 ) to one of its
sidewalls (called the hot surface); and a negative heat flux
00
(
Qout ) to the opposite sidewall (called the cold surface) for
drawing out the heat, as shown in Fig. 2. Based on Fourier’s F2
law, we have the equivalent, kxy, which can be expressed as
Thot
Tcold
Qin00 ¼ kxy 
P
where Thot and Tcold are the average temperature of the hot
surface and the cold surface, respectively, and P is the TSV pitch.
For extracting the Cu-filled TSV cross-plane equivalent ther-
mal conductivity (kz), we add one buffer block on the top side of
the TSV and one at the bottom side as shown in Fig. 3. The F3
buffer blocks serve to smooth the heat flow that enters and exits
the cell in order to obtain a more reliable and accurate result.
Again, by using Fourier’s law, the equivalent thermal con-
ductivity kz can be expressed as
Thot
Tcold
Qin00 ¼ kz 

H
where Thot and Tcold are defined as the average temperature of
the hot section and the cold section, respectively, and DH is
the spacing between both sections and is assumed to be 2 mm.
2 Journal of Microelectronics and Electronic Packaging, Vol. 9, No. 2, 2nd Qtr 2012

Fig. 1. Schematic diagram of a TSV cell.

Table I
The Analyzed Parameters Matrix

DTSV (mm) 10 20 30 40 50
H (mm) 10, 20, 30, 10, 20, 50, 10, 20, 50, 10, 20, 50, 10, 20, 50,
50, 100, 100, 150, 100, 150, 100, 150, 100, 150,
150 200 250 250 250
P (mm) 25, 35, 40, 35, 45, 55, 45, 55, 65, 55, 65, 75, 65, 75, 85,
50, 70, 65, 80, 75, 100, 85, 100, 100, 150,
100, 130 120, 150 150, 200 150, 200 200
tSi02 (mm) 0.2, 0.5, 0.2, 0.5, 0.2, 0.5, 0.2, 0.5, 0.2, 0.5,
1.0 1.0 1.0 1.0 1.0

Fig. 2. TSV cell for kxy extraction. (a) The stereogram of the cell, and (b) the
The hot and cold sections are mutually parallel and symmetri- cross section of the cell.
cal to the cell horizontal central line of the Cu-filled TSV.

B. Boundary Conditions and Material Properties

In this study, we use Icepak 12.1.6 as the simulation tool to
solve heat conduction problems using the finite volume method.
The thermal conductivities of silicon, TSV filled copper, copper
pad, and SiO2 are 148, 401, 401, and 1.38 W/mK, respectively.
As for the thermal conductivity of the buffer block, the value is
flexible because the purpose of this block is to smooth the heat
flow that enters and exits the TSV cell. Thus, in this study, the
thermal conductivity of the buffer blocks is assumed to be
500 W/mK, and their thickness is 50 mm.
The boundary conditions for the simulations are shown in
Figs. 2 and 3. A constant heat flux (Qin00 ) is applied to the
heating surface and the value is assumed to be 108 W/m2.
00
Also, at the cooling surface, a negative heat flux (Qout ) is
applied to draw out the heat. According to the law of energy
conservation, the absolute values of both heat fluxes must be
equal. As for other boundary conditions, all other surfaces are
defined as adiabatic for structure symmetry.

C. Equivalent Thermal Conductivity Calculation

For demonstration purposes, we consider the following
values: DTSV ¼ 20 mm, tSiO2 ¼ 1 mm, H ¼ 50 mm, P ¼ 65 mm, Fig. 3. TSV cell for kz extraction. (a) The stereogram of the cell, and (b) the
and heat flux Qin00 ¼ 108 W/m2. cross section of the cell.
 Chien et al.: Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV) 3

For equivalent kxy extraction, from the simulation results, we

determine the average temperature difference (Thot
Tcold ¼
48.3 C) between the hot surface and the cold surface. Since P ¼
65 mm and Qin00 ¼ 108 W/m2, the equivalent kxy can be calculated
from Fourier’s law and is equal to 134.57 W/mK.
For equivalent kz extraction, from the simulation results, we
determine the average temperature difference (Thot
Tcold ¼
1.06 C) between the hot section and the cold section. Since
Qin00 ¼ 108 W/m2, and DH ¼ 2mm, then from Fourier’s law, the
equivalent kz is 188.68 W/mK.

THERMAL BEHAVIOR OF A TSV CELL

A. The Lateral Heat Transport of the Cell
F4 Fig. 4 shows the temperature distribution on the horizon
central portion of a TSV cell. The length and width of the cell Fig. 5. Typical correlations between equivalent kxy and SiO2 thickness: the
are the same and equal to the TSV pitch. The passivation layer chip thickness (H ) is 50 mm and the pitch is 65 mm.
(SiO2) and the filled copper is embedded in the cell. It can be
observed that, for a thick (>0.2 mm) passivation layer, the heat
flow detours around the TSV, because the passivation layer has
rather poor thermal conductivity (k ¼ 1.38 W/mK for SiO2)
compared with the silicon (k ¼ 148 W/mK). In fact, even
though the filled copper of the TSV has a very high thermal
conductivity (k ¼ 401 W/mK), the heat flow is still blocked by
the passivation layer, and thus wears down the contribution of
copper for thermal performance enhancement in the chip lat-
eral direction.
Based on parameter studies, it is found that the effect of chip
thickness (H) on equivalent kxy is insignificant compared to other
parameters. In addition, for thicker (>0.2 mm) passivation (SiO2)
layers, which block the heat from entering the filled Cu, and thus
curve (i.e., make) the heat flow path longer. All the equivalent
lateral thermal conductivities (kxy) are smaller than that of silicon
(148 W/mK), especially for larger TSV diameters.
Fig. 6. Typical correlations between equivalent kxy and TSV diameter with
different TSV pitches. The chip thickness (H ) is 50 mm and the SiO2 thick-
nesses (tSiO2) are 0.2 and 0.5 mm.

The effect of SiO2 thickness on equivalent kxy is noticeable,

as shown in Fig. 5. It can be seen that a thicker SiO2 layer F5

(>0.2 mm) and a larger TSV diameter (>10 mm) result in a

lower equivalent kxy. However, for a thinner SiO2 layer (0.2 mm),
regardless of the TSV diameters, the equivalent kxy approaches
that of silicon (148 W/mK), as shown in Fig. 5.
The effect of the TSV pitch on the equivalent kxy is notice-
able, as shown in Fig. 6. In general, a larger TSV density F6

(smaller TSV pitch), a thicker (>0.2 mm) SiO2 layer, and a

larger TSV diameter (>10 mm) result in a lower equivalent kxy.
However, when the SiO2 thickness is 0.2 mm, regardless of the
TSV diameter and the TSV pitch, the equivalent kxy approaches
the value of silicon (148 W/mK), as shown in Fig. 6.
The diameter and pitch of TSV are the other two significant
parameters for equivalent kxy. Fig. 6 shows the correlation
between kxy and TSV diameter, and between kxy and TSV
pitch. A larger equivalent kxy is caused by a smaller TSV
dimension ratio expressed as DTSV P. In other words, the
Fig. 4. Heat flow path and temperature distribution in lateral direction of a chip/interposer with higher TSV density will have a worse
TSV cell. thermal conductivity in the lateral direction.
 4 Journal of Microelectronics and Electronic Packaging, Vol. 9, No. 2, 2nd Qtr 2012

B. The Longitudinal Heat Transport of the Cell

F7 Fig. 7 shows the temperature distribution in the vertical
direction of a Cu-filled TSV cell. Since copper has a higher
thermal conductivity than silicon, there is more heat flow
inpour and outflow through the cell via the filled copper. Also,
the temperature of the filled copper and silicon must equalize
at the vertical central portion, due to energy equilibrium.
Therefore, some heat flow may cross the passivation layer
from copper to silicon after entering the TSV cell, and the heat
flow may cross the passivation layer again from silicon to the
filled copper before exiting the TSV cell.
The passivation layer (SiO2) serves as a thermal barrier in
F8 the TSV cell. Fig. 8 shows the effect of SiO2 thickness and
TSV thickness (H ) on the equivalent longitudinal thermal con-
ductivity (kz) for the case where TSV pitch ¼ 50 mm and TSV
diameter ¼ 10 mm. It can be seen that, in general: (1) for all the Fig. 8. Typical correlations between equivalent kz and passivation layer
SiO2 thicknesses and TSV thicknesses, the value of kz is larger thickness: the TSV pitch is 50 mm, and the TSV diameter is 10 mm.
than that of silicon (due to the positive effect of Cu and the
negative effect of SiO2); (2) for H ¼ 100 mm (like interposers),
the SiO2 thickness has no effect on kz; (3) for H ¼ 50 mm (e.g.,
for memory-chip stacking), the SiO2 thickness (from 0.2-0.5 mm)
has little effect on kz; and (4) at SiO2 ¼ 0.2 mm, the kz is almost
the same for H ¼ 50 mm (memory-chip stacking) and H ¼
100 mm (interposers).
F9 Fig. 9 shows the effect of TSV diameter and TSV pitch on kz
where TSV thickness (H) ¼ 50 mm and SiO2 thickness ¼ 0.2 mm.
It can be seen that: (1) in general the larger the TSV diameter,
the larger the kz; (2) the smaller the TSV pitch the larger the kz;
and (3) again, for all SiO2 thicknesses, TSV thicknesses, TSV

Fig. 9. Correlations between equivalent kz and the TSV diameter. The chip
thickness (H ) is 50 mm and the SiO2 thickness (tSiO2) is 0.2 mm.

pitches, and TSV diameters, the kz is larger than that of sili-

con (due to the positive effect of Cu and the negative effect
of SiO2).
The simple explanation of previous results is that a thicker
passivation layer may obstruct the heat exchange between the
filled Cu and Si; thus, more heat flux remains to flow through
the Cu, which consequently enhances the weight (influence) of
the filled Cu for the cell thermal performance. On the other
hand, a TSV with higher aspect ratio (H/DTSV) leads to a lower
equivalent kz, because more heat exchange has occurred
between the Cu and Si during the heat flow through the TSV
cell, which reduces the influence of the filled Cu for the TSV
cell thermal performance.

CU-FILLED TSV EQUIVALENT THERMAL

Fig. 7. Temperature distribution in the vertical direction of a TSV cell.
CONDUCTIVITY EQUATIONS
A. Equivalent Thermal Conductivity Equations kxy and kz
By curve fitting of the simulation results for all the cases
considered in Table I, we have the empirical equations of the
Cu-filled TSV equivalent thermal conductivity equations.
 Chien et al.: Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV) 5

For equivalent kxy, the empirical equation is

 

0:33

DTSV
kxy ¼ 90  tSiO2
148   H 0:1 þ 160  tSiO2
0:07
P
For equivalent kz, the empirical equation is
 
tSiO2 DTSV
0:002   0:01 ) kz ¼ 128  exp
H P
where
0:2 mm  tSiO2  0:5 mm
10 mm  DTSV  0:5 mm
H  20 mm
D
0:1  TSV
P  0:77

Fig. 11. Comparison between the simulation data (dot) and equivalent kz
B. Comparison Between the Results Obtained from kxy and kz equation (curve). The error bar is 10%.
and from 3D Heat Transfer Simulations
F10
F11
F10 ; F11 Figs. 10 and 11 show the comparisons between the 3D
simulation data and the equivalent equations. For equivalent
kxy and equivalent kz, it can be seen that the largest error of
the empirical equations is less than 15%. Most simulation
data agree with the equivalent equations, with an error of less
than 10%.

C. How to Use Equivalent Thermal Conductivity Equations

(kxy and kz ) for 3D IC Integration
The equivalent equations can be used for the design and anal-
ysis of 3D IC SiPs by establishing an equivalent model. This
equivalent model is used to replace the real detailed TSV model
F12F12 for simplifying the thermal simulations. Fig. 12 shows how a

detailed TSV model can be converted into an equivalent model.

The equivalent model regards the TSV group as an equiva-
lent zone (block), which is represented with the calculated
equivalent kxy and kz. The passivation layers (SiO2) outside
the TSVs are modeled. The solder balls (or bumps) and the
Fig. 12. The conversion from a detailed model to an equivalent model. (a) The
detailed model, and (b) the equivalent model.

traces are converted to other equivalent zones by using the

common thermal resistance (series/parallel) calculations.

VERIFICATION OF THE TSV EQUIVALENT THERMAL

CONDUCTIVITY EQUATIONS
Fig. 13 shows a 3D IC integration SiP. There are four mem- F13

Fig. 10. Comparison between the simulation data (dot) and equivalent kxy
equation (curve). The error bar is 10%.
ory chips (each with three TSVs and the TSV diameter is
DTSV ¼ 10 mm) bonded together (with a 20 mm diameter
microbump) on top of an interposer. Each chip has two heaters
(on opposite directions) and each heater generates a heat flux
of 1 × 106 W/m2. The chip thickness is 50 mm. The SiO2
thickness ¼ 0.2 mm. Each chip size is 10 mm × 10 mm and
each dissipates 0.8 W of heat. Thus, for the four-chip stacking,
the total power generated from the heat is 3.2 W.
The boundary conditions are: h ¼ 10,000 W/m2K on the
top side of the model and h ¼ 500 W/m2K on the bottom of
 6 Journal of Microelectronics and Electronic Packaging, Vol. 9, No. 2, 2nd Qtr 2012
Fig. 13. Detail and equivalent models for feasibility verification. (a) The
detailed model, and (b) the equivalent model. There are two heaters on a chip
and each heater generates 106 W/m2.
the interposer. Physically, it means the SiP has an air cooling
heat sink on the top side and natural convection cooling on
the bottom side. The slice model is introduced: (1) because it
is a semi-2D model that can simplify the simulation effort,
and (2) for the verification and demonstration of its accuracy
and feasibility.
F14F14 Fig. 14 shows the temperature distributions of the detailed
model (left) and the equivalent model (right). It can be seen
that: (1) the TSVs are dissipating the accumulated heat from
the chips to ambient (left), and (2) even the heat flow within
both models is different; however, the temperatures of the
heaters of the two models are quite the same.
F15F15 Fig. 15 shows the heater temperature comparisons between the
detailed model and the equivalent model. It can be seen that: (1)
for all the TSV pitches, both models predict almost the same
heater temperature; (2) for all the TSV pitches, the smallest
heater temperature occurs at the top chip #4 and the largest heater
temperature occurs at the bottom chip #1 (this is because the
main dissipation path of the heat is via the model top side to
the ambient); and (3) except for the top chip, the smaller the
TSV pitch (a denser TSV arrangement), the lower the heater
temperature (this is caused by the higher longitude equivalent
thermal conductivity (kz) of TSV and microbumps).
Fig. 14. A typical temperature distribution of the detailed model (left) and
the equivalent model (right). Here, DTSV, tSiO2, H, and bump diameter are 10,
0.2, 50, and 20 mm, respectively. The boundary conditions and heat generation
are shown in Fig.13.
Fig. 15. Heater temperature comparison: DTSV, H, tSiO2, and bump diameter
are 10, 50, 0.2, and 20 mm, respectively. The ambient temperature is 35 C.
What would the thermal path and temperature distribution of
the memory-chip stacking be with microbumps but without
TSVs? The simulation results show that all the chip tempera-
tures are higher than those of the model with TSVs (Cu-filled
TSVs provide a better thermal conducting path than Si). The
temperature is higher by about 2.5 C for chip #4, 2 C for chip
#3, 1.2 C for chip #2, and 0.1 C for chip #1. These results
indicate that TSVs do indeed increase the chips’ heat dissipa-
tion effect, and thermal performance. For this simple example,
the thermal performance enhancement is about 6%.
SUMMARY AND RECOMMENDATIONS
Empirical equations for the equivalent thermal conductivi-
ties of Cu-filled TSV chips/interposers with various passiv-
ation thicknesses, TSV diameters, TSV pitches, TSV thicknesses,
and microbump pads were determined in this investigation.
Also, the thermal behavior of a SiO2-Cu-filled TSV cell was
discussed. Furthermore, the accuracy of the equivalent equa-
tions was verified by 3D heat transfer simulations. Finally,
the feasibility of these equivalent equations was demon-
strated through a simple 3D memory-chip stacking structure.
Some important results and recommendations are summarized
as follows.
1. kxy and kz for SiO2-Cu-filled TSV memory-chip stacking
and interposer have been provided and they are very useful
for 3D IC integration design and analysis.
2. Based on the 3D simulation results, most errors of kxy and kz
are within 10% and in a few cases the maximum error is 15%.
3. For thermal performance of 3D IC integration, the SiO2
layer serves as a thermal barrier in a TSV, which reduces
the value of kxy and kz. On the other hand, the filled Cu
increases the value of kxy and kz.
4. For most cases considered in this study, the value of kxy is
smaller than that of silicon, that is, the effect of the SiO2
layer is larger than that from the filled Cu (i.e., the SiO2
layer blocks the heat flow into the filled Cu). However,
for the practical cases (real applications) such as SiO2 ¼
0.2 mm and H ¼ 50 mm for memory-chip stacking and H ¼
100-200 mm for interposer, the value of kxy is almost the
same as silicon’s.
Chien et al.: Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV)
5. For all the cases considered in this study, the value of kz is
larger than that of silicon, that is, the contribution of the
filled Cu is larger than the negative effect of the SiO2 layer.
6. The guidelines for using kxy and kz for 3D IC integration SiP
have been provided through examples.
7. For the simple 3D IC integration SiP examples considered
herein (memory-chip stacking with TSVs and without TSVs),
the TSV thermal performance enhancement is about 6%.
8. Thermal management is on the critical path of 3D IC inte-
gration and 3D Si integration. The research institutions and
electronic industry should: (a) perform more innovative
researches and collect more useful data in this area, and (b)
provide some effective thermal management design methods,
tools, guidelines, and solutions for the widespread use of
3D Si/IC integrations.
ACKNOWLEDGMENTS
The authors would like to thank the VP and Director of
Electronics & Optoelectronics Research Labs, Dr. Ian Yi-Jen
Chan for his strong supports on this project. Also, the authors
are grateful for financial support from the Ministry of Eco-
nomic Affairs (MOEA), Taiwan.
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