Layout Tut2

NC State University Spring 2019
ECE Department ECE 546 W. Rhett Davis

Layout Tutorial 2: LVS and Parasitic
Extraction using Calibre
In this tutorial you will create the schematic and layout for a NAND gate, and then perform a layout-vs.-
schematic (LVS) check to verify the connectivity. You’ll also perform a parasitic extraction and generate
an HSPICE netlist with accurate wire- and source-/drain, adjacent wires capacitances, as well as wire
resistances generated from the layout.
Contents
1. Launch the Environment .................................................................................................................................... 1
2. Create the NAND2 Schematic ........................................................................................................................... 1
3. Create the NAND2 Symbol ............................................................................................................................... 2
4. Create the NAND2 Layout ................................................................................................................................ 3
5. LVS .................................................................................................................................................................... 6
5.1. Perform an LVS Check without Errors ...................................................................................................... 8
5.2. Perform an LVS Check with Errors ..........................................................................................................11
6. Extract Parasitics ...............................................................................................................................................14
6.1. Extract with Parasitic Capacitances and Resistances ................................................................................14
6.2. Extract with Parasitic Capacitances Only .................................................................................................20
7. Testing the Extracted Netlist in Simulation ......................................................................................................21
7.1. Config and Hierarchy Editor .....................................................................................................................28
7.2. Simulations ...............................................................................................................................................28
1. Launch the Environment

add cadence2018 calibre2018.2 synopsys2018
setup_freepdk15
virtuoso &
2. Create the NAND2 Schematic

Create a cell called “nand2”, and make a schematic like the one shown below. Give each transistor three fins. Note
that you can add a “Wire Name” to internal nodes by selecting Create→Wire Name or by hitting the “l” (lower
case “L”) key. The figure shows that the node between the two NMOS transistors has been given the name “X”.
When you generate an HSPICE netlist, this node will now have a more meaningful name, rather than something
random like “NET41”.
Check and save the schematic.
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3. Create the NAND2 Symbol

Open the schematic view of NAND2. Choose Create→Cellview→From Cellview, and then you see a
pop-out. Leave the defaults, and hit “OK”. Then You have chance to modify it. See the plots below:
Check and save the schematic.
You may edit the shape to look like the NAND gate below, but it is not required. If you do edit the
symbol, then make sure that all the ports are on the peripheries of the red box and that all the lines and
shapes inside of the red box are connected each other. Remember to always click “check and save” when
you are done with your edits.
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4. Create the NAND2 Layout

Now create the layout view. For the fastest results, start with the completed layout from Layout Tutorial 1.
Use the Library Manager to copy the layout cell-view from that cell into this one.
Open the layout and make a few changes. First, we won't be using the M1A and M1B layers anymore, since
they're not supported for LVS and parasitic extraction. Instead, we will use M1, which is an "uncolored"
layer that uses the most dense spacing rules (i.e. M1A-to-M1B spacing rules, rather than M1A-to-M1A
spacing rules). Select every M1A and M1B shape and then hit the "q" key to edit it's properties. Change the
layer to M1 and click "Ok". Note that if you have multiple shapes selected, then you can click the "common"
button in the properties dialog to change the layer for multiple shapes at the same time. After changing the
shapes, change the via instances by swapping the M1A_AIL2 and M1B_AIL2 vias for M1_AIL2. This can
be done in the properties dialog by changing the cell-name. Also swap the M1A_GIL via for M1_GIL.
When you are done, assuming you have the "used" checkbox selected in your layer-list, you should see only
M1 appear in the layer-list, and M1A and M1B should disappear.
Finally delete the pins "in" and "out", to be consistent with our new schematic. Create new pins in the M1
layer named "A" and "Z" as shown below. Note that the NW, NIM, and PIM layers are not shown, for
clarity. Note also that the pin-names have been enhanced to appear white in these images, for clarity. They
should appear blue for you (the same color as the rectangle).
-3-
Now add another finger to each transistor by adding two instances each of nmos_pcell and pmos_pcell to
the right of the nmos/pmos_pcell instances that are already there. Change the GATE parameter for these
instances from A to B. Then, make sure that the GATEA and GATEB shapes overlap exactly. Finally, paint
a small rectangle of GATEA to connect the new dummy shape as shown below. What was previously a
dummy GATEB shape is now a new transistor that shares the same active area.
-4-
Next, we need to make the M1 connections to match our schematic. Make the following changes. When
done, your layout should look like the one below.
 Move the NMOS-drain-connected M1_AIL2 via from the center drain to the right-most drain and
create a new M1 rectangle to maintain its connection to the Z output.
 Copy the PMOS-source-connected M1_AIL2 via to the right-most source.
 Copy the M1_GIL via and GIL rectangle from the GATEA line to the opposite side of the
GATEB line. Then add a pin in the M1 layers named "B" to this via.
-5-
When you are done creating the layout, save the design. Make sure that the layout is DRC clean.
5. LVS
To perform a layout-vs.-schematic (LVS), choose Calibre→Run LVS.... The LVS form appears, as shown
below. If you do not see the window appear, or if you get an error, then it's possible that you didn't type
"add calibre" as instructed above. You will need to exit Virtoso, log out, and log back in, setting up your
environment in the correct order. If that still doesn't work, then try typing 'mgc_calibre_run_lvs' in the CIW.
-6-
There are a number of options you need to set and know what they are.
Rules
Calibre-LVS Rules File and Calibre-LVS Run Directory are already filled in by the tool,leave them as it is.
Inputs
 Select "Hierarchial", "Layout vs Netlist"

 Under the Layout tab
 Files : nand2.calibre.gds
 Top Cell: nand2
 Layout Netlist: nand2.sp
 These options are already be filled in by the tool, leave them as is
 Format: select "GDSII" and select the option "Export from layout viewer" (This is very important)
 Under the Netlist tab

 Files: nand2.src.net
 Top Cell:nand2
 These options are already be filled in by the tool, leave them as it is
 Format: select "SPICE" and select the option "Export from schematic viewer" (This is very important)
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Outputs
 Under the Report/SVDB

 LVS Report File: nand2.lvs.report
 This option is already be filled in by the tool, leave it as is
 svdb directory: svdb
 Select "View Report after LVS Finishes"
5.1. Perform an LVS Check without Errors

Set the LVS form with the options shown above. Then click the “Run LVS” button.
If LVS runs successfully, with out any error, then you will see the below window with a smile :)
Click on the "Transcript" tab in Calibre Interactive - LVS to see the log file.
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The LVS Report File - NAND2.lvs.report is also opened and a part of the report is shown below. Note that
the netlist was transformed for faster checking, and that the NAND function was recognized in the
transformation in both the layout and the schematic (which is called the "source" by Calibre). Note also that
the pins were recognized as correspondence points.
CELL COMPARISON RESULTS ( TOP LEVEL )
# ################### _ _
# # # * *
# # # CORRECT # |
# # # # \___/
# ###################
LAYOUT CELL NAME: NAND2

SOURCE CELL NAME: NAND2
------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type

------ ------ --------------
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Ports: 5 5
Nets: 6 6
Instances: 2 2 MN (4 pins)
2 2 MP (4 pins)
------ ------
Total Inst: 4 4
NUMBERS OF OBJECTS AFTER TRANSFORMATION

---------------------------------------

------ ------ --------------
Ports: 5 5
Nets: 5 5
Instances: 1 1 _nand2v (5 pins)

------ ------
Total Inst: 1 1
***********************************************************************************
INFORMATION AND WARNINGS
***********************************************************************************
Matched Matched Unmatched Unmatched Component

Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 5 5 0 0
Nets: 5 5 0 0
Instances: 1 1 0 0 _nand2v
------- ------- --------- ---------
Total Inst: 1 1 0 0
o Initial Correspondence Points:
Ports: A GND! Z B VDD!
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5.2. Perform an LVS Check with Errors
Just as an example of what can go wrong when running LVS, try removing the M1_AIL2 via that
connects the PMOS source node to VDD! in the upper right-hand corner of the layout, as shown below.
Then save the design and re-run the LVS check. You should see the following output.
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and the Error report will be as follows:
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of nets (see below).

Error: Different numbers of instances (see below).
LAYOUT CELL NAME: nand2

SOURCE CELL NAME: nand2
--------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------

------ ------ --------------
Ports: 5 5
Nets: 7 6 *
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Instances: 2 2 MN (4 pins)
2 2 MP (4 pins)
------ ------
Total Inst: 4 4
NUMBERS OF OBJECTS AFTER TRANSFORMATION

---------------------------------------

------ ------ --------------
Ports: 5 5
Nets: 6 5 *
Instances: 2 0 * MP (4 pins)
0 1 * _nand2v (5 pins)
1 0 * _smn2v (4 pins)
------ ------
Total Inst: 3 1
* = Number of objects in layout different from number in source.
***************************************************************************************
INFORMATION AND WARNINGS
***************************************************************************************
Matched Matched Unmatched Unmatched Component

Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 5 5 0 0
Nets: 5 5 1 0
Instances: 0 0 2 0 MP(PFET)
0 0 0 1 _nand2v
0 0 1 0 _smn2v
------- ------- --------- ---------
Total Inst: 0 0 3 1
o Initial Correspondence Points:
Ports: A GND! VDD! Z B
- 13 -
How would you figure out what the problem is from all this information? One thing that you should notice
is that the number of nets is listed as 7 in the layout, but only 6 in the schematic (under the INITIAL
NUMBERS OF OBJECTS). That means there is an open circuit somewhere. You can double click on the
Nets in the RVE and they should be highlighted in the layout. You can also tell the RVE to draw a simple
schematic that it has extracted from the layout in the RVE. I use this feature very often when debugging
LVS errors. Make sure that everything is connected as you think it should be.
You can also purposefully make a short circuit in either the layout or schematic to see an error. Try making
some more errors to get familiar with debugging LVS errors. (IMPORTANT NOTE - whenever you make
any change to schematic, make sure you "Check and Save" and not just "Save", before you run LVS once
again. If you dont do so, the LVS will give an error saying it cannot export the schematic.) One aspect that
is not currently checked by our LVS rules is the transistor dimensions. Therefore, changing parameters such
as NFINS, W, and L in the schematic will not affect the LVS check at all. We hope to fix this in a future
release of the FreePDK15.
In general, fixing LVS errors can be hard, so it’s a good idea to add hierarchy to your layout (explained in
the next tutorial) and keep things from getting too complex.
6. Extract Parasitics
Next, fix the layout of the nand2 gate and save the design. Now we’re going to extract the parasitic wire capacitances
and resistances from the layout.
To perform a Parasitic Extraction(PEX), choose Calibre→Run PEX.... The PEX form appears, as shown below.
If you can't find the Run PEX command, you may type 'mgc_calibre_run_pex' in the CIW window and it should
appear.
6.1. Extract with Parasitic Capacitances and Resistances

There are a number of options you need to set and know what they are. For options not mentioned below, leave
them as it is. We will use them in future if required.
Rules
Calibre-LVS Rules File and Calibre-LVS Run Directory are already filled in by the tool,leave them as it is.
- 14 -
Inputs
 Under the Layout tab

 Files : NAND2.calibre.gds
 Top Cell: NAND2
 Format: select "GDSII" and select the option "Export from layout viewer" (This is very important)

 Files: NAND2.src.net
 Top Cell:NAND2
 Format: select "SPICE" and select the option "Export from schematic viewer" (This is very important)
Outputs
 Extraction Type: Select Transistor Level, R + C + CC, No Inductance
- 15 -
 File: NAND2.pex.netlist
 Format: SPICE
 Use Names From: SCHEMATIC
 select "View netlist after PEX finishes"
 Under the Nets tab

 Extract parasitics for: Select "All Nets"
 Under the Reports tab

 PEX Report File: NAND2.pex.report
 Select "Generate PEX Report" and "View Report after PEX finishes"
 Under the SVDB tab
- 16 -
 SVDB Directory: svdb
You are going to need to select PEX → Setup → PEX Options flag. Once you have selected this, a new menu
appears called PEX Options.
PEX Options
 Under the Include tab add the following lines to Include Rules Statements:
LAYOUT CASE YES
SOURCE CASE YES
Make sure to click the check box next to Include Rules Statements
- 17 -
This will ensure that the global vdd! and gnd! nets are captured correctly for simulation later.
Finally, setup the multi-threading option in Run Control to speed up your simulation
Set the PEX form with the options shown above. Then click Run PEX button.
- 18 -
Also, if PEX has run successfully, with out any error, then you will be able to manually view PEX Report File -
NAND2.pex.report and also PEX Netlist File - NAND2.pex.netlist, which is the extracted netlist from the layout
along with parasitic capacitances and resistances.
Click on the "Transcript" tab in Calibre Interactive - PEX to see the log file.
Now let us understand the NAND2.pex.netlist File
The main hspice netlist "NAND2.pex.netlist" contains only the intentionally designed devices.
Filenames with the extensions ".pex" and ".pxi" files are included in the "NAND2.pex.netlist"
 The .pex file (actually called "NAND2.pex.netlist.pex") contains one subckt per net: each subckt containing
the RC tree structure modeling the net.
 The .pxi file (actually called "NAND2.pex.netlist.NAND2.pxi") contains the connections between the
parasitic networks i.e. containing the instance calls to the net model subckts along with the coupling
capacitors connecting between these net model instances.
The NAND2.pex.netlist is as shown below
* File: NAND2.pex.netlist
* Created: Sat Jan 30 07:09:41 2016
* Program "Calibre xRC"
* Version "v2013.4_37.29"
*
.include "NAND2.pex.netlist.pex"
.subckt NAND2 A GND! Z B VDD!
*
* VDD! VDD!
* B B
* Z Z
* GND! GND!
* A A
MM0 X N_A_MM0_g N_GND!_MM0_s N_GND!_MM0_b NFET L=2e-08 W=8.8e-08 NFIN=3
+ ADEJ=5.28e-16 ASEJ=4.56e-16 PDEJ=1.32e-07 PSEJ=1.14e-07
MM3 N_Z_MM3_d N_B_MM3_g X N_GND!_MM0_b NFET L=2e-08 W=8.8e-08 NFIN=3
MM1 N_Z_MM1_d N_A_MM0_g N_VDD!_MM1_s N_VDD!_MM1_b PFET L=2e-08 W=8.8e-08 NFIN=3
MM2 N_Z_MM1_d N_B_MM3_g N_VDD!_MM2_s N_VDD!_MM1_b PFET L=2e-08 W=8.8e-08 NFIN=3
c_87 X 0 0.0428739f
*
.include "NAND2.pex.netlist.NAND2.pxi"
*
.ends
*
*
- 19 -
Note also that Calibre has extracted the dimensions of each transistor and the source/drain regions for HSPICE
simulation. The L and NFIN parameters are set as we would expect, but the W parameter matches the width of the
ACT shape in the layout, not the effective width of the transistor. That's Ok, because the BSIM-CMG transistor
model will ignore the W parameter when the NFIN parameter is present. Also, note that for transistors MM2 &
MM3, the areas and perimeters are smaller for the shared source/drain regions than for the non-shared regions.
Calibre is calculating these areas according to the shapes in the layout for more accurate HSPICE simulation. You
may note these values are also different for MM0 and MM1, but a bug in our LVS rules is currently preventing
correct extraction for these values. We anticipate fixing this bug soon.
6.2. Extract with Parasitic Capacitances Only
Looking through the .pex and .pxi files, you should see that even this very simple circuit has resulted in hundreds
of capacitors and resistors. This level of detail is necessary to achieve the highest degree of accuracy, but for larger
circuits, it can slow an HSPICE simulation to a crawl. While the resistances are necessary to accurately understand
the delay of a circuit, the power dissipation can be predicted very well using capacitances only. We often call this a
"lumped-C model" for a net, as opposed to an "RC-tree model".
To extract a lumped-C model, make the following change in the Calibre Interactive - PEX window:
Outputs
 Extraction Type: Change from "R + C + CC" to "C + CC"

Re-run PEX as in the previous section to generate the Calibre cell view in Layout manager cell's view (see Testing
the Extracted Netlist in Simulation section below) , and you should find that you have capacitances only. Not only
that, but the number of capacitances has reduced by a factor of 10. Also, if you manually view the netlist is
simpler to read and recognize from your original schematic. Finally, note that the file "NAND2.pex.netlist.pex" is
no longer used (or created), because there is no RC tree for each net.
The new, simplified NAND2.pex.netlist is as shown below.
* File: NAND2.pex.netlist
* Created: Sat Jan 30 07:12:14 2016
* Program "Calibre xRC"
* Version "v2013.4_37.29"
*
.subckt NAND2 A GND! Z B VDD!
*
MM0 X A GND! GND! NFET L=2e-08 W=8.8e-08 NFIN=3 ADEJ=5.28e-16 ASEJ=4.56e-16
+ PDEJ=1.32e-07 PSEJ=1.14e-07
MM3 Z B X GND! NFET L=2e-08 W=8.8e-08 NFIN=3 ADEJ=9.12e-16 ASEJ=5.28e-16
+ PDEJ=2.52e-07 PSEJ=1.32e-07
MM1 Z A VDD! VDD! PFET L=2e-08 W=8.8e-08 NFIN=3 ADEJ=5.28e-16 ASEJ=4.56e-16
+ PDEJ=1.32e-07 PSEJ=1.14e-07
MM2 Z B VDD! VDD! PFET L=2e-08 W=8.8e-08 NFIN=3 ADEJ=9.12e-16 ASEJ=5.28e-16
+ PDEJ=2.52e-07 PSEJ=1.32e-07
c_5 A 0 0.0162435f
c_10 GND! 0 0.0761176f
c_16 Z 0 0.0748617f
c_20 B 0 0.0158927f
c_25 VDD! 0 0.112382f
- 20 -
c_28 X 0 0.0442415f
*
.include "NAND2.pex.netlist.NAND2.pxi"
*
.ends
*
*
ECE 546 Students:

Save your final netlist (.pex.netlist, .pex, pxi) and submit it along with the rest of your assignment.
Also submit your LVS results (make sure that the netlists match for full credit).
7. Testing the Extracted Netlist in Simulation

To simulate and run inside of ADE L then you need to extract a different view than HSPICE from the PEX Output.
To do this, use the same settings as the Manual HSPICE Extraction except modify the PEX Output to the following:
Outputs
 Extraction Type: Select Transistor Level, R + C + CC, No Inductance

 File: NAND2.pex.netlist
 Format: CALIBREVIEW
 Use Names From: SCHEMATIC
 select "View netlist after PEX finishes"
- 21 -
Then click the “Run PEX” button. It will show the pop-out below:
- 22 -
- 23 -
Note the image above has the CellMap pointing to the wrong directory. To be fixed....
You can keep most of the options as default, EXCEPT:
 Fill in the “cellmap file” as: $PDK_DIR/calibre/freepdk15.calibre.cellmap

 Calibre View Type: select “Schematic”
 Create Terminal: select “if matching terminal exists on symbol
 Always show dialog: check it
The $PDK_DIR should resolve to:
/afs/eos.ncsu.edu/lockers/research/ece/wdavis/tech/FreePDK15/calibre/freepdk15.calibre.cellmap but if it doesn't
you can put the hard coded link.
Then hit OK.
If PEX runs successfully, then return to the library manager, and you will see the calibred file generated for the
cell under your library together with its schematic, layout and symbol. You may need to unselect the cell or library
and then reselect the cell to refresh the cells list of views. Seen below:
If you get the following error, you might need to make a local copy of the cellmap file and try again: ERROR:
Length of input name (or member)
/afs/eos.ncsu.edu/lockers/research/ece/wdavis/tech/FreePDK15/calibre/freepdk15.calibre.cellmap is not valid
You can open this file and it should have a schematic representation of the extracted netlist (FETs, Capacitances,
and Resistances) inside of it.
First you need to create a testbench cell:
Using your NAND2 symbol, create a simple testbench, shown below (note, your symbol should not be a box, but
actually look like a NAND symbol. This is pretty much Schematic Tutorial 0 just with a new circuit. The symbol
geometry needs to be updated in the schematic for this example later as well as better quality images:
- 24 -
The simplest way to use your paracitic extraction you need to go into ADE L→Setup→Environment and add the
word calibre to the beginning of the switch view list. It is important to add to the beginning as when the netlist is
run, it looks for the cellviews in that order. The items in the beginning of the list have a higher priority than those
at the end of the list. This is simple and quick, but does have limitations as the extracted view will always be used.
Below I detail a more advanced method in Config and Hierarchy Editor.
- 25 -
- 26 -
- 27 -
7.1. Config and Hierarchy Editor

In some cases, you might want to switch between them and even a behavioral model. So, Later in the
semester with bigger designs you will want to use something called the hierarchy editor. To do this you
have to create a new cell view called config.
In the Library Manager window, select File→New→Cellview and select config as the view to create. This
will allow you to selectively decide what views to use in your simulation. You will want to do this for the
testbench you have created (you must do this at the top of the hierarchy).
Once you create the cell view name, you should get a popup window for configuration (if not, go double
click the config view in the library manager if you do, you will want to make sure you open both the
configuration view and the top cell view). The top cell should read your current library and testbench name.
Then click browse and select the testbench schematic for the view.
Next click Use Template... and select your hspice simulator your using (could be hspiceD or HSPICE). If
using Synopsys HSPICE then select the HSPICE from the dropdown under templates. If you dont see
HSPICE then you need to use the following template file:
/afs/eos.ncsu.edu/lockers/research/ece/wdavis/tech/FreePDK15/cdslib/setup/HSPICE
So, in that case select "OTHER" instead of hspiceD and then fill in the file name and path. Make sure there are no
trailing whitespaces if there are then the template will not fill in the correct values and be blank after you click OK.
Once you add the filename in click OK. It will automatically populate the global bindings fields (again, if these are
blank the template file path is wrong, make sure there are no whitespaces). you should see hspice in the list of global
bindings. If you chose hspiceD then you should see hspiceD in the global bindings. Click OK
You are now presented with a Hierarchy Editor with all of your cells and libraries. You can then right click the view
(usually defaults to schematic) set cell view and to use from the dropdown and use either the schematic or the calibre
view for simulation. When you make changes you need to update under the view menu to reflect the changes. You
can also launch ADE L from within the hierarchy editor and perform simulations. Note, you will want to make sure
your simulator is HSPICE in the ADE L → Setup → Simulator/Directory/Host... menu as it defaults to AMS
when using the config view.
7.2. Simulations
You should be able to create some input vectors for the 2-terminal inputs A and B. Here for example, I uses
two “vpulse” as the inputs for both A and B. The one for A has 0 and 0.8V as the voltage levels, with the
cycle time 200ps, rise time 20ps, and pulse width 80ps; the one for B also has 0 and 0.8V voltage levels,
with the cycle time 400ps, rise time 20ps, and pulse width 180ps. Then launch the ADE L as you have done
in the prior tutorials, set transient simulation from 0 to 1n, and also select net A, B, Z to be plotted, shown
below:
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See the plot shown below after running:
Congratulations! You have completed the tutorial.
- 29 -

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NC State University Spring 2019

ECE Department ECE 546 W. Rhett Davis

1. Launch the Environment

2. Create the NAND2 Schematic

3. Create the NAND2 Symbol

Check and save the schematic.

4. Create the NAND2 Layout

 Select "Hierarchial", "Layout vs Netlist"

 Under the Netlist tab

 Under the Report/SVDB

5.1. Perform an LVS Check without Errors

CELL COMPARISON RESULTS ( TOP LEVEL )

LAYOUT CELL NAME: NAND2

Layout Source Component Type

NUMBERS OF OBJECTS AFTER TRANSFORMATION

Layout Source Component Type

Instances: 1 1 _nand2v (5 pins)

Matched Matched Unmatched Unmatched Component

o Initial Correspondence Points:

Ports: A GND! Z B VDD!

and the Error report will be as follows:

CELL COMPARISON RESULTS ( TOP LEVEL )

Error: Different numbers of nets (see below).

LAYOUT CELL NAME: nand2

Layout Source Component Type

NUMBERS OF OBJECTS AFTER TRANSFORMATION

Layout Source Component Type

* = Number of objects in layout different from number in source.

Matched Matched Unmatched Unmatched Component

Ports: A GND! VDD! Z B

6.1. Extract with Parasitic Capacitances and Resistances

 Under the Layout tab

 Under the Netlist tab

 Extraction Type: Select Transistor Level, R + C + CC, No Inductance

 Under the Nets tab

 Under the Reports tab

 Extraction Type: Change from "R + C + CC" to "C + CC"

ECE 546 Students:

7. Testing the Extracted Netlist in Simulation

 Extraction Type: Select Transistor Level, R + C + CC, No Inductance

 Fill in the “cellmap file” as: $PDK_DIR/calibre/freepdk15.calibre.cellmap

7.1. Config and Hierarchy Editor

See the plot shown below after running:

Congratulations! You have completed the tutorial.

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