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Digital Circuits (DELD) Sanfoundry
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Number
System – 1”.
1. Any signed negative binary number is recognised by its ________

a) MSB
b) LSB
c) Byte
d) Nibble
View Answer
Answer: a
Explanation: Any negative number is recognized by its MSB (Most Signi icant Bit).
If it’s 1, then ı́t’s negative, else if it’s 0, then positive.
2. The parameter through which 16 distinct values can be represented is known as ________
a) Bit
b) Byte
c) Word
d) Nibble
View Answer
Answer: c
Explanation: It can be represented up to 16 different values with the help of a Word. Nibble is a
combination of four bits and Byte is a combination of 8 bits. It is “word” which is said to be a collection of
16-bits on most of the systems.
3. If the decimal number is a fraction then its binary equivalent is obtained by ________ the number
continuously by 2.
a) Dividing
b) Multiplying
c) Adding
d) Subtracting
View Answer
Answer: b
Explanation: On multiplying the decimal number continuously by 2, the binary equivalent is obtained by
the collection of the integer part. However, if it’s an integer, then it’s binary equivalent is determined by
dividing the number by 2 and collecting the remainders.
4. The representation of octal number (532.2)8 in decimal is ________

a) (346.25)10
b) (532.864)10
Created by ASHUTOSH
c) (340.67)10
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d) (531.668)10
View Answer
Answer: a
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along
with the value at that index position.
(532.2)8 = 5 * 82 + 3 * 81 + 2 * 80 + 2 * 8-1 = (346.25)10
5. The decimal equivalent of the binary number (1011.011)2 is ________

a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10
View Answer
Answer: a
Explanation: Binary to Decimal conversion is obtained by multiplying 2 to the power of base index along
1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-1 +1 * 2-2 + 1 * 2-3 = (11.375)10
Hence, (1011.011)2 = (11.375)10
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6. An important drawback of binary system is ________

a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal number
d) It requires small string of 1’s and large string of 0’s to represent a decimal number
View Answer
Answer: a
Explanation: The most vital drawback of binary system is that it requires very large string of 1’s and 0’s
to represent a decimal number. Hence, Hexadecimal systems are used by processors for calculation
purposes as it compresses the long binary strings into small parts.
7. The decimal equivalent of the octal number (645)8 is ______

a) (450)10
b) (451)10
c) (421)10
d) (501)10
View Answer
Answer: c
The decimal equivalent of the octal number (645)8 is 6 * 82 + 4 * 81 + 5 * 80 = 6 * 64 + 4 * 8 + 5 = 384 +
32 + 5 = (421)10.
8. The largest two digit hexadecimal number is ________

a) (FE)16
b) (FD)16
c) (FF)16
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d) (EF)16
View Answer
Answer: c
Explanation: (FE)16 is 254 in decimal system, while (FD)16 is 253. (EF)16 is 239 in decimal system. And,
(FF)16 is 255. Thus, The largest two-digit hexadecimal number is (FF)16.
9. Representation of hexadecimal number (6DE)H in decimal:

a) 6 * 162 + 13 * 161 + 14 * 160
b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
View Answer
Answer: a
Explanation: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of base
index along with the value at that index position.
In hexadecimal number D & E represents 13 & 14 respectively.
So, 6DE = 6 * 162 + 13 * 161 + 14 * 160.
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10. The quantity of double word is ________

a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits
View Answer
Answer: b
Explanation: One word means 16 bits, Thus, the quantity of double word is 32 bits.
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Answers.
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Digital Circuits Questions and Answers – Number

System – 2
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Number
System – 2”.
1. The given hexadecimal number (1E.53)16 is equivalent to ____________

a) (35.684)8
b) (36.246)8
c) (34.340)8
d) (35.599)8
View Answer
Answer: b
Explanation: First, the hexadecimal number is converted to it’s equivalent binary form, by writing the
binary equivalent of each digit in form of 4 bits. Then, the binary equivalent bits are grouped in terms of
3 bits and then for each of the 3-bits, the respective digit is written. Thus, the octal equivalent is obtained.
(1E.53)16 = (0001 1110.0101 0011)2
= (00011110.01010011)2
= (011110.010100110)2
= (011 110.010 100 110)2
= (36.246)8
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2. The octal number (651.124)8 is equivalent to ______

a) (1A9.2A)16
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b) (1B0.10)16
c) (1A8.A3)16
d) (1B0.B0)16
View Answer
Answer: a
Explanation: First, the octal number is converted to it’s equivalent binary form, by writing the binary
equivalent of each digit in form of 3 bits. Then, the binary equivalent bits are grouped in terms of 4 bits
and then for each of the 4-bits, the respective digit is written. Thus, the hexadecimal equivalent is
obtained.
(651.124)8 = (110 101 001.001 010 100)2
= (110101001.001010100)2
= (0001 1010 1001.0010 1010)2
= (1A9.2A)16
3. The octal equivalent of the decimal number (417)10 is _____

a) (641)8
b) (619)8
c) (640)8
d) (598)8
View Answer
Answer: a
Explanation: Octal equivalent of decimal number is obtained by dividing the number by 8 and collecting
the remainders in reverse order.
8 | 417
8 | 52 — 1
8|6–4
So, (417)10= (641)8
4. Convert the hexadecimal number (1E2)16 to decimal:

a) 480
b) 483
c) 482
d) 484
View Answer
Answer: c
Explanation: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of base
index along with the value at that index position.
(1E2)16 = 1 * 162 + 14 * 161 + 2 * 160 (Since, E = 14)
= 256 + 224 + 2 = (482)10
5. (170)10 is equivalent to
a) (FD)16
b) (DF)16
c) (AA)16
d) (AF)16
View Answer
Answer: c
Explanation: Hexadecimal equivalent of decimal number is obtained by dividing the number by 16 and
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collecting the remainders in reverse order.

16 | 170
16 | 10 – 10
Hence, (170)10 = (AA)16
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6. Convert (214)8 into decimal:

a) (140)10
b) (141)10
c) (142)10
d) (130)10
View Answer
Answer: a
(214)8 = 2 * 8v + 1 * 81 + 4 * 80
= 128 + 8 + 4 = (140)10
7. Convert (0.345)10 into an octal number:

a) (0.16050)8
b) (0.26050)8
c) (0.19450)8
d) (0.24040)8
View Answer
Answer: b
Explanation: Converting decimal fraction into octal number is achieved by multiplying the fraction part
by 8 everytime and collecting the integer part of the result, unless the result is 1.
0.345*8 = 2.76 2
0.760*8 = 6.08 6
00.08*8 = 0.64 0
0.640*8 = 5.12 5
0.120*8 = 0.96 0
So, (0.345)10 = (0.26050)8
8. Convert the binary number (01011.1011)2 into decimal:

a) (11.6875)10
b) (11.5874)10
c) (10.9876)10
d) (10.7893)10
View Answer
Answer: a
Explanation: Binary to Decimal conversion is obtained by multiplying 2 to the power of base index along
(01011)2 = 0 * 24 + 1 * 23 + 0 * 22 + 1 * 21 + 1 * 20 = 11
(1011)2 = 1 * 2-1 + 0 * 2-2 + 1 * 2-3 + 1 * 2-4 = 0.6875
So, (01011.1011)2 = (11.6875)10
9. Octal to binary conversion: (24)8 =?

a) (111101)2
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b) (010100)2
c) (111100)2
d) (101010)2
View Answer
Answer: b
Explanation: Each digit of the octal number is expressed in terms of group of 3 bits. Thus, the binary
equivalent of the octal number is obtained.
(24)8 = (010100)2
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10. Convert binary to octal: (110110001010)2 =?

a) (5512)8
b) (6612)8
c) (4532)8
d) (6745)8
View Answer
Answer: b
Explanation: The binary equivalent is segregated into groups of 3 bits, starting from left. And then for
each group, the respective digit is written. Thus, the octal equivalent is obtained.
(110110001010)2 = (6612)8
Answers.

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Digital Circuits Questions and Answers –

Arithmetic Operation
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on
“Arithmetic Operation”
1. What is the addition of the binary numbers 11011011010 and 010100101?

a) 0111001000
b) 1100110110
c) 11101111111
d) 10011010011
View Answer
Answer: c
Explanation: The rules for Binary Addition are :
0+0=0
0+1=1
1+0=1
1 + 1 = 0 ( Carry 1)
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1 1 0 1 1 0 1 1 0 1 0
+ 0 0 0 1 0 1 0 0 1 0 1
_______________________
1 1 1 0 1 1 1 1 1 1 1
_______________________
2. Perform binary addition: 101101 + 011011 = ?

a) 011010
b) 1010100
c) 101110
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d) 1001000
View Answer
Answer: d
Explanation:The rules for Binary Addition are :
0+0=0
0+1=1
1+0=1
1 + 1 = 0 ( Carry 1)
1 1 1 1 1 1
1 0 1 1 0 1
+ 0 1 1 0 1 1
_______________
1 0 0 1 0 0 0
_______________
Therefore, the addition of 101101 + 011011 = 1001000.
3. Perform binary subtraction: 101111 – 010101 = ?

a) 100100
b) 010101
c) 011010
d) 011001
View Answer
Answer: c
Explanation: The rules for Binary Subtraction are :
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
1 0 1 1 1 1
- 0 1 0 1 0 1
____________
0 1 1 0 1 0
_____________
Therefore, The subtraction of 101111 – 010101 = 011010.

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4. Binary subtraction of 100101 – 011110 is

a) 000111
b) 111000
c) 010101
d) 101010
View Answer
Answer: a
Explanation: The rules for Binary Subtraction are :
0–0=0
0 – 1 = 1 ( Borrow 1)
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1–0=1
1–1=0
1 0 0 1 0 1
- 0 1 1 1 1 0
___________
0 0 0 1 1 1
___________
Therefore, The subtraction of 100101 – 011110 = 000111.
5. Perform multiplication of the binary numbers: 01001 × 01011 = ?

a) 001100011
b) 110011100
c) 010100110
d) 101010111
View Answer
Answer: a
Explanation: The rules for binary multiplication are:
0*0=0
0*1=0
1*0=0
1*1=1
0 1 0 0 1
x 0 1 0 1 1
____________
0 1 0 0 1
0 1 0 0 1 0
0 0 0 0 0 0 0
0 1 0 0 1 0 0 0
0 0 0 0 0 0 0 0 0
___________________
0 0 1 1 0 0 0 1 1
___________________
Therefore, 01001 × 01011 = 001100011.
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6. 100101 × 0110 = ?
a) 1011001111
b) 0100110011
c) 101111110
d) 0110100101
View Answer
Answer: c
0*0=0
0*1=0
1*0=0
1*1=1
1 0 0 1 0 1
x 0 1 1 0
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___________
0 0 0 0 0 0
1 0 0 1 0 1 0
1 0 0 1 0 1 0 0
0 0 0 0 0 0 0 0 0
__________________
0 1 1 0 1 1 1 1 0
___________________
Therefore, 100101 x 0110 = 011011110.
7. On multiplication of (10.10) and (01.01), we get

a) 101.0010
b) 0010.101
c) 011.0010
d) 110.0011
View Answer
Answer: c
0*0=0
0*1=0
1*0=0
1*1=1
1 0.1 0
x 0 1.0 1
__________
1 0 1 0
0 0 0 0 0
1 0 1 0 0 0
0 0 0 0 0 0 0
_______________
0 1 1.0 0 1 0
_________________
Therefore, 10.10 x 01.01 = 011.0010.
8. Divide the binary numbers: 111101 ÷ 1001 and ind the remainder
a) 0010
b) 1010
c) 1100
d) 0011
View Answer
Answer: d
Explanation: Binary Division is accomplished using long division method.
1 0 0 1 ) 1 1 1 1 0 1 ( 1 1
1 0 0 1
__________
0 1 1 0 0
1 0 0 1
___________
0 1 1 1
Therefore, the remainder of 111101 ÷ 1001 = 0111.
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9. Divide the binary number (011010000) by (0101) and ind the quotient
a) 100011
b) 101001
c) 110010
d) 010001
View Answer
Answer: b
Explanation:
0 1 0 1 ) 0 1 1 0 1 0 0 0 0 ( 0 1 0 1 1 1
0 0 0 0
_____________________
0 1 1 0 1
0 0 1 0 1
______________
0 1 0 0 0 0
0 0 0 0 0 0
______________________
1 0 0 0 0
0 0 1 0 1
____________________
0 1 0 1 1 0
0 0 0 1 0 1
____________________
1 0 0 0 1 0
0 0 0 1 0 1
________________________
1 1 1 0 1 0
0 0 0 1 0 1
________________________
1 0 1 0 1
0 0 1 0 1
________________________
1 0 0 0 0
Therefore, the quotient of 011010000 ÷ 1001 = 101001.
10. Binary subtraction of 101101 – 001011 = ?

a) 100010
b) 010110
c) 110101
d) 101100
View Answer
Answer: a
Explanation: The rules for binary subtraction are:
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
1 0 1 1 0 1
- 0 0 1 0 1 1
____________
1 0 0 0 1 0
____________
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Therefore, the subtraction of 101101 – 001011 = 100010.
Answers.

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Digital Circuits Questions and Answers – 1’s, 2’s,

9’s & 10’s Complements – 1
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “1’s, 2’s,
9’s & 10’s Complements – 1”.
1. 1’s complement of 1011101 is ____________

a) 0101110
b) 1001101
c) 0100010
d) 1100101
View Answer
Answer: c
Explanation: 1’s complement of a binary number is obtained by reversing the binary bits. All the 1’s to
0’s and 0’s to 1’s.
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Thus, 1’s complement of 1011101 = 0100010.
2. 2’s complement of 11001011 is ____________

a) 01010111
b) 11010100
c) 00110101
d) 11100010
View Answer
Answer: c
Explanation: 2’s complement of a binary number is obtained by inding the 1’s complement of the
number and then adding 1 to it.
2’s complement of 11001011 = 00110100 + 1 = 00110101.
3. On subtracting (01010)2 from (11110)2 using 1’s complement, we get ____________

a) 01001
b) 11010
c) 10101
d) 10100
View Answer
Answer: d
Explanation: Steps For Subtraction using 1’s complement are:
-> 1’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and 1 is added to the last bit of the result.
-> Else, if there is no carry, then 1’s complement of the result is found out and a ‘-’ sign preceeds the
result.
1 1 1
Minuend - 1 1 1 1 0
1’s complement of subtrahend - 1 0 1 0 1
____________
Carry over - 1 1 0 0 1 1
1
_____________
1 0 1 0 0

a) 0111001
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b) 1100101
c) 0110110
d) 1000011
View Answer
Answer: d
-> If the result has a carry, then it is dropped and the result is positive.
result.
1’s complement of subtrahend - 1 1 0 1 0 0 1
_________________
1 1 1
Minuend - 1 0 1 1 0 0 1
2’s complement of subtrahend - 1 1 0 1 0 1 0
_________________
Carry over - 1 1 0 0 0 0 1 1
Answer: 1000011

a) 1101100
b) 011101
c) 11010101
d) 11010111
View Answer
Answer: b
result.
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1’s complement of subtrahend - 1 1 0 0 1 1

_________________
Minuend - 1 0 1 0 0 1
_________________
Carry over - 1 0 1 1 1 0 1
Answer: 011101
6. On addition of 28 and 18 using 2’s complement, we get ____________

a) 00101110
b) 0101110
c) 00101111
d) 1001111
View Answer
Answer: b
Explanation: Steps for Binary Addition Using 2’s complement:
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-> The binary equivalent of the two numbers are obtained and added using the rules of binary addition.
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Augend - 0 0 1 1 1 0 0
Addend - 0 0 1 0 0 1 0
_________________
0 1 0 1 1 1 0
Answer: 0 1 0 1 1 1 0
7. On addition of +38 and -20 using 2’s complement, we get ____________

a) 11110001
b) 100001110
c) 010010
d) 110101011
View Answer
Answer: c
Explanation: Steps for Binary Addition Using 2’s complement:
-> The 2’s complement of the addend is found out and added to the irst number.
-> The result is the 2’s complement of the sum obtained.
Augend - 0 1 0 0 1 1 0
2’s Complement of Subtrahend: 1 1 0 1 1 0 0
_________________
1 0 0 1 0 0 1 0
Answer: 0 1 0 0 1 0
8. On addition of -46 and +28 using 2’s complement, we get ____________

a) -10010
b) -00101
c) 01011
d) 0100101
View Answer
Answer: a
Explanation: The BCD form is written of the two given numbers, in their signed form. After which,
normal binary addition is performed.
Augend is 28 and Subtrahend is -46.
Augend - 0 0 1 1 1 0 0 .....(a)
2’s Complement of Subtrahend: 1 0 1 0 0 1 0 .....(b)
_________________
Addiing (a) and (b): 1 1 0 1 1 1 0
Since, there is no carry, so answer will be negative
and 2's complement of the above result is determined.
0 0 1 0 0 0 1
+ 1
_________________
0 0 1 0 0 1 0
Answer: - 1 0 0 1 0
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9. On addition of -33 and -40 using 2’s complement, we get ____________

a) 1001110
b) -110101
c) 0110001
d) -1001001
View Answer
Answer: d
Explanation: The BCD form is written of the two given numbers, in their signed form. After which,
normal binary addition is performed.
Augend is -40 and Subtrahend is -33.
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Augend - 1 0 1 0 0 0 0 1 .....(a)
2’s Complement of Subtrahend: 1 1 0 1 1 0 0 1 .....(b)
______________________
Addiing (a) and (b): 1 0 1 0 0 1 0 0 0
Since, there is no carry, so answer will be negative
and 2's complement of the above result is determined.
1 0 0 1 0 0 0
+ 1
_________________
1 0 0 1 0 0 1
Answer: -1001001
10. On subtracting +28 from +29 using 2’s complement, we get ____________
a) 11111010
b) 111111001
c) 100001
d) 1
View Answer
Answer: d
result.
Minuend - 0 1 1 1 0 1
____________________
Carry over - 1 0 0 0 0 0 1
Answer: 000001 = 1
Answers.
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Digital Circuits Questions and Answers – 1’s, 2’s,

9’s & 10’s Complements – 2
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This set of Digital Electronic Circuits Interview Questions and Answers focuses on “1’s,2’s,9’s & 10’s
Complements-2”.
1. If the number of bits in the sum exceeds the number of bits in each added numbers, it results in
_________
a) Successor
b) Over low
c) Under low
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d) Predecessor
View Answer
Answer: b
Explanation: If the number of bits in the sum exceeds the number of bits in each added numbers, it
results in over low and is also known as excess-one. In case of any arithmetic operation, if the result has
less number of bits than the operands, then it is known as under low condition.
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2. An over low is a _________

a) Hardware problem
b) Software problem
c) User input problem
d) Input Output Error
View Answer
Answer: b
Explanation: An over low is a software problem which occurs when the processor cannot handle the
result properly when it produces an out of the range output.
3. An over low occurs in _________

a) MSD position
b) LSD position
c) Middle position
d) Signed Bit
View Answer
Answer: a
Explanation: An over low occurs at Most Signi icant Digit position. It occurs when the processor cannot
handle the result properly when it produces an out of the range output.
4. Logic circuitry is used to detect _________

a) Under low
b) MSD
c) Over low
d) LSD
View Answer
Answer: c
Explanation: To check the over low logic circuitry is used in each case. Over low occurs when the
processor cannot handle the result properly when it produces an out of the range output.
5. 1’s complement can be easily obtained by using _________

a) Comparator
b) Inverter
c) Adder
d) Subtractor
View Answer
Answer: b
Explanation: With the help of inverter the 1’s complement is easily obtained. Since, during the operation
of 1’s complement 1 is converted into 0 and vice-versa and this is well suited for the inverter.
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6. The advantage of 2’s complement system is that _________

a) Only one arithmetic operation is required
b) Two arithmetic operations are required
c) No arithmetic operations are required
d) Different Arithmetic operations are required
View Answer
Answer: a
Explanation: The advantage of 2’s complement is that only one arithmetic operation is required for 2’s
complement’s operation and that is only addition. Just by adding a 1 bit to 1’s complement, we get 2’s
complement.
7. The 1’s complements requires _________

a) One operation
b) Two operations
c) Three operations
d) Combined Operations
View Answer
Answer: a
Explanation: Only one operation is required for 1’s complement operation. This includes only inversion
of 1’s to 0’s and 0’s to 1’s.
8. Which one is used for logical manipulations?

a) 2’s complement
b) 9’s complement
c) 1’s complement
d) 10’s complement
View Answer
Answer: c
Explanation: For logical manipulations 1’s complement is used, as all logical operations take place with
binary numbers.
9. For arithmetic operations only _________

a) 1’s complement is used
b) 2’s complement
c) 10’s complement
d) 9’s complement
View Answer
Answer: b
Explanation: Only 2’s complement is used for arithmetic operations, as it is more fast.
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10. The addition of +19 and +43 results as _________ in 2’s complement system.
a) 11001010
b) 101011010
c) 00101010
d) 0111110
View Answer
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Answer: d
Explanation: The decimal numbers are converted to their respective binary equivalent and then the
binary addition rules are applied.
To practice all areas of Digital Electronic Circuits for Interviews, here is complete set of 1000+ Multiple
Choice Questions and Answers.

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Digital Circuits Questions and Answers – Binary

Coded Decimal(BCD)
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« Prev Next »
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Binary
Coded Decimal(BCD)”.
1. Binary coded decimal is a combination of __________

a) Two binary digits
b) Three binary digits
c) Four binary digits
d) Five binary digits
View Answer
Answer: c
Explanation: Binary coded decimal is a combination of 4 binary digits. For example-8421.
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2. The decimal number 10 is represented in its BCD form as __________

a) 10100000
b) 01010111
c) 00010000
d) 00101011
View Answer
Answer: c
Explanation: The decimal number 10 is represented in its BCD form as 0001 0000, in accordance to
8421 for each of the two digits.
3. Add the two BCD numbers: 1001 + 0100 = ?

a) 10101111
b) 01010000
c) 00010011
d) 00101011
View Answer
Answer: c
Explanation: Firstly, Add the 1001 and 0100. We get 1101 as output but it’s not in BCD form. So, we add
0110 (i.e. 6) with 1101. As a result we get 10011 and it’s BCD form is 0001 0011.
4. Carry out BCD subtraction for (68) – (61) using 10’s complement method.
a) 00000111
b) 01110000
c) 100000111
d) 011111000
View Answer
Answer: a
Explanation: First the two numbers are converted into their respective BCD form using 8421 sequence.
Then binary subtraction is carried out.
5. Code is a symbolic representation of __________ information.

a) Continuous
b) Discrete
c) Analog
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d) Both continuous and discrete

View Answer
Answer: b
Explanation: Code is a symbolic representation of discrete information, which may be present in the
form of numbers, letters or physical quantities. Mostly, it is represented using a particular number
system like decimal or binary and such like.
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6. When numbers, letters or words are represented by a special group of symbols, this process is called
__________
a) Decoding
b) Encoding
c) Digitizing
d) Inverting
View Answer
Answer: b
Explanation: When numbers, letters or words are represented by a special group of symbols, this
process is called encoding. Encoding in the sense of fetching the codes or words in a computer. It is done
to secure the transmission of information.
7. A three digit decimal number requires ________ for representation in the conventional BCD format.
a) 3 bits
b) 6 bits
c) 12 bits
d) 24 bits
View Answer
Answer: c
Explanation: The number of bits needed to represent a given decimal number is always greater than the
number of bits required for a straight binary encoding of the same. Hence, a three digit decimal number
requires 12 bits for representation in BCD format.
8. How many bits would be required to encode decimal numbers 0 to 9999 in straight binary codes?
a) 12
b) 14
c) 16
d) 18
View Answer
Answer: b
Explanation: Total number of decimals to be represented = 10000 = 104 = 2n (where n is the number of
bits required) = 213.29. Therefore, the number of bits required for straight binary encoding = 14.
9. The excess-3 code for 597 is given by __________

a) 100011001010
b) 100010100111
c) 010110010111
d) 010110101101
View Answer
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Answer: a
Explanation: The addition of ‘3’ to each digit yields the three new digits ‘8’, ’12’ and ’10’. Hence, the
corresponding four-bit binary equivalents are 100011001010, in accordance to 8421 format.
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10. The decimal equivalent of the excess-3 number 110010100011.01110101 is _____________

a) 970.42
b) 1253.75
c) 861.75
d) 1132.87
View Answer
Answer: a
Explanation: The conversion of binary numbers into digits ‘1100’, ‘1010’, ‘0011’, ‘0111’ and ‘0101’ gives
’12’, ‘5’, ‘3’, ‘7’ and ‘5’ respectively. Hence, the decimal number is 970.42.
Answers.

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Digital Circuits Questions and Answers – Boolean

Logic Operations
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Boolean
Logic Operations”.
1. In boolean algebra, the OR operation is performed by which properties?

a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned
View Answer
Answer: d
Explanation: The expression for Associative property is given by A+(B+C) = (A+B)+C & A*(B*C) =
(A*B)*C.
The expression for Commutative property is given by A+B = B+A & A*B = B*A.
The expression for Distributive property is given by A+BC=(A+B)(A+C) & A(B+C) = AB+AC.
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2. The expression for Absorption law is given by _________

a) A + AB = A
b) A + AB = B
c) AB + AA’ = A
d) A + B = B + A
View Answer
Answer: a
Explanation: The expression for Absorption Law is given by: A+AB = A.
Proof: A + AB = A(1+B) = A (Since 1 + B = 1 as per 1’s Property).
3. According to boolean law: A + 1 = ?

a) 1
b) A
c) 0
d) A’
View Answer
Answer: a
Explanation: A + 1 = 1, as per 1’s Property.
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4. The involution of A is equal to _________

a) A
b) A’
c) 1
d) 0
View Answer
Answer: a
Explanation: The involution of A means double inversion of A (i.e. A”) and is equal to A.
Proof: ((A)’)’ = A
5. A(A + B) = ?
a) AB
b) 1
c) (1 + AB)
d) A
View Answer
Answer: d
Explanation: A(A + B) = AA + AB (By Distributive Property) = A + AB (A.A = A By Commutative Property)
= A(1 + B) = A*1 (1 + B = 1 by 1’s Property) = A.
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6. DeMorgan’s theorem states that _________

a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B
View Answer
Answer: a
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the Dual Property.
7. (A + B)(A’ * B’) = ?
a) 1
b) 0
c) AB
d) AB’
View Answer
Answer: b
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the Dual Property.
8. Complement of the expression A’B + CD’ is _________

a) (A’ + B)(C’ + D)
b) (A + B’)(C’ + D)
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)
View Answer
Answer: b
Explanation: (A’B + CD’)’ = (A’B)'(CD’)’ (By DeMorgan’s Theorem) = (A” + B’)(C’ + D”) (By DeMorgan’s
Theorem) = (A + B’)(C’ + D).
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9. Simplify Y = AB’ + (A’ + B)C.

a) AB’ + C
b) AB + AC
c) A’B + AC’
d) AB + A
View Answer
Answer: a
Explanation: Y = AB’ + (A’ + B)C = AB’ + (AB’)’C = (AB’ + C)( AB’ + AB’) = (AB’ + C).1 = (AB’ + C).
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10. The boolean function A + BC is a reduced form of ____________

a) AB + BC
b) (A + B)(A + C)
c) A’B + AB’C
d) (A + C)B
View Answer
Answer: b
Explanation: (A + B)(A + C) = AA + AC + AB + BC = A + AC + AB + BC (By Commutative Property) = A(1 +
C + B) + BC = A + BC (1 + B + C =1 By 1’s Property).
Answers.

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Digital Circuits Questions and Answers – Sum of

Products and Products of Sum
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Sum of
Products and Products of Sum”.
1. The logical sum of two or more logical product terms is called __________
a) SOP
b) POS
c) OR operation
d) NAND operation
View Answer
Answer: a
Explanation: The logical sum of two or more logical product terms, is called SOP (i.e. sum of product).
The logical product of two or more logical sum terms, is called POS (i.e. product of sums).
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2. The expression Y=AB+BC+AC shows the _________ operation.

a) EX-OR
b) SOP
c) POS
d) NOR
View Answer
Answer: b
Explanation: The given expression has the operation product as well as the sum of that. So, it shows SOP
operation. POS will be the product of sum terms.
3. The expression Y=(A+B)(B+C)(C+A) shows the _________ operation.

a) AND
b) POS
c) SOP
d) NAND
View Answer
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Answer: b
Explanation: The given expression has the operation sum as well as the product of that. So, it shows
POS(product of sum) operation. SOP will be the sum of product terms.
4. A product term containing all K variables of the function in either complemented or uncomplemented
form is called a __________
a) Minterm
b) Maxterm
c) Midterm
d) ∑ term
View Answer
Answer: a
Explanation: A product term containing all K variables of the function in either complemented or
uncomplemented form is called a minterm. A sum term containing all K variables of the function in either
complemented or uncomplemented form is called a maxterm.
5. According to the property of minterm, how many combination will have value equal to 1 for K input
variables?
a) 0
b) 1
c) 2
d) 3
View Answer
Answer: b
Explanation: The main property of a minterm is that it possesses the value 1 for only one combination of
K input variables and the remaining will have the value 0.
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6. The canonical sum of product form of the function y(A,B) = A + B is __________

a) AB + BB + A’A
b) AB + AB’ + A’B
c) BA + BA’ + A’B’
d) AB’ + A’B + A’B’
View Answer
Answer: b
Explanation: A + B = A.1 + B.1 = A(B + B’) + B(A + A’) = AB + AB’ + BA +BA’ = AB + AB’ + A’B = AB + AB’ +
A’B.
7. A variable on its own or in its complemented form is known as a __________

a) Product Term
b) Literal
c) Sum Term
d) Word
View Answer
Answer: b
Explanation: A literal is a single logic variable or its complement. For example — X, Y, A’, Z, X’ etc.
8. Maxterm is the sum of __________ of the corresponding Minterm with its literal complemented.
a) Terms
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b) Words
c) Numbers
d) Nibble
View Answer
Answer: a
Explanation: Maxterm is the sum of terms of the corresponding Minterm with its literal complemented.
9. Canonical form is a unique way of representing ____________

a) SOP
b) Minterm
c) Boolean Expressions
d) POS
View Answer
Answer: c
Explanation: Boolean Expressions are represented through canonical form. An example of canonical
form is A’B’C’ + AB’C + ABC’.
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10. There are _____________ Minterms for 3 variables (a, b, c).

a) 0
b) 2
c) 8
d) 1
View Answer
Answer: c
Explanation: Minterm is given by 2n. So, 23 = 8 minterms are required.
11. _____________ expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-
level NAND logic circuits.
a) POS
b) Literals
c) SOP
d) POS
View Answer
Answer: c
Explanation: SOP expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-
level NAND logic circuits.
Answers.
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Karnaugh Map
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“Karnaugh Map”.
1. A Karnaugh map (K-map) is an abstract form of ____________ diagram organized as a matrix of squares.
a) Venn Diagram
b) Cycle Diagram
c) Block diagram
d) Triangular Diagram
View Answer
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Answer: a
Explanation: A Karnaugh map (K-map) is an abstract form of Venn diagram organized as a matrix of
squares, where each square represents a Maxterm or a Minterm.
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2. There are ______ cells in a 4-variable K-map.

a) 12
b) 16
c) 18
d) 8
View Answer
Answer: b
Explanation: There are 16 = (24) cells in a 4-variable K-map.
3. The K-map based Boolean reduction is based on the following Unifying Theorem: A + A’ = 1.
a) Impact
b) Non Impact
c) Force
d) Complementarity
View Answer
Answer: b
Explanation: The given expression A +A’ = 1 is based on non-impact unifying theorem.
4. Each product term of a group, w’.x.y’ and w.y, represents the ____________in that group.
a) Input
b) POS
c) Sum-of-Minterms
d) Sum of Maxterms
View Answer
Answer: c
Explanation: In a minterm, each variable w, x or y appears once either as the variable itself or as the
inverse. So, the given expression satis ies the property of Sum of Minterm.
5. The prime implicant which has at least one element that is not present in any other implicant is known
as ___________
a) Essential Prime Implicant
b) Implicant
c) Complement
d) Prime Complement
View Answer
Answer: a
Explanation: Essential prime implicants are prime implicants that cover an output of the function that no
combination of other prime implicants is able to cover.
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6. Product-of-Sums expressions can be implemented using ___________

a) 2-level OR-AND logic circuits
b) 2-level NOR logic circuits
c) 2-level XOR logic circuits
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d) Both 2-level OR-AND and NOR logic circuits

View Answer
Answer: d
Explanation: Product-of-Sums expressions can be implemented using 2-level OR-AND & NOR logic
circuits.
7. Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible product
term of the given ___________
a) Function
b) Value
c) Set
d) Word
View Answer
Answer: a
Explanation: Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible
product term of the given function.
8. Don’t care conditions can be used for simplifying Boolean expressions in ___________
a) Registers
b) Terms
c) K-maps
d) Latches
View Answer
Answer: c
Explanation: Don’t care conditions can be used for simplifying Boolean expressions in K-maps which
helps in pairing with 1/0.
9. It should be kept in mind that don’t care terms should be used along with the terms that are present in
___________
a) Minterms
b) Expressions
c) K-Map
d) Latches
View Answer
Answer: a
Explanation: It should be kept in mind that don’t care terms should be used along with the terms that are
present in minterms as well as maxterms which reduces the complexity of the boolean expression.
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10. Using the transformation method you can realize any POS realization of OR-AND with only.
a) XOR
b) NAND
c) AND
d) NOR
View Answer
Answer: d
Explanation: Using the transformation method we can realize any POS realization of OR-AND with only
NOR.
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11. There are many situations in logic design in which simpli ication of logic expression is possible in
terms of XOR and _________________ operations.
a) X-NOR
b) XOR
c) NOR
d) NAND
View Answer
Answer: a
Explanation: There are many situations in logic design in which simpli ication of logic expression is
possible in terms of XOR and XNOR operations.
Expression of XOR : AB’ + A’B
Expression of XNOR : AB + A’B’
12. These logic gates are widely used in _______________ design and therefore are available in IC form.
a) Sampling
b) Digital
c) Analog
d) Systems
View Answer
Answer: b
Explanation: These logic gates(XOR,XNOR,NOR) are widely used in digital design and therefore are
available in IC form as digital circuits deals with data transmission in the form of binary digits.
13. In case of XOR/XNOR simpli ication we have to look for the following _______________
a) Diagonal Adjacencies
b) Offset Adjacencies
c) Straight Adjacencies
d) Both diagonal and offset adjencies
View Answer
Answer: d
Explanation: In case of XOR/XNOR simpli ication we have to look for the following diagonal and offset
adjacencies. XOR gives output 1 when odd number of 1s are present in input while XNOR gives output 1
when even number of 1s or all 0s are present in input.
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14. Entries known as _______________ mapping.

a) Diagonal
b) Straight
c) K
d) Boolean
View Answer
Answer: a
Explanation: Entries known as diagonal mapping. The diagonal mapping holds true when for any
relation, there is a projection of product on the factor.
Answers.
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Digital Circuits Questions and Answers – Quine

McCluskey or Tabular Method of Minimization of
Logic Functions
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This set of Digital Electronic Circuits Questions and Answers for freshers focuses on “Quine-McCluskey
or Tabular Method of Minimization of Logic Functions”.
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1. The output of an EX-NOR gate is 1. Which input combination is correct?

a) A = 1, B = 0
b) A = 0, B = 1
c) A = 0, B = 0
d) A = 0, B’ = 1
View Answer
Answer: c
Explanation: The output of EX-NOR gate is given by AB + A’B’. So, for A = 0 and B = 0 the output will be 1.
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2. In which of the following gates the output is 1 if and only if at least one input is 1?
a) AND
b) NOR
c) NAND
d) OR
View Answer
Answer: d
Explanation: In or gate we need at least one bit to be equal to 1 to generate the output as 1 because OR
means any of the condition out of two is equal to 1 which means if at least one input is 1 then it shows
output as 1.
3. The time required for a gate or inverter to change its state is called __________
a) Rise time
b) Decay time
c) Propagation time
d) Charging time
View Answer
Answer: c
Explanation: The time required for a gate or inverter to change its state is called propagation time.
4. What is the minimum number of two input NAND gates used to perform the function of two input OR
gates?
a) One
b) Two
c) Three
d) Four
View Answer
Answer: c
Explanation: Y = A + B. This is the equation of OR gate. We require 3 NAND gates to create OR gate. We
can also write,
1st, 2nd and 3rd NAND operations as: Y = ((NOT A) AND (NOT B))’ = A’’ + B’’ = (A+B).
5. Odd parity of word can be conveniently tested by ___________

a) OR gate
b) AND gate
c) NAND gate
d) XOR gate
View Answer
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Answer: d
Explanation: Odd parity of word can be conveniently tested by XOR gate, since, XOR outputs 1 only when
the input has odd number of 1’s.
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6. The number of full and half adders are required to add 16-bit number is __________
a) 8 half adders, 8 full adders
b) 1 half adders, 15 full adders
c) 16 half adders, 0 full adders
d) 4 half adders, 12 full adders
View Answer
Answer: b
Explanation: Half adder has two inputs and two outputs whereas Full Adder has 3 inputs and 2 outputs.
One half adder can add the least signi icant bit of the two numbers whereas full adders are required to
add the remaining 15 bits as they all involve adding carries.
7. Which of the following will give the sum of full adders as output?
a) Three point major circuit
b) Three bit parity checker
c) Three bit comparator
d) Three bit counter
View Answer
Answer: d
Explanation: Counters are used for counting purposes in ascending or descending order. Three bit
counter will give the sum of full adders as output.
8. Which of the following gate is known as coincidence detector?

a) AND gate
b) OR gate
c) NOR gate
d) NAND gate
View Answer
Answer: a
Explanation: AND gate is known as coincidence detector due to multiplicity behaviour, as it outputs 1
only when all the inputs are 1.
9. An OR gate can be imagined as ____________

a) Switches connected in series
b) Switches connected in parallel
c) MOS transistor connected in series
d) BJT transistor connected in series
View Answer
Answer: b
Explanation: OR gate means addition of two inputs, which outputs when any of the input is high. Due to
this reason, it is imagined as switches connected in parallel.
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10. How many full adders are required to construct an m-bit parallel adder?
a) m/2
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b) m
c) m-1
d) m+1
View Answer
Answer: c
Explanation: We need adder for every bit. So we should need m bit adders. A full adder adds a carry bit
to two inputs and produces an output and a carry. But the most signi icant bits can use a half adder
which differs from the full adder as in that it has no carry input, so we need m-1 full adders and 1 half
adder in m bit parallel adder.
To practice all areas of Digital Electronic Circuits for Freshers, here is complete set of 1000+ Multiple

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Digital Circuits Questions and Answers – Logic

Gates and Networks – 1
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Logic
Gates and Networks – 1”.
1. The output of a logic gate is 1 when all the input are at logic 0 as shown below:
INPUT OUTPUT
A B C
0 0 1
0 1 0
1 0 0
1 1 0
INPUT OUTPUT
A B C
0 0 1
0 1 0
1 0 0
1 1 1
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The gate is either _________

a) A NAND or an EX-OR
b) An OR or an EX-NOR
c) An AND or an EX-OR
d) A NOR or an EX-NOR
View Answer
Answer: d
Explanation: The output of a logic gate is 1 when all inputs are at logic 0. The gate is NOR. The output of a
logic gate is 1 when all inputs are at logic 0 or all inputs are at logic 1, then it is EX-NOR. (The truth tables
for NOR and EX-NOR Gates are shown in above table).
2. The code where all successive numbers differ from their preceding number by single bit is __________
a) Alphanumeric Code
b) BCD
c) Excess 3
d) Gray
View Answer
Answer: d
Explanation: The code where all successive numbers differ from their preceding number by single bit is
gray code. It is an unweighted code. The most important characteristic of this code is that only a single bit
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change occurs when going from one code number to next. BCD Code is one in which decimal digits are
represented by a group of 4-bits each, whereas, in Excess-3 Code, the decimal numbers are incremented
by 3 and then written in their BCD format.
3. The following switching functions are to be implemented using a decoder:

f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum con iguration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
View Answer
Answer: c
Explanation: 4 to 16 line decoder as the minterms are ranging from 1 to 14.
4. How many AND gates are required to realize Y = CD + EF + G?

a) 4
b) 5
c) 3
d) 2
View Answer
Answer: d
Explanation: To realize Y = CD + EF + G, two AND gates are required and two OR gates are required.
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5. The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11
View Answer
Answer: a
Explanation: In 01, 10 or 11 output is low if any of the I/P is high. So, the correct option will be 00.
6. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) 3, 2
View Answer
Answer: a
Explanation: Y = CD + EF + G
The number of two input AND gate = 2
The number of two input OR gate = 2.
7. A universal logic gate is one which can be used to generate any logic function. Which of the following is
a universal logic gate?
a) OR
b) AND
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c) XOR
d) NAND
View Answer
Answer: d
Explanation: An Universal Logic Gate is one which can generate any logic function and also the three
basic gates: AND, OR and NOT. Thus, NOR and NAND can generate any logic function and are thus
Universal Logic Gates.
8. A full adder logic circuit will have __________

a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs
View Answer
Answer: d
Explanation: A full adder circuit will add two bits and it will also accounts the carry input generated in
the previous stage. Thus three inputs and two outputs (Sum and Carry) are there. In case of half adder
circuit, there are only two inputs bits and two outputs (SUM and CARRY).
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9. How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?
a) 3, 2
b) 4, 2
c) 1, 1
d) 2, 3
View Answer
Answer: a
Explanation: There are three product terms. So, three AND gates of two inputs are required. As only two
input OR gates are available, so two OR gates are required to get the logical sum of three product terms.
10. Which of following are known as universal gates?

a) NAND & NOR
b) AND & OR
c) XOR & OR
d) EX-NOR & XOR
View Answer
Answer: a
Explanation: The NAND & NOR gates are known as universal gates because any digital circuit can be
realized completely by using either of these two gates, and also they can generate the 3 basic gates AND,
OR and NOT.
11. The gates required to build a half adder are __________

a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate
View Answer
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Answer: c
Explanation: The gates required to build a half adder are EX-OR gate and AND gate. EX-OR outputs the
SUM of the two input bits whereas AND outputs the CARRY of the two input bits.

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Answers.

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Digital Circuits Questions and Answers – Logic

Gates and Networks – 2
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This set of Digital Electronic Circuits Inteview Questions and Answers for freshers focuses on “Logic
Gates and Networks-2”.
1. A single transistor can be used to build which of the following digital logic gates?
a) AND gates
b) OR gates
c) NOT gates
d) NAND gates
View Answer
Answer: c
Explanation: A transistor can be used as a switch. That is, when base is low collector is high (input zero,
output one) and base is high collector is low (input 1, output 0).
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2. How many truth table entries are necessary for a four-input circuit?
a) 4
b) 8
c) 12
d) 16
View Answer
Answer: d
Explanation: For 4 inputs: 24 = 16 truth table entries are necessary.
3. Which input values will cause an AND logic gate to produce a HIGH output?
a) At least one input is HIGH
b) At least one input is LOW
c) All inputs are HIGH
d) All inputs are LOW
View Answer
Answer: c
Explanation: For AND gate, the output is high only when both inputs are high. That’s why the high output
in AND will occurs only when all the inputs are high. However, in case of OR gate, if atleast one input is
high, the output will be high.
4. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a) OR gates only
b) AND gates and NOT gates
c) AND gates, OR gates, and NOT gates
d) OR gates and NOT gates
View Answer
Answer: c
Explanation: Expression for XOR is: A.(B’)+(A’).B
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So in the above expression, the following logic gates are used: AND, OR, NOT.
Thus, 2 AND gates with two-inputs and 1 OR gate with two-inputs will be required for constructing a XOR
gate.
5. The basic logic gate whose output is the complement of the input is the ___________
a) OR gate
b) AND gate
c) INVERTER gate
d) XOR gate
View Answer
Answer: c
Explanation: It is also called NOT gate and it simply inverts the input, such that 1 becomes 0 and 0
becomes 1.
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6. The AND function can be used to ___________ and the OR function can be used to _____________
a) Enable, disable
b) Disable, enable
c) Synchronize, energize
d) Detect, invert
View Answer
Answer: a
Explanation: The AND gate and OR gate are used for enabling and disabling respectively because of their
multiplicity and additivity property. The AND gate outputs 1 when all inputs are at logic 1, whereas the
OR gate outputs 0 when all inputs are at logic 0.
7. The dependency notation “>=1” inside a block stands for which operation?
a) OR
b) XOR
c) AND
d) XNOR
View Answer
Answer: a
Explanation: The dependency notation “>=1” inside a block stands for OR operation.
8. If we use an AND gate to inhibit a signal from passing one of the inputs must be ___________
a) LOW
b) HIGH
c) Inverted
d) Floating
View Answer
Answer: a
Explanation: AND gate means A*B and OR gate means A+B and to inhibit means to get low signal, one of
the input must be low. It means (0*1=0 or 1*0=0) we will get low output signal. Thus, AND gate outputs 1
only when all inputs are at logic level 1 else it outputs 0.
9. Logic gate circuits contain predictable gate functions that open theirs ____________
a) Outputs
b) Inputs
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c) Pre-state
d) Impedance state
View Answer
Answer: b
Explanation: Logic gate circuits contain predictable gate functions that open their inputs because we are
free to give any types of inputs.
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10. How many NAND circuits are contained in a 7400 NAND IC?
a) 1
b) 2
c) 4
d) 8
View Answer
Answer: c
Explanation: 7400 IC’s pin has total 14 pin. Pin no 7 use for GND and pin no 14 used for +vcc and
remaining pins used for connections. For a NAND gate two inputs are required and one output is
obtained means for NAND gate 3 pin connections are required. Thus, a 7400IC contains 4 NAND gates
with each having 3 pins. Therefore, total 12 pins dedicated for the NAND operation. Rest 2 pins for
power supply.
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Digital Circuits Questions and Answers – Digital

Integrated Circuits – 1
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Digital
Integrated Circuits – 1”.
1. Which of the following logic families has the highest maximum clock frequency?
a) S-TTL
b) AS-TTL
c) HS-TTL
d) HCMOS
View Answer
Answer: b
Explanation: AS-TTL (Advanced Schottky) has a maximum clock frequency of 105 MHz. S-TTL (Schottky
High Speed TTL) has 100 MHz. Found nothing as HS-TTL. There are H and S separate TTL. HCMOS has
50 MHz clock frequency.
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2. Why is the fan-out of CMOS gates frequency dependent?

a) Each CMOS input gate has a speci ic propagation time and this limits the number of different gates that
can be connected to the output of a CMOS gate
b) When the frequency reaches the critical value the gate will only be capable of delivering 70% of the
normal output voltage and consequently the output power will be one-half of normal and this de ines
the upper operating frequency
c) The higher number of gates attached to the output the more frequently they will have to be serviced
thus reducing the frequency at which each will be serviced with an input signal
d) The input gates of the FETs are predominantly capacitive and as the signal frequency increases the
capacitive loading also increases thereby limiting the number of loads that may be attached to the output
of the driving gate
View Answer
Answer: d
Explanation: Fan out is the measure of maximum number of inputs that a single logic gate output can
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drive. Actually power dissipation in CMOS circuits depends on clock frequency. As the frequency
increases Pd also increases so fan-out depends on frequency.
3. Logic circuits that are designated as buffers, drivers or buffers/drivers are designed to have:
a) A greater current/voltage capability than an ordinary logic circuit
b) Greater input current/voltage capability than an ordinary logic circuit
c) A smaller output current/voltage capability than an ordinary logic
d) Greater the input and output current/voltage capability than an ordinary logic circuit
View Answer
Answer: a
Explanation: Buffer circuits are usually incorporated to isolate the input from the output. Logic circuits
that are designated as buffers, drivers or buffer/drivers are designed to have a greater current/voltage
capability than an ordinary logic circuit.
4. Which of the following will not normally be found on a data sheet?

a) Minimum HIGH level output voltage
b) Maximum LOW level output voltage
c) Minimum LOW level output voltage
d) Maximum HIGH level input current
View Answer
Answer: c
Explanation: Minimum LOW level output voltage will not normally be found on a data sheet.
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5. Which of the following logic families has the shortest propagation delay?
a) S-TTL
b) AS-TTL
c) HS-TTL
d) HCMOS
View Answer
Answer: b
Explanation: AS-TTL (Advanced Schottky) has a maximum clock frequency that is 105 MHz. So, the
propagation delay will be given by 1/105 sec which is the lowest one. It is followed by S-TTL and HCMOS
in terms of increasing propagation delay.
6. What is the static charge that can be stored by your body as you walk across a carpet?
a) 300 volts
b) 3000 volts
c) 30000 volts
d) Over 30000 volts
View Answer
Answer: d
Explanation: When a person walks across a carpeted or tile loor electric charge builds up in the body
due to the friction between shoes and loor material. If the friction static is greater the voltage potential
develop in the body will be greater. You start act as a capacitor. This is called Electrostatic discharge. The
potential static charge that can develop from walking on tile loors is greater than 15000 volts while
carpeted loors can generate in excess of 30000 volts.
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7. What must be done to interface TTL to CMOS?

a) A dropping resistor must be used on the CMOS of 12 V supply to reduce it to 5 V for the TTL
b) As long as the CMOS supply voltage is 5 V they can be interfaced (however, the fan-out of the TTL is
limited to ive CMOS gates)
c) A 5 V zener diode must be placed across the inputs of the TTL gates in order to protect them from the
higher output voltages of the CMOS gates
d) A pull-up resistor must be used between the TTL output-CMOS input node and Vcc; the value of RP
will depend on the number of CMOS gates connected to the node
View Answer
Answer: d
Explanation: To interface TTL to CMOS a pull-up resistor must be used between the TTL output-CMOS
input node and Vcc. A pull-up resistor is used to avoid the loating state on the input node of the CMOS,
thus using a small amount of current. The value of RP will depend on the number of CMOS gates
connected to the node.
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8. What causes low-power Schottky TTL to use less power than the 74XX series TTL?
a) The Schottky-clamped transistor
b) A larger value resistor
c) The Schottky-clamped MOSFET
d) A small value resistor
View Answer
Answer: b
Explanation: A larger value resistor causes low power low-power Schottky TTL to use less power than
the 74XX series TTL.
9. What are the major differences between the 5400 and 7400 series of ICs?
a) The 5400 series are military grade and require tighter supply voltages and temperatures
b) The 5400 series are military grade and allow for a wider range of supply voltages and temperatures
c) The 7400 series are an improvement over the original 5400s
d) The 7400 series was originally developed by Texas Instruments and the 5400 series was brought out
by National Semiconductors after TI’s patents expired as a second supply source
View Answer
Answer: b
Explanation: The 5400 series are military grade and allow for a wider range of supply voltages and
temperatures, these are the major differences between the 5400 and 7400 series of ICs. Also, the
working temperature range of 5400 series is -50 to 125C while that for 7400 is 0 to 70C.
10. Which of the following statements apply to CMOS devices?

a) The devices should not be inserted into circuits with the power on
b) All tools, test equipment and metal workbenches should be tied to earth ground
c) The devices should be stored and shipped in antistatic tubes or conductive foam
View Answer
Answer: d
Explanation: For CMOS devices, all the mentioned statements are applicable. The devices should not be
inserted into circuits with the power on. All tools, test equipment and metal workbenches should be tied
to earth ground. Also, the devices should be stored and shipped in antistatic tubes or conductive foam.
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Answers.

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This set of Digital Electronic/Circuits Questions and Answers for experienced focuses on “Digital
Integrated Circuits-2”.
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1. SSI refers to ___________

a) Small Scale Integration
B) Short Scale Integration
c) Small Set Integration
d) Short Set Integration
View Answer
Answer: a
Explanation: SSI refers to Small Scale Integration.
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2. Small Scale Integration(SSI) refers to ICs with __________ gates on the same chip.
a) Fewer than 10
b) Greater than 10
c) Equal to 10
d) Greater than 50
View Answer
Answer: a
Explanation: Small Scale Integration(SSI) refers to ICs with fewer than 10 gates on the same chip.
3. MSI means ___________

a) Merged Scale Integration
b) Main Scale Integration
c) Medium Scale Integration
d) Main Set Integration
View Answer
Answer: c
Explanation: MSI means Medium Scale Integration.
4. MSI includes _______ gates per chip.

a) 12 to 100
b) 13 to 50
c) greater than 10
d) greater than 100
View Answer
Answer: a
Explanation: Medium Scale Integration includes 12 to 100 gates per chip.
5. LSI means ________ and refers to ________ gates per chip.

a) Long Scale Integration, more than 10 upto 10000
b) Large Scale Integration, more than 100 upto 5000
c) Large Short Integration, less than 10 and greater than 5000
d) Long Short Integration, more than 10 upto 10000
View Answer
Answer: b
Explanation: The full form of LSI is Large Scale Integration and refers to more than 100 upto 5000 gates
per chip.
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6. Integrated circuits are classi ied as ___________

a) Large, Small and Medium
b) Very Large, Small and Linear
c) Linear and Digital
d) Non-Linear and Digital
View Answer
Answer: c
Explanation: Integrated circuits are classi ied as Linear and Digital. Linear operates with continuous and
digital refers to discrete signals.
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7. According to the IC fabrication process logic families can be divided into two broad categories as:
a) RTL and TTL
b) HTL and MOS
c) ECL and DTL
d) Bipolar and MOS
View Answer
Answer: d
Explanation: According to the IC fabrication process logic families can be divided into two broad
categories as: Bipolar and Metal-oxide semiconductor. The mentioned all others are part of bipolar.
Bipolar IC fabrication refers to TTL logic where MOS refers to CMOS logic.
8. The full form of DIP is ___________

a) Dual-in-Long Package
b) Dual-in-Line Package
c) Double Integrated Package
d) Double-in-Line Package
View Answer
Answer: b
Explanation: The full form of DIP is Dual-in-Line Package.
9. LCC refers to ___________

a) Longest Chip Carrier
b) Leadless Chip Carrier
c) Leaded Chip Carrier
d) Large Chip Carrier
View Answer
Answer: b
Explanation: LCC refers to Leadless Chip Carrier.
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10. PGA refers to ____________

a) Plastic Grid Array
b) Pin Grid Array
c) Pin Greater Array
d) Plastic Greater Array
View Answer
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Answer: b
Explanation: PGA refers to Pin Grid Array.
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« Prev Next »
This set of Digital Electronic/Circuits Interview Questions and Answers for experienced focuses on
“Digital Integrated Circuits – 3”.
1. MOS families includes __________

a) PMOS and NMOS
b) CMOS and NMOS
c) PMOS, NMOS and CMOS
d) EMOS, NMOS and PMOS
View Answer
Answer: c
Explanation: Metal Oxide Semiconductor families includes PMOS, NMOS and CMOS.
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2. CMOS refers to __________

a) Continuous Metal Oxide Semiconductor
b) Complementary Metal Oxide Semiconductor
c) Centred Metal Oxide Semiconductor
d) Concrete Metal Oxide Semiconductor
View Answer
Answer: b
Explanation: CMOS refers to Complementary Metal Oxide Semiconductor.
3. Propagation delay is de ined as __________

a) the time taken for the output of a gate to change after the inputs have changed
b) the time taken for the input of a gate to change after the outputs have changed
c) the time taken for the input of a gate to change after the intermediates have changed
d) the time taken for the output of a gate to change after the intermediates have changed
View Answer
Answer: a
Explanation: Propagation delay is de ined as the time taken for the output of a gate to change after the
inputs have changed.
4. Propagation delay times can be divided as __________

a) t(PLH) and t(LPH)
b) t(LPH) and t(PHL)
c) t(PLH) and t(PHL)
d) t(HPL) and t(LPH)
View Answer
Answer: c
Explanation: Propagation delay times can be divided as: t(PLH) and t(PHL). t(PLH) stands for
propagation from low to high and t(PHL) stands for propagation from high to low.
5. The delay times are measured between the __________ % voltage levels of the input and output
waveforms.
a) 50
b) 75
c) 25
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d) 100
View Answer
Answer: a
Explanation: Propagation delay is the time taken by the output to change it’s state when the input
changes. The average of the two propagation delays is given by (t1 + t2)/2, which gives the intermediate
value. So, the delay times are measured between the 50% voltage levels of the input and output
waveforms.
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6. Power Dissipation in DIC is expressed in __________

a) Watts or kilowatts
b) Milliwatts or nanowatts
c) DB
d) Mdb
View Answer
Answer: b
Explanation: Power Dissipation in DIC is expressed in milliwatts or nanowatts.
7. Fan-in is de ined as __________

a) the number of outputs connected to gate without any degradation in the voltage levels
b) the number of inputs connected to gate without any degradation in the voltage levels
c) the number of outputs connected to gate with degradation in the voltage levels
d) the number of inputs connected to gate with degradation in the voltage levels
View Answer
Answer: b
Explanation: Fan-in is de ined as the maximum number of inputs that can be connected to the output of
a gate without any degradation in the voltage levels. For example, an eight-input gate requires one Unit
Load per input. It’s fan-in is 8.
8. The maximum noise voltage that may appear at the input of a logic gate without changing the logical
state of its output is termed as __________
a) Noise Margin
b) Noise Immunity
c) White Noise
d) Signal to Noise Ratio
View Answer
Answer: b
Explanation: The maximum noise voltage that may appear at the input of a logic gate without changing
the logical state of its output is termed as noise immunity.
9. Depending upon the low of current from the output of one logic circuit to the input of another the
logic families can be divides into _________ categories.
a) 2
b) 3
c) 4
d) 5
View Answer
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Answer: a
Explanation: Depending upon the low of current from the output of one logic circuit to the input of
another the logic families can be divides into two categories and they are current sourcing and current
sinking. Source means from where the current originates or exits while Sink means where the current
enters or is accepted.
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10. Fan-in and Fan-out are the characteristics of ___________

a) Registers
b) Logic families
c) Sequential Circuits
d) Combinational Circuits
View Answer
Answer: b
Explanation: Fan-in and Fan-out are the characteristics of logic families. Fan-in is the measure of
maximum number of inputs that a single gate output can drive or accept. Whereas, Fan-out means the
maximum number of inputs that can be fed by a single output.
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Register-Transistor Logic(RTL)
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Register-
Transistor Logic(RTL)”.
1. All input of NOR as low produces result as __________

a) Low
b) Mid
c) High
d) Floating
View Answer
Answer: c
Explanation: All input of NOR as low produces the result as high, whereas, rest all conditions produce
output as low.
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2. In RTL NOR gate, the output is at logic 1 only when all the inputs are at __________
a) logic 0
b) logic 1
c) +10V
d) Floating
View Answer
Answer: a
Explanation: RTL NOR gate behaves as NOR gate and the output of NOR gate will be 1 only when all the
inputs are at logic 0 and in rest conditions of the input, the output is 0.
3. Resistor–transistor logic (RTL) is a class of digital circuits built using _______ as the input network and
_______ as switching devices.
a) Resistors, bipolar junction transistors (BJTs)
b) Bipolar junction transistors (BJTs), Resistors
c) Capacitors, resistors
d) Resistors, capacitors
View Answer
Answer: a
Explanation: Resistor–transistor logic (RTL) is a class of digital circuits built using resistors as the input
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network and bipolar junction transistors (BJTs) as switching devices.
4. RTL consists of a common emitter stage with a _______ connected between the base and the input
voltage source.
a) collector
b) base resistor
c) capacitor
d) inductor
View Answer
Answer: b
Explanation: RTL consist of a common emitter stage with a base resistor connected between the base
and the input voltage source. The role of base resistor is to expand the negligible transistor input voltage
range (about 0.7 V) to the logical “1” level (about 3.5 V) by converting the input voltage into a current.
Thus, base resistor plays a major role in biasing of the transistor.
5. The role of the _______ is to convert the collector current into a voltage in RTL.
a) Collector resistor
b) Base resistor
c) Capacitor
d) Inductor
View Answer
Answer: a
Explanation: The role of the collector resistor is to convert the collector current into a voltage; its
resistance is chosen high enough to saturate the transistor and low enough to obtain low output
resistance. Base Resistor is to provide the necessary biasing to the base of the transistor in order to
activate it.
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6. The limitations of the one transistor RTL NOR gate are overcome by __________
a) Two-transistor RTL implementation
b) Three-transistor RTL implementation
c) Multi-transistor RTL implementation
d) Four-transistor RTL implementation
View Answer
Answer: c
Explanation: The limitations of the one transistor RTL NOR gate are overcome by the use of multi
transistor RTL. It consists of a set of parallel connected transistor switches driven by the logic inputs.
7. The primary advantage of RTL technology was that __________

a) It results as low power dissipation
b) It uses a minimum number of resistors
c) It uses a minimum number of transistors
d) It operates swiftly
View Answer
Answer: c
Explanation: The primary advantage of RTL technology was that it uses a minimum number of
transistors. It consists of registers in large amount and it results in as high power dissipation. The
resistors act as the input network and the transistors performs the switching operation.
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8. The disadvantage of RTL is that __________

a) It uses a maximum number of resistors
b) It results in high power dissipation
c) High noise creation
d) It uses minimum number of transistors
View Answer
Answer: b
Explanation: The disadvantage of RTL is its high power dissipation when the transistor is switched on by
current lowing in the collector and base resistor. This requires that more current be supplied to and
heat be removed from RTL circuits. In contrast, TTL circuits with “totem-pole” output stage minimize
both of these requirements.
9. TTL circuits with “totem-pole” output stage minimize __________

a) The power dissipation in RTL
b) The time consumption in RTL
c) The speed of transferring rate in RTL
d) Propagation delay in RTL
View Answer
Answer: a
Explanation: TTL circuits with “totem-pole” output stage minimize the power dissipation and heating
effect in RTL.
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10. The minimum number of transistors can be used by 2 input AND gate is __________
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: The minimum number of transistors can be used by 2 input AND gate is 2 and maximum up
to 3.
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Digital Circuits Questions and Answers – Diode-

Transistor Logic(DTL)
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his set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Diode-
Transistor Logic(DTL)”.
1. Diode–transistor logic (DTL) is the direct ancestor of _____________

a) Register-transistor logic
b) Transistor–transistor logic
c) High threshold logic
d) Emitter Coupled Logic
View Answer
Answer: b
Explanation: Diode–transistor logic (DTL) is a class of digital circuits that is the direct ancestor of
transistor–transistor logic. To overcome the shortcomings of DTL, TTL came into existence.
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2. In DTL logic gating function is performed by ___________

a) Diode
b) Transistor
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c) Inductor
d) Capacitor
View Answer
Answer: a
Explanation: Diode serves as the input network and the switching operation is performed by the
transistor.
3. In DTL amplifying function is performed by ___________

a) Diode
b) Transistor
c) Inductor
d) Capacitor
View Answer
Answer: b
Explanation: The amplifying and switching function is performed by a transistor and the diode acts an
input network in DTL.
4. How many stages a DTL consist of?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: b
Explanation: The DTL circuit shown in the picture consists of three stages: an input diode logic stage, an
intermediate level shifting stage and an output common-emitter ampli ier stage.
5. The full form of CTDL is ___________

a) Complemented transistor diode logic
b) Complemented transistor direct logic
c) Complementary transistor diode logic
d) Complementary transistor direct logic
View Answer
Answer: a
Explanation: The full form of CTDL is Complemented transistor diode logic.
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6. The DTL propagation delay is relatively ___________

a) Large
b) Small
c) Moderate
d) Negligible
View Answer
Answer: a
Explanation: Propagation delay refers to the time taken by the output to change it’s state when the input
is altered. When the transistor goes into saturation from all inputs being high charge is stored in the
base region. When it comes out of saturation (one input goes low) this charge has to be removed and
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will dominate the propagation time which results as a large propagation delay. Thus, it has small clock
frequency.
7. The way to speed up DTL is to add an across intermediate resister is ___________

a) Small “speed-up” capacitor
b) Large “speed-up” capacitor
c) Small “speed-up” transistor
d) Large ” speed-up” transistor
View Answer
Answer: a
Explanation: One way to speed up DTL is to add a small “speed-up” capacitor across intermediate
resister. The capacitor helps to turn off the transistor by removing the stored base charge; the capacitor
also helps to turn on the transistor by increasing the initial base drive.
8. The process to avoid saturating the switching transistor is performed by ___________

a) Baker clamp
b) James R. Biard
c) Chris Brown
d) Totem-Pole
View Answer
Answer: a
Explanation: Another way to speed up DTL other than adding a small “speed-up” capacitor across
intermediate resister is to avoid saturating the switching transistor which can be done with a Baker
clamp. The name Baker clamp is given at the name of Richard H. Baker, who described it in his 1956
technical report “Maximum Ef iciency Switching Circuits”.
9. A major advantage of DTL over the earlier resistor–transistor logic is the ___________
a) Increased fan out
b) Increased fan in
c) Decreased fan out
d) Decreased fan in
View Answer
Answer: b
Explanation: A major advantage over the earlier resistor–transistor logic is the increased fan in. Fan-in is
the measure of the maximum number of inputs that a single gate output can accept.
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10. To increase fan-out of the gate in DTL ___________

a) An additional capacitor may be used
b) An additional resister may be used
c) An additional transistor and diode may be used
d) Only an additional diode may be used
View Answer
Answer: c
Explanation: To increase fan-out of the gate in DTL, an additional transistor and diode may be used.
Here, the fan out means the number of maximum input that a single gate output can feed.
11. A disadvantage of DTL is ___________

a) The input transistor to the resister
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b) The input resister to the transistor

c) The increased fan-in
d) The increased fan-out
View Answer
Answer: b
Explanation: A disadvantage of DTL is the input resistor to the transistor and its presence tends to slow
the circuit down. Hence limiting the speed at which the transistor is able to switch states. Thus, the
propagation delay increases.
Answers.
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Transistor Transistor Logic(TTL)
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Digital
Circuits Questions and Answers – Transistor Transistor Logic(TTL or T2L)”.
1. Transistor–transistor logic (TTL) is a class of digital circuits built from ____________

a) JFET only
b) Bipolar junction transistors (BJT)
c) Resistors
d) Bipolar junction transistors (BJT) and resistors
View Answer
Answer: d
Explanation: Transistor–transistor logic (TTL) is a class of digital circuits built from bipolar junction
transistors (BJT) and resistors. However, resistors have a small role to play and both logic gating and
amplifying functions are performed by the transistors.
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2. TTL is called transistor–transistor logic because both the logic gating function and the amplifying
function are performed by ____________
a) Resistors
b) Bipolar junction transistors
c) One transistor
d) Resistors and transistors respectively
View Answer
Answer: b
Explanation: TTL is called transistor–transistor logic because both the logic gating function and the
amplifying function are performed by bipolar junction transistors (BJTs).
3. TTL was invented in 1961 by ____________

a) Baker clamp
b) James L. Buie
c) Chris Brown
d) Frank Wanlass
View Answer
Answer: b
Explanation: TTL was invented in 1961 by James L Buie.
4. The full form of TCTL is ____________

a) Transistor-coupled transistor logic
b) Transistor-capacitor transistor logic
c) Transistor-complemented transistor logic
d) Transistor-complementary transistor logic
View Answer
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Answer: a
Explanation: The full form of TCTL is transistor-coupled transistor logic.
5. The _______ ancestor to the irst personal computers.

a) PARAM 1
b) SATYAM 1
c) KENBAK 1
d) MITS Altair
View Answer
Answer: c
Explanation: The KENBAK 1, ancestor to the irst personal computers.
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6. TTL inputs are the emitters of a ____________

a) Transistor-transistor logic
b) Multiple-emitter transistor
c) Resistor-transistor logic
d) Diode-transistor logic
View Answer
Answer: b
Explanation: TTL inputs are the emitters of a multiple-emitter transistor.
7. TTL is a ____________
a) Current sinking
b) Current sourcing
c) Voltage sinking
d) Voltage sourcing
View Answer
Answer: a
Explanation: Like DTL, TTL is a current-sinking logic since a current must be drawn from inputs to bring
them to a logic 0 level. Current Sink means it accepts current coming out from a source.
8. Standard TTL circuits operate with a __ volt power supply.

a) 2
b) 4
c) 5
d) 3
View Answer
Answer: c
Explanation: Standard TTL circuits operate with a 5-volt power supply.
9. TTL devices consume substantially ______ power than equivalent CMOS devices at rest.
a) Less
b) More
c) Equal
d) Very High
View Answer
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Answer: b
Explanation: TTL devices consume substantially more power than equivalent CMOS devices at rest. Thus,
CMOS devices are faster than TTL devices.
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10. A TTL gate may operate inadvertently as an ____________

a) Digital ampli ier
b) Analog ampli ier
c) Inverter
d) Regulator
View Answer
Answer: b
Explanation: A TTL gate may operate inadvertently as an analog ampli ier if the input is connected to a
slowly changing input signal that traverses the unspeci ied region from 0.7V to 3.3V.
11. The speed of ______ circuits is limited by the tendency of common emitter circuits to go into
saturation.
a) TTL
b) ECL
c) RTL
d) DTL
View Answer
Answer: a
Explanation: The speed of TTL circuits is limited by the tendency of common emitter circuits to go into
saturation due to the injection of minority carriers into the collector region. Hence, it functions slowly
compared to CMOS devices.
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Digital Circuits Questions and Answers – Emitter-

Coupled Logic(ECL)
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Emitter-
Coupled Logic(ECL)”.
1. The full form of ECL is __________

a) Emitter-collector logic
b) Emitter-complementary logic
c) Emitter-coupled logic
d) Emitter-cored logic
View Answer
Answer: c
Explanation: The full form of ECL is emitter-coupled logic.
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2. Which logic is the fastest of all the logic families?

a) TTL
b) ECL
c) HTL
d) DTL
View Answer
Answer: b
Explanation: ECL is the fastest of all the logic families because of the emitters of many transistors are
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coupled together which results in the highest transmission rate.
3. The full form of CML is __________

a) Complementary mode logic
b) Current mode logic
c) Collector mode logic
d) Collector Mixed Logic
View Answer
Answer: c
Explanation: The full form of CML is Collector Mode Logic.
4. Sometimes ECL can also be named as __________

a) EEL
b) CEL
c) CML
d) CCL
View Answer
Answer: c
Explanation: ECL (Emitter Coupled Logic) can also be named as CML(Collector Mode Logic).
5. In an ECL the output is taken from __________

a) Emitter
b) Base
c) Collector
d) Junction of emitter and base
View Answer
Answer: c
Explanation: Though, the emitter and collector of the ECL are coupled together. So, the output will be
taken from a collector.
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6. The ECL behaves as __________

a) NOT gate
b) NOR gate
c) NAND gate
d) AND gate
View Answer
Answer: b
Explanation: The ECL behaves as NOR gate because if any of the input voltages go high as compared to
the reference voltage, the output is low and the output is high only when all the input voltages are low.
7. In ECL the fanout capability is __________

a) High
b) Low
c) Zero
d) Sometimes high and sometimes low
View Answer
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Answer: a
Explanation: If the input impedance is high and the output resistance is low; as a result, the transistors
change states quickly, gate delays are low, and the fanout capability is high. Fan-out is the measure of the
maximum number of inputs that a single gate output can accept.
8. ECL’s major disadvantage is that __________

a) It requires more power
b) It’s fanout capability is high
c) It creates more noise
d) It is slow
View Answer
Answer: a
Explanation: ECL’s major disadvantage is that each gate continuously draws current, which means it
requires (and dissipates) signi icantly more power than those of other logic families. But ECL logic gates
have clock frequency. Thus, they have a fast operation.
9. The full form of SCFL is __________

a) Source-collector logic
b) Source-coupled logic
c) Source-complementary logic
d) Source Cored Logic
View Answer
Answer: b
Explanation: The full form of SCFL is source-coupled logic.
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10. The equivalent of emitter-coupled logic made out of FETs is called __________
a) CML
b) SCFL
c) FECL
d) EFCL
View Answer
Answer: b
Explanation: The equivalent of emitter-coupled logic made out of FETs is called Source-coupled
logic(SCFL). Like ECL, SCL is also the fastest among the logic families.
11. ECL was invented in _______ by __________

a) 1956, Baker clamp
b) 1976, James R. Biard
c) 1956, Hannon S. Yourke
d) 1976, Yourke
View Answer
Answer: c
Explanation: ECL was invented in August 1956 at IBM by Hannon S Yourke.
12. At the time of invention, an ECL was called as __________

a) Source-coupled logic
b) Current Mode Logic
c) Current-steering logic
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d) Emitter-coupled logic
View Answer
Answer: c
Explanation: At the time of invention, an ECL was called as current-steering logic because it involved
current switching.
13. The ECL circuits usually operates with __________

a) Negative voltage
b) Positive voltage
c) Grounded voltage
d) High Voltage
View Answer
Answer: a
Explanation: The ECL circuits usually operate with negative power supplies (positive end of the supply is
connected to ground), in comparison to other logic families in which negative end of the supply is
grounded. It is done mainly to minimize the in luence of the power supply variations on the logic levels
as ECL is more sensitive to noise on the VCC and relatively immune to noise on VEE.
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14. Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of __________
a) ECL
b) VECL
c) PECL
d) LECL
View Answer
Answer: c
Explanation: Low voltage positive emitter coupled logic (LVPECL) is a power optimized version of PECL
using a +3.3 V instead of 5 V supply.
Answers.

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Integrated-injection Logic(I^2L)
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“Integrated-injection Logic(I2L)”.
1. The full form of IIL is __________

a) Injection integrated logic
b) Integrated inspected logic
c) Integrated injection logic
d) Injection Inspected Logic
View Answer
Answer: c
Explanation: The full form of IIL is Integrated injection logic. It is made up of multiple bipolar junction
transistors and had speed comparable to TTl and power consumption equivalent to CMOS.
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2. Integrated injection logic is a class of digital circuits built with __________

a) Single collector BJT
b) Double emitter BJT
c) Multiple emitter BJT
d) Multiple collector BJT
View Answer
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Answer: d
Explanation: Integrated injection logic is a class of digital circuits built with multiple collector bipolar
junction transistors (BJT).
3. IIL has _____ noise immunity.

a) High
b) Low
c) Neutral
d) Nil
View Answer
Answer: a
transistors and had speed comparable to TTl and power consumption equivalent to CMOS. IIL has high
noise immunity because it operates by current instead of voltage.
4. IIL is sometimes also known as __________

a) Single transistor logic
b) Multiple transistor logic
c) Merged transistor logic
d) Mixed Transistor Logic
View Answer
Answer: c
transistors and had speed comparable to TTl and power consumption equivalent to CMOS. IIL is
sometimes also known as merged transistor logic.
5. Integrated Injection logic cannot be denoted as __________

a) IIL
b) I2L
c) I2L
d) I TWO L
View Answer
Answer: d
transistors and had speed comparable to TTl and power consumption equivalent to CMOS. Integrated
Injection logic can be denoted as IIL, I2L and I2L as well.
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6. The heart of an I2L circuit is the __________

a) Common collector open emitter inverter
b) Common emitter open collector inverter
c) Open emitter common collector inverter
d) Open Emitter Open Collector Inverter
View Answer
Answer: b
Explanation: The heart of an I2L circuit is the common emitter open collector inverter. The emitter is
connected to the ground, with the base having an input behaving as either current sink or high
impedance loating condition. The output of an inverter is connected to the collector.
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7. In Integrated Injection, logic input is supplied to the __________

a) Emitter
b) Base
c) Collector
d) Collector Emitter
View Answer
Answer: b
Explanation: In IIL, the input is supplied to the base as either a current sink (low logic level) or as a high
impedance loating condition (high logic level). The output of an inverter is connected to the collector.
8. In Integrated Injection, logic output is received through the __________

a) Emitter
b) Base
c) Collector
d) Base Emitter Junction
View Answer
Answer: c
Explanation: In Integrated Injection logic output is received through the collector. The output of an
inverter is connected at the collector.
9. When the outputs of two inverters are wired together the result is __________
a) A two-input NOR gate
b) A single-input NOR gate
c) A two-input NAND gate
d) A single-input NAND gate
View Answer
Answer: a
Explanation: When the outputs of two inverters are wired together then the result is a two-input NOR
gate because the con iguration (NOT A) AND (NOT B) is equivalent to NOT (A OR B). In a NOR gate, the
output is high only when all of its input are at logic 0 else, the output is low.
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10. IIL was commonly used before the advent of CMOS logic by company ___________
a) Samsung
b) Nokia
c) Motorola
d) Apple
View Answer
Answer: c
Explanation: I2L is relatively simple to construct on an integrated circuit and was commonly used before
the advent of CMOS logic by companies such as Motorola.
11. Which company introduced one of the irst consumer-grade digital watches (the Black Watch) which
used I2L technology?
a) Cambridge Consultants Pvt Ltd
b) Sinclair Radionics Ltd
c) National Research and Development Council
d) Westminster
View Answer
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Answer: b
Explanation: Sinclair Radionics Ltd introduced one of the irst consumer-grade digital watches (the Black
Watch) in August 1975, which used I2L technology.
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Digital Circuits Questions and Answers – MOS

Digital Integrated Circuits
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “MOS
Digital Integrated Circuits”.
1. The full form of MOS is ___________

a) Metal oxide semiconductor
b) Metal oxygen semiconductor
c) Metallic oxide semiconductor
d) Metallic oxygen semiconductor
View Answer
Answer: a
Explanation: The full form of MOS is “Metal Oxide Semiconductor”. It is a type of transistor having 3
layers: a metal conductor, an insulating silicon layer and a semiconductor silicon layer.
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2. What are the types of MOSFET devices available?

a) P-type enhancement type MOSFET
b) N-type enhancement type MOSFET
c) Depletion type MOSFET
d) All of the mentioned
View Answer
Answer: d
Explanation: MOSFET are of two types: enhancement and depletion type. Further, these are classi ied
into n-type and p-type device. The depletion type is switched on without the application of gate bias
voltage and the enhancement type is switched on with the application of gate voltage.
3. Which insulating layer used in the fabrication of MOSFET?

a) Aluminium oxide
b) Silicon Nitride
c) Silicon dioxide
d) Aluminium Nitrate
View Answer
Answer: c
Explanation: Silicon dioxide is used as an insulating layer in the fabrication of MOSFET. It gives an
extremely high input resistance in the order of 10^10 to 10^15 Ω for MOSFET.
4. Which of the following plays an important role in improving device performance of MOSFET?
a) Dielectric constant
b) Threshold voltage
c) Power supply voltage
d) Gate to drain voltage
View Answer
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Answer: b
Explanation: In MOSFET, the threshold voltage is typically 3 to 6V. This large voltage is not compatible
with the supply of 5V which is used in digital ICs. So, for the improvement of the device’s performance
the magnitude of threshold voltage should be reduced.
5. A technique used to reduce the magnitude of threshold voltage of MOSFET is the ___________
a) Use of complementary MOSFET
b) Use of Silicon nitride
c) Using thin ilm technology
d) Increasing potential of the channel
View Answer
Answer: b
Explanation: Silicon nitride is sandwiched between two SiO2 layer and provide necessary barrier. The
dielectric constant of Si3N4 is 7.5, whereas that of SiO2 is 4. This increase in overall dielectric constant
reduces threshold voltage.
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6. What is used to higher the speed of operation in MOSFET fabrication?

a) Ceramic gate
b) Silicon dioxide
c) Silicon nitride
d) Poly silicon gate
View Answer
Answer: d
Explanation: In conventional metal gate small overlap capacitance is present, which lowers the speed of
operation. With the presence of self aligning property of the poly silicon gate it eliminates this
capacitance. Using a process called ion-implantation, polysilicon, the drain and the source get doped.
However, the thin oxide under silicon gate acting as a mask for the process and thus develops the gate
aligning property.
7. Find the sequence of steps involved in fabrication of poly silicon gate MOSFET?
Step 1: Entire wafer surface of a Si3N4 is coated and is etched away with the help of mask to include
source, gate and drain.
Step 2: The contact areas are de ined using photolithographic process.
Step 3: Selective etching of Si3N4 and growth of thin oxide.
Step 4: The deposition of poly silicon gate.
Step 5: The growth of thick oxide is called ield oxide and P implantation.
Step 6: The metallization and interconnection between substrate and source.
a) 1->5->3->4->2->6
b) 1->3->4->2->5->6
c) 1->5->4->3->2->6
d) 1->4->2->5->3->6
View Answer
Answer: a
Explanation: These steps are the sequence of steps involved in fabrication of poly silicon gate MOSFET.
With the help of poly silicon gate doping, it highers the speed of operation of the MOSFET.
8. Why MOSFET is preferred over BJT in IC components?

a) MOSFET has low packing density
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b) MOSFET has medium packing density

c) MOSFET has high packing density
d) MOSFET has no packing density
View Answer
Answer: a
Explanation: MOSFET is preferred over BJT because of its low packaging density. Thus, more number of
MOSFET memory cells can be accommodated in a particular area as compared to BJT.
9. Critical defects per unit chip area is ________ for a MOS transistor.
a) High
b) Low
c) Neutral
d) Very High
View Answer
Answer: b
Explanation: Critical defects per unit chip area is low for a MOS transistor because it involves fewer steps
in the fabrication of a MOS transistor. Also, MOSFET has low packaing density.
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10. MOS is being used in ___________

a) LSI
b) VLSI
c) MSI
d) Both LSI and VLSI
View Answer
Answer: d
Explanation: Since more transistor and circuitry functions can be achieved on a single chip with MOS
technology that is why MOS is being used in LSI and VLSI. LSI stands for Large Scale Integration and
VLSI stands for Very Large Scale Integration.
Answers.

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Characteristics of CMOS
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“Characteristics of CMOS”.
1. The full form of CMOS is ____________

a) Capacitive metal oxide semiconductor
b) Capacitive metallic oxide semiconductor
c) Complementary metal oxide semiconductor
d) Complemented metal oxide semiconductor
View Answer
Answer: c
Explanation: The full form of CMOS is complementary metal oxide semiconductor. In this type of device,
both n-type and p-type transistors are used in a complementary way.
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2. The full form of COS-MOS is ____________

a) Complementary symmetry metal oxide semiconductor
b) Complementary systematic metal oxide semiconductor
c) Capacitive symmetry metal oxide semiconductor
d) Complemented systematic metal oxide semiconductor
View Answer
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Answer: a
Explanation: The full form of COS-MOS is complementary systematic metal oxide semiconductor. In this
type of device, both n-type and p-type transistors are used in a complementary way. Usually, the
transistors used are MOSFETs.
3. CMOS is also sometimes referred to as ____________

a) Capacitive metal oxide semiconductor
b) Capacitive symmetry metal oxide semiconductor
c) Complementary symmetry metal oxide semiconductor
d) Complemented symmetry metal oxide semiconductor
View Answer
Answer: c
Explanation: CMOS is also sometimes referred to as complementary systematic metal oxide–
semiconductor (COS-MOS). In this type of device, both n-type and p-type transistors are used in a
complementary way. Usually, the transistors used are MOSFETs.
4. CMOS technology is used in ____________

a) Inverter
b) Microprocessor
c) Digital logic
d) Both microprocessor and digital logic
View Answer
Answer: d
Explanation: CMOS technology is used in Microprocessor, Microcontroller, static RAM and other digital
logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS
sensor), data converters and highly integrated transceivers for many types of communication.
5. Two important characteristics of CMOS devices are ____________

a) High noise immunity
b) Low static power consumption
c) High resistivity
d) Both high noise immunity and low static power consumption
View Answer
Answer: d
Explanation: Two important characteristics of CMOS devices are high noise immunity and low static
power consumption. Since one transistor of the pair is always off and the series combination draws
signi icant power only momentarily during switching between on and off states. Also, the performance of
CMOS is not altered with the presence of noise and thus it has high noise immunity.
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6. CMOS behaves as a/an ____________

a) Adder
b) Subtractor
c) Inverter
d) Comparator
View Answer
Answer: c
Explanation: Since, the outputs of the PMOS and NMOS transistors are complementary such that when
the input is low, the output is high and when the input is high, the output is low. Because of this
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behaviour of input and output, the CMOS circuit’s output is the inverse of the input. Whereas, adders and
subtractors are combinational circuits.
7. An important characteristic of a CMOS circuit is the ____________

a) Noise immunity
b) Duality
c) Symmetricity
d) Noise Margin
View Answer
Answer: b
Explanation: An important characteristic of a CMOS circuit is the duality that exists between its PMOS
transistors and NMOS transistors. Due to the presence of two different types of transistors, the device
has the complementary function.
8. CMOS logic dissipates _______ power than NMOS logic circuits.

a) More
b) Less
c) Equal
d) Very High
View Answer
Answer: b
Explanation: CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power
only when switching (“dynamic power”). Thus, CMOS has less power consumption and is more ef icient.
9. Semiconductors are made of ____________

a) Ge and Si
b) Si and Pb
c) Ge and Pb
d) Pb and Au
View Answer
Answer: a
Explanation: Semiconductors are made of Silicon (Si) and Germanium (Ge). Semiconductors are devices
having conductivity between conductors and insulators.
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10. Which chip were the irst RTC and CMOS RAM chip to be used in early IBM computers, capable of
storing a total of 64 bytes?
a) The Samsung 146818
b) The Samsung 146819
c) The Motorola 146818
d) The Motorola 146819
View Answer
Answer: c
Explanation: The Motorola 146818 was the irst RTC and CMOS RAM chip to be used in early IBM
computers; capable of storing a total of 64 bytes.
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Answers.

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Digital Circuits Questions and Answers – BiCMOS

Logic Circuits
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “BiCMOS
Logic Circuits”.
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1. BiCMOS is an evolved semiconductor technology that integrates two formerly separate semiconductor
technologies those of the _____________
a) CMOS and FET
b) MOSFET and CMOS
c) BJT and CMOS
d) BJT and MOSFET
View Answer
Answer: c
Explanation: BiCMOS is an evolved semiconductor technology that integrates two formerly separate
semiconductor technologies those of the BJT and CMOS. CMOS ensures low power dissipation, smaller
noise margin and higher packaging density, while BJT offers high switching speed and improved noise
performance.
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2. We use BJT in BiCMOS because of its _____________

a) High speed
b) High gain
c) Low output resistance
View Answer
Answer: d
Explanation: Bipolar junction transistors offer high speed, high gain and low output resistance, which are
excellent properties for high-frequency analog ampli iers. It also offers high switching speed and
improved noise performance.
3. We use CMOS transistor in BiCMOS because of its _____________

a) High input resistance
b) Simple construction
c) Low power logic gates
View Answer
Answer: d
Explanation: CMOS ensures low power dissipation, smaller noise margin and higher packaging density. It
also offers high input resistance and is excellent for constructing simple, low-power logic gates.
4. When was BiCMOS technology introduced?

a) 1990
b) 1991
c) 1992
d) 1989
View Answer
Answer: a
Explanation: BiCMOS technology was introduced in 1990s. BiCMOS is an evolved semiconductor
technology that integrates two formerly separate semiconductor technologies those of the BJT and
CMOS. CMOS ensures low power dissipation, smaller noise margin and higher packaging density, while
BJT offers high switching speed and improved noise performance.
5. On which technology the Pentium is based?

a) MOSFET
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b) CMOS
c) BiCMOS
d) BJT
View Answer
Answer: c
Explanation: The Pentium technology is based on BiCMOS technology because BiCMOS circuits use the
characteristics of each type of transistor most appropriately. CMOS ensures low power dissipation,
smaller noise margin and higher packaging density, while BJT offers high switching speed and improved
noise performance.
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6. The advantage of BiCMOS circuit is that it gives _____________

a) Large fan-out
b) Large fan-in
c) Small fan-in
d) Small fan-out
View Answer
Answer: a
Explanation: Fan-out is the measure of maximum number of inputs that a single gate output can feed.
BiCMOS circuits are particularly useful for logic with large fan-out (large capacitive load).
7. How many members a BiCMOS family have?

a) 5
b) 6
c) 7
d) 8
View Answer
Answer: a
Explanation: BICMOS is a combination of both CMOS and BJT technology. The BiCMOS family has mainly 5
members and those are ABT logic, ALB logic, ALVT logic, BCT logic and LVT logic.
8. What is LVT logic?

a) Lower threshold voltage
b) Lower supply threshold voltage
c) Lower supply voltage while retaining TTL logic levels
View Answer
Answer: c
Explanation: LVT stands for Low Voltage BiCMOS Technology which is an integration of less power
dissipation and less noise of CMOS along with the high switching speed and output drive of BJT. LVT logic
is nothing but the lower supply voltage while retaining TTL logic levels.
9. What does ALVT mean?

a) All lower supply voltage while retaining TTL logic levels
b) ABT lower supply voltage while retaining TTL logic levels
c) Advanced version of LVT logic
d) All version of LVT logic
View Answer
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Answer: c
Explanation: ALVT stands for Advanced Low Voltage BiCMOS Technology (ALVT). It is a faster version of
LVT family. It is an integration of less power dissipation and less noise of CMOS along with the high
switching speed and output drive of BJT.
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10. The full form of PTL is _____________

a) Pull transistor logic
b) Push transistor logic
c) Pass transistor logic
d) Post Transistor Logic
View Answer
Answer: c
Explanation: The full form of PTL is “pass transistor logic”. It combines different logic families to design
an integrated circuit. Thus, it reduces the number of transistors used by scraping off the unnecessary
transistors.
11. CVSL means _____________

a) Complementary Voltage Switch Logic
c) Cascode Voltage Switch Logic
d) Complemented Voltage Switch Logic
d) Cascade Voltage Switch Logic
View Answer
Answer: c
Explanation: Cascode Voltage Switch Logic (CVSL) refers to a CMOS-type logic family which is designed
for certain advantages. It requires mainly N-channel MOSFET transistors to implement the logic using
true and complementary input signals and also needs two P-channel transistors at the top to pull one of
the outputs high.
Answers.
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Compatibility or Interfacing
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“Compatibility or Interfacing”.
1. Compatibility refers to ____________

a) The output of a circuit should match with the input of another circuit
b) The output of a circuit should match with the input of the same circuit
c) The input of a circuit should match with the output of another circuit
d) The input of a circuit should match with the output of same circuit
View Answer
Answer: a
Explanation: The output(s) of a circuit or a system should match the input(s) of another circuit or system
that has different electrical characteristics. This is referred to as compatibility.
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2. The method of connecting a driving device to a loading device is known as ___________

a) Compatibility
b) Interface
c) Sourcing
d) Sinking
View Answer
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Answer: b
Explanation: The method of connecting a driving device to a loading device is known as interface. The
output(s) of a circuit or a system should match the input(s) of another circuit or system that has
different electrical characteristics. This is referred to as compatibility.
3. The irst CML logic was introduced by General Electric in ___________

a) 1960
b) 1981
c) 1961
d) 1990
View Answer
Answer: c
Explanation: CML stands for Current Mode Logic. The irst CML logic was introduced by General Electric
in 1961.
4. Commercial ECL families are not nearly as popular as TTL and CMOS mainly because they ___________
a) Produces too much noise
b) Consume too much power
c) Have high fan-in
d) Have high fan-out
View Answer
Answer: b
Explanation: Commercial ECL families are not nearly as popular as TTL and CMOS mainly because they
consume too much power. CMOS consumes the least power while TTL provides high speed.
5. The key to propagation delay in bipolar logic family is to prevent the transistors in a gate from
___________
a) Fan-in
b) Fan-out
c) Saturation
d) Cut-off
View Answer
Answer: c
Explanation: The key to propagation delay in bipolar logic family is to prevent the transistors in a gate
from saturation. In Saturation mode, the transistor is in “ON”mode, where it seems like a short circuit
between collector and emitter.
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6. Schottky families prevent the saturating using ___________

a) Transistors
b) Schottky transistors
c) Diodes
d) Schottky diodes
View Answer
Answer: d
Explanation: Schottky families prevent the saturating using Schottky diodes across the base-collector
junctions of transistors. In Saturation mode, the transistor is in “ON”mode, where it seems like a short
circuit between collector and emitter.
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7. The basic idea of basic CML circuit came from an ___________

a) Inverter
b) Buffer
c) Transistor
d) Both inverter and buffer
View Answer
Answer: d
Explanation: CML is Current Mode Logic in which data is transmitted at high speed of Mbps. Since this
circuit has both inverting and non-inverting output. So, It behaves like an inverter/buffer.
8. The full form of MECL is ___________

a) Mono emitter coupled logic
b) Motorola emitter coupled logic
c) Motorola emitter capacitor logic
d) Both mono emitter and motorola coupled logic
View Answer
Answer: b
Explanation: The full form of MECL is Motorola emitter coupled logic. ECL is a high speed BJT. It uses BJT
differential ampli ier with single input and restricted current to avoid the transistor going into saturation
and thus turning off operation.
9. Motorola has offered MECL circuits in ______ logic families.

a) 3
b) 4
c) 5
d) 6
View Answer
Answer: c
Explanation: Motorola has offered MECL circuits in ive logic families: MECL I, MECL II, MECL III, MECL
10000 (MECL 10K) and MECL 10H000 (MECL 10KH). The full form of MECL is Motorola emitter coupled
logic. ECL is a high speed BJT. It uses BJT differential ampli ier with single input and restricted current to
avoid the transistor going into saturation and thus turning off operation.
10. The latest entrant to the ECL family is ___________

a) ECL 10K
b) ECL 100K
c) ECL 1000K
d) ECL 10000K
View Answer
Answer: b
Explanation: The latest entrant to the ECL family is ECL 100K, having 6-digit part numbers. This family
offers functions, in general, different from those offered by 10K series. This family operates with a
reduced power supply voltage -4.5 V, has shorter propagation delay of 0.75 ns, and transition time of 0.7
ns. However, the power consumption per gate is about 40 mW.
11. All input of NOR as low produces result as ___________

a) Low
b) Mid
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c) High
d) High Impedance
View Answer
Answer: c
Explanation: According to the properties of NOR gate, if all the input of NOR as low produces result as
high. While if any input of NOR is high, then it produces low output.
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12. In RTL NOR gate, the output is at logic 1 only when all the inputs are at ___________
a) logic 0
b) logic 1
c) +10v
d) loating
View Answer
Answer: a
Explanation: RTL NOR gate behaves as NOR gate and the output of NOR gate will be 1 only when all the
inputs are at logic 0. The output of NOR will be 0 if any of the input is 1.

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Answers.

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Introduction of Arithmetic Operation
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“Introduction of Arithmetic Operation”.
1. The basic building blocks of the arithmetic unit in a digital computers are __________
a) Subtractors
b) Adders
c) Multiplexer
d) Comparator
View Answer
Answer: b
Explanation: The basic building blocks of the arithmetic unit in digital computers are adders. Since a
parallel adder is constructed with a number of full-adder circuits connected in cascade. By controlling
the data inputs to the parallel adder, it is possible to obtain different types of arithmetic operations.
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2. A digital system consists of _____ types of circuits.

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: A digital system consists of two types of circuits and these are a combinational and
sequential logic circuit. Combinational circuits are the ones which do not depend on previous inputs
while Sequential circuits depend on past inputs.
3. In a combinational circuit, the output at any time depends only on the _______ at that time.
a) Voltage
b) Intermediate values
c) Input values
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d) Clock pulses
View Answer
Answer: c
Explanation: In a combinational circuit, the output at any time depends only on the input values at that
time and not on past or intermediate values.
4. In a sequential circuit, the output at any time depends only on the input values at that time.
a) Past output values
c) Both past output and present input
d) Present input values
View Answer
Answer: c
Explanation: In a sequential circuit, the output at any time depends on the present input values as well as
past output values. It also depends on clock pulses depending on whether it’s synchronous or
asynchronous sequential circuits.
5. Procedure for the design of combinational circuits are:

A. From the word description of the problem, identify the inputs and outputs and draw a block diagram.
B. Draw the truth table such that it completely describes the operation of the circuit for different
combinations of inputs.
C. Simplify the switching expression(s) for the output(s).
D. Implement the simpli ied expression using logic gates.
E. Write down the switching expression(s) for the output(s).
a) B, C, D, E, A
b) A, D, E, B, C
c) A, B, E, C, D
d) B, A, E, C, D
View Answer
Answer: c
Explanation: Combinational circuits are the ones which do not depend on previous inputs and depends
only on the present values. The given arrangement A, B, E, C, D is the right sequence for the designing of
the combinational circuits.
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6. All logic operations can be obtained by means of __________

a) AND and NAND operations
b) OR and NOR operations
c) OR and NOT operations
d) NAND and NOR operations
View Answer
Answer: d
Explanation: Since the logic gates NOR and NAND are known as universal logic gates, therefore it can be
used to design all the three basic gates AND, OR and NOT. Thus, it means that any operations can be
obtained by implementation of these gates.
7. The design of an ALU is based on __________

a) Sequential logic
b) Combinational logic
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c) Multiplexing
d) De-Multiplexing
View Answer
Answer: b
Explanation: The design of an ALU is based on combinational logic. Because the unit has a regular
pattern, it can be broken into identical stages connected in cascade through carries.
8. If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a possible _____
result.
a) Input, zero
b) Output, one
c) Input, one
d) Output, zero
View Answer
Answer: d
Explanation: If the two numbers are unsigned, the bit conditions of interest are the output carry and a
possible zero result.
9. If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the
sign of the result, a zero indication and __________
a) An under low condition
b) A neutral condition
c) An over low condition
d) One indication
View Answer
Answer: c
Explanation: If the two numbers include a sign bit in the highest order position, the bit conditions of
interest are the sign of the result, a zero indication and an over low condition.
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10. The lag bits in an ALU is de ined as ___________

a) The total number of registers
b) The status bit conditions
c) The total number of control lines
View Answer
Answer: b
Explanation: In an ALU, status bit conditions are sometimes called condition code bits or lag bits. It is so
called because they tend to represent the status of the respect lags after any operation.
Answers.

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Digital Circuits Questions and Answers – Half

Adder & Full Adder
« Prev Next »
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Half
Adder & Full Adder”.
1. In parts of the processor, adders are used to calculate ____________

a) Addresses
b) Table indices
c) Increment and decrement operators
View Answer
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Answer: d
Explanation: Adders are used to perform the operation of addition. Thus, in parts of the processor,
adders are used to calculate addresses, table indices, increment and decrement operators, and similar
operations.
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2. Total number of inputs in a half adder is __________

a) 2
b) 3
c) 4
d) 1
View Answer
Answer: a
Explanation: Total number of inputs in a half adder is two. Since, an EXOR gates has 2 inputs and carry is
connected with the input of EXOR gates. The output of half-adder is also 2, them being, SUM and CARRY.
The output of EXOR gives SUM and that of AND gives carry.
3. In which operation carry is obtained?

a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction
View Answer
Answer: b
Explanation: In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example carry is
obtained after 1st addition (i.e. 1 + 1 = 1 0). In subtraction, borrow is obtained. Like, 0 – 1 = 1 (borrow
1).
4. If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
View Answer
Answer: c
Explanation: If A and B are the inputs of a half adder, the sum is given by A XOR B, while the carry is
given by A AND B.
5. If A and B are the inputs of a half adder, the carry is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
View Answer
Answer: a
Explanation: If A and B are the inputs of a half adder, the carry is given by: A(AND)B, while the sum is
given by A XOR B.
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6. Half-adders have a major limitation in that they cannot __________

a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages
View Answer
Answer: c
Explanation: Half-adders have a major limitation in that they cannot accept a carry bit from a previous
stage, meaning that they cannot be chained together to add multi-bit numbers. However, the two output
bits of a half-adder can also represent the result A+B=3 as sum and carry both being high.
7. The difference between half adder and full adder is __________

a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
View Answer
Answer: c
Explanation: Half adder has two inputs while full adder has three outputs; this is the difference between
them, while both have two outputs SUM and CARRY.
8. If A, B and C are the inputs of a full adder then the sum is given by __________
a) A AND B AND C
b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C
View Answer
Answer: c
Explanation: If A, B and C are the inputs of a full adder then the sum is given by A XOR B XOR C.
9. If A, B and C are the inputs of a full adder then the carry is given by __________
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
View Answer
Answer: a
Explanation: If A, B and C are the inputs of a full adder then the carry is given by A AND B OR (A OR B)
AND C, which is equivalent to (A AND B) OR (B AND C) OR (C AND A).
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10. How many AND, OR and EXOR gates are required for the con iguration of full adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
View Answer
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Answer: b
Explanation: There are 2 AND, 1 OR and 2 EXOR gates required for the con iguration of full adder,
provided using half adder. Otherwise, con iguration of full adder would require 3 AND, 2 OR and 2 EXOR.
Answers.

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Digital Circuits Questions and Answers – Half &

Full Subtractor
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« Prev Next »
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Half &
Full Subtractor”.
1. Half subtractor is used to perform subtraction of ___________

a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
View Answer
Answer: a
Explanation: Half subtractor is a combinational circuit which is used to perform subtraction of two bits,
namely minuend and subtrahend and produces two outputs, borrow and difference.
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2. For subtracting 1 from 0, we use to take a _______ from neighbouring bits.

a) Carry
b) Borrow
c) Input
d) Output
View Answer
Answer: b
Explanation: For subtracting 1 from 0, we use to take a borrow from neighbouring bits because carry is
taken into consideration during addition process.
3. How many outputs are required for the implementation of a subtractor?

a) 1
b) 2
c) 3
d) 4
View Answer
Answer: b
Explanation: There are two outputs required for the implementation of a subtractor. One for the
difference and another for borrow.
4. Let the input of a subtractor is A and B then what the output will be if A = B?
a) 0
b) 1
c) A
d) B
View Answer
Answer: a
Explanation: The output for A = B will be 0. If A = B, it means that A = B = 0 or A = B = 1. In both of the
situation subtractor gives 0 as the output.
5. Let A and B is the input of a subtractor then the output will be ___________
a) A XOR B
b) A AND B
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c) A OR B
d) A EXNOR B
View Answer
Answer: a
Explanation: The subtractor has two outputs BOROW and DIFFERENCE. Since, the difference output of a
subtractor is given by AB’ + BA’ and this is the output of a XOR gate. So, the inal difference output is AB’
+ BA’.
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6. Let A and B is the input of a subtractor then the borrow will be ___________
a) A AND B’
b) A’ AND B
c) A OR B
d) A AND B
View Answer
Answer: b
Explanation: The borrow of a subtractor is received through AND gate whose one input is inverted. On
that basis the borrow will be (A’ AND B).
7. What does minuend and subtrahend denotes in a subtractor?

a) Their corresponding bits of input
b) Its outputs
c) Its inputs
d) Borrow bits
View Answer
Answer: c
Explanation: Minuend and subtrahend are the two bits of input of a subtractor. If A and B are the two
inputs of a subtractor then A is called minuend and B as subtrahend.
8. Full subtractor is used to perform subtraction of ___________

a) 2 bits
b) 3 bits
c) 4 bits
d) 8 bits
View Answer
Answer: b
Explanation: Full subtractor is used to perform subtraction of 3 bits, namely minuend bit, subtrahend bit
and borrow from the previous stage. However, it also produces 2 outputs BORROW and DIFFERENCE.
9. The full subtractor can be implemented using ___________

a) Two XOR and an OR gates
b) Two half subtractors and an OR gate
c) Two multiplexers and an AND gate
d) Two comparators and an AND gate
View Answer
Answer: b
Explanation: A full subtractor has 3 input bits and two outputs bits BORROW and DIFFERENCE. The full
subtractor can be implemented using two half subtractors and an OR gate.
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10. The output of a subtractor is given by (if A, B and X are the inputs).
a) A AND B XOR X
b) A XOR B XOR X
c) A OR B NOR X
d) A NOR B XOR X
View Answer
Answer: b
Explanation: The difference output of a subtractor is given by (if A, B and X are the inputs) A XOR B XOR
X.
11. The output of a full subtractor is same as ____________

a) Half adder
b) Full adder
c) Half subtractor
d) Decoder
View Answer
Answer: b
Explanation: The sum and difference output of a full adder and a full subtractor are same. If A, B and C
are the input of a full adder and a full subtractor then the output will be given by (A XOR B XOR C),
respectively.
Answers.
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19. Analytical Instrumentation Questions and Answers – Digital Circuits
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Procedure For The Design of Combinational
Circuits
« Prev Next »
“Procedure For The Design of Combinational Circuits”.
1. The basic building blocks of the arithmetic unit in a digital computers are ____________
a) Subtractors
b) Adders
c) Multiplexer
d) Comparator
View Answer
Answer: b
Explanation: The basic building blocks of the arithmetic unit in a digital computers are adders. Since, a
parallel adder is constructed with a number of full-adder circuits connected in cascade. By controlling
the data inputs to the parallel adder, it is possible to obtain different types of arithmetic operations.
advertisement
2. A digital system consists of _____ types of circuits.

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: A digital system consists of two types of circuits and these are combinational and sequential
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logic circuit. Combinational circuits are the ones which do not depend on previous inputs while
Sequential circuits depend on past inputs.
3. In a combinational circuit, the output at any time depends only on the _______ at that time.
a) Voltage
c) Input values
d) Clock pulses
View Answer
Answer: c
Explanation: In a combinational circuit, the output at any time depends only on the input values at that
time and not on past or intermediate values.
4. In a sequential circuit, the output at any time depends only on the input values at that time.
a) Past output values
c) Both past output and present input
d) Present input values
View Answer
Answer: c
Explanation: In a sequential circuit, the output at any time depends on the present input values as well as
past output values. It also depends on clock pulses depending whether it’s synchronous or
asynchronous sequential circuits.
5. Procedure for the design of combinational circuits are:

A. From the word description of the problem, identify the inputs and outputs and draw a block diagram.
B. Draw the truth table such that it completely describes the operation of the circuit for different
combinations of inputs.
C. Simplify the switching expression(s) for the output(s).
D. Implement the simpli ied expression using logic gates.
E. Write down the switching expression(s) for the output(s).
a) B, C, D, E, A
b) A, D, E, B, C
c) A, B, E, C, D
d) B, A, E, C, D
View Answer
Answer: c
Explanation: Combinational circuits are the ones which do not depend on previous inputs and depends
only on the present values. The given arrangement in option c is the right sequence for the designing of
the combinational circuits.
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6. All logic operations can be obtained by means of ____________

a) AND and NAND operations
b) OR and NOR operations
c) OR and NOT operations
d) NAND and NOR operations
View Answer
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Answer: d
Explanation: Since, the logic gates NOR and NAND are known as universal logic gates, therefore it can be
used to design all the three basic gates AND, OR and NOT. Thus, it means that any operations can be
obtained by implementation of these gates.
7. The design of an ALU is based on ____________

a) Sequential logic
b) Combinational logic
c) Multiplexing
d) De-Multiplexing
View Answer
Answer: b
Explanation: The design of an ALU is based on combinational logic. Because the unit has a regular
pattern, it can be broken into identical stages connected in cascade through carries.
8. If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a possible _____
result.
a) Input, zero
b) Output, one
c) Input, one
d) Output, zero
View Answer
Answer: d
Explanation: If the two numbers are unsigned, the bit conditions of interest are the output carry and a
possible zero result.
9. If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the
sign of the result, a zero indication and ___________
a) An under low condition
b) A neutral condition
c) An over low condition
d) One indication
View Answer
Answer: c
Explanation: If the two numbers include a sign bit in the highest order position, the bit conditions of
interest are the sign of the result, a zero indication and an over low condition.
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10. The lag bits in an ALU is de ined as ____________

a) The total number of registers
b) The status bit conditions
c) The total number of control lines
View Answer
Answer: b
Explanation: In an ALU, status bit conditions are sometimes called condition code bits or lag bits. It is so
called because they tend to represent the status of the respect lags after any operation.

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Answers.

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Digital Circuits Questions and Answers – K-Map

Simpli ication
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “K-Map
Simpli ication”.
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1. Which statement below best describes a Karnaugh map?

a) It is simply a rearranged truth table
b) The Karnaugh map eliminates the need for using NAND and NOR gates
c) Variable complements can be eliminated by using Karnaugh maps
d) A Karnaugh map can be used to replace Boolean rules
View Answer
Answer: a
Explanation: K-map is simply a rearranged truth table. It is a pictorial representation of truth table
having a speci ic number of cells or squares, where each cell represents a Maxterm or a Minterm.
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2. Which of the examples below expresses the commutative law of multiplication?

a) A + B = B + A
b) A • B = B + A
c) A • (B • C) = (A • B) • C
d) A • B = B • A
View Answer
Answer: d
Explanation: The commutative law of multiplication is (A * B) = (B * A).
The commutative law of addition is (A + B) = (B + A).
3. The Boolean expression Y = (AB)’ is logically equivalent to what single gate?

a) NAND
b) NOR
c) AND
d) OR
View Answer
Answer: a
Explanation: If A and B are the input for AND gate the output is obtained as AB and after inversion we
get (AB)’, which is the expression of NAND gate. NAND gate produces high output when any of the input
is 0 and produces low output when all inputs are 1.
4. The observation that a bubbled input OR gate is interchangeable with a bubbled output AND gate is
referred to as:
a) A Karnaugh map
b) DeMorgan’s second theorem
c) The commutative law of addition
d) The associative law of multiplication
View Answer
Answer: b
Explanation: DeMorgan’s Law: ~(P+Q) <=> (~P).(~Q) Also,
~(P.Q) <=> (~P)+(~Q).
5. The systematic reduction of logic circuits is accomplished by:

a) Symbolic reduction
b) TTL logic
c) Using Boolean algebra
d) Using a truth table
View Answer
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Answer: c
Explanation: The systematic reduction of logic circuits is accomplished by using boolean algebra.
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6. Each “1” entry in a K-map square represents:

a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON’T CARE condition for all possible input truth table combinations
View Answer
Answer: a
Explanation: Each “1” entry in a K-map square represents a HIGH for each input truth table condition
that produces a HIGH output. Thus, it represents a minterm.
7. Each “0” entry in a K-map square represents:

a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON’T CARE condition for all possible input truth table combinations
View Answer
Answer: a
Explanation: Each “0” entry in a K-map square represents a LOW output for all possible HIGH input
conditions. Thus, it represents a Maxterm.
8. Which of the following statements accurately represents the two BEST methods of logic circuit
simpli ication?
a) Actual circuit trial and error evaluation and waveform analysis
b) Karnaugh mapping and circuit waveform analysis
c) Boolean algebra and Karnaugh mapping
d) Boolean algebra and actual circuit trial and error evaluation
View Answer
Answer: c
Explanation: The two BEST methods of logic circuit simpli ication are Boolean algebra and Karnaugh
mapping. Boolean Algebra uses the Laws of Boolean Algebra for minimization of Boolean expressions
while Karnaugh Map is a pictorial representation and reduction of the Boolean expression.
9. Looping on a K-map always results in the elimination of __________

a) Variables within the loop that appear only in their complemented form
b) Variables that remain unchanged within the loop
c) Variables within the loop that appear in both complemented and uncomplemented form
d) Variables within the loop that appear only in their uncomplemented form
View Answer
Answer: c
Explanation: Looping on a K-map always results in the elimination of variables within the loop that
appear in both complemented and uncomplemented form.
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10. Which of the following expressions is in the sum-of-products form?

a) (A + B)(C + D)
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b) (A * B)(C * D)
c) A* B *(CD)
d) A * B + C * D
View Answer
Answer: d
Explanation: Sum of product means that it is the sum of all product terms. Thus, the number is multiplied
irst and then it is added: A * B + C * D.
11. Which of the following is an important feature of the sum-of-products form of expressions?
a) All logic circuits are reduced to nothing more than simple AND and OR operations
b) The delay times are greatly reduced over other forms
c) No signal must pass through more than two gates, not including inverters
d) The maximum number of gates that any signal must pass through is reduced by a factor of two
View Answer
Answer: a
Explanation: An important feature of the sum-of-products form of expressions in the given option is that
all logic circuits are reduced to nothing more than simple AND and OR operations. Sum Of Product
means it is the sum of product terms containing variables in complemented as well as uncomplemented
forms.
12. Which of the following expressions is in the product-of-sums form?

a) (A + B)(C + D)
b) (AB)(CD)
c) AB(CD)
d) AB + CD
View Answer
Answer:
Explanation: (A + B)(C + D) represents the product-of-sums form.

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Answers.

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Controlled Inverter
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“Controlled Inverter”.
1. Controlled inverter is also known as _____________

a) Controlled buffer
b) NOT gate
c) Both controlled buffer and NOT gate
d) Controlled gate
View Answer
Answer: c
Explanation: Controlled inverter is also known as controlled buffer and NOT gate as well. It is used
between output and a bus so that one can control whether the output is fed to the bus or not.
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2. Why XOR gate is called an inverter?

a) Because of the same input
b) Because of the same output
c) It behaves like a NOT gate
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d) It behaves like a AND gate

View Answer
Answer: c
Explanation: The XOR (Exclusive Or) gate has a true output when the two inputs are different. When one
input is true, the output is the inversion of the other. When one input is false, the output is the non-
inversion of the other.
3. Controlled buffers can be useful __________

a) To control the circuit’s output into the bus
b) In comparison of component’s output with its input
c) In increasing the output from its low input
View Answer
Answer: a
Explanation: Controlled buffers can be useful when you have a wire (often called a bus) whose value
should match the output of one of several components. By placing a controlled buffer between each
component output and the bus, you can control whether that component’s output is fed onto the bus or
not.
4. A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is __________
a) Ex-NOR gate
b) OR gate
c) Ex-OR gate
d) NAND gate
View Answer
Answer: a
Explanation: EX-OR gate gives 1 if both inputs are different means 0 or 1 and gives 0 if both are same
and EX-NOR is opposite of EX-OR gate, so it provides a HIGH output for both inputs HIGH or both inputs
are LOW. Thus, EX-NOR produces output for even number of 1’s or all 0s, while EXOR produces output
for odd number of 1’s.
5. What is the irst thing you will need if you are going to use a macro-function?
a) A complicated design project
b) An experienced design engineer
c) Good documentation
d) Experience in HDL
View Answer
Answer: d
Explanation: HDL stands for Hardware Description Language. In order to use a macro function, one
needs to have experience in HDL for representing the structure and behaviour of digital circuits.
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6. What is the major difference between half-adders and full-adders?

a) Full-adders are made up of two half-adders
b) Full adders can handle double-digit numbers
c) Full adders have a carry input capability
d) Half adders can handle only single-digit numbers
View Answer
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Answer: c
Explanation: Half adders have only two inputs A and B. When we add two 4 bit binary number like 0001
and 0011, then half adder can not be used because if the irst bit of both the numbers is 1, then the sum
would be 0 and carry would be 1. But this carry can not be added with the second bits addition of the
number. So, half adders are useless. But in full adders, one more carry input is present, so that, if carry
of one stage is present, it can be added with the next stage as it is done in normal addition. So, therefore,
full adders have a carry input capability.
7. The binary subtraction of 0 – 0 = ?

a) Difference = 0, borrow = 0
b) Difference = 1, borrow = 0
c) Difference = 1, borrow = 1
d) Difference = 0, borrow = 1
View Answer
Answer: a
Explanation: The binary subtraction of 0 – 0 = 0. Thus, it’s difference is 0 as well as it’s borrow.
8. How many basic binary subtraction operations are possible?

a) 1
b) 4
c) 3
d) 2
View Answer
Answer: b
Explanation: 4 basic binary subtraction operations (0-0, 1-0, 0-1, 1-1) are possible.
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
9. When performing subtraction by addition in the 2’s-complement system:

a) The minuend and the subtrahend are both changed to the 2’s-complement
b) The minuend is changed to 2’s-complement and the subtrahend is left in its original form
c) The minuend is left in its original form and the subtrahend is changed to its 2’s-complement
d) The minuend and subtrahend are both left in their original form
View Answer
Answer: c
Explanation: When performing subtraction by addition in the 2’s-complement system, the minuend is left
in its original form and the subtrahend is changed to its 2’s-complement. It is then added to the minuend.
If the result has carry, then it’s dropped and that’s the inal answer. Else, if the result has no carry, then
the result is again converted to it’s 2’s complement form and that’s the inal answer with a ‘negative’
sign.
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10. What are the two types of basic adder circuits?

a) Sum and carry
b) Half-adder and full-adder
c) Asynchronous and synchronous
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d) One and two’s-complement

View Answer
Answer: b
Explanation: There are two types of adder circuits: half-adder and full-adder. Half-Adder has 2 inputs
while Full-Adder has 3 inputs. Whereas, both have two outputs SUM and CARRY.
11. Which of the following is correct for full adders?

a) Full adders have the capability of directly adding decimal numbers
b) Full adders are used to make half adders
c) Full adders are limited to two inputs since there are only two binary digits
d) In a parallel full adder, the irst stage may be a half adder
View Answer
Answer: d
Explanation: By using maximum of two half adders we can make a full adder for the irst stage of a
Parallel Full adder.
12. The selector inputs to an arithmetic/logic unit (ALU) determine the __________
a) Selection of the IC
b) Arithmetic or logic function
c) Data word selection
d) Clock frequency to be used
View Answer
Answer: b
Explanation: An ALU performs basic arithmetic and logic operations and stores it in the accumulator.
Examples of arithmetic operations are addition, subtraction, multiplication, and division. Examples of
logic operations are comparisons of values such as NOT, AND and OR and any logical operations.

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Digital Circuits Questions and Answers – 4-Bit

Parallel Adder/Subtractor – 1
« Prev Next »
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “4-Bit
Parallel Adder/Subtractor – 1”.
1. Controlled inverter is also known as ____________

a) Controlled buffer
b) NOT gate
c) Both controlled buffer and NOT gate
d) Controlled gate
View Answer
Answer: c
Explanation: Controlled inverter is also known as controlled buffer and NOT gate as well. It is used
between output and a bus so that one can control whether the output is fed to the bus or not.
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2. Why XOR gate is called an inverter?

a) Because of the same input
b) Because of the same output
c) It behaves like a NOT gate
d) It behaves like a AND gate
View Answer
11/5/2020 deld.html
Answer: c
Explanation: The XOR (Exclusive Or) gate has a true output when the two inputs are different. When one
input is true, the output is the inversion of the other. When one input is false, the output is the non-
inversion of the other.
3. Controlled buffers can be useful ____________

a) To control the circuit’s output into the bus
b) In comparison of component’s output with its input
c) In increasing the output from its low input
View Answer
Answer: a
Explanation: Controlled buffers can be useful when you have a wire (often called a bus) whose value
should match the output of one of several components. By placing a controlled buffer between each
component output and the bus, you can control whether that component’s output is fed onto the bus or
not.
4. A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is ____________
a) Ex-NOR gate
b) OR gate
c) Ex-OR gate
d) NAND gate
View Answer
Answer: a
Explanation: EX-OR gate gives 1 if both inputs are different means 0 or 1 and gives 0 if both are same
and EX-NOR is opposite of EX-OR gate, so it provides a HIGH output for both inputs HIGH or both inputs
are LOW. Thus, EX-NOR produces output for even number of 1’s or all 0s, while EXOR produces output
for odd number of 1’s.
5. What is the irst thing you will need if you are going to use a macro-function?
a) A complicated design project
b) An experienced design engineer
c) Good documentation
d) Experience in HDL
View Answer
Answer: d
Explanation: HDL stands for Hardware Description Language. In order to use a macro function, one
needs to have experience in HDL for representing the structure and behaviour of digital circuits.
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6. What is the major difference between half-adders and full-adders?

a) Full-adders are made up of two half-adders
b) Full adders can handle double-digit numbers
c) Full adders have a carry input capability
d) Half adders can handle only single-digit numbers
View Answer
Answer: c
Explanation: Half adders have only two inputs A and B. When we add two 4 bit binary number like 0001
and 0011, then half adder can not be used because if the irst bit of both the numbers is 1, then the sum
11/5/2020 deld.html
would be 0 and carry would be 1. But this carry can not be added with the second bits addition of the
number. So, half adders are useless. But in full adders, one more carry input is present, so that, if carry
of one stage is present, it can be added with the next stage as it is done in normal addition. So, therefore,
full adders have a carry input capability.
7. The binary subtraction of 0 – 0 = ?

a) Difference = 0, borrow = 0
b) Difference = 1, borrow = 0
c) Difference = 1, borrow = 1
d) Difference = 0, borrow = 1
View Answer
Answer: a
Explanation: The binary subtraction of 0 – 0 = 0. Thus, it’s difference is 0 as well as it’s borrow.
8. How many basic binary subtraction operations are possible?

a) 1
b) 4
c) 3
d) 2
View Answer
Answer: b
Explanation: 4 basic binary subtraction operations (0-0, 1-0, 0-1, 1-1) are possible.
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
9. When performing subtraction by addition in the 2’s-complement system ____________

a) The minuend and the subtrahend are both changed to the 2’s-complement
b) The minuend is changed to 2’s-complement and the subtrahend is left in its original form
c) The minuend is left in its original form and the subtrahend is changed to its 2’s-complement
d) The minuend and subtrahend are both left in their original form
View Answer
Answer: c
Explanation: When performing subtraction by addition in the 2’s-complement system, the minuend is left
in its original form and the subtrahend is changed to its 2’s-complement. It is then added to the minuend.
If the result has carry, then it’s dropped and that’s the inal answer. Else, if the result has no carry, then
the result is again converted to it’s 2’s complement form and that’s the inal answer with a ‘negative’
sign.
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10. What are the two types of basic adder circuits?

a) Sum and carry
b) Half-adder and full-adder
c) Asynchronous and synchronous
d) One and two’s-complement
View Answer
Answer: b
Explanation: There are two types of adder circuits: half-adder and full-adder. Half-Adder has 2 inputs
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while Full-Adder has 3 inputs. Whereas, both have two outputs SUM and CARRY.
11. Which of the following is correct for full adders?

a) Full adders have the capability of directly adding decimal numbers
b) Full adders are used to make half adders
c) Full adders are limited to two inputs since there are only two binary digits
d) In a parallel full adder, the irst stage may be a half adder
View Answer
Answer: d
Explanation: By using maximum of two half adders we can make a full adder for the irst stage of a
Parallel Full adder.
12. The selector inputs to an arithmetic/logic unit (ALU) determine the ____________
a) Selection of the IC
b) Arithmetic or logic function
c) Data word selection
d) Clock frequency to be used
View Answer
Answer: b
Explanation: An ALU performs basic arithmetic and logic operations and stores it in the accumulator.
Examples of arithmetic operations are addition, subtraction, multiplication, and division. Examples of
logic operations are comparisons of values such as NOT, AND and OR and any logical operations.

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Answers.

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Digital Circuits Questions and Answers – 4-Bit

Parallel Adder/Subtractor – 2
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This set of Digital Electronic/Circuits Test focuses on “4-Bit Parallel Adder/Subtractor – 2”.
1. For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is ___________
a) The same as if the carry-in is tied LOW since the least signi icant carry-in is ignored
b) That carry-out will always be HIGH
c) A one will be added to the inal result
d) The carry-out is ignored
View Answer
Answer: c
Explanation: For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, one will be added to
the inal result as a result because carry-in gives output as 1.
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2. Fast-look-ahead carry circuits found in most 4-bit full-adder circuits which ___________
a) Determine sign and magnitude
b) Reduce propagation delay
c) Add a 1 to complemented inputs
d) Increase ripple delay
View Answer
Answer: b
Explanation: A carry-lookahead adder (CLA) is a type of adder used in digital logic. A carry-lookahead
adder improves speed by reducing the amount of time required to determine carry bits. It reduces the
propagation delay by making the hardware more complex. The ripple carry design is converted in such a
way that carry over a group of bits of the adder becomes 2-level logic.
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3. One way to make a four-bit adder to perform subtraction is by ___________

a) Inverting the output
b) Inverting the carry-in
c) Inverting the B inputs
d) Grounding the B inputs
View Answer
Answer: c
Explanation: A adder is a digital circuit which adds bits along with a carry bit from a previous stage, thus
producing 2 outputs SUM and CARRY. Since, a four bit adder has four A, four B and a carry at the input
end. So, for subtraction to be performed, all the Bs terminal should be inverted.
4. What distinguishes the look-ahead-carry adder?

a) It is slower than the ripple-carry adder
b) It is easier to implement logically than a full adder
c) It is faster than a ripple-carry adder
d) It requires advance knowledge of the inal answer
View Answer
Answer: c
Explanation: It is faster than ripple carry adder as it reduces the propagation delay by converting the
ripple carry in such a way that the carry over a group of bits of the adder becomes 2-level logic.
5. Carry lookahead logic uses the concepts of ___________

a) Inverting the inputs
b) Complementing the outputs
c) Generating and propagating carries
d) Ripple factor
View Answer
Answer: c
Explanation: Look Ahead Carry Adder is a type of digital circuit which reduces the propagation delay.
Carry lookahead logic uses the concepts of generating and propagating carries. Although in the context
of a carry lookahead adder, it is most natural to think of generating and propagating in the context of
binary addition, the concepts can be used more generally than this.
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6. What is one disadvantage of the ripple-carry adder?

a) The interconnections are more complex
b) More stages are required to a full adder
c) It is slow due to propagation time
View Answer
Answer: c
Explanation: The main disadvantage in using this type of adders is that the time delay increases as for
each adder to add the carry should be generated in the previous adder, and for that to add the carry
from the one before is required. However, this disadvantage is taken care of in Carry Look Ahead adder
in which the ripple carry is converted in such a way that the carry over a group of bits of the adder
becomes 2-level logic.
7. The carry propagation delay in 4-bit full-adder circuits ___________

a) Is cumulative for each stage and limits the speed at which arithmetic operations are performed
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b) Is normally not a consideration because the delays are usually in the nanosecond range
c) Decreases in direct ratio to the total number of full-adder stages
d) Increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the
speed of arithmetic operations
View Answer
Answer: a
Explanation: A full adder is a digital circuit with 3 inputs and two outputs SUM and CARRY. The carry
propagation delay in 4-bit full-adder circuits is cumulative for each stage and limits the speed at which
arithmetic operations are performed.
8. What is Manchester carry chain?

a) Is a chain of controlled inverter
b) Variation of a carry-lookahead adder
c) Variation of a full-adder
d) Variation of a ripple carry adder
View Answer
Answer: b
Explanation: The Manchester carry chain is a variation of the carry-lookahead adder that uses shared
logic to lower the transistor count. However, the carry generating logic depends on the logic to generate
the carries in the past.
9. The main disadvantage of Manchester carry chain is ___________

a) Ripple factor
b) Propagation delay
c) Capacitive load
d) Both propagation delay and capacitive load
View Answer
Answer: d
Explanation: Propagation delay is the measure of time taken by the output to go to the next state when
the input is altered. One of the major downsides of the Manchester carry chain is that the capacitive load
of all of these outputs, together with the resistance of the transistors causes the propagation delay to
increase much more quickly than a regular carry lookahead.
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10. The summing outputs of a half or full-adder are designated by which Greek symbol?
a) Omega
b) Theta
c) Lambda
d) Sigma
View Answer
Answer: d
Explanation: The summing outputs of a half or full-adder are designated by “sigma” which is a Greek
symbol. This same symbol is used to signify the Minterms in case of an SOP expression.
11. Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder?
a) To decrease the cost
b) To make it smaller
c) To slow down the circuit
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d) To speed up the circuit

View Answer
Answer: d
Explanation: A Carry Look Ahead (CLA) Adder is a type of adder that reduce the propagation delay. A
fast Carry Look Ahead Adder is more fast than a normal CLA. Since, it is easy to implement and can be
implemented on any types of chip and have the capability to reduce propagation delay, which helps in
increasing the speed of 7483 4-bit full-adder.

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Digital Circuits Questions and Answers – Fast

Adder & Serial Adder – 1
« Prev Next »
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Fast
Adder & Serial Adder – 1”.
1. The inverter can be produced with how many NAND gates?

a) 2
b) 1
c) 3
d) 4
View Answer
Answer: b
Explanation: The inverter can be produced with the help of single NAND gate, because we can send a
single input twice through the same NAND gate together, thus producing the inverted version of the
input as output. It works as an inverter.
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2. One positive pulse with tw = 75 µs is applied to one of the inputs of an exclusive-OR circuit. A second
positive pulse with tw = 15 µs is applied to the other input beginning 20 µs after the leading edge of the
irst pulse. Which statement describes the output’s relation with the inputs?
a) The exclusive-OR output is a 20 s pulse followed by a 40 s pulse, with a separation of 15 s between the
pulses
b) The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, with a separation of 40 s between the
pulses
c) The exclusive-OR output is a 15 s pulse followed by a 40 s pulse
d) The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, followed by a 40 s pulse
View Answer
Answer: d
Explanation: When both the input pulses are high or low X-OR output is low. But when one of the input is
high and another is low or vice-versa, output is high. In this problem for the irst 20uS one input is high
and another is low. So, obviously output is a high. for next 15uS both the input is high so output is low
and for remaining 40uS(75-20-15) irst input is still high and second one is low so output is high.
3. How many NOT gates are required to implement the Boolean expression: X = AB’C + A’BC?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: Since in the given expression two inputs are complemented. So, we require two NOT gate at
the input. A NOT gate is a basic gate which accepts a single input and produces a single output, which is
the inverted version of the input.
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4. The carry look ahead adder is based on the principle of looking at the lower order bits of ________ and
________ if a high order carry is generated.
a) Addend, minuend
b) Minuend, subtrahend
c) Addend, minuend
d) Augend, addend
View Answer
Answer: d
Explanation: The carry look ahead adder is based on the principle of looking at the lower order bits of
the augend and addend if a high order carry is generated. A carry look ahead adder is a type of adder
which reduces the propagation delay.
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5. What are carry generate combinations?

a) If all the input are same then a carry is generated
b) If all of the output are independent of the inputs
c) If all of the input are dependent on the output
d) If all of the output are dependent on the input
View Answer
Answer: b
Explanation: If the input is either 0, 0, 0 or 0, 0, 1 then the output will be 0 (i.e. independent of input) and
if the input is either 1, 1, 0 or 1, 1, 1 then the output is 1 (i.e independent of input). Such situation is
known as carry generate combinations.
6. In serial addition, the addition is carried out __________

a) 3 bit per second
b) Byte by byte
c) Bit by bit
d) All bits at the same time
View Answer
Answer: c
Explanation: In serial addition, the addition is carried out bit by bit.
7. How many shift registers are used in a 4 bit serial adder?

a) 4
b) 3
c) 2
d) 5
View Answer
Answer: c
Explanation: There are two shift registers are used in a 4-bit serial adder, which is used to store the
numbers to be added serially. Serial addition takes place bit by bit.
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8. A D lip- lop is used in a 4-bit serial adder, why?

a) It is used to invert the input of the full adder
b) It is used to store the output of the full adder
c) It is used to store the carry output of the full adder
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d) It is used to store the sum output of the full adder

View Answer
Answer: c
Explanation: The D lip- lop, i.e. carry lip- lop, is used to store the carry output of the full adder so that it
can be added to the next signi icant position of the numbers in the registers.
9. What is ripple carry adder?

a) The carry output of the lower order stage is connected to the carry input of the next higher order
stage
b) The carry input of the lower order stage is connected to the carry output of the next higher order
stage
c) The carry output of the higher order stage is connected to the carry input of the next lower order
stage
d) The carry input of the higher order stage is connected to the carry output of the lower order stage
View Answer
Answer: a
Explanation: When the carry output of the lower order stage is connected to the carry input of the next
higher order stage, such types of connection is called ripple carry adder in a 4-bit binary parallel adder.
10. If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will
be __________
a) 0
b) 1
c) Floating
d) High Impedance
View Answer
Answer: b
Explanation: If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow
output will be 1. Because on subtracting 0 and 1, one borrow is taken and it proceeds till the next step
(i.e 0 – 1 – 1 = 0, borrow = 1).
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Answers.

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Digital Circuits Questions and Answers – Fast

Adder & Serial Adder – 2
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This set of Digital Electronic/Circuits Quiz focuses on “Fast Adder & Serial Adder – 2”.
1. A serial subtractor can be obtained by converting the serial adder by using the _____________
a) 1’s complement system
b) 2’s complement system
c) 10’s complement
d) 9’s complement
View Answer
Answer: b
Explanation: A serial subtractor can be obtained by converting the serial adder by using the 2’s
complement system. 9’s complement and 10’s complement are used for decimal numbers while adders
deal with binary numbers.
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2. The hexadecimal number (4B)16 is transmitted as an 8-bit word in parallel. What is the time required
for this transmission if the clock frequency is 2.25 MHz?
a) 444 ns
b) 444 s
c) 3.55 s
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d) 3.55 ms
View Answer
Answer: a
Explanation: Because the clock pulse of 4-bit transmits the data of 8-bit word in parallel mode and this
transmission is done at 2.25 MHz frequency. We know that: f=1/t and we can ind the time required for
this transmission by the clock pulse.
Therefore, time = (1/2.25) = 0.4444 us = 444.44 ns ~ 444ns.
3. Internally, a computer’s binary data are always transmitted on parallel channels which is commonly
referred to as the __________
a) Parallel bus
b) Serial bus
c) Data bus
d) Memory bus
View Answer
Answer: c
Explanation: A process consists of 3 types of buses: Control Bus, Data Bus and Address Bus. A
computer’s data is always in the binary form which is stored in the bus that transmits the data on any
channels. It doesn’t matter that it’s in parallel or serial.
4. What is the frequency of a clock waveform if the period of that waveform is 1.25sec?
a) 8 kHz
b) 0.8 kHz
c) 0.8 MHz
d) 8 MHz
View Answer
Answer: c
Explanation: By using the formula of frequency, we can ind the frequency of clock waveform. Time
period(t) of the waveform is = 1.25microseconds
f=1/t
Where ‘t’ is the time taken by the clock waveform;
f=(1/1.25)
so, f=0.8 MHz.
5. Why is parallel data transmission preferred over serial data transmission for most applications?
a) It is much slower
b) It is cheaper
c) More people use it
d) It is much faster
View Answer
Answer: d
Explanation: Parallel data transmission preferred over serial data transmission for most applications
because it is much faster as bits are transmitted simultaneously, whereas in serial data transmission, bits
are transmitted one by one.
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6. With surface-mount technology (SMT), the devices should __________

a) Utilize transistor outline connections
b) Mount directly
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c) Have parallel connecting pins

d) Require holes and pads
View Answer
Answer: b
Explanation: Surface-mount technology (SMT) is a method for producing electronic circuits in which the
components are mounted or placed directly onto the surface of printed circuit boards (PCBs). An
electronic device so made is called a surface-mount device (SMD). In the industry, it has largely replaced
the through-hole technology construction method of itting components with wire leads into holes in the
circuit board. Both technologies can be used on the same board for components not suited to surface
mounting such as large transformers and heat-sinked power semiconductors.
7. In most applications, transistor switches used in place of relays?

a) They consume less power
b) They are faster
c) They are quieter and smaller
View Answer
Answer: d
Explanation: Transistors are of less consuming power, faster, quieter, smaller and its implementation is
too easy. So, in most applications transistor switches are more preferred. And also, transistors can be
current-controlled or voltage-controlled depending on our choice.
8. What can a relay provide between the triggering source and the output that semiconductor switching
devices cannot?
a) Total isolation
b) Faster
c) Higher current rating
d) Total isolation and higher current rating
View Answer
Answer: d
Explanation: A relay provides total isolation and higher current rating between the triggering source and
the output that semiconductor switching devices cannot provide. This is why relays are used to drive
high watt appliances at of ices or other buildings.
9. The serial format for transmitting binary information uses __________

a) A single conductor
b) Multiple conductors
c) Infrared technology
d) Fiber-optic
View Answer
Answer: a
Explanation: A conductor accepts the whole data and arranges it in a serial manner, which is transmitted
as binary information. In serial transmission, data is transmitted bit by bit while in parallel transmission
data is transmitted simultaneously.
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10. Serial communication can be sped up by __________

a) Using silver or gold conductors instead of copper
b) Using high-speed clock signals
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c) Adjusting the duty cycle of the binary information

d) Using silver or gold conductors instead of copper and high-speed clock signals
View Answer
Answer: b
Explanation: For any serial data transmission there is required of continuously data supply and if the
input supply (i.e. high speed clock signals) in a high amount the speed of serial communication can be
increased. In serial communication, data is transmitted bit by bit. So the use of high speed clock pulses
would make the process faster.
To practice all areas of Digital Electronic Circuits for quizzes, here is complete set of 1000+ Multiple

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Digital Circuits Questions and Answers – BCD

Adder
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “BCD
Adder”.
1. The decimal number system represents the decimal number in the form of ____________
a) Hexadecimal
b) Binary coded
c) Octal
d) Decimal
View Answer
Answer: b
Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each
decimal digit is represented by a ixed number of bits, usually four or eight. Hexadecimal and Octal are
number systems having base 16 and 8 respectively.
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2. 29 input circuit will have total of ____________

a) 32 entries
b) 128 entries
c) 256 entries
d) 512 entries
View Answer
Answer: d
Explanation: 29 input circuit would have 512(2*2*2*2*2*2*2*2*2 = 512) entries.
3. BCD adder can be constructed with 3 IC packages each of ____________

a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
View Answer
Answer: c
decimal digit is represented by a ixed number of bits, usually four or eight. BCD adder can be
constructed with 3 IC packages. Each of 4-bit adders is an MSI(Medium scale Integration) function and 3
gates for the correction logic need one SSI (Small Scale Integration) package.
4. The output sum of two decimal digits can be represented in ____________

a) Gray Code
b) Excess-3
c) BCD
d) Hexadecimal
View Answer
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Answer: c
Explanation: The output sum of two decimal digits can be represented in BCD(Binary-coded decimal).
Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit
is represented by a ixed number of bits, usually four or eight.
5. The addition of two decimal digits in BCD can be done through ____________
a) BCD adder
b) Full adder
c) Ripple carry adder
d) Carry look ahead
View Answer
Answer: a
Explanation: The addition of two decimal digits in BCD can be done through BCD adder. Every input
inserted, in addition by the user converted into binary and then proceed for the addition. Whereas, Full
Adder, Ripple Carry Adder and Carry Look Adder are for the addition of binary bits.
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6. 3 bits full adder contains ____________

a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
View Answer
Answer: d
Explanation: 3 bits full adder contains 23 = 8 combinational inputs.
7. The simpli ied expression of full adder carry is ____________

a) c = xy+xz+yz
b) c = xy+xz
c) c = xy+yz
d) c = x+y+z
View Answer
Answer: a
Explanation: A full adder is a combinational circuit having 3 inputs and 2 outputs, namely SUM and
CARRY. The simpli ied expression of full adder carry is c = xy+xz+yz.
8. Complement of F’ gives back __________

a) F’
b) F
c) FF
d) FF’
View Answer
Answer: b
Explanation: Complement means inversion. So, complement of F’ gives back F, as per the Law of
Involution.
9. Decimal digit in BCD can be represented by ____________

a) 1 input line
b) 2 input lines
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c) 3 input lines
d) 4 input lines
View Answer
Answer: d
decimal digit is represented by a ixed number of bits, usually four or eight. Decimal digit in BCD can be
represented by 4 input lines. Since it is constructed with 4-bits.
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10. The number of logic gates and the way of their interconnections can be classi ied as ____________
a) Logical network
b) System network
c) Circuit network
d) Gate network
View Answer
Answer: a
Explanation: The number of different levels of logic gates is represented in a fashion which is known as a
logical network.
Answers.

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Digital Circuits Questions and Answers – Combinational Circuits
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Combinational Circuits
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“Combinational Circuits”.
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1. Which of the circuits in igure (a to d) is the sum-of-products implementation of igure (e)?
a) a
b) b
c) c
d) d
View Answer
Answer: d
Explanation: SOP means Sum Of Products form which represents the sum of product terms having
variables in complemented as well as in uncomplemented form. Here, the diagram of d contains the OR
gate followed by the AND gates, so it is in SOP form.
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2. Which of the following logic expressions represents the logic diagram shown?
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a) X=AB’+A’B
b) X=(AB)’+AB
c) X=(AB)’+A’B’
d) X=A’B’+AB
View Answer
Answer: d
Explanation: 1st output of AND gate is = A’B’
2nd AND gate’s output is = AB and,
OR gate’s output is = (A’B’)+(AB) = AB + A’B’.
3. The device shown here is most likely a ________
a) Comparator
b) Multiplexer
c) Inverter
d) Demultiplexer
View Answer
Answer: d
Explanation: The given diagram is demultiplexer, because it takes single input & gives many outputs. A
demultiplexer is a combinational circuit that takes a single output and latches it to multiple outputs
depending on the select lines.
4. What type of logic circuit is represented by the igure shown below?
a) XOR
b) XNOR
c) AND
d) XAND
View Answer
Answer: b
Explanation: After solving the circuit we get (A’B’)+AB as output, which is XNOR operation. Thus, it will
produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is odd number of 1s.
5. For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is
correct?
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a) d
b) a
c) c
d) b
View Answer
Answer: a
Explanation: When both inputs are same then the o/p is high for a XNOR gate.
i.e., A B O/P
001
010
100
1 1 1.
Thus, it will produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is odd
number of 1s.
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6. Which of the following combinations of logic gates can decode binary 1101?
a) One 4-input AND gate
b) One 4-input AND gate, one inverter
c) One 4-input AND gate, one OR gate
d) One 4-input NAND gate, one inverter
View Answer
Answer: b
Explanation: For decoding any number output must be high for that code and this is possible in One 4-
input NAND gate, one inverter option only. A decoder is a combinational circuit that converts binary data
to n-coded data upto 2n outputs.
7. What is the indication of a short to ground in the output of a driving gate?

a) Only the output of the defective gate is affected
b) There is a signal loss to all load gates
c) The node may be stuck in either the HIGH or the LOW state
d) The affected node will be stuck in the HIGH state
View Answer
Answer: b
Explanation: Short to ground in the output of a driving gate indicates of a signal loss to all load gates.
This results in information being disrupted and loss of data.
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8. For the device shown here, assume the D input is LOW, both S inputs are LOW and the input is LOW.
What is the status of the Y’ outputs?
a) All are HIGH

b) All are LOW
c) All but Y0 are LOW
d) All but Y0 are HIGH
View Answer
Answer: d
Explanation: In the given diagram, S0 and S1 are selection bits. So,
I/P S0 S1 O/P
D = 0 0 0 Y0
D = 0 0 1 Y1
D = 0 1 0 Y2
D = 0 1 1 Y3
Hence, inputs are S0 and S1 are Low means 0, so output is Y0 and rest all are HIGH.
9. The carry propagation can be expressed as ________

a) Cp = AB
b) Cp = A + B
c) All but Y0 are LOW
d) All but Y0 are HIGH
View Answer
Answer: b
Explanation: This happens in parallel adders (where we try to add numbers in parallel via more than
one adders). A carry propagation occurs when carry from one adder needs to be forwarded to other
adder and that second adder is holding the computation (addition) because carry from irst adder has
not come yet. So, there is a slight delay for second adder and this is known as carry propagation.
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10. 3 bits full adder contains ________

a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
View Answer
Answer: d
Explanation: Full Adder is a combinational circuit with 3 input bits and 2 output bits CARRY and SUM.
Three bits full adder requires 23 = 8 combinational circuits.
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Multiplexers (Data Selectors) – 1
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“Multiplexers (Data Selectors) – 1”.
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1. What is a multiplexer?
a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one
c) It takes one input and results into many output
d) It is a type of encoder which decodes several inputs and gives one output
View Answer
Answer: b
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital input signals
and forwards the selected input into a single line, depending on the active select lines.
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2. Which combinational circuit is renowned for selecting a single input from multiple inputs & directing
the binary information to output line?
a) Data Selector
b) Data distributor
c) Both data selector and data distributor
d) DeMultiplexer
View Answer
Answer: a
Explanation: Data Selector is another name of Multiplexer. A multiplexer (or MUX) is a device that selects
one of several analog or digital input signals and forwards the selected input into a single line, depending
on the active select lines.
3. It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the
digital multiplexer with the pro iciency of large number of ___________
a) Inputs
b) Outputs
c) Selection lines
d) Enable lines
View Answer
Answer: a
Explanation: It is possible for an enable or strobe input to undergo an expansion of two or more MUX
ICs to the digital multiplexer with the pro iciency of large number of inputs.
4. Which is the major functioning responsibility of the multiplexing combinational circuit?

a) Decoding the binary information
b) Generation of all minterms in an output function with OR-gate
c) Generation of selected path between multiple sources and a single destination
d) Encoding of binary information
View Answer
Answer: c
Explanation: The major functioning responsibility of the multiplexing combinational circuit is generation
of selected path between multiple sources and a single destination because it makes the circuit too
lexible. A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and
forwards the selected input into a single line, depending on the active select lines.
5. What is the function of an enable input on a multiplexer chip?

a) To apply Vcc
b) To connect ground
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c) To active the entire chip

d) To active one half of the chip
View Answer
Answer: c
Explanation: Enable input is used to active the chip, when enable is high the chip works (ACTIVE), when
enable is low the chip does not work (MEMORY). However, Enable can be Active-High or Active-Low,
indicating it is active either when it is connected to VCC or GND respectively.
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6. One multiplexer can take the place of ___________

a) Several SSI logic gates
b) Combinational logic circuits
c) Several Ex-NOR gates
d) Several SSI logic gates or combinational logic circuits
View Answer
Answer: d
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital input signals
and forwards the selected input into a single line, depending on the active select lines. Since many
operational behaviour can be performed by using a multiplexer. Whereas, a combinational circuit is a
combination of many logic gates which makes the circuit more complex.
7. A digital multiplexer is a combinational circuit that selects ___________

a) One digital information from several sources and transmits the selected one
b) Many digital information and convert them into one
c) Many decimal inputs and transmits the selected information
d) Many decimal outputs and accepts the selected information
View Answer
Answer: a
Explanation: A digital multiplexer is a combinational circuit that selects one digital information from
several sources and transmits the selected information on a single output line depending on the status of
the select lines. That is why it is also known as a data selector.
8. In a multiplexer, the selection of a particular input line is controlled by ___________

a) Data controller
b) Selected lines
c) Logic gates
d) Both data controller and selected lines
View Answer
Answer: b
Explanation: The selection of a particular input line is controlled by a set of selected lines in a
multiplexer, which helps to select a particular input from several sources.
9. If the number of n selected input lines is equal to 2^m then it requires _____ select lines.
a) 2
b) m
c) n
d) 2n
View Answer
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Answer: b
Explanation: If the number of n selected input lines is equal to 2^m then it requires m select lines to
select one of m select lines.
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10. How many select lines would be required for an 8-line-to-1-line multiplexer?
a) 2
b) 4
c) 8
d) 3
View Answer
Answer: d
Explanation: 2n input lines, n control lines and 1 output line available for MUX. Here, 8 input lines mean
23 inputs. So, 3 control lines are possible. Depending on the status of the select lines, the input is selected
and fed to the output.
11. A basic multiplexer principle can be demonstrated through the use of a ___________
a) Single-pole relay
b) DPDT switch
c) Rotary switch
d) Linear stepper
View Answer
Answer: c
Explanation: A basic multiplexer principle can be demonstrated through the use of a rotary switch. Since
its behaviour is similar to the multiplexer. There are around 10 digits out of which one is selected one at
a time and fed to the output.
12. How many NOT gates are required for the construction of a 4-to-1 multiplexer?
a) 3
b) 4
c) 2
d) 5
View Answer
Answer: c
Explanation: There are two NOT gates required for the construction of 4-to-1 multiplexer. x0, x1, x2 and
x3 are the inputs and C1 and C0 are the select lines and M is the output.
The diagram of a 4-to-1 multiplexer is shown below:
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13. In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is ___________
a) X0
b) X1
c) X2
d) X3
View Answer
Answer: b
Explanation: The output will be X1, because c1 = 0 and c0 = 1 results into 1 which further results as X1.
And rest of the AND gates gives output as 0.
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14. The enable input is also known as ___________

a) Select input
b) Decoded input
c) Strobe
d) Sink
View Answer
Answer: c
Explanation: The enable input is also known as strobe which is used to cascade two or more multiplexer
ICs to construct a multiplexer with a larger number of inputs. Enable input activates the multiplexer to
operate.
Answers.

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Multiplexers (Data Selectors) – 2
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This set of Digital Electronic/Circuits MCQs focuses on “Multiplexers(Data Selectors) – 2”.
1. 4 to 1 MUX would have ____________

a) 2 inputs
b) 3 inputs
c) 4 inputs
d) 5 inputs
View Answer
Answer: c
Explanation: 4 to 1 multiplexer would have 4 inputs (X0, X1, X2, X3), 2 select lines (C1, C0) and 1 output
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(M). It can be observed from this diagram:
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2. The two input MUX would have ____________

a) 1 select line
b) 2 select lines
c) 4 select lines
d) 3 select lines
View Answer
Answer: a
Explanation: The two input multiplexer would have n select lines in 2n. Thus n =1. Therefore, it has 1
select line.
3. A combinational circuit that selects one from many inputs are ____________
a) Encoder
b) Decoder
c) Demultiplexer
d) Multiplexer
View Answer
Answer: d
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer. Whereas,
a combinational circuit that divides one input into multiple outputs is known as Demultiplexer.
4. 4 to 1 MUX would have ____________

a) 1 output
b) 2 outputs
c) 3 outputs
d) 4 outputs
View Answer
Answer: a
Explanation: 4 to 1 multiplexer would have 4 inputs (X0, X1, X2, X3), 2 select lines (C1, C0) and 1 output
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(M). It can be observed from this diagram:
5. Which of the following circuit can be used as parallel to serial converter?

a) Multiplexer
b) Demultiplexer
c) Decoder
d) Digital counter
View Answer
Answer: a
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer. In
multiplexer, different inputs are inserted parallely and then it gives one output which is in serial form.
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6. A combinational circuit is one in which the output depends on the ____________

a) Input combination at the time
b) Input combination and the previous output
c) Input combination at that time and the previous input combination
d) Present output and the previous output
View Answer
Answer: a
Explanation: A combinational circuit is one in which the output depends on the input combination at the
time, whereas, a sequential circuit is one in which the output depends on present input as well past
outputs.
7. Without any additional circuitry an 8:1 MUX can be used to obtain ____________
a) Some but not all Boolean functions of 3 variables
b) All function of 3 variables but none of 4 variables
c) All functions of 3 variables and some but not all of 4 variables
d) All functions of 4 variables
View Answer
Answer: d
Explanation: A 2^n:1 MUX can implement all logic functions of (n+1) variables without any additional
circuitry. Thus 8:1 MUX can implement all logic functions of (3+1) variables, for 4 variables there are 16
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possible combinations. So to use 8:1 MUX use 3 inputs as select lines of MUX and the 4th input as input
of MUX.
8. A basic multiplexer principle can be demonstrated through the use of a ____________

a) Single-pole relay
b) DPDT switch
c) Rotary switch
d) Linear stepper
View Answer
Answer: c
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer. A basic
multiplexer principle can be demonstrated through the use of a rotary switch. Because rotary switch
gives one output corresponding to their inputs.
9. One multiplexer can take the place of ____________

a) Several SSI logic gates
b) Combinational logic circuits
c) Several Ex-NOR gates
d) Several SSI logic gates or combinational logic circuits
View Answer
Answer: d
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer. One
multiplexer can take the place of several SSI logic gates or combinational logic circuits because it has a lot
of functions to perform different operations.
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10. The inputs/outputs of an analog multiplexer/demultiplexer are ____________

a) Bidirectional
b) Unidirectional
c) Even parity
d) Binary-coded decimal
View Answer
Answer: a
Explanation: One multiplexer can be used as demultiplexer. Hence, it is called bidirectional or two-way
transmission.
11. If enable input is high then the multiplexer is ______________

a) Enable
b) Disable
c) Saturation
d) High Impedance
View Answer
Answer: b
Explanation: If enable input is high then the multiplexer is disabled because enable input is in inverted
mode always (i.e. E’).
12. What is data routing in a multiplexer?

a) It spreads the information to the control unit
b) It can be used to route data from one of several source to destination
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c) It is an application of multiplexer
d) Both it can be used to route data and it is an application of multiplexer
View Answer
Answer: d
Explanation: Multiplexing means passing more than one data through the same channel. Data routing is
an application of multiplexer and it can be used to route data from one of several source to destination.

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Demultiplexers (Data Distributors) – 1
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“Demultiplexers (Data Distributors) – 1”.
1. The word demultiplex means ___________

a) One into many
b) Many into one
c) Distributor
d) One into many as well as Distributor
View Answer
Answer: d
Explanation: The word demultiplex means “one into many” and distributor. A demultiplexer sends a
single input to multiple outputs, depending on the select lines. It is clear from the diagram:
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2. Why is a demultiplexer called a data distributor?

a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input to Single Output
View Answer
Answer: a
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. For
one input, the demultiplexer gives several outputs. That is why, it is called a data distributor.
3. Most demultiplexers facilitate which type of conversion?

a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
View Answer
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines.
Demultiplexer converts single input into multiple outputs.
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4. In 1-to-4 demultiplexer, how many select lines are required?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines.
Therefore, for 1:4 demultiplexer, 2 select lines are required.
5. In a multiplexer the output depends on its ___________

a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
View Answer
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. As
the select input changes, the output of the multiplexer varies according to that input.
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6. In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be ___________

a) Y0
b) Y1
c) Y2
d) Y3
View Answer
Answer: b
Explanation: It can be calculated from the igure shown below:
For C0 =1 and C1 =0, Y1 will be the output as 0 and 1 are the bit combinations of 1.
7. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ___________

a) Y0
b) Y1
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c) Y2
d) Y3
View Answer
Answer: d
8. How many select lines are required for a 1-to-8 demultiplexer?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: b
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. In this
case n = 3 since 23 = 8.
9. How many AND gates are required for a 1-to-8 multiplexer?

a) 2
b) 6
c) 8
d) 5
View Answer
Answer: c
Explanation: The number of AND gates required will be equal to the number of outputs in a
demultiplexer, which are 8.
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10. The output Q4 of this 1-to-8 demultiplexer is ____________
a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) Q2.(Q1).Q0.I
View Answer
Answer: c
Explanation: The output Y4 = Q2.(Q1)’.(Q0)’.I. since the bit combinations of 4 are 100.
11. Which IC is used for the implementation of 1-to-16 DEMUX?

a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
View Answer
Answer: a
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input.

Answers.
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Demultiplexers (Data Distributors) – 2
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This set of Digital Electronic/Circuits Multiple Choice Questions & Answers focuses on
“Demultiplexers(Data Distributors) – 2”.
1. Why is a demultiplexer called a data distributor?

a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
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c) The output will be distributed to one of the inputs

d) Single input gives single output
View Answer
Answer: a
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. For
one input, the demultiplexer gives several outputs. That is why it is called a data distributor.
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2. Most demultiplexers facilitate which type of conversion?

a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
View Answer
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines.
Demultiplexer converts single input into multiple outputs.
3. In 1-to-4 demultiplexer, how many select lines are required?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines.
Therefore, for 1:4 demultiplexer, 2 select lines are required.
4. In a multiplexer the output depends on its ____________

a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
View Answer
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. As
the select input changes, the output of the multiplexer varies according to that input.
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5. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ____________

a) Y0
b) Y1
c) Y2
d) Y3
View Answer
Answer: d
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6. How many select lines are required for a 1-to-8 demultiplexer?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: b
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. In this
case n = 3 since 23 = 8.
7. How many AND gates are required for a 1-to-8 multiplexer?

a) 2
b) 6
c) 8
d) 5
View Answer
Answer: c
Explanation: The number of AND gates required will be equal to the number of outputs in a
demultiplexer, which are 8.
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8. Which IC is used for the implementation of 1-to-16 DEMUX?

a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
View Answer
Answer: a
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input.
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To practice all areas of Digital Electronic Circuits, here is complete set of 1000+ Multiple Choice
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Digital Circuits Questions and Answers – Liquid

Crystal Displays
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Liquid
Crystal Displays”.
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1. The full form of LCD is ____________

a) Liquid Crystal Display
b) Liquid Crystalline Display
c) Logical Crystal Display
d) Logical Crystalline Display
View Answer
Answer: a
Explanation: The full form of LCD is “Liquid Crystal Display”. They provide thinner displays as compared
to Cathode Ray Tubes.
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2. The optical properties of liquid crystals depend on the direction of ___________

a) Air
b) Solid
c) Light
d) Water
View Answer
Answer: c
Explanation: The optical properties of liquid crystals depend on the direction of light travels through a
layer of the material.
3. By which properties, the orientation of molecules in a layer of liquid crystals can be changed?
a) Magnetic ield
b) Electric ield
c) Electromagnetic ield
d) Gallois ield
View Answer
Answer: b
Explanation: In LCD, the electric ield is induced by a small electric voltage applied across it; Due to which
the orientation of molecules in a layer of liquid crystals can be changed.
4. Electro-optical effect is produced in ___________

a) LED
b) LCD
c) OFC
d) OLED
View Answer
Answer: b
Explanation: An electric ield (induced by a small electric voltage) can change the orientation of
molecules in a layer of liquid crystal and thus affect its optical properties. Such a process is termed an
electro-optical effect, and it forms the basis for LCDs.
5. The direction of electric ield in an LCD is determined by ___________

a) the molecule’s chemical structure
b) Crystalline surface structure
c) Molecular Orbital Theory
d) Quantum Cellular Automata
View Answer
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Answer: a
Explanation: For LCDs, the change in optical properties results from orienting the molecular axes either
along or perpendicular to the applied electric ield, the preferred direction being determined by the
details of the molecule’s chemical structure.
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6. The irst LCDs became commercially available in ___________

a) 1950s
b) 1980s
c) 1960s
d) 1970s
View Answer
Answer: c
Explanation: The irst LCDs became commercially available in the late 1960s and were based on a light-
scattering effect known as the dynamic scattering mode.
7. LCDs operate from a voltage ranges from ___________

a) 3 to 15V
b) 10 to 15V
c) 10V
d) 5V
View Answer
Answer: a
Explanation: LCDs operate from a voltage ranges from 3 to 15V rms. They provide thinner displays as
compared to Cathode Ray Tubes.
8. LCDs operate from a frequency ranges from ___________

a) 10Hz to 60Hz
b) 50Hz to 70Hz
c) 30Hz to 60Hz
d) None of the Mentioned
View Answer
Answer: c
Explanation: LCDs operate from a frequency ranges from 30Hz to 60Hz. LCDs operate from a voltage
ranges from 3 to 15V rms. They provide thinner displays as compared to Cathode Ray Tubes.
9. In 7 segment display, how many LEDs are used?

a) 8
b) 7
c) 10
d) 9
View Answer
Answer: b
Explanation: There are 7 LEDs used in a 7 segment display. 7 segment displays are used for displaying
decimal numerals which are comparatively convenient to dot matrix displays.
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10. What is backplane in LCD?

a) The ac voltage applied between segment and a common element
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b) The dc voltage applied between segment and a common element

c) The amount of power consumed
d) For adjusting the intensity of the LCD
View Answer
Answer: a
Explanation: The ac voltage applied between segment and a common element is called the
backplane(bp). In which each segment is driven by an EX-OR gate.
Answers.

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Encoders
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“Encoders”.
1. How many inputs will a decimal-to-BCD encoder have?

a) 4
b) 8
c) 10
d) 16
View Answer
Answer: c
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to n output
lines, thus producing the binary equivalent of the input. Thus, a Decimal-to-bcd converter has decimal
values as inputs which range from 0-9. So, total 10 inputs are there in a decimal-to-BCD encoder.
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2. How many outputs will a decimal-to-BCD encoder have?

a) 4
b) 8
c) 12
d) 16
View Answer
Answer: a
lines, thus producing the binary equivalent of the input. Thus, a decimal to BCD encoder has 4 outputs.
3. How is an encoder different from a decoder?

a) The output of an encoder is a binary code for 1-of-N input
b) The output of a decoder is a binary code for 1-of-N input
c) The output of an encoder is a binary code for N-of-1 output
d) The output of a decoder is a binary code for N-of-1 output
View Answer
Answer: a
lines, thus producing the binary equivalent of the input. It performs the opposite operation of a decoder
which results in 2n outputs from n inputs. Thus, an encoder different from a decoder because of the
output of an encoder is a binary code for 1-of-N input.
4. If we record any music in any recorder, such types of process is called ___________
a) Multiplexing
b) Encoding
c) Decoding
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d) Demultiplexing
View Answer
Answer: b
Explanation: If we record any music in any recorder, it means that we are giving data to a recorder. So,
such process is called encoding. Getting back the music from the recorded data, is known as decoding.
5. Can an encoder be a transducer?

a) Yes
b) No
c) May or may not be
d) Both are not even related slightly
View Answer
Answer: a
Explanation: Of course, a transducer is a device which has the capability to emit data as well as to accept.
Transducer converts signal from one form of energy to another.
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6. How many OR gates are required for a Decimal-to-bcd encoder?

a) 2
b) 10
c) 3
d) 4
View Answer
Answer: d
Explanation: An encoder is a combinational circuit encoding the information of 2^n input lines to n
output lines, thus producing the binary equivalent of the input.
This is clear from the diagram that it requires 4 OR gates:
7. How many OR gates are required for an octal-to-binary encoder?

a) 3
b) 2
c) 8
d) 10
View Answer
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Answer: a
lines, thus producing the binary equivalent of the input. Thus, in octal to binary encoder there are 8
(=23) inputs, thus 3 output lines.
8. For 8-bit input encoder how many combinations are possible?

a) 8
b) 2^8
c) 4
d) 2^4
View Answer
Answer: b
lines, thus producing the binary equivalent of the input. There are 28 combinations are possible for an 8-
bit input encoder but out of which only 8 are used using 3 output lines. It is a disadvantage of encoder.
9. The discrepancy of 0 output due to all inputs being 0 or D0, being 0 is resolved by using additional
input known as ___________
a) Enable
b) Disable
c) Strobe
d) Clock
View Answer
Answer: a
Explanation: Such problems are resolved by using enable input, which behaves as active if it gets 0 as
input since it is an active-low pin.
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10. Can an encoder be called as multiplexer?

a) No
b) Yes
c) Sometimes
d) Never
View Answer
Answer: b
Explanation: A multiplexer or MUX is a combination circuit that contains more than one input line, one
output line and more than one selection line. Whereas, an encoder is also considered a type of
multiplexer but without a single output line and without any selection lines.
11. If two inputs are active on a priority encoder, which will be coded on the output?
a) The higher value
b) The lower value
c) Neither of the inputs
d) Both of the inputs
View Answer
Answer: a
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lines, thus producing the binary equivalent of the input. If two inputs are active on a priority encoder, the
input of higher value will be coded in the output.
Answers.
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Digital Circuits Questions and Answers – Parity

Generators/Checkers – 1
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« Prev Next »
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Parity
Generators/Checkers – 1”.
1. How many outputs are present in a BCD decoder?

a) 4
b) 5
c) 15
d) 10
View Answer
Answer: d
Explanation: A binary decoder is a combinational logic circuit which decodes binary information from n-
inputs to a maximum of 2n outputs. A BCD to Decimal decoder has 10 number of outputs because the
decimal digit’s range is from 0 to 9.
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2. Which digital system translates coded characters into a more useful form?
a) Encoder
b) Display
c) Counter
d) Decoder
View Answer
Answer: d
inputs to a maximum of 2n outputs. Decoder converts the coded characters into our required data form.
3. What control signals may be necessary to operate a 1-line-to-16 line decoder?

a) Flasher circuit control signal
b) A LOW on all gate enable inputs
c) Input from a hexadecimal counter
d) A HIGH on all gate enable circuits
View Answer
Answer: b
Explanation: A LOW on all gate enable inputs is necessary to operate a 1-line-to-16 line decoder because
enable pins are usually, active-low pins.
4. How many inputs are required for a 1-of-10 BCD decoder?

a) 4
b) 8
c) 10
d) 2
View Answer
Answer: a
inputs to a maximum of 2n outputs. Therefore, for a BCD to decimal decoder, No. of inputs = 4 such that
number of outputs is <= 2n.
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5. A BCD decoder will have how many rows in its truth table?
a) 10
b) 9
c) 8
d) 3
View Answer
Answer: a
inputs to a maximum of 2n outputs. Thus, BCD decoder will have 10 rows as it’s input ranges from 0 to 9.
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6. How many possible outputs would a decoder have with a 6-bit binary input?
a) 32
b) 64
c) 128
d) 16
View Answer
Answer: c
Explanation: The possible outputs would be: 2n = 64 (Since n = 6 here).
7. One way to convert BCD to binary using the hardware approach is:
a) By using MSI IC circuits
b) By using a keyboard encoder
c) By using an ALU
d) By using UART
View Answer
Answer: a
Explanation: One way to convert BCD to binary using the hardware approach is MSI (medium scale
integration) IC circuits.
8. How many inputs are required for a 1-of-16 decoder?

a) 2
b) 16
c) 8
d) 4
View Answer
Answer: d
inputs to a maximum of 2n outputs. Here, number of outputs = 16.
16 = 24 = 2n. Thus, number of inputs is 4.
9. A truth table with output columns numbered 0–15 may be for which type of decoder IC?
a) Hexadecimal 1-of-16
b) Dual octal outputs
c) Binary-to-hexadecimal
d) Hexadecimal-to-binary
View Answer
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Answer: a
inputs to a maximum of 2n outputs. A truth table with output columns numbered 0–15 may be for
Hexadecimal 1-of-16. Because, hexadecimal occupies less space in a system.
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10. How can the active condition (HIGH or LOW) or the decoder output be determined from the logic
symbol?
a) A bubble indicates active-HIGH
b) A bubble indicates active-LOW
c) A triangle indicates active-HIGH
d) A triangle indicates active-LOW
View Answer
Answer: b
Explanation: A bubble indicates active-LOW in a decoder always. Enable pin of the decoder is usually
active-LOW and is triggered on input being at 0.
Answers.

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Digital Circuits Questions and Answers – Parity

Generators/Checkers – 2
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This set of Digital Electronic/Circuits online test focuses on “Parity Generators/Checkers – 2”.
1. Which error detection method uses one’s complement arithmetic?

a) Simple parity check
b) Two-dimensional parity check
c) CRC
d) Checksum
View Answer
Answer: d
Explanation: A checksum is an error detection method used for the purpose of detecting errors that may
have been incorporated during transmission. The checksum can be generated simply by adding bits.
Hence, one’s complement arithmetic uses checksum.
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2. Which error detection method consists of just one redundant bit per data unit?
c) CRC
d) Checksum
View Answer
Answer: a
Explanation: A parity checker is an error detection method used for the purpose of detecting errors that
may have been incorporated during transmission. Simple parity check method consists of just one
redundant bit per data unit. It is again classi ied as even parity and odd parity.
3. How many types of parity bits are found?

a) 2
b) 3
c) 4
d) 1
View Answer
Answer: a
Explanation: There are two types of parity bits, namely even parity and odd parity. In even parity, a 1 bit
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is added in order to make a group of data bits have even number of 1s. While, in odd parity, a 1 bit is
added in order to make a group of data bits have odd number of 1s.
4. What is a parity bit?

a) An error detection is achieved by adding an extra bit
b) After addition, the carry is found
c) Bit generated during data transmission
d) After addition, the total number of bits
View Answer
Answer: a
Explanation: A simple form of error detection is achieved by adding an extra bit to the transmitted word.
The additional bit is known as parity bits.
5. The BCD number 101011 has _______ priority.

a) Even
b) Odd
c) Both even and odd
d) Unde ined
View Answer
Answer: a
Explanation: The given BCD number 101011 has even priority because it has even number of 1’s (i.e. 4).
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6. Which error detection method involves polynomials?

b) CRC
c) Two-dimensional parity check
d) Checksum
View Answer
Answer: b
Explanation: Cyclic Redundancy Check(CRC) involves parity check polynomials. In the even parity case of
CRC, the 1-bit is generated by checking the polynomial x+1.
7. The odd parity output of decimal number 9 is ___________

a) 0
b) 1
c) 1001
d) 0011
View Answer
Answer: b
Explanation: The odd parity output of decimal number 9 is 1 because the BCD number for 9 is 1001 and
it has even number of 1’s.
8. If odd parity is used for ASCII error detection, the number of 0s per 8-bit symbol is _______
a) Indeterminate
b) 42
c) Even
d) Odd
View Answer
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Answer: a
Explanation: Odd parity bit is 1 when the group of data bits consist of even number of 1s. So to make the
group of data bits have odd number of 1s, 1 extra bit is added. If odd parity is used for ASCII error
detection, the number of 0s per 8-bit symbol is indeterminate because it is applicable only for 6-bit
symbol.
9. Which error detection method can detect a single-bit error?

c) CRC
d) Checksum
View Answer
Answer: b
Explanation: A single-bit error can be detected by using two-dimensional parity check method. Since, it
converts the 4-bit number into 8-bit and count the number of one’s.
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10. Which gates are ideal for checking the parity bits?
a) AND
b) NAND
c) EX-OR
d) EX-NOR
View Answer
Answer: c
Explanation: Exclusive-OR gates are ideal for checking the parity of a binary number because they
produce an output when the input has an odd number of 1’s. Therefore, an even-parity input to an EX-
OR gate produces a low output, while an odd parity input produces a high output. While, in case of AND,
it produces high output when all inputs are 1 else low. Whereas, NAND, does the opposite, by producing
low output when all inputs are 1 else high.
To practice all areas of Digital Electronic Circuits for online test, here is complete set of 1000+ Multiple

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3. C# Programming Examples on Threads
4. Java Programming Examples on Classes
5. Java Programming Examples on Java.Lang
8. C Programming Examples on Computational Geometry Problems & Algorithms
9. Java Programming Examples on Multithreading
10. C++ Programming Examples on Computational Geometry Problems & Algorithms
13. Java Programming Examples on Computational Geometry Problems & Algorithms
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Digital Circuits Questions and Answers – Code

Converters
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Code
Converters”.
1. A code converter is a logic circuit that _____________

a) Inverts the given input
b) Converts into decimal number
c) Converts data of one type into another type
d) Converts to octal
View Answer
Answer: c
Explanation: A code converter is a logic circuit that changes data presented in one type of binary code to
another type of binary code.
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2. Use the weighting factors to convert the following BCD numbers to binary ___________
0101 0011 & 0010 0110 1000
a) 01010011 001001101000
b) 11010100 100001100000
c) 110101 100001100
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d) 101011 001100001
View Answer
Answer: c
Explanation: Firstly, convert every 4 sets of binary to decimal from the given: 0101=5, 0011=3. Then
convert 53 to binary, which will give 110101. Again, do the same with the next 4 set of binary digits.
3. The primary use for Gray code is ___________

a) Coded representation of a shaft’s mechanical position
b) Turning on/off software switches
c) To represent the correct ASCII code to indicate the angular position of a shaft on rotating machinery
d) To convert the angular position of a shaft on rotating machinery into hexadecimal code
View Answer
Answer: a
Explanation: Gray code is useful because only one bit changes at a time, which is implemented easily in
Coded representation of a shaft’s mechanical position. In Gray Code, every sequence of successive bits
differs by 1 bit only.
4. Code is a symbolic representation of ___________

a) Discrete information
b) Continuous information
c) Decimal information into binary
d) Binary information into decimal
View Answer
Answer: a
Explanation: Code is a symbolic representation of discrete information. Codes can be anything like
numbers, letter or words, written in terms of group of symbols.
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5. One way to convert BCD to binary using the hardware approach is ___________
a) With MSI IC circuits
b) With a keyboard encoder
c) With an ALU
d) UART
View Answer
Answer: a
Explanation: One way to convert BCD to binary using the hardware approach is MSI IC (i.e. medium scale
integration) circuits.
6. Why is the Gray code more practical to use when coding the position of a rotating shaft?
a) All digits change between counts
b) Two digits change between counts
c) Only one digit changes between counts
d) Alternate digit changes between counts
View Answer
Answer: c
Explanation: The Gray code is more practical to use when coding the position of a rotating shaft because
only one digit changes between counts that is re lected to the next count.
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7. Re lected binary code is also known as ___________

a) BCD code
b) Binary code
c) ASCII code
d) Gray Code
View Answer
Answer: d
Explanation: The re lected binary code is also known as gray code because one digit re lected to the next
bit. In Gray Code, every sequence of successive bits differs by 1 bit only.
8. Why do we use gray codes?

a) To count the no of bits changes
b) To rotate a shaft
c) Error correction
d) Error Detetction
View Answer
Answer: c
Explanation: Today, Gray codes are widely used to facilitate error correction in digital communications
such as digital terrestrial television and some cable TV systems.
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9. Earlier, re lected binary codes were applied to ___________

a) Binary addition
b) 2’s complement
c) Mathematical puzzles
d) Binary multiplication
View Answer
Answer: c
Explanation: The re lected binary code is also known as gray code because one digit re lected to the next
bit. In Gray Code, every sequence of successive bits differs by 1 bit only. Re lected binary codes were
applied to mathematical puzzles before they became known to engineers.
10. The binary representation of BCD number 00101001 (decimal 29) is ___________
a) 0011101
b) 0110101
c) 1101001
d) 0101011
View Answer
Answer: a
Explanation: The given BCD number 00101001 has three 1s. So, it can be rewritten as 0000001-1,
0001000-8, 0010100-20 and after addition, we get 0011101 as output.
11. Convert binary number into gray code: 100101.

a) 101101
b) 001110
c) 110111
d) 111001
View Answer
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Answer: c
Explanation: : Conversion from Binary To Gray Code:
1 (XOR) 0 (XOR) 0 (XOR) 1 (XOR) 0 (XOR) 1
↓ ↓ ↓ ↓ ↓
1 1 0 1 1 1

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Answers.

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Magnitude Comparator
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“Magnitude Comparator”.
1. All the comparisons made by comparator is done using ____________

a) 1 circuit
b) 2 circuits
c) 3 circuits
d) 4 circuits
View Answer
Answer: a
Explanation: A comparator is a combinational circuit that takes two numbers as input in binary form and
results whether one input is greater, lesser or equal to the other input. Because, all the input is
compared to each other, therefore it is possible only by using 1 circuit.
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2. One that is not the outcome of magnitude comparator is ____________

a) a > b
b) a – b
c) a < b
d) a = b
View Answer
Answer: b
results whether one input is greater, lesser or equal to the other input. In a digital comparator, only 3
outputs are possible (i.e. A = B, A > B, A < B). So, a – b is incorrect option.
3. If two numbers are not equal then binary variable will be ____________
a) 0
b) 1
c) A
d) B
View Answer
Answer: a
results whether one input is greater, lesser or equal to the other input. In a digital comparator, only 3
outputs are possible (i.e. A = B, A >B, A < B). Other than this, the output will be 0.
4. How many inputs are required for a digital comparator?

a) 1
b) 2
c) 3
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d) 4
View Answer
Answer: a
results whether one input is greater, lesser or equal to the other input. Thus, there are two inputs
required for a digital comparator (i.e. A & B).
5. In a comparator, if we get input as A>B then the output will be ____________

a) 1
b) 0
c) A
d) B
View Answer
Answer: a
results whether one input is greater, lesser or equal to the other input. If A > B, it means that it satis ies
one of the condition among three. Hence the output will be 1.
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6. Which one is a basic comparator?

a) XOR
b) XNOR
c) AND
d) NAND
View Answer
Answer: a
Explanation: Generally, an XNOR outputs high for even number of 1s or all 0s and outputs low for
otherwise. Thus, an XNOR gate is a basic comparator, because its output is “1” only if its two input bits
are equal.
7. Comparators are used in ____________

a) Memory
b) CPU
c) Motherboard
d) Hard drive
View Answer
Answer: b
Explanation: Comparators are used in central processing unit (CPUs). Because all the arithmetic and
logical operations are performed in the ALU(Arithmetic Logic Unit) part of the CPU.
8. A circuit that compares two numbers and determine their magnitude is called ____________
a) Height comparator
b) Size comparator
c) Comparator
d) Magnitude comparator
View Answer
Answer: d
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results whether one input is greater, lesser or equal to the other input. A circuit that compares two
numbers and determine their magnitude is called magnitude comparator.
9. A procedure that speci ies inite set of steps is called ____________

a) Algorithm
b) Flow chart
c) Chart
d) Venn diagram
View Answer
Answer: a
Explanation: A procedure that speci ies inite set of steps is called algorithm, While a lowchart is a
pictorial representation of the algorithm.
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10. How many types of digital comparators are?

a) 1
b) 2
c) 3
d) 4
View Answer
Answer: b
Explanation: There are two main types of Digital Comparator available and these are: Identity
Comparator & Magnitude Comparator. Identity Comparator checks only the equality of the inputs and
thus has one output terminal. While Magnitude Comparator checks for greater than, less than as well as
equality of the inputs, and thus has 3 output terminals.
11. An identify comparator is de ined as a digital comparator which has ____________

a) Only one output terminal
b) Two output terminals
c) Three output terminals
d) No output terminal
View Answer
Answer: a
Explanation: An Identity Comparator is a digital comparator that has only one output terminal for when
A = B either “HIGH” A = B = 1 or “LOW” A = B = 0.
12. A magnitude comparator is de ined as a digital comparator which has ____________

a) Only one output terminal
b) Two output terminals
c) Three output terminals
d) No output terminal
View Answer
Answer: c
Explanation: A Magnitude Comparator is a digital comparator which has three output terminals, one
each for equality, A = B greater than, A > B and less than A < B.
13. The purpose of a Digital Comparator is ____________

a) To convert analog input into digital
b) To create different outputs
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c) To add a set of different numbers

d) To compare a set of variables or unknown numbers
View Answer
Answer: d
results whether one input is greater, lesser or equal to the other input. The purpose of a Digital
Comparator is to compare a set of variables or unknown numbers, for example A (A1, A2, A3, …. An, etc)
against that of a constant or unknown value such as B (B1, B2, B3, …. Bn, etc) and produce an output
condition or lag depending upon the result of the comparison.
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14. TTL 74LS85 is a _____________

a) 1-bit digital comparator
b) 4-bit magnitude comparator
c) 8-bit magnitude comparator
d) 8-bit word comparator
View Answer
Answer: b
Explanation: TTL 74LS85 is a 4-bit magnitude comparator.
Answers.

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Digital Circuits Questions and Answers – Latches

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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Latches”.
1. A latch is an example of a ___________

a) Monostable multivibrator
b) Astable multivibrator
c) Bistable multivibrator
d) 555 timer
View Answer
Answer: c
Explanation: A latch is an example of a bistable multivibrator. A Bistable multivibrator is one in which the
circuit is stable in either of two states. It can be lipped from one state to the other state and vice-versa.
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2. Latch is a device with ___________

a) One stable state
b) Two stable state
c) Three stable state
d) In inite stable states
View Answer
Answer: b
Explanation: Since, a latch works on the principal of bistable multivibrator. A Bistable multivibrator is one
in which the circuit is stable in either of two states. It can be lipped from one state to the other state and
vice-versa. So a latch has two stable states.
3. Why latches are called a memory devices?

a) It has capability to stare 8 bits of data
b) It has internal memory of 4 bit
c) It can store one bit of data
d) It can store in inite amount of data
View Answer
Answer: c
Explanation: Latches can be memory devices, and can store one bit of data for as long as the device is
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powered. Once device is turned off, the memory gets refreshed.
4. Two stable states of latches are ___________

a) Astable & Monostable
b) Low input & high output
c) High output & low output
d) Low output & high input
View Answer
Answer: c
Explanation: A latch has two stable states, following the principle of Bistable Multivibrator. There are two
stable states of latches and these states are high-output and low-output.
5. How many types of latches are ___________

a) 4
b) 3
c) 2
d) 5
View Answer
Answer: a
Explanation: There are four types of latches: SR latch, D latch, JK latch and T latch. D latch is a modi ied
form of SR latch whereas, T latch is an advanced form of JK latch.
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6. The full form of SR is ___________

a) System rated
b) Set reset
c) Set ready
d) Set Rated
View Answer
Answer: b
Explanation: The full form of SR is set/reset. It is a type of latch having two stable states.
7. The SR latch consists of ___________

a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs
View Answer
Answer: b
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states.
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The diagram of SR latch is shown below:
8. The outputs of SR latch are ___________

a) x and y
b) a and b
c) s and r
d) q and q’
View Answer
Answer: d
The inputs of SR latch are s and r while outputs are q and q’. It is clear from the diagram:
9. The NAND latch works when both inputs are ___________

a) 1
b) 0
c) Inverted
d) Don’t cares
View Answer
Answer: a
Explanation: The NAND latch works when both inputs are 1. Since, both of the inputs are inverted in a
NAND latch.
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10. The irst step of analysis procedure of SR latch is to ___________

a) label inputs
b) label outputs
c) label states
d) label tables
View Answer
Answer: b
Explanation: All lip lops have at least one output labeled Q (i.e. inverted). This is so because the lip
lops have inverting gates inside them, hence in order to have both Q and Q complement available, we
have atleast one output labelled.
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11. The inputs of SR latch are ___________

a) x and y
b) a and b
c) s and r
d) j and k
View Answer
Answer: c
The inputs of SR latch are s and r while outputs are q and q’. It is clear from the diagram:
12. When a high is applied to the Set line of an SR latch, then ___________
a) Q output goes high
b) Q’ output goes high
c) Q output goes low
d) Both Q and Q’ go high
View Answer
Answer: a
Explanation: S input of a SR latch is directly connected to the output Q. So, when a high is applied Q
output goes high and Q’ low.
13. When both inputs of SR latches are low, the latch ___________
a) Q output goes high
b) Q’ output goes high
c) It remains in its previously set or reset state
d) it goes to its next set or reset state
View Answer
Answer: c
Explanation: When both inputs of SR latches are low, the latch remains in it’s present state. There is no
change in the output.
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14. When both inputs of SR latches are high, the latch goes ___________
a) Unstable
b) Stable
c) Metastable
d) Bistable
View Answer
Answer: c
Explanation: When both gates are identical and this is “metastable”, and the device will be in an
unde ined state for an inde inite period.
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Answers.

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Digital Circuits Questions and Answers – Flip

Flops – 1
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Flip
Flops – 1”.
1. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which
con iguration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
View Answer
Answer: d
Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs of a latch are
directly connected to the other’s output. Such types of structure is called cross coupling and due to
which latches remain in the latched condition.
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2. One example of the use of an S-R lip- lop is as ___________

a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
View Answer
Answer: c
Explanation: The SR lip- lop is very effective in removing the effects of switch bounce, which is the
unwanted noise caused during the switching of electronic devices.
3. The truth table for an S-R lip- lop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: c
Explanation: The SR lip- lop actually has three inputs, Set, Reset and its current state. The Invalid or
Unde ined State occurs at both S and R being at 1.
4. When both inputs of a J-K lip- lop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle
View Answer
Answer: c
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0 and K=1.
After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle complete). The J & K lip-
lop has 4 stable states: Latch, Reset, Set and Toggle.
5. Which of the following is correct for a gated D-type lip- lop?

a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
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b) The output complement follows the input when enabled

c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
View Answer
Answer: a
Explanation: In D lip lop, when the clock is high then the output depends on the input otherwise
reminds previous output. In a state of clock high, when D is high the output Q also high, if D is ‘0’ then
output is also zero. Like SR lip- lop, the D- lip- lop also have an invalid state at both inputs being 1.
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6. A basic S-R lip- lop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
View Answer
Answer: c
Explanation: The basic S-R lip- lop can be constructed by cross coupling of NOR or NAND gates. Cross
coupling means the output of second gate is fed to the input of irst gate and vice-versa.
7. The logic circuits whose outputs at any instant of time depends only on the present input but also on
the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip- lops
View Answer
Answer: b
Explanation: In sequential circuits, the output signals are fed back to the input side. So, The circuits
whose outputs at any instant of time depends only on the present input but also on the past outputs are
called sequential circuits. Unlike sequential circuits, if output depends only on the present state, then it’s
known as combinational circuits.
8. Whose operations are more faster among the following?

a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip- lops
View Answer
Answer: a
Explanation: Combinational circuits are often faster than sequential circuits. Since, the combinational
circuits do not require memory elements whereas the sequential circuits need memory devices to
perform their operations in sequence. Latches and Flip- lops come under sequential circuits.
9. How many types of sequential circuits are?

a) 2
b) 3
c) 4
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d) 5
View Answer
Answer: a
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii)
asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the presence of a clock
signal, whereas, Asynchronous Sequential Circuits function in the absence of a clock signal.
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10. The sequential circuit is also called ___________

a) Flip- lop
b) Latch
c) Strobe
d) Adder
View Answer
Answer: b
Explanation: The sequential circuit is also called a latch because both are a memory cell, which are
capable of storing one bit of information.
11. The basic latch consists of ___________

a) Two inverters
b) Two comparators
c) Two ampli iers
d) Two adders
View Answer
Answer: a
Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q = 0 then the
second output Q’ = 1 and vice versa.
12. In S-R lip- lop, if Q = 0 the output is said to be ___________

a) Set
b) Reset
c) Previous state
d) Current state
View Answer
Answer: b
Explanation: In S-R lip- lop, if Q = 0 the output is said to be reset and set for Q = 1.
13. The output of latches will remain in set/reset untill ___________

a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) The pulse is edge-triggered
View Answer
Answer: a
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to change the
state.
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14. What is a trigger pulse?

a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation
View Answer
Answer: a
Explanation: Trigger pulse is de ined as a pulse that starts a cycle of operation.
15. The circuits of NOR based S-R latch classi ied as asynchronous sequential circuits, why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Because of inverted outputs & triggering functionality
View Answer
Answer: c
Explanation: The cross-coupled connections from the output of one gate to the input of the other gate
constitute a feedback path. For this reason, the circuits of NOR based S-R latch classi ied as
asynchronous sequential circuits. Moreover, they are referred to as asynchronous because they function
in the absence of a clock pulse.
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17. Digital Circuits Questions and Answers – Counters
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Flops – 2
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This set of Digital Electronic/Circuits online quiz focuses on “Flip Flops – 2”.
1. What is an ambiguous condition in a NAND based S’-R’ latch?

a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
View Answer
Answer: d
Explanation: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’) goes HIGH and
this condition is called as ambiguous/forbidden state. This state is also known as an Invalid state as the
system goes into an unexpected situation.
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2. In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is ____________
a) No change
b) Set
c) Reset
d) Forbidden
View Answer
Answer: a
Explanation: In a NAND based S’-R, latch if S’=1 & R’=1 then there is no any change in the state. It
remains in its prior state. This state is used for the storage of data.
3. A NAND based S’-R’ latch can be converted into S-R latch by placing ____________
a) A D latch at each of its input
b) An inverter at each of its input
c) It can never be converted
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d) Both a D latch and an inverter at its input

View Answer
Answer: d
Explanation: A NAND based S’-R’ latch can be converted into S-R latch by placing either a D latch or an
inverter at its input as it’s operations will be complementary.
4. One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is ____________
a) The inputs of NOR latch are 0 but 1 for NAND latch
b) The inputs of NOR latch are 1 but 0 for NAND latch
c) The output of NAND latch becomes set if S’=0 & R’=1 and vice versa for NOR latch
d) The output of NOR latch is 1 but 0 for NAND latch
View Answer
Answer: a
Explanation: Due to inverted input of NAND based S’-R’ latch, the inputs of NOR latch are 0 but 1 for
NAND latch.
5. The characteristic equation of S-R latch is ____________

a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R
View Answer
Answer: a
Explanation: A characteristic equation is needed when a speci ic gate requires a speci ic output in order
to satisfy the truth table. The characteristic equation of S-R latch is Q(n+1) = (S + Q(n))R’.
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6. The difference between a lip- lop & latch is ____________

a) Both are same
b) Flip- lop consist of an extra output
c) Latches has one input but lip- lop has two
d) Latch has two inputs but lip- lop has one
View Answer
Answer: c
Explanation: Flip- lop is a modi ied version of latch. To determine the changes in states, an additional
control input is provided to the latch.
7. How many types of lip- lops are?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: c
Explanation: There are 4 types of lip- lops, viz., S-R, J-K, D, and T. D lip- lop is an advanced version of S-
R lip- lop, while T lip- lop is an advanced version of J-K lip- lop.
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8. The S-R lip lop consist of ____________

a) 4 AND gates
b) Two additional AND gates
c) An additional clock input
d) 3 AND gates
View Answer
Answer: b
Explanation: The S-R lip lop consist of two additional AND gates at the S and R inputs of S-R latch.
9. What is one disadvantage of an S-R lip- lop?

a) It has no Enable input
b) It has a RACE condition
c) It has no clock input
d) Invalid State
View Answer
Answer: d
Explanation: The main drawback of s-r lip lop is invalid output when both the inputs are high, which is
referred to as Invalid State.
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10. One example of the use of an S-R lip- lop is as ____________

a) Racer
b) Stable oscillator
c) Binary storage register
d) Transition pulse generator
View Answer
Answer: c
Explanation: S-R refers to set-reset. So, it is used to store two values 0 and 1. Hence, it is referred to as
binary storage element. It functions as memory storage during the No Change State.
11. When is a lip- lop said to be transparent?

a) When the Q output is opposite the input
b) When the Q output follows the input
c) When you can see through the IC packaging
d) When the Q output is complementary of the input
View Answer
Answer: b
Explanation: Flip- lop have the property of responding immediately to the changes in its inputs. This
property is called transparency.
12. On a positive edge-triggered S-R lip- lop, the outputs re lect the input condition when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
View Answer
Answer: c
Explanation: Edge triggered device will follow when there is transition. It is a positive edge triggered
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when transition takes place from low to high, while, it is negative edge triggered when the transition
takes place from high to low.
13. What is the hold condition of a lip- lop?

a) Both S and R inputs activated
b) No active S or R input
c) Only S is active
d) Only R is active
View Answer
Answer: b
Explanation: The hold condition in a lip- lop is obtained when both of the inputs are LOW. It is the No
Change State or Memory Storage state if a lip- lop.
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14. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to
0, the latch will be ________
a) SET
b) RESET
c) Clear
d) Invalid
View Answer
Answer: b
Explanation: If S=0, R=1, the lip lop is at reset condition. Then at S=0, R=0, there is no change. So, it
remains in reset. If S=1, R=0, the lip lop is at the set condition.
15. The circuit that is primarily responsible for certain lip- lops to be designated as edge-triggered is the
_____________
a) Edge-detection circuit
b) NOR latch
c) NAND latch
d) Pulse-steering circuit
View Answer
Answer: a
Explanation: The circuit that is primarily responsible for certain lip- lops to be designated as edge-
triggered is the edge-detection circuit.
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Flops – 3
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This set of Digital Electronic/Circuits question bank focuses on “Flip Flops – 3”.
1. Which circuit is generated from D lip- lop due to addition of an inverter by causing reduction in the
number of inputs?
a) Gated JK-latch
b) Gated SR-latch
c) Gated T-latch
d) Gated D-latch
View Answer
Answer: d
Explanation: Since, both inputs of the D lip- lop are connected through an inverter. And this causes
reduction in the number of inputs.
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2. The characteristic of J-K lip- lop is similar to _____________

a) S-R lip- lop
b) D lip- lop
c) T lip- lop
d) Gated T lip- lop
View Answer
Answer: a
Explanation: In an S-R lip- lop, S refers to “SET” whereas R refers to “RESET”. The same behaviour is
shown by J-K lip- lop.
3. A J-K lip- lop can be obtained from the clocked S-R lip- lop by augmenting ___________
a) Two AND gates
b) Two NAND gates
c) Two NOT gates
d) Two OR gates
View Answer
Answer: a
Explanation: A J-K lip- lop can be obtained from the clocked S-R lip- lop by augmenting two AND gates.
4. How is a J-K lip- lop made to toggle?

a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
View Answer
Answer: d
Explanation: When j=k=1 then the race condition is occurs that means both output wants to be HIGH.
Hence, there is toggle condition is occurs, where 0 becomes 1 and 1 becomes 0. That is device is either
set or reset.
5. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called
___________
a) Parity error checking
b) Ones catching
c) Digital discrimination
d) Digital iltering
View Answer
Answer: b
Explanation: Ones catching means that the input transitioned to a 1 and back very brie ly
(unintentionally due to a glitch), but the lip- lop responded and latched it in anyway, i.e., it caught the 1.
Similarly for 0’s catching.
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6. In J-K lip- lop, “no change” condition appears when ___________

a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0
View Answer
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Answer: d
Explanation: If J = 0, K = 0, the output remains unchanged. This is the memory storing state.
7. A J-K lip- lop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________
a) Constantly LOW
b) Constantly HIGH
c) A 20 kHz square wave
d) A 10 kHz square wave
View Answer
Answer: d
Explanation: The lip lop is sensitive only to the positive or negative edge of the clock pulse. So, the lip-
lop toggles whenever the clock is falling/rising at edge. This triggering of lip- lop during the transition
state, is known as Edge-triggered lip- lop. Thus, the output curve has a time period twice that of the
clock. Frequency is inversely related to time period and hence frequency gets halved.
8. What is the signi icance of the J and K terminals on the J-K lip- lop?
a) There is no known signi icance in their designations
b) The J represents “jump,” which is how the Q output reacts whenever the clock goes high and the J
input is also HIGH
c) The letters were chosen in honour of Jack Kilby, the inventory of the integrated circuit
d) All of the other letters of the alphabet are already in use
View Answer
Answer: c
Explanation: The letters J & K were chosen in honour of Jack Kilby, the inventory of the integrated circuit.
In J&K lip- lops, the invalid state problem is resolved, thus leading to the toggling of states.
9. On a J-K lip- lop, when is the lip- lop in a hold condition?

a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
View Answer
Answer: a
Explanation: At J=0 k=0 output continues to be in the same state. This is the memory storing state.
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10. Two J-K lip- lops with their J-K inputs tied HIGH are cascaded to be used as counters. After four
input clock pulses, the binary count is ________
a) 00
b) 11
c) 01
d) 10
View Answer
Answer: a
Explanation: Every O/P repeats after its mod. Here mod is 4 (because 2 lip- lops are used. So mod = 22
= 4). So after 4 clock pulses the O/P repeats i.e. 00.
11. Four J-K lip- lops are cascaded with their J-K inputs tied HIGH. If the input frequency ( in) to the irst
lip- lop is 32 kHz, the output frequency (fout) is ________
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a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz
View Answer
Answer: b
Explanation: 32/2=16:- irst lip- lop, 16/2=8:- second lip- lop, 8/2=4:- third lip- lop, 4/2=2:- fourth lip-
lop. Since the output frequency is determined on basis of the 4th lip- lop.
12. Determine the output frequency for a frequency division circuit that contains 12 lip- lops with an
input clock frequency of 20.48 MHz.
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz
View Answer
Answer: b
Explanation: 12 lip lops = 212 = 4096
Input Clock frequency = 20.48*106 = 20480000
Output Clock frequency = 20480000/4096 = 5000 i.e., 5 kHz.
13. How many lip- lops are in the 7475 IC?

a) 2
b) 1
c) 4
d) 8
View Answer
Answer: c
Explanation: There are 4 lip- lops used in 7475 IC and those are D lip- lops only.
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Digital Circuits Questions and Answers – D Flip

Flop
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “D Flip
Flop”.
1. In D lip- lop, D stands for _____________

a) Distant
b) Data
c) Desired
d) Delay
View Answer
Answer: b
Explanation: The D of D- lip- lop stands for “data”. It stores the value on the data line.
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2. The D lip- lop has _______ input.

a) 1
b) 2
c) 3
d) 4
View Answer
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Answer: a
Explanation: The D lip- lop has one input. The D of D- lip- lop stands for “data”. It stores the value on the
data line.
3. The D lip- lop has ______ output/outputs.

a) 2
b) 3
c) 4
d) 1
View Answer
Answer: a
Explanation: The D lip- lop has two outputs: Q and Q complement. The D lip- lop has one input. The D
of D- lip- lop stands for “data”. It stores the value on the data line.
4. A D lip- lop can be constructed from an ______ lip- lop.

a) S-R
b) J-K
c) T
d) S-K
View Answer
Answer: a
Explanation: A D lip- lop can be constructed from an S-R lip- lop by inserting an inverter between S and
R and assigning the symbol D to the S input.
5. In D lip- lop, if clock input is LOW, the D input ___________

a) Has no effect
b) Goes high
c) Goes low
d) Has effect
View Answer
Answer: a
Explanation: In D lip- lop, if clock input is LOW, the D input has no effect, since the set and reset inputs
of the NAND lip- lop are kept HIGH.
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6. In D lip- lop, if clock input is HIGH & D=1, then output is ___________
a) 0
b) 1
c) Forbidden
d) Toggle
View Answer
Answer: a
Explanation: If clock input is HIGH & D=1, then output is 0. It can be observed from this diagram:
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7. Which statement describes the BEST operation of a negative-edge-triggered D lip- lop?

a) The logic level at the D input is transferred to Q on NGT of CLK
b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH
c) The Q output is ALWAYS identical to the D input when CLK = PGT
d) The Q output is ALWAYS identical to the D input
View Answer
Answer: a
Explanation: By the truth table of D lip lop, we can observe that Q always depends on D. Hence, for
every negative trigger pulse, the logic at input D is shifted to Output Q.
8. Which of the following is correct for a gated D lip- lop?

a) The output toggles if one of the inputs is held HIGH
b) Only one of the inputs can be HIGH at a time
c) The output complement follows the input when enabled
d) Q output follows the input D when the enable is HIGH
View Answer
Answer: d
Explanation: If clock is high then the D lip- lop operate and we know that input is equals to output in
case of D lip- lop. It stores the value on the data line.
9. With regard to a D latch ________

a) The Q output follows the D input when EN is LOW
b) The Q output is opposite the D input when EN is LOW
c) The Q output follows the D input when EN is HIGH
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d) The Q output is HIGH regardless of EN’s input state

View Answer
Answer: c
Explanation: Latch is nothing but lip lop which holds the o/p or i/p state. And in D lip- lop output
follows the input. It stores the value on the data line.
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10. Which of the following is correct for a D latch?

a) The output toggles if one of the inputs is held HIGH
b) Q output follows the input D when the enable is HIGH
c) Only one of the inputs can be HIGH at a time
d) The output complement follows the input when enabled
View Answer
Answer: b
Explanation: If the clock is HIGH then the D lip- lop operates and we know that input equals to output in
case of D lip lop. It stores the value on the data line.
11. Which of the following describes the operation of a positive edge-triggered D lip- lop?
a) If both inputs are HIGH, the output will toggle
b) The output will follow the input on the leading edge of the clock
c) When both inputs are LOW, an invalid state exists
d) The input is toggled into the lip- lop on the leading edge of the clock and is passed to the output on
the trailing edge of the clock
View Answer
Answer: b
Explanation: Edge-triggered lip- lop means the device will change state during the rising or falling edge
of the clock pulse. The main phenomenon of the D lip- lop is that the o/p will follow the i/p when the
enable pin is HIGH.
12. A D lip- lop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause
it to change states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1
View Answer
Answer: d
Explanation: PGT refers to Positive Going Transition and NGT refers to negative Going Transition. Earlier,
the DFF is in a clear state (output is 0). So, if D = 1 then in the next stage output will be 1 and hence the
stage will be changed.
13. A positive edge-triggered D lip- lop will store a 1 when ________

a) The D input is HIGH and the clock transitions from HIGH to LOW
b) The D input is HIGH and the clock transitions from LOW to HIGH
c) The D input is HIGH and the clock is LOW
d) The D input is HIGH and the clock is HIGH
View Answer
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Answer: b
Explanation: A positive edge-triggered D lip- lop will store a 1 when the D input is HIGH and the clock
transitions from LOW to HIGH. While a negative edge-triggered D lip- lop will store a 0 when the D input
is HIGH and the clock transitions from HIGH to LOW.
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14. Why do the D lip- lops receive its designation or nomenclature as ‘Data Flip- lops’?
a) Due to its capability to receive data from lip- lop
b) Due to its capability to store data in lip- lop
c) Due to its capability to transfer the data into lip- lop
d) Due to erasing the data from the lip- lop
View Answer
Answer: c
Explanation: Due to its capability to transfer the data into lip- lop. D- lip- lops stores the value on the
data line.
15. The characteristic equation of D- lip- lop implies that ___________

a) The next state is dependent on previous state
b) The next state is dependent on present state
c) The next state is independent of previous state
d) The next state is independent of present state
View Answer
Answer: d
to satisfy the truth table. The characteristic equation of D lip- lop is given by Q(n+1) = D; which indicates
that the next state is independent of the present state.
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Triggering of Flip Flops
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“Triggering of Flip Flops”.
1. The characteristic equation of J-K lip- lop is ______________

a) Q(n+1)=JQ(n)+K’Q(n)
b) Q(n+1)=J’Q(n)+KQ'(n)
c) Q(n+1)=JQ'(n)+KQ(n)
d) Q(n+1)=JQ'(n)+K’Q(n)
View Answer
Answer: d
to satisfy the truth table. The characteristic equation of J-K lip- lop is given by: Q(n+1)=JQ'(n)+K’Q(n).
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2. In a J-K lip- lop, if J=K the resulting lip- lop is referred to as _____________
a) D lip- lop
b) S-R lip- lop
c) T lip- lop
d) S-K lip- lop
View Answer
Answer: c
Explanation: In J-K lip- lop, if both the inputs are same then it behaves like T lip- lop.
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3. In J-K lip- lop, the function K=J is used to realize _____________

a) D lip- lop
b) S-R lip- lop
c) T lip- lop
d) S-K lip- lop
View Answer
Answer: c
Explanation: T lip- lop allows the same inputs. So, in J-K lip- lop J=K then it will work as T lip- lop.
4. The only difference between a combinational circuit and a lip- lop is that _____________
a) The lip- lop requires previous state
b) The lip- lop requires next state
c) The lip- lop requires a clock pulse
d) The lip- lop depends on the past as well as present states
View Answer
Answer: c
Explanation: Both lip- lop and latches are memory elements with clock/control inputs. They depend on
the past as well as present states. Whereas, in case of combinational circuits, they only depend on the
present state.
5. How many stable states a combinational circuits have?

a) 3
b) 4
c) 2
d) 5
View Answer
Answer: c
Explanation: The two stable states of combinational circuits are 1 and 0. Whereas, in lip- lops there is an
additional state known as Forbidden State.
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6. The lip- lop is only activated by _____________

a) Positive edge trigger
b) Negative edge trigger
c) Either positive or Negative edge trigger
d) Sinusoidal trigger
View Answer
Answer: c
Explanation: Flip lops can be activated with either a positive or negative edge trigger.
7. The S-R latch composed of NAND gates is called an active low circuit because _____________
a) It is only activated by a positive level trigger
b) It is only activated by a negative level trigger
c) It is only activated by either a positive or negative level trigger
d) It is only activated by sinusoidal trigger
View Answer
Answer: b
Explanation: Active low indicates that only an input value of 0 sets or resets the circuit.
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8. Both the J-K & the T lip- lop are derived from the basic _____________
a) S-R lip- lop
b) S-R latch
c) D latch
d) D lip- lop
View Answer
Answer: b
Explanation: The SR latch is the basic block for the D latch/ lip lop from which the JK and T lip lops are
derived. A latch is similar to a lip- lop, only without a clock input.
9. The lip- lops which has not any invalid states are _____________
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
View Answer
Answer: d
Explanation: Unlike the SR latch, these circuits have no invalid states. The SR latch or lip- lop has an
invalid or forbidden state where no output could be determined.
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10. What does the triangle on the clock input of a J-K lip- lop mean?
a) Level enabled
b) Edge triggered
c) Both Level enabled & Edge triggered
d) Level triggered
View Answer
Answer: b
Explanation: The triangle on the clock input of a J-K lip- lop mean edge triggered. Whereas the absence
of triangle symbol implies that the lip- lop is level-triggered.
11. What does the circle on the clock input of a J-K lip- lop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
View Answer
Answer: c
Explanation: The circle on the clock input of a J-K lip- lop mean negative edge triggered. Whereas the
absence of triangle symbol implies that the lip- lop is level-triggered.
12. What does the direct line on the clock input of a J-K lip- lop mean?
a) Level enabled
d) Level triggered
View Answer
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Answer: d
Explanation: The direct line on the clock input of a J-K lip- lop mean level triggered. Whereas the
presence of triangle symbol implies that the lip- lop is edge-triggered.
13. What does the half circle on the clock input of a J-K lip- lop mean?
a) Level enabled
d) Level triggered
View Answer
Answer: d
Explanation: The half circle on the clock input of a J-K lip- lop mean level triggered. Whereas the
presence of triangle symbol implies that the lip- lop is edge-triggered.
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14. A J-K lip- lop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is _____________
a) Constantly LOW
b) Constantly HIGH
c) A 20 kHz square wave
d) A 10 kHz square wave
View Answer
Answer: d
Explanation: As one lip lop is used so there are two states available. So, 20/2 = 10Hz frequency is
available at the output.
15. On a positive edge-triggered S-R lip- lop, the outputs re lect the input condition when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
View Answer
Answer: c
Explanation: Edge triggered device will follow the input condition when there is a transition. It is said to
be positive edge triggered when transition occurs from LOW to HIGH. While it is said to be negative edge
triggered when a transition occurs from HIGH to LOW.
Answers.

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Digital Circuits Questions and Answers – Master-

Slave Flip-Flops
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Master-
Slave Flip-Flops”.
1. The asynchronous input can be used to set the lip- lop to the ____________
a) 1 state
b) 0 state
c) either 1 or 0 state
d) forbidden State
View Answer
Answer: c
Explanation: The asynchronous input can be used to set the lip- lop to the 1 state or clear the lip- lop to
the 0 state at any time, regardless of the condition at the other inputs.
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2. Input clock of RS lip- lop is given to ____________

a) Input
b) Pulser
c) Output
d) Master slave lip- lop
View Answer
Answer: b
Explanation: Pulser behaves like an arithmetic operator, to perform the operation or determination of
corresponding states.
3. D lip- lop is a circuit having ____________

a) 2 NAND gates
b) 3 NAND gates
c) 4 NAND gates
d) 5 NAND gates
View Answer
Answer: c
Explanation: D lip- lop is a circuit having 4 NAND gates. Two of them are connected with each other.
4. In JK lip lop same input, i.e. at a particular time or during a clock pulse, the output will oscillate back
and forth between 0 and 1. At the end of the clock pulse the value of output Q is uncertain. The situation
is referred to as?
a) Conversion condition
b) Race around condition
c) Lock out state
d) Forbidden State
View Answer
Answer: b
Explanation: A race around condition is a law in an electronic system or process whereby the output
and result of the process is unexpectedly dependent on the sequence or timing of other events.
5. Master slave lip lop is also referred to as?

a) Level triggered lip lop
b) Pulse triggered lip lop
c) Edge triggered lip lop
d) Edge-Level triggered lip lop
View Answer
Answer: b
Explanation: The term pulse triggered means the data is entered on the rising edge of the clock pulse,
but the output does not re lect the change until the falling edge of the clock pulse.
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6. In a positive edge triggered JK lip lop, a low J and low K produces?

a) High state
b) Low state
c) Toggle state
d) No Change State
View Answer
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Answer: d
Explanation: In JK Flip Flop if J = K = 0 then it holds its current state. There will be no change.
7. If one wants to design a binary counter, the preferred type of lip- lop is ____________
a) D type
b) S-R type
c) Latch
d) J-K type
View Answer
Answer: d
Explanation: If one wants to design a binary counter, the preferred type of lip- lop is J-K type because it
has capability to recover from toggle condition. SR lip- lop is not suitable as it produces the “Invalid
State”.
8. S-R type lip- lop can be converted into D type lip- lop if S is connected to R through ____________
a) OR Gate
b) AND Gate
c) Inverter
d) Full Adder
View Answer
Answer: c
Explanation: S-R type lip- lop can be converted into D type lip- lop if S is connected to R through an
Inverter gate.
9. Which of the following lip- lops is free from the race around the problem?
a) T lip- lop
b) SR lip- lop
c) Master-Slave Flip- lop
d) D lip- lop
View Answer
Answer: a
Explanation: T lip- lop is free from the race around condition because its output depends only on the
input; hence there is no any problem creates as like toggle.
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10. Which of the following is the Universal Flip- lop?

a) S-R lip- lop
b) J-K lip- lop
c) Master slave lip- lop
d) D Flip- lop
View Answer
Answer: b
Explanation: There are lots of lip- lops can be prepared by using J-K lip- lop. So, the name is a universal
lip- lop. Also, the JK lip- lop resolves the Forbidden State.
11. How many types of triggering takes place in a lip lops?

a) 3
b) 2
c) 4
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d) 5
View Answer
Answer: a
Explanation: There are three types of triggering in a lip- lop, viz., level triggering, edge triggering and
pulse triggering.
12. Flip- lops are ____________

a) Stable devices
b) Astable devices
c) Bistable devices
d) Monostable devices
View Answer
Answer: c
Explanation: Flip- lops are synchronous bistable devices known as bistable multivibrators as they have 2
stable states.
13. The term synchronous means ____________

a) The output changes state only when any of the input is triggered
b) The output changes state only when the clock input is triggered
c) The output changes state only when the input is reversed
d) The output changes state only when the input follows it
View Answer
Answer: b
Explanation: The term synchronous means the output changes state only when the clock input is
triggered. That is, changes in the output occur in synchronization with the clock.
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14. The S-R, J-K and D inputs are called ____________

a) Asynchronous inputs
b) Synchronous inputs
c) Bidirectional inputs
d) Unidirectional inputs
View Answer
Answer: b
Explanation: The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are
transferred to the lip- lop’s output only on the triggering edge or level triggering of the clock pulse.
Moreover, lip- lops have a clock input whereas latches don’t. Hence, known as synchronous inputs.
15. The circuit that generates a spike in response to a momentary change of input signal is called
____________
a) R-C differentiator circuit
b) L-R differentiator circuit
c) R-C integrator circuit
d) L-R integrator circuit
View Answer
Answer: a
Explanation: The circuit that generates a spike in response to a momentary change of input signal is
called R-C differentiator circuit.
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Realisation of one lip- lop using other lip- lops
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This set of Digital Electronic/Circuits Questions & Answers for entrance exams focuses on “Realisation of
one lip- lop using other lip- lops”.
1. To realise one lip- lop using another lip- lop along with a combinational circuit, known as ____________
a) PREVIOUS state decoder
b) NEXT state decoder
c) MIDDLE state decoder
d) PRESENT state decoder
View Answer
Answer: b
Explanation: To realise one lip- lop using another lip- lop along with a combinational circuit, known as
NEXT state decoder which acts as like a lip- lop.
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2. For realisation of JK lip- lop from SR lip- lop, the input J and K will be given as ___________
a) External inputs to S and R
b) Internal inputs to S and R
c) External inputs to combinational circuit
d) Internal inputs to combinational circuit
View Answer
Answer: a
Explanation: If a JK Flip Flop is required, the inputs are given to the combinational circuit and the output
of the combinational circuit is connected to the inputs of the actual lip lop. So, J and K will be given as
external inputs to S and R. As SR lip- lop have invalid state and JK lip- lop don’t.
3. For realisation of JK lip- lop from SR lip- lop, if J=0 & K=0 then the input is ___________
a) S=0, R=0
b) S=0, R=X
c) S=X, R=0
d) S=X, R=X
View Answer
Answer: b
Explanation: If J=0 & K=0, the output will be as: Q(n)=0, Q(n+1)=0 and it is fed into both the AND gates
which results as S=0 & R=X(i.e. don’t care).
4. For realisation of JK lip- lop from SR lip- lop, if J=1, K=0 & present state is 0(i.e. Q(n)=0) then
excitation input will be ___________
a) S=0, R=1
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b) S=X, R=0
c) S=1, R=0
d) S=1, R=1
View Answer
Answer: c
Explanation: If J=1, K=0 & present state is 0(i.e. Q(n)=0) then next state will be 1 which results excitation
inputs as S=1 & R=0.
5. For realisation of SR lip- lop from JK lip- lop, the excitation input will be obtained from ___________
a) S and R
b) R input
c) J and K input
d) D input
View Answer
Answer: c
Explanation: It is the reverse process of SR lip- lop to JK lip- lop. So, for realisation of SR lip- lop from
JK lip- lop, the excitation input will be obtained from J and K.
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6. For realisation of SR lip- lop from JK lip- lop, if S=1, R=0 & present state is 0 then next state will be
___________
a) 1
b) 0
c) Don’t care
d) Toggle
View Answer
Answer: a
Explanation: For JK lip- lop to SR lip- lop, if S=1, R=0 & present state is 0 then next state will be 1
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because next stage is complement of present stage.
7. For realisation of SR lip- lop from JK lip- lop, if S=1, R=0 & present state is 0 then the excitation input
will be ___________
a) J=1, K=1
b) J=X, K=1
c) J=1, K=X
d) J=0, K=0
View Answer
Answer: c
Explanation: For realisation of SR lip- lop from JK lip- lop, if S=1, R=0 & present state is 0 then the
excitation input will be J=1, K=X.
8. The K-map simpli ication for realisation of SR lip- lop from JK lip- lop is ___________
a) J=1, K=0
b) J=R, K=S
c) J=S, K=R
d) J=0, K=1
View Answer
Answer: c
Explanation: The K-map simpli ication for realisation of SR lip- lop from JK lip- lop is given by: J=S, K=R.
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9. For realisation of D lip- lop from SR lip- lop, the external input is given through ___________
a) S
b) R
c) D
d) Both S and R
View Answer
Answer: c
Explanation: For realisation of D lip- lop from SR lip- lop, S and R are the actual inputs of the lip lop
which is connected together via NOT gate and it is called external input as D.
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10. For D lip- lop to JK lip- lop, the characteristics equation is given by ___________
a) D=JQ(p)’+Q(p)K’
b) D=JQ(p)’+KQ(p)’
c) D=JQ(p)+Q(p)K’
d) D=J’Q(p)+Q(p)K
View Answer
Answer: a
to satisfy the truth table. For D lip- lop to JK lip- lop, the characteristics equation is given by
D=JQ(p)’+Q(p)K’.
To practice all areas of Digital Electronic Circuits for entrance exams, here is complete set of 1000+

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Counters
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“Counters”.
1. In digital logic, a counter is a device which ____________

a) Counts the number of outputs
b) Stores the number of times a particular event or process has occurred
c) Stores the number of times a clock pulse rises and falls
d) Counts the number of inputs
View Answer
Answer: b
Explanation: In digital logic and computing, a counter is a device which stores (and sometimes displays)
the number of times a particular event or process has occurred, often in relationship to a clock signal.
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2. A counter circuit is usually constructed of ____________

a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of lip- lops connected in cascade
d) A number of NOR gates connected in cascade form
View Answer
Answer: c
Explanation: A counter circuit is usually constructed of a number of lip- lops connected in cascade.
Preferably, JK Flip- lops are used to construct counters and registers.
3. What is the maximum possible range of bit-count speci ically in n-bit binary counter consisting of ‘n’
number of lip- lops?
a) 0 to 2n
b) 0 to 2n + 1
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c) 0 to 2n – 1
d) 0 to 2n+1/2
View Answer
Answer: c
Explanation: The maximum possible range of bit-count speci ically in n-bit binary counter consisting of
‘n’ number of lip- lops is 0 to 2n-1. For say, there is a 2-bit counter, then it will count till 22-1 = 3. Thus, it
will count from 0 to 3.
4. How many types of the counter are there?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: b
Explanation: Counters are of 3 types, namely, (i)asynchronous/synchronous, (ii)single and multi-mode &
(iii)modulus counter. These further can be subdivided into Ring Counter, Johnson Counter, Cascade
Counter, Up/Down Counter and such like.
5. A decimal counter has ______ states.

a) 5
b) 10
c) 15
d) 20
View Answer
Answer: b
Explanation: Decimal counter is also known as 10 stage counter. So, it has 10 states. It is also known as
Decade Counter counting from 0 to 9.
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6. Ripple counters are also called ____________

a) SSI counters
b) Asynchronous counters
c) Synchronous counters
d) VLSI counters
View Answer
Answer: b
Explanation: Ripple counters are also called asynchronous counter. In Asynchronous counters, only the
irst lip- lop is connected to an external clock while the rest of the lip- lops have their preceding lip-
lop output as clock to them.
7. Synchronous counter is a type of ____________

a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters
View Answer
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Answer: c
Explanation: Synchronous Counter is a Medium Scale Integrated (MSI). In Synchronous Counters, the
clock pulse is supplied to all the lip- lops simultaneously.
8. Three decade counter would have ____________

a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
View Answer
Answer: b
Explanation: Three decade counter has 30 states and a BCD counter has 10 states. So, it would require 3
BCD counters. Thus, a three decade counter will count from 0 to 29.
9. BCD counter is also known as ____________

a) Parallel counter
b) Decade counter
c) Synchronous counter
d) VLSI counter
View Answer
Answer: b
Explanation: BCD counter is also known as decade counter because both have the same number of
stages and both count from 0 to 9.
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10. The parallel outputs of a counter circuit represent the _____________

a) Parallel data word
b) Clock frequency
c) Counter modulus
d) Clock count
View Answer
Answer: d
Explanation: The parallel outputs of a counter circuit represent the clock count. A counter counts the
number of times an event takes place in accordance to the clock pulse.
Answers.

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Asynchronous Counter
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“Asynchronous Counter”.
1. How many natural states will there be in a 4-bit ripple counter?

a) 4
b) 8
c) 16
d) 32
View Answer
Answer: c
Explanation: In an n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.
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2. A ripple counter’s speed is limited by the propagation delay of _____________

a) Each lip- lop
b) All lip- lops and gates
c) The lip- lops only with gates
d) Only circuit gates
View Answer
Answer: a
Explanation: A ripple counter is something that is derived by other lip- lops. It’s like a series of Flip
Flops. Output of one FF becomes the input of the next. Because ripple counter is composed of FF only
and no gates are there other than FF, so only propagation delay of FF will be taken into account.
Propagation delay refers to the amount of time taken in producing an output when the input is altered.
3. One of the major drawbacks to the use of asynchronous counters is that ____________
a) Low-frequency applications are limited because of internal propagation delays
b) High-frequency applications are limited because of internal propagation delays
c) Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-
frequency counting applications
d) Asynchronous counters do not have propagation delays, which limits their use in high-frequency
applications
View Answer
Answer: b
Explanation: One of the major drawbacks to the use of asynchronous counters is that High-frequency
applications are limited because of internal propagation delays. Propagation delay refers to the amount
of time taken in producing an output when the input is altered.
4. Internal propagation delay of asynchronous counter is removed by ____________

a) Ripple counter
b) Ring counter
c) Modulus counter
d) Synchronous counter
View Answer
Answer: d
Explanation: Propagation delay refers to the amount of time taken in producing an output when the
input is altered. Internal propagation delay of asynchronous counter is removed by synchronous
counter because clock input is given to each lip- lop individually in synchronous counter.
5. What happens to the parallel output word in an asynchronous binary down counter whenever a clock
pulse occurs?
a) The output increases by 1
b) The output decreases by 1
c) The output word increases by 2
d) The output word decreases by 2
View Answer
Answer: b
Explanation: In an asynchronous counter, there isn’t any clock input. The output of 1st lip- lop is given to
second lip- lop as clock input. So, in case of binary down counter the output word decreases by 1.
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6. How many lip- lops are required to construct a decade counter?

a) 4
b) 8
c) 5
d) 10
View Answer
Answer: a
Explanation: Number of lip- lop required is calculated by this formula: 2(n-1) <= N< = 2n. 24=16and23=8,
therefore, 4 lip lops needed.
7. The terminal count of a typical modulus-10 binary counter is ____________

a) 0000
b) 1010
c) 1001
d) 1111
View Answer
Answer: c
Explanation: A binary counter counts or produces the equivalent binary number depending on the
cycles of the clock input. Modulus-10 means count from 0 to 9. So, terminal count is 9 (1001).
8. How many different states does a 3-bit asynchronous counter have?

a) 2
b) 4
c) 8
d) 16
View Answer
Answer: c
Explanation: In a n-bit counter, the total number of states = 2n.
9. A 5-bit asynchronous binary counter is made up of ive lip- lops, each with a 12 ns propagation delay.
The total propagation delay (tp(total)) is ____________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
View Answer
Answer: d
Explanation: Since a counter is constructed using lip- lops, therefore, the propagation delay in the
counter occurs only due to the lip- lops. Each bit has propagation delay = 12ns. So, 5 bits = 12ns * 5 =
60ns.
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10. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional
states are required?
a) 1
b) 2
c) 8
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d) 15
View Answer
Answer: d
Explanation: Transitional state is given by (2n – 1). Since, it’s a 4-bit counter, therefore, transition states =
24 – 1 = 15. So, total transitional states are 15.
11. A 4-bit ripple counter consists of lip- lops, which each have a propagation delay from clock to Q
output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ____________
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
View Answer
Answer: d
counter occurs only due to the lip- lops. One bit change is 15 ns, so 4-bit change = 15 * 4 = 60.
12. Three cascaded decade counters will divide the input frequency by ____________
a) 10
b) 20
c) 100
d) 1000
View Answer
Answer: d
Explanation: Decade counter has 10 states. So, three decade counters are cascaded i.e. 10*10*10=1000
states.
13. A ripple counter’s speed is limited by the propagation delay of ____________

a) Each lip- lop
View Answer
Answer: a
Explanation: A ripple counter is something that is derived by other lip- lops. Its like a series of Flip
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14. A 4-bit counter has a maximum modulus of ____________

a) 3
b) 6
c) 8
d) 16
View Answer
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Answer: d
15. A principle regarding most display decoders is that when the correct input is present, the related
output will switch ____________
a) HIGH
b) To high impedance
c) To an open
d) LOW
View Answer
Answer: d
Explanation: A principle regarding most display decoders is that when the correct input is present, the
related output will switch LOW. Since it’s an active-low device.
Answers.

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Digital Circuits Questions and Answers – Counter

ICs
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Counter
ICs”.
1. What is the difference between a 7490 and a 7493?

a) 7490 is a MOD-10, 7493 is a MOD-16
b) 7490 is a MOD-16, 7493 is a MOD-10
c) 7490 is a MOD-12, 7493 is a MOD-16
d) 7490 is a MOD-10, 7493 is a MOD-12
View Answer
Answer: a
Explanation: The difference between a 7490 and a 7493 is that 7490 is a MOD-10, 7493 is a MOD-16
counter. Thus, 7490 traverses 10 states and 7493 traverses 16 states.
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2. How many different states does a 2-bit asynchronous counter have?

a) 1
b) 4
c) 2
d) 8
View Answer
Answer: b
Explanation: For a n-bit counter, total number of states = 2n. Thus, for 2-bit counter, total number of
states = 22 = 4.
3. A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a

modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is ________
a) 10 kHz
b) 20 kHz
c) 30 kHz
d) 60 kHz
View Answer
Answer: c
Explanation: Cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10
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counter. So, 5*8*10=400. Applied clock frequency = 12 MHz; hence, the lowest output frequency possible
is 12MHz/400=30 kHz.
4. Which one is a 4-bit binary ripple counter?

a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
View Answer
Answer: b
Explanation: IC 7493 is a 4-bit binary ripple counter. It is a MOD-16 counter with 24 = 16 states.
5. IC 7493 consist of ____________

a) 4 S-R lip- lop
b) 4 J-K lip- lop
c) 4 master-slave lip- lop
d) 4 D lip- lop
View Answer
Answer: c
Explanation: IC 7493 consist of 4 J-K master-slave lip- lop. It is a MOD-16 counter with 24 = 16 states.
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6. A reset input is used in IC 7493, why?

a) For increment of bit by 1
b) For decrement of bit by 1
c) For reset the counter
d) For setting the counter
View Answer
Answer: c
Explanation: The reset inputs are used to reset the counter to 0000.
7. In a 4-bit binary ripple counter, four master-slave lip- lops are internally connected to provide a
________ bit counter.
a) Divide-by-2 & divide-by-6
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b) Divide-by-6 & divide-by-8

c) Divide-by-2 & divide-by-8
d) Divide-by-4 & divide-by-8
View Answer
Answer: c
Explanation: In a 4-bit binary ripple counter, four master-slave lip- lops are internally connected to
provide a Divide-by-2 & divide-by-8 bit counter.
8. Which of the following is decade counter?

a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
View Answer
Answer: b
Explanation: IC 7490 is called as decade counter or MOD-10. Thus, it has 10 states.
9. In a 4-bit decade counter, four master-slave lip- lops are internally connected to provide a ________ bit
counter.
a) Divide-by-2 & divide-by-6
b) Divide-by-6 & divide-by-8
c) Divide-by-2 & divide-by-5
d) Divide-by-4 & divide-by-8
View Answer
Answer: c
Explanation: In a decade counter, four master-slave lip- lops are internally connected to provide a
Divide-by-2 & divide-by-5 bit counter.
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10. Reset inputs are used in IC 7490, why?

a) For increment of bit by 1
b) For decrement of bit by 1
c) For reset the counter
d) For setting the counter
View Answer
Answer: c
Explanation: The reset inputs are used to reset the counter to 0000.
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11. The set inputs are used in a decade counter, why?

a) To set the counter to 0011
b) To set the counter to 1000
c) To set the counter to 1001
d) To set the counter to 0001
View Answer
Answer: c
Explanation: The set inputs are used in a decade counter to set the counter to 1001 which is 9 in
decimal, as a decade counter counts from 0 to 9.
12. List which pins need to be connected together on a 7493 to make a MOD-12 counter.
a) 12 to 1, 11 to 3, 9 to 2
b) 12 to 1, 11 to 3, 12 to 2
c) 12 to 1, 11 to 3, 8 to 2
d) 12 to 1, 11 to 3, 1 to 2
View Answer
Answer: c
Explanation: IC-7493 is a MOD-16 counter. So maximum, it can have 16 states. A MOD-12 counter will
have 12-states. Thus, it is clear from the diagram shown below: 12 & 1 are clear pins, 11 & 3 are clock
pins, 8 & 2 are input for 7493 FF.
13. Ripple counter IC has _____________

a) 10 pins
b) 11 pins
c) 12 pins
d) 14 pins
View Answer
Answer: d
Explanation: A ripple counter is of 4-bit and has 4 J-K lip- lops. Ripple counter IC has 14 pins.
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14. Integrated-circuit counter chips are used in numerous applications including ____________
a) Timing operations, counting operations, sequencing, and frequency multiplication
b) Timing operations, counting operations, sequencing, and frequency division
c) Timing operations, decoding operations, sequencing, and frequency multiplication
d) Data generation, counting operations, sequencing, and frequency multiplication
View Answer
Answer: b
Explanation: There are no integrated circuit counter chips employed for frequency multiplication. In the
rest of the options, frequency multiplication is mentioned which is not related to counters in anyway. So,
they are not the correct answers. Thus, counters are used for timing operations, counting operations,
sequencing and frequency division.
15. What is the difference between a 7490 and a 7492?

a) 7490 is a MOD-12, 7492 is a MOD-10
b) 7490 is a MOD-12, 7492 is a MOD-16
c) 7490 is a MOD-16, 7492 is a MOD-10
d) 7490 is a MOD-10, 7492 is a MOD-12
View Answer
Answer: d
Explanation: From the properties of both ICs, we have 7490 is a MOD-10, 7492 is a MOD-12. Thus, IC-
7490 can have maximum 10 states, while IC-7492 can have maximum 12 states.
Answers.

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Asynchronous down counter
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“Asynchronous down counter”.
1. Which of the following statements are true?

a) Asynchronous events does not occur at the same time
b) Asynchronous events are controlled by a clock
c) Synchronous events does not need a clock to control them
d) Only asynchronous events need a control clock
View Answer
Answer: a
Explanation: Asynchronous events does not occur at the same time because of propagation delay and
they do need a clock pulse to trigger them. Whereas, synchronous events occur in presence of clock
pulse.
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2. A down counter using n- lip- lops count ______________

a) Downward from a maximum count
b) Upward from a minimum count
c) Downward from a minimum to maximum count
d) Toggles between Up and Down count
View Answer
Answer: a
Explanation: As the name suggests down counter means counting occurs from a higher value to lower
value (i.e. (2^n – 1) to 0).
3. UP Counter is ____________
a) It counts in upward manner
b) It count in down ward manner
c) It counts in both the direction
View Answer
Answer: a
Explanation: UP counter counts in an upward manner from 0 to (2^n – 1).
4. DOWN counter is ____________

a) It counts in upward manner
b) It count in downward manner
c) It counts in both the direction
View Answer
Answer: b
Explanation: DOWN counter counts in a downward manner from (2^n – 1) to 0.
5. How many different states does a 3-bit asynchronous down counter have?
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: d
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6. In a down counter, which lip- lop doesn’t toggle when the inverted output of the preceeding lip- lop
goes from HIGH to LOW.
a) MSB lip- lop
b) LSB lip- lop
c) Master slave lip- lop
d) Latch
View Answer
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Answer: b
Explanation: Since, the LSB lip- lop changes its state at each negative transition of clock. That is why LSB
lip- lop doesn’t have toggle.
7. In a 3-bit asynchronous down counter, the initial content is ____________

a) 000
b) 111
c) 010
d) 101
View Answer
Answer: a
Explanation: Initially, all the lip- lops are RESET. So, the initial content is 000. At the irst negative
transition of the clock, the counter content becomes 101.
8. In a 3-bit asynchronous down counter, at the irst negative transition of the clock, the counter content
becomes ____________
a) 000
b) 111
c) 101
d) 010
View Answer
Answer: b
Explanation: Since, in the down counter, the counter content is decremented by 1 for every negative
transition. Hence, in a 3-bit asynchronous down counter, at the irst negative transition of the clock, the
counter content becomes 111.
9. In a 3-bit asynchronous down counter, at the irst negative transition of the clock, the counter content
becomes ____________
a) 000
b) 111
c) 101
d) 010
View Answer
Answer: c
Explanation: Since, in the down counter, the counter content is decremented by 1 for every negative
transition. Hence, in a 3-bit asynchronous down counter, at the irst negative transition of the clock, the
counter content becomes 101.
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10. The hexadecimal equivalent of 15,536 is ________

a) 3CB0
b) 3C66
c) 63C0
d) 6300
View Answer
Answer: a
Explanation: You just divide the number by 16 at the end and store the remainder from bottom to top.
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11. In order to check the CLR function of a counter ____________

a) Apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset
state
b) Ground the CLR input and check to be sure that all of the Q outputs are LOW
c) Connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH
d) Connect the CLR to its correct active level while clocking the counter; check to make sure that all of the
Q outputs are toggling
View Answer
Answer: a
Explanation: CLR stands for clearing or resetting all states of lip- lop. In order to check the CLR function
of a counter, apply the active level to the CLR input and check all of the Q outputs to see if they are all in
their reset state.
Answers.
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Propagation Delay in Ripple Counter
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“Propagation Delay in Ripple Counter”.
1. Modulus refers to ____________

a) A method used to fabricate decade counter units
b) The modulus of elasticity, or the ability of a circuit to be stretched from one mode to another
c) An input on a counter that is used to set the counter state, such as UP/DOWN
d) The maximum number of states in a counter sequence
View Answer
Answer: d
Explanation: Modulus is de ined as the maximum number of stages/states a counter has. It is
independent of the number of states the counter will actually traverse.
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2. A sequential circuit design is used to ____________

a) Count up
b) Count down
c) Decode an end count
d) Count in a random order
View Answer
Answer: d
Explanation: A sequential circuit design is used to count in a random manner which is faster than the
combinational circuit. It is used for storing data.
3. In general, when using a scope to troubleshoot digital systems, the instrument should be triggered by
____________
a) The A channel or channel 1
b) The vertical input mode, when using more than one channel
c) The system clock
d) Line sync, in order to observe troublesome power line glitches
View Answer
Answer: c
Explanation: All the information is sent from one end to another end through the clock pulse which
behaves like a carrier. So, for troubleshooting it should be triggered by the same. Since the system clock
is internally produced.
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4. Which counters are often used whenever pulses are to be counted and the results displayed in
decimal?
a) Synchronous
b) Bean
c) Decade
d) BCD
View Answer
Answer: d
Explanation: BCD means Binary Coded Decimal, which means that decimal numbers coded of binary
numbers. It displays the decimal equivalent of corresponding binary numbers.
5. The ________ counter in the Altera library has controls that allow it to count up or down, and perform
synchronous parallel load and asynchronous cascading.
a) 74134
b) LPM
c) Synchronous
d) AHDL
View Answer
Answer: b
Explanation: The library of parameterized modules (LPM) counter in the Altera library has controls that
allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.
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6. The minimum number of lip- lops that can be used to construct a modulus-5 counter is ____________
a) 3
b) 8
c) 5
d) 10
View Answer
Answer: a
Explanation: The minimum number of lip- lops used in a counter is given by: 2(n-1)<=N<=2n.
Thus, for modulus-5 counter: 22 <= N <= 23, where N = 5 and n = 3.
7. The duty cycle of the most signi icant bit from a 4-bit (0–9) BCD counter is ____________
a) 20%
b) 50%
c) 10%
d) 80%
View Answer
Answer: a
Explanation: There are 10 states, out of which MSB is high only for (1000, 1001) 2 times. Hence duty
cycle is 2/10*100 = 20%. Since the duty cycle is the ratio of on-time to the total time.
8. Normally, the synchronous counter is designed using ____________

a) S-R lip- lops
b) J-K lip- lops
c) D lip- lops
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d) T lip- lops
View Answer
Answer: b
Explanation: Since J-K lip- lops have options of recovery from toggle condition and by using less number
of J-K lip- lops a synchronous counter can be designed. So, it is more preferred. Also, because JK- lip-
lops resolves the problem of Forbidden States.
9. MOD-16 counter requires ________ no. of states.

a) 8
b) 4
c) 16
d) 32
View Answer
Answer: c
Explanation: 2n >= N >= 2(n-1), by using this formula we get the value of N=16 for n=4.
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10. What is state diagram?

a) It provides the graphical representation of states
b) It provides exactly the same information as the state table
c) It is same as the truth table
d) It is similar to the characteristic equation
View Answer
Answer: b
Explanation: The state diagram provides exactly the same information as the state table and is obtained
directly from the state table.
11. High speed counter is ____________

a) Ring counter
b) Ripple counter
c) Synchronous counter
d) Asynchronous counter
View Answer
Answer: c
Explanation: Synchronous counter doesn’t have propagation delay. Propagation delay refers to the
amount of time taken in producing the output when the input is altered.
12. Program counter in a digital computer ____________

a) Counts the number of programs run in the machine
b) Counts the number of times a subroutine
c) Counts the number of time the loops are executed
d) Points the memory address of the current or the next instruction
View Answer
Answer: d
Explanation: Program counter in a digital computer points the memory address of the current or the
next instruction which is to be executed.
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13. Fundamental mode is another name for ____________

a) Level operation
b) Pulse operation
c) Clock operation
d) Edge operation
View Answer
Answer: b
Explanation: Whatever the input given to the devices are in the form of pulses always. That is why it is
known as a fundamental mode.
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Answers.

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Digital Circuits Questions and Answers – Counter

Implementation and Applications
« Prev Next »
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Counter
Implementation and Applications”.
1. A ripple counter’s speed is limited by the propagation delay of ____________

a) Each lip- lop
View Answer
Answer: a
Explanation: A ripple counter is something that is derived by other lip- lops. It’s like a series of Flip
Flops. The output of one FF becomes the input of the next. Because ripple counter is composed of FF
only and no gates are there other than FF, so only propagation delay of FF will be taken into account.
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2. A 5-bit asynchronous binary counter is made up of ive lip- lops, each with a 12 ns propagation delay.
The total propagation delay (tp(tot)) is ________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
View Answer
Answer: d
60ns.
3. A 4-bit ripple counter consists of lip- lops, which each have a propagation delay from clock to Q
output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
View Answer
Answer: d
60ns.
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4. A ripple counter’s speed is limited by the propagation delay of __________

a) Each lip- lop
View Answer
Answer: a
Explanation: A ripple counter is something that is derived by other lip- lops. Its like a series of Flip
5. What is the maximum delay that can occur if four lip- lops are connected as a ripple counter and each
lip- lop has propagation delays of tPHL = 22 ns and tPLH = 15 ns?
a) 15 ns
b) 22 ns
c) 60 ns
d) 88 ns
View Answer
Answer: d
Explanation: Maximum propagation delay is the longest delay between an input changing value and the
output changing value. Hence, 22 * n = 22*4 (Since there are 4 FFs) = 88ns.
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6. The main drawback of a ripple counter is that __________

a) It has a cumulative settling time
b) It has a distributive settling time
c) It has a productive settling time
d) It has an associative settling time
View Answer
Answer: a
Explanation: The main drawback of a ripple counter is that it has a cumulative settling time (i.e. another
bit is transmitted just after one consequently).
7. A 4 bit modulo-16 ripple counter uses JK lip- lops. If the propagation delay of each lip- lop is 50 nsec,
the maximum clock frequency that can be used is equal to __________
a) 20 MHz
b) 10 MHz
c) 5 MHz
d) 4 MHz
View Answer
Answer: c
counter occurs only due to the lip- lops. Each bit has propagation delay = 50ns. So, 4 bits or FFs = 50ns
* 4 = 200ns. Clock frequency = 1/200ns = 5 MHz.
8. As the number of lip lops are increased, the total propagation delay of __________
a) Ripple counter increases but that of synchronous counter remains the same
b) Both ripple and synchronous counters increase
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c) Both ripple and synchronous counters remain the same

d) Ripple counter remains the same but that of synchronous counter increases
View Answer
Answer: a
Explanation: In ripple counter, the clock pulses are applied to one lip- lop only. Hence, as the number of
lip- lops increases the delay increases. In the synchronous counter, clock pulses to all lip- lops are
applied simultaneously.
9. A reliable method for eliminating decoder spikes is the technique called ________
a) Strobing
b) Feeding
c) Wagging
d) Waving
View Answer
Answer: a
Explanation: A reliable method for eliminating decoder spikes is the technique called strobing. A strobe
signal validates the availability of data on consecutive parallel lines.
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10. A glitch that appears on the decoded output of a ripple counter is often dif icult to see on an
oscilloscope because of __________
a) It is a random event
b) It occurs less frequently than the normal decoded output
c) It is very fast
View Answer
Answer: d
Explanation: A glitch is a transition that occurs before a signal settles to a speci ic value. A glitch that
appears on the decoded output of a ripple counter is often dif icult to see on an oscilloscope because it
is a random event and very fast and it occurs less frequently than the normal decoded output.
11. Assume a 4-bit ripple counter has a failure in the second lip- lop such that it “locks up”. The third and
fourth stages will __________
a) Continue to count with correct outputs
b) Continue to count but have incorrect outputs
c) Stop counting
d) Turn into molten silicon
View Answer
Answer: c
Explanation: The ripple counter would stop counting because next lip- lop’s input depends on the
output of the previous lip- lop.
Answers.
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19. VHDL Questions and Answers – Designing Counters with VHDL
20. Instrumentation Transducers Questions and Answers – Shift Registors and Counters
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Digital Circuits Questions and Answers – Up

down counter
« Prev Next »
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Up down
counter”.
1. UP-DOWN counter is a combination of ____________

a) Latches
b) Flip- lops
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c) UP counter
d) Up counter & down counter
View Answer
Answer: d
Explanation: As the name suggests UP-DOWN, it means that it has up-counter and down-counter as well.
It alternatively counts up and down.
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2. UP-DOWN counter is also known as ___________

a) Dual counter
b) Multi counter
c) Multimode counter
d) Two Counter
View Answer
Answer: c
Explanation: UP-DOWN counter is also known as multimode counter because it has capability of counting
upward as well as downwards.
3. In an UP-counter, each lip- lop is triggered by ___________

a) The output of the next lip- lop
b) The normal output of the preceding lip- lop
c) The clock pulse of the previous lip- lop
d) The inverted output of the preceding lip- lop
View Answer
Answer: b
Explanation: In an UP-counter, each lip- lop is triggered by the normal output of the preceding lip- lop.
UP-counter counts from 0 to a maximum value.
4. In DOWN-counter, each lip- lop is triggered by ___________

a) The output of the next lip- lop
b) The normal output of the preceding lip- lop
c) The clock pulse of the previous lip- lop
d) The inverted output of the preceding lip- lop
View Answer
Answer: d
Explanation: In DOWN-counter, each lip- lop is triggered by the inverted output of the preceding lip-
lop. DOWN-counter counts from a maximum value to 0.
5. Binary counter that count incrementally and decrement is called ___________

a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter
View Answer
Answer: a
Explanation: Binary counter that counts incrementally and decrement is called UP-DOWN
counter/multimode counter. It alternately counts up and down.
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6. Once an up-/down-counter begins its count sequence, it ___________

a) Starts counting
b) Can be reversed
c) Can’t be reversed
d) Can be altered
View Answer
Answer: d
Explanation: In up/down ripple counter once the counting begins, we can simply change the pulse M
(mode control) M = 0 or 1 respectively for UP counter or Down counter.
7. In 4-bit up-down counter, how many lip- lops are required?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: c
Explanation: An n-bit bit counter requires n number of FFs. In a 4-bit up-down counter, there are 4 J-K
lip- lops required.
8. A modulus-10 counter must have ________

a) 10 lip- lops
b) 4 Flip- lops
c) 2 lip- lops
d) Synchronous clocking
View Answer
Answer: b
Explanation: 2n-1 < = N < = 2n
For modulus-10 counter, N = 10. Therefore, 23 < = 10 < = 24. Thus, n = 4, and therefore, we require 4
FFs.
9. Which is not an example of a truncated modulus?

a) 8
b) 9
c) 11
d) 15
View Answer
Answer: a
Explanation: An n-bit counter whose modulus is less than the maximum possible is called a truncated
counter. Here, 9, 11 and 15 modulus counters are truncated counters. Whereas, modulus-8 is not a
truncated counter.
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10. The designation means that the ________

a) Up count is active-HIGH, the down count is active-LOW
b) Up count is active-LOW, the down count is active-HIGH
c) Up and down counts are both active-LOW
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d) Up and down counts are both active-HIGH

View Answer
Answer: a
Explanation: The designation means that the up count is active-HIGH, the down count is active-LOW.
Active-High means that up-count would be triggered when clock is 1 else when clock is 0, down-count
would be triggered, which is referred to as Active-low.
11. An asynchronous binary up counter, made from a series of leading edge-triggered lip- lops, can be
changed to a down counter by ________
a) Taking the output on the other side of the lip- lops (instead of Q)
b) Clocking of each succeeding lip- lop from the other side (instead of Q)
c) Changing the lip- lops to trailing edge triggering
View Answer
Answer: d
Explanation: By all of the mentioned ideas, an asynchronous binary up counter, made from a series of
leading edge-triggered lip- lops, can be changed to a down counter. Edge-triggered FFs refer to FFs
being triggered during a clock transition from LOW to HIGH or HIGH to LOW.
12. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most
signi icant bit is ________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz
View Answer
Answer: a
Explanation: Input clock is given by 20/2 kHz. So, count on the basis of 10 kHz clock. And MSB changes
on 8th stage; Hence, f = 10/8 = 1.25 kHz.
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Answers.

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Registers
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“Registers”.
1. A register is de ined as ___________

a) The group of latches for storing one bit of information
b) The group of latches for storing n-bit of information
c) The group of lip- lops suitable for storing one bit of information
d) The group of lip- lops suitable for storing binary information
View Answer
Answer: d
Explanation: A register is de ined as the group of lip- lops suitable for storing binary information. Each
lip- lop is a binary cell capable of storing one bit of information. The data in a register can be
transferred from one lip- lop to another.
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2. The register is a type of ___________

a) Sequential circuit
b) Combinational circuit
c) CPU
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d) Latches
View Answer
Answer: a
Explanation: Register’s output depends on the past and present states of the inputs. The device which
follows these properties is termed as a sequential circuit. Whereas, combinational circuits only depend
on the present values of inputs.
3. How many types of registers are?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: c
Explanation: There are 4 types of shift registers, viz., Serial-In/Serial-Out, Serial-In/Parallel-Out, Parallel-
In/Serial-Out and Parallel-In/Parallel-Out.
4. The main difference between a register and a counter is ___________

a) A register has no speci ic sequence of states
b) A counter has no speci ic sequence of states
c) A register has capability to store one bit of information but counter has n-bit
d) A register counts data
View Answer
Answer: a
Explanation: The main difference between a register and a counter is that a register has no speci ic
sequence of states except in certain specialised applications.
5. In D register, ‘D’ stands for ___________

a) Delay
b) Decrement
c) Data
d) Decay
View Answer
Answer: c
Explanation: D stands for “data” in case of lip- lops and not delay. Registers are made of a group of lip-
lops.
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6. Registers capable of shifting in one direction is ___________

a) Universal shift register
b) Unidirectional shift register
c) Unipolar shift register
d) Unique shift register
View Answer
Answer: b
Explanation: The register capable of shifting in one direction is unidirectional shift register. The register
capable of shifting in both directions is known as a bidirectional shift register.
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7. A register that is used to store binary information is called ___________

a) Data register
b) Binary register
c) Shift register
d) D – Register
View Answer
Answer: b
Explanation: A register that is used to store binary information is called a binary register. A register in
which data can be shifted is called shift register.
8. A shift register is de ined as ___________

a) The register capable of shifting information to another register
b) The register capable of shifting information either to the right or to the left
c) The register capable of shifting information to the right only
d) The register capable of shifting information to the left only
View Answer
Answer: b
Explanation: The register capable of shifting information either to the right or to the left is termed as
shift register. A register in which data can be shifted only in one direction is called unidirectional shift
register, while if data can shifted in both directions, it is known as a bidirectional shift register.
9. How many methods of shifting of data are available?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: There are two types of shifting of data are available and these are serial shifting & parallel
shifting.
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10. In serial shifting method, data shifting occurs ____________

a) One bit at a time
b) simultaneously
c) Two bit at a time
d) Four bit at a time
View Answer
Answer: a
Explanation: As the name suggests serial shifting, it means that data shifting will take place one bit at a
time for each clock pulse in a serial fashion. While in parallel shifting, shifting will take place with all bits
simultaneously for each clock pulse in a parallel fashion.
Answers.
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Digital Circuits Questions and Answers – Shift

Registers
« Prev Next »
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Shift
Registers”.
1. Based on how binary information is entered or shifted out, shift registers are classi ied into _______
categories.
a) 2
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b) 3
c) 4
d) 5
View Answer
Answer: c
Explanation: The registers in which data can be shifted serially or parallelly are known as shift registers.
Based on how binary information is entered or shifted out, shift registers are classi ied into 4 categories,
viz., Serial-In/Serial-Out(SISO), Serial-In/Parallel-Out (SIPO), Parallel-In/Serial-Out (PISO), Parallel-
In/Parallel-Out (PIPO).
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2. The full form of SIPO is ___________

a) Serial-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-In Peripheral-Out
View Answer
Answer: a
Explanation: SIPO is always known as Serial-in Parallel-out.
3. A shift register that will accept a parallel input or a bidirectional serial load and internal shift features
is called as?
a) Tristate
b) End around
c) Universal
d) Conversion
View Answer
Answer: c
Explanation: A shift register can shift it’s data either left or right. The universal shift register is capable of
shifting data left, right and parallel load capabilities.
4. How can parallel data be taken out of a shift register simultaneously?

a) Use the Q output of the irst FF
b) Use the Q output of the last FF
c) Tie all of the Q outputs together
d) Use the Q output of each FF
View Answer
Answer: d
Explanation: Because no other lip- lops are connected with the output Q, therefore one can use the Q
out of each FF to take out parallel data.
5. What is meant by parallel load of a shift register?

a) All FFs are preset with data
b) Each FF is loaded with data, one at a time
c) Parallel shifting of data
d) All FFs are set with data
View Answer
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Answer: a
Explanation: At Preset condition, outputs of lip- lops will be 1. Preset = 1 means Q = 1, thus input is
de initely 1.
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6. The group of bits 11001 is serially shifted (right-most bit irst) into a 5-bit parallel output shift register
with an initial state 01110. After three clock pulses, the register contains ________
a) 01110
b) 00001
c) 00101
d) 00110
View Answer
Answer: c
Explanation: LSB bit is inverted and feed back to MSB:
01110->initial
10111-> irst clock pulse
01011->second
00101->third.
7. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100.
What will be the 4-bit pattern after the second clock pulse? (Right-most bit irst)
a) 1100
b) 0011
c) 0000
d) 1111
View Answer
Answer: c
Explanation: In Serial-In/Serial-Out shift register, data will be shifted one at a time with every clock pulse.
Therefore,
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.
8. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to
enter. After four clock pulses, the register contains ________
a) 0000
b) 1111
c) 0111
d) 1000
View Answer
Answer: c
Explanation: In Serial-In/Parallel-Out shift register, data will be shifted all at a time with every clock pulse.
Therefore,
Wait | Store
0111 | 0000
011 | 1000 1st clk
01 | 1100 2nd clk
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0 | 1110 3rd clk

X | 1111 4th clk.
9. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
View Answer
Answer: b
Explanation: f = 200 KHZ; T = (1/200) m sec = (1/0.2) micro-sec = 5 micro-sec;
In serial transmission, data enters one bit at a time. After 8 clock cycles only 8 bit will be loaded = 8 * 5 =
40 micro-sec.
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10. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time
delay (td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us
View Answer
Answer: c
Explanation: One clock period is = (½) micro-s = 0.5 microseconds. In serial transmission, data enters
one bit at a time. So, the total delay = 0.5*8 = 4 micro seconds time is required to transmit information of
8 bits.
Answers.

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Universal Shift Registers
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“Universal Shift Registers”.
1. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
a) Ring shift
b) Clock
c) Johnson
d) Binary
View Answer
Answer: a
Explanation: In Ring counter, the feedback of the output of the FF is fed to the same FF’s input. Thus, it
generates equally spaced timing pulses.
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2. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is
waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing
________
a) 1101
b) 0111
c) 0001
d) 1110
View Answer
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Answer: b
Explanation: Mode is high means it’s a right shift register. Then after 3 clock pulses enter bits are 011
and remained bit in register is 1. Therefore, 0111 is required solution.
1011 | 1101
101 | 1110 -> 1st clock pulse
10 | 1111 -> 2nd clock pulse
1 | 0111 -> 3rd clock pulse.
3. To operate correctly, starting a ring shift counter requires __________

a) Clearing all the lip- lops
b) Presetting one lip- lop and clearing all others
c) Clearing one lip- lop and presetting all others
d) Presetting all the lip- lops
View Answer
Answer: b
Explanation: In Ring counter, the feedback of the output of the FF is fed to the same FF’s input. To
operate correctly, starting a ring shift counter requires presetting one lip- lop and clearing all others so
that it can shift to the next bit.
4. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position for
each clock pulse.
a) Right, one
b) Right, two
c) Left, one
d) Left, three
View Answer
Answer: a
Explanation: If register shifts towards left then it shift by a bit to the left and if register shifts right then it
shift to the right by one bit. Since, it receives parallel data, then by default, it will shift to right by one
position.
5. How many clock pulses will be required to completely load serially a 5-bit shift register?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: d
Explanation: A register is a collection of FFS. To load a bit, we require 1 clock pulse for 1 shift register.
So, for 5-bit shift register we would require of 5 clock pulses.
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6. How is an strobe signal used when serially loading a shift register?

a) To turn the register on and off
b) To control the number of clocks
c) To determine which output Qs are used
d) To determine the FFs that will be used
View Answer
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Answer: b
Explanation: A strobe is used to validate the availability of data on the data line. It (an auxiliary signal
used to help synchronize the real data in an electrical bus when the bus components have no common
clock) signal is used to control the number of clocks during serially loading a shift register.
7. An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time
delay between the serial input and the Q3 output?
a) 1.67 s
b) 26.67 s
c) 26.7 ms
d) 267 ms
View Answer
Answer: b
Explanation: In serial-sifting, one bit of data is shifted one at a time. From Q0 to Q3 total of 4 bit shifting
takes place. Therefore, 4/150kHz = 26.67 microseconds.
8. What are the three output conditions of a three-state buffer?

a) HIGH, LOW, loat
b) High-Z, 0, loat
c) Negative, positive, 0
d) 1, Low-Z, loat
View Answer
Answer: a
Explanation: Three conditions of a three-state buffer are HIGH, LOW & loat.
9. The primary purpose of a three-state buffer is usually ____________

a) To provide isolation between the input device and the data bus
b) To provide the sink or source current required by any device connected to its output without loading
down the output device
c) Temporary data storage
d) To control data low
View Answer
Answer: a
Explanation: The primary purpose of a three-state buffer is usually to provide isolation between the
input device or peripheral devices and the data bus. Three conditions of a three-state buffer are HIGH,
LOW & loat.
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10. What is the difference between a ring shift counter and a Johnson shift counter?
a) There is no difference
b) A ring is faster
c) The feedback is reversed
d) The Johnson is faster
View Answer
Answer: c
Explanation: A ring counter is a shift register (a cascade connection of lip- lops) with the output of the
last one connected to the input of the irst, that is, in a ring. Whereas, a Johnson counter (or switchtail
ring counter, twisted-ring counter, walking-ring counter, or Moebius counter) is a modi ied ring counter,
where the output from the last stage is inverted and fed back as input to the irst stage.
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Digital Circuits Questions and Answers – Shift

Register Counters
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Shift
Register Counters”.
1. What is a recirculating register?

a) Serial out connected to serial in
b) All Q outputs connected together
c) A register that can be used over again
d) Parallel out connected to Parallel in
View Answer
Answer: a
Explanation: A recirculating register is a register whose serial output is connected to the serial input in a
circulated manner.
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2. When is it important to use a three-state buffer?

a) When two or more outputs are connected to the same input
b) When all outputs are normally HIGH
c) When all outputs are normally LOW
d) When two or more outputs are connected to two or more inputs
View Answer
Answer: a
Explanation: When two or more outputs are connected to the same input, in such situation we use of
tristate buffer always because it has the capability to take upto three inputs. A buffer is a circuit where
the output follows the input.
3. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is
waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing
________
a) 1110
b) 0111
c) 1000
d) 1001
View Answer
Answer: d
Explanation: Stored nibble | waiting nibble
0111 | 1110, Initially
111 | 1100, 1st pulse
11 | 1001, 2nd pulse.
4. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses,
the data outputs are ________
a) 1110
b) 0001
c) 1100
d) 1000
View Answer
Answer: b
Explanation: Parallel in parallel out gives the same output as input. Thus, after three clock pulses, the
data outputs are 0001.
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5. The group of bits 10110111 is serially shifted (right-most bit irst) into an 8-bit parallel output shift
register with an initial state 11110000. After two clock pulses, the register contains
a) 10111000
b) 10110111
c) 11110000
d) 11111100
View Answer
Answer: d
Explanation: After irst clock pulse, the register contains 11111000. After second clock pulse, the register
would contain 11111100. Since, the bits are shifted to the right at every clock pulse.
6. By adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a ________ ________
and ________ out register.
a) Parallel-in, serial, parallel
b) Serial-in, parallel, serial
c) Series-parallel-in, series, parallel
d) Bidirectional in, parallel, series
View Answer
Answer: a
Explanation: One bit shifting takes place just after the output obtained on every register. Hence, by
adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a Parallel-in, Serial, and
Parallel-out register. Since, the bots can be inputted all at the same time, while the data can be outputted
either one at a time or simultaneously.
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7. What type of register would have a complete binary number shifted in one bit at a time and have all
the stored bits shifted out one at a time?
a) Parallel-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-in Parallel-out
View Answer
Answer: c
Explanation: Serial-in Serial-out register would have a complete binary number shifted in one bit at a
time and have all the stored bits shifted out one at a time. Since in serial transmission, bits are
transmitted or received one at a time and not simultaneously.
8. In a 4-bit Johnson counter sequence, there are a total of how many states, or bit patterns?
a) 1
b) 3
c) 4
d) 8
View Answer
Answer: d
Explanation: In johnson counter, total number of states are determined by 2N = 2*4 = 16
Total Number of Used states = 2N = 2*4 = 8
Total Number of Unused states = 16 – 8 = 8.
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9. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?
a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000
View Answer
Answer: b
Explanation: After shifting 2-bit we get the output as 0011010000 (Since two zeros are at 1st position
and 2nd position which came from the last two bits). As in a ring counter, the bits rotate in clockwise
direction.
10. How much storage capacity does each stage in a shift register represent?
a) One bit
b) Two bits
c) Four bits
d) Eight bits
View Answer
Answer: a
Explanation: A register is made of lip- lops. And each lip- lop stores 1 bit of data. Thus, a shift register
has the capability to store one bit and if another bit is to store, in such situation it deletes the previous
data and stores them.
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Digital Circuits Questions and Answers – Ring

Counter
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Ring
Counter”.
1. Ring shift and Johnson counters are ____________

a) Synchronous counters
b) Asynchronous counters
c) True binary counters
d) Synchronous and true binary counters
View Answer
Answer: a
Explanation: Synchronous counters are the counters being triggered in the presence of a clock pulse.
Since, all of the clock inputs are connected through a single clock pulse in ring shift and johnson
counters. So, both are synchronous counters.
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2. What is the difference between a shift-right register and a shift-left register?

a) There is no difference
b) The direction of the shift
c) Propagation delay
d) The clock input
View Answer
Answer: b
Explanation: In shift-right register, shifting of bit takes place towards the right and towards left for shift-
left register. Thus, both the registers vary in the shifting of their direction.
3. What is a transceiver circuit?

a) A buffer that transfers data from input to output
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b) A buffer that transfers data from output to input

c) A buffer that can operate in both directions
d) A buffer that can operate in one direction
View Answer
Answer: c
Explanation: A transceiver circuit is a buffer that can operate in both directions right as well as left.
4. A 74HC195 4-bit parallel access shift register can be used for ____________
a) Serial in/serial out operation
b) Serial in/parallel out operation
c) Parallel in/serial out operation
View Answer
Answer: d
Explanation: 74HC195 is an IC, which can be used for all of the given operations, as well as for, parallel-
in/parallel-out.
5. Which type of device may be used to interface a parallel data format with external equipment’s serial
format?
a) UART
b) Key matrix
c) Memory chip
d) Series in Parallel out
View Answer
Answer: a
Explanation: UART means Universal Asynchronous Receiver/Transmitter which converts the bytes it
receives from the computer along parallel circuits into a single serial bit stream for outbound
transmission. And also receives data in serial form and converts it into parallel form and sent to the
processor.
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6. What is the function of a buffer circuit?

a) To provide an output that is inverted from that on the input
b) To provide an output that is equal to its input
c) To clean up the input
d) To clean up the output
View Answer
Answer: b
Explanation: The function of a buffer circuit is to provide an output that is equal to its input. A
transceiver circuit is a buffer that can operate in both directions right as well as left.
7. What is the preset condition for a ring shift counter?

a) All FFs set to 1
b) All FFs cleared to 0
c) A single 0, the rest 1
d) A single 1, the rest 0
View Answer
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Answer: d
Explanation: A ring shift counter is a counter in which the output of one FF connected to the input of the
adjacent FF. In preset condition, all of the bits are 0 except irst one.
8. Which is not characteristic of a shift register?

a) Serial in/parallel in
b) Serial in/parallel out
c) Parallel in/serial out
d) Parallel in/parallel out
View Answer
Answer: a
Explanation: There is no such type of register present who doesn’t have output end. Thus, Serial
in/Parallel in is not a characteristic of a shift register. There has to be an output, be it serial or parallel.
9. To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ____________
a) Divide-by-4 clock pulse
b) Sequence generator
c) Strobe line
d) Multiplexer
View Answer
Answer: c
Explanation: In computer or memory technology, a strobe is a signal that is sent that validates data or
other signals on adjacent parallel lines. Thus, in registers the strobe line is there to check the availability
of data.
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10. Another way to connect devices to a shared data bus is to use a ____________
a) Circulating gate
b) Transceiver
c) Bidirectional encoder
d) Strobed latch
View Answer
Answer: b
Explanation: A transceiver is a device comprising both a transmitter and a receiver which are combined
and share common circuitry or a single housing. When no circuitry is common between transmit and
receive functions, the device is a transmitter-receiver.
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Introduction of Memory Devices – 1
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“Introduction of Memory Devices – 1”.
1. Memory is a/an ___________

a) Device to collect data from other computer
b) Block of data to keep data separately
c) Indispensable part of computer
d) Device to connect through all over the world
View Answer
Answer: c
Explanation: Memory is an indispensable unit of a computer and microprocessor based systems which
stores permanent or temporary data.
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2. The instruction used in a program for executing them is stored in the __________
a) CPU
b) Control Unit
c) Memory
d) Microprocessor
View Answer
Answer: c
Explanation: All of the program and the instructions are stored in the memory. The processor fetches it
as and when required.
3. A lip lop stores __________

a) 10 bit of information
b) 1 bit of information
c) 2 bit of information
d) 3-bit information
View Answer
Answer: b
Explanation: A lip- lop has capability to store 1 bit of information. It can be used further after erasing
previous information.
4. A register is able to hold __________

a) Data
b) Word
c) Nibble
d) Both data and word
View Answer
Answer: b
Explanation: Register is also a part of memory inside a computer. It stands there to hold a word. A word
is a group of 16-bits or 2-bytes.
5. A register ile holds __________

a) A large number of word of information
b) A small number of word of information
c) A large number of programs
d) A modest number of words of information
View Answer
Answer: d
Explanation: A register ile is different from a simple register because of capability to hold a modest
number of words of information. A word is a group of 16-bits or 2-bytes.
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6. The very irst computer memory consisted of __________

a) A small display
b) A large memory storage equipment
c) An automatic keyboard input
d) An automatic mouse input
View Answer
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Answer: b
Explanation: The very irst computer memory consisted of a minute magnetic toroid, which required
large, bulky circuit boards stored in large cabinates.
7. A minute magnetic toroid is also called as __________

a) Large memory
b) Small memory
c) Core memory
d) Both small and large memory
View Answer
Answer: c
Explanation: A minute magnetic toroid is also called as core memory which is made up of a
semiconductor. A semiconductor is a device whose electrical conductivity lies between that of conductor
and insulator.
8. Which one of the following has capability to store data in extremely high densities?
a) Register
b) Capacitor
c) Semiconductor
d) Flip-Flop
View Answer
Answer: c
Explanation: Semiconductor has capability to store data in extremely high densities.
9. A large memory is compressed into a small one by using __________

a) LSI semiconductor
b) VLSI semiconductor
c) CDR semiconductor
d) SSI semiconductor
View Answer
Answer: b
Explanation: VLSI (Very Large Scale Integration) semiconductor is used in modern computers to short
the size of memory.
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10. VLSI chip utilizes __________

a) NMOS
b) CMOS
c) BJT
View Answer
Answer: d
Explanation: VLSI (Very Large Scale Integration) is a memory chip which is made up of NMOS, CMOS, BJT,
and BiCMOS. It can include 10,000 to 100,000 gates per IC.
11. CD-ROM refers to __________

a) Floppy disk
b) Compact Disk-Read Only Memory
c) Compressed Disk-Read Only Memory
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d) Compressed Disk- Random Access Memory

View Answer
Answer: b
Explanation: CD-ROM refers to Compact Disk-Read Only Memory.
12. Data stored in an electronic memory cell can be accessed at random and on demand using __________
a) Memory addressing
b) Direct addressing
c) Indirect addressing
d) Control Unit
View Answer
Answer: b
Explanation: Direct addressing eliminates the need to process a large stream of irrelevant data in order
to the desired data word.
13. The full form of PLD is __________

a) Programmable Large Device
b) Programmable Long Device
c) Programmable Logic Device
d) Programmable Lengthy Device
View Answer
Answer: c
Explanation: The full form of PLD is Programmable Logic Device.
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14. The evolution of PLD began with __________

a) EROM
b) RAM
c) PROM
d) EEPROM
View Answer
Answer: a
Explanation: The evolution of PLD (Programmable Logic Device) began with Programmable Read Only
Memory (i.e. PROM). Here, the ROM can be externally programmed as per the user.
15. A ROM is de ined as __________

a) Read Out Memory
b) Read Once Memory
c) Read Only Memory
d) Read One Memory
View Answer
Answer: c
Explanation: A ROM is de ined as Read Only Memory which can read the instruction stored in a
computer.
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This set of Digital Electronic/Circuits assessment questions focuses on “Introduction of Memory Devices-
2”.
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1. The full form of ROM is __________

a) Read Outside Memory
b) Read Out Memory
c) Read Only Memory
d) Read One Memory
View Answer
Answer: c
Explanation: The full form of ROM is Read Only Memory.
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2. ROM consist of __________

a) NOR and OR arrays
b) NAND and NOR arrays
c) NAND and OR arrays
d) NOR and AND arrays
View Answer
Answer: c
Explanation: ROM consists of NAND and OR arrays which can be programmed by the user to implement
combinational & sequential functions. Combinational Operations like that of adders and subtractors and
Sequential Functions like that of storing in the memory.
3. For reprogrammability, PLDs use __________

a) PROM
b) EPROM
c) CDROM
d) PLA
View Answer
Answer: b
Explanation: For reprogrammability, PLDs use EPROM (i.e. Erasable PROM). It erases the previous
program and starts uploading a new one. However, data is erased by exposing it to UV-light, which is a
tedious and time-consuming process.
4. The full form of PROM is __________

a) Previous Read Only Memory
b) Programmable Read Out Memory
c) Programmable Read Only Memory
d) Previous Read Out Memory
View Answer
Answer: c
Explanation: The full form of PROM is Programmable Read Only Memory, where the ROM can be
programmed by the user.
5. The full form of EPROM is __________

a) Easy Programmable Read Only Memory
b) Erasable Programmable Read Only Memory
c) Eradicate Programmable Read Only Memory
d) Easy Programmable Read Out Memory
View Answer
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Answer: b
Explanation: The full form of EPROM is Erasable Programmable Read Only Memory, where the ROM can
be erased and re-used by the user.
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6. PLDs with programmable AND and ixed OR arrays are called __________
a) PAL
b) PLA
c) APL
d) PPL
View Answer
Answer: a
Explanation: PLDs with programmable AND and ixed OR arrays are called PAL (i.e. Programmable Array
Logic). However, PAL is less lexible but has higher speed.
7. When both the AND and OR are programmable, such PLDs are known as __________
a) PAL
b) PPL
c) PLA
d) APL
View Answer
Answer: c
Explanation: When both the AND and OR are programmable, such PLDs are known as PLA (i.e.
Programmable Logic Array). However, PLA is more lexible but has less speed.
8. ASIC stands for __________

a) Application Special Integrated Circuits
b) Applied Special Integrated Circuits
c) Application Speci ic Integrated Circuits
d) Applied Speci ic Integrated Circuits
View Answer
Answer: c
Explanation: In digital electronics, ASIC stands for Application Speci ic Integrated Circuits. It is a
customized integrated circuit which is produced for a speci ic use and not for a common-purpose.
9. The programmability and high density of PLDs make them useful in the design of __________
a) ISAC
b) ASIC
c) SACC
d) CISF
View Answer
Answer: b
Explanation: The programmability and high density of PLDs make them useful in the design of ASIC (i.e.
Application Speci ic Integrated Circuits) where design changes can be more rapidly and inexpensively.
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10. FPGA stands for __________

a) Full Programmable Gate Array
b) Full Programmable Genuine Array
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c) First Programmable Gate Array

d) Field Programmable Gate Array
View Answer
Answer: d
Explanation: In digital electronics, FPGA stands for Field Programmable Gate Array. This type of
integrated circuit is for general-purpose which is con igured by the user as per their requirement.
11. Which of the following is a reprogrammable gate array?

a) EPROM
b) FPGA
c) Both EPROM and FPGA
d) ROM
View Answer
Answer: c
Explanation: Both FPGA and EPROM are reprogrammable gate array.
12. The difference between FPGA and PLD is that __________

a) FPGA is slower than PLD
b) FPGA has high power dissipation
c) FPGA incorporates logic blocks
View Answer
Answer: c
Explanation: The differences between FPGA and PLD is that FPGA incorporates logic blocks instead of
ixed AND-OR gates and is faster with low power dissipation. FPGAs are designed for having higher gate
count whereas, PLDs are used for lesser gate counts.

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To practice assessment questions on all areas of Digital Electronic Circuits, here is complete set of 1000+

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This set of Digital Electronic/Circuits Puzzles focuses on “Introduction of Memory Devices-3”.
1. Memories are classi ied into _____ categories.

a) 3
b) 4
c) 5
d) 6
View Answer
Answer: c
Explanation: Memory is typically classi ied of 2 types: Primary and Secondary. These are further
classi ied into 5 types of memories and these are Secondary, RAM, Dynamic/Static, Volatile/Non-volatile,
Magnetic/Semiconductor Memory.
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2. Secondary memory is also known as ___________

a) Registers
b) Main Memory
c) RAM
d) Both registers and main memory
View Answer
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Answer: d
Explanation: Secondary memory is also known as Registers/Main Memory. In secondary memory, data is
usually stored for a long-term.
3. In a computer, registers are present __________

a) Within control unit
b) Within RAM
c) Within ROM
d) Within CPU
View Answer
Answer: d
Explanation: In a computer, registers are present within the CPU to store data temporarily during
arithmetic and logical operations and during the functioning of the ALU.
4. Which of the following has the lowest access time?

a) RAM
b) ROM
c) Registers
d) Flag
View Answer
Answer: c
Explanation: Registers has the lowest access time, as they are available inside the CPU. Registers are
present within the CPU to store data temporarily during arithmetic and logical operations and during the
functioning of the ALU.
5. Main memories of a computer, usually made up of __________

a) Registers
b) Semiconductors
c) Counters
d) PLDs
View Answer
Answer: b
Explanation: Main memories of a computer, usually made up of semiconductors which are available
external to the CPU to store program and data during execution of a program. Registers are present
within the CPU to store data temporarily during arithmetic and logical operations and during the
functioning of the ALU.
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6. As the storage capacity of main memory is inadequate, which memory is used to enhance it?
a) Secondary Memory
b) Auxiliary Memory
c) Static Memory
d) Both Secondary Memory and Auxiliary Memory
View Answer
Answer: d
Explanation: As the storage capacity of the main memory is inadequate, Secondary memory is used to
enhance it and it is also known as auxiliary memory. Secondary memory is also known as
Registers/Main Memory. In secondary memory, data is usually stored for a long-term.
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7. Which memories are if magnetic memory type?

a) Main Memory
b) Secondary Memory
c) Static Memory
d) Volatile Memory
View Answer
Answer: b
Explanation: Usually, secondary memories are of magnetic memory type that are used to store large type
quantities of data. In secondary memory, data is usually stored for a long-term.
8. Which of the following comes under secondary memory/ies?

a) Floppy disk
b) Magnetic drum
c) Hard disk
View Answer
Answer: d
Explanation: All of the mentioned equipments are of external storage which is known as secondary
memories. In secondary memory, data is usually stored for a long-term.
9. Based on method of access, memory devices are classi ied into ____________ categories.
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: Based on the method of access, memory devices are classi ied into two categories and these
are sequential access memory and RAM. A sequential access memory is one in which a particular
memory location is accessed sequentially.
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10. A sequential access memory is one in which __________

a) A particular memory location is accessed rapidly
b) A particular memory location is accessed sequentially
c) A particular memory location is accessed serially
d) A particular memory location is accessed parallely
View Answer
Answer: b
Explanation: A sequential access memory is one in which A particular memory location is accessed
sequentially (i.e. the ith memory location is accessed only after sequencing through previous (i-1)
memory locations).
11. An example of sequential access memory is __________

a) Floppy disk
b) Hard disk
c) Magnetic tape memory
d) RAM
View Answer
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Answer: c
Explanation: A sequential access memory is one in which a particular memory location is accessed
sequentially. In magnetic tape memory, data is accessed sequentially.
12. A Random Access Memory is one in which __________

a) Any location can be accessed sequentially
b) Any location can be accessed randomly
c) Any location can be accessed serially
d) Any location can be accessed parallely
View Answer
Answer: b
Explanation: A Random Access Memory is one in which any location can be accessed randomly.
13. An example of RAM is __________

a) Floppy disk
b) Hard disk
c) Magnetic tape memory
d) Semiconductor RAM
View Answer
Answer: d
Explanation: A Random Access Memory is one in which any location can be accessed randomly. A
semiconductor RAM is too much fast and can occupy any space in the memory location.
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14. A static memory is one in which __________

a) Content changes with time
b) Content doesn’t changes with time
c) Memory is static always
d) Memory is dynamic always
View Answer
Answer: d
Explanation: A static memory is one in which content doesn’t changes with time (i.e. stable). Dynamic
memory is one in which content changes with time (i.e. unstable).
15. A dynamic memory is one in which __________

a) Content changes with time
b) Content doesn’t changes with time
c) Memory is static always
d) Memory is dynamic always
View Answer
Answer: d
Explanation: A static memory is one in which content doesn’t change with time (i.e. stable). Dynamic
memory is one in which content changes with time (i.e. unstable).
To practice puzzles on all areas of Digital Electronic Circuits, here is complete set of 1000+ Multiple
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This set of Advanced Digital Electronic/Circuits Questions & Answers focuses on “Introduction of
Memory Devices-4”.
1. Dynamic memory cells use _______________ as the storage device.

a) The reactance of a transistor
b) The impedance of a transistor
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c) The capacitance of a transistor

d) The inductance of a transistor
View Answer
Answer: c
Explanation: Capacitance of a transistor prevents from loss of information in a dynamic memory cell.
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2. To store 1-bit of information, how many transistor is/are used ____________

a) 1
b) 2
c) 3
d) 4
View Answer
Answer: a
Explanation: Only one bit transistor is needed to store 1-bit of information.
3. Static memory holds data as long as __________

a) AC power is applied
b) DC power is applied
c) Capacitor is fully charged
d) High Conductivity
View Answer
Answer: b
Explanation: In any semiconductor equipment, AC power can’t be supplied directly. So, static memory
holds the data as long as DC power is applied.
4. The example of dynamic memory is __________

a) CCD
b) Semiconductor dynamic RAM
c) Both CCD and semiconductor dynamic RAM
d) Floppy-Disk
View Answer
Answer: c
Explanation: The examples of dynamic memories are CCD and semiconductor dynamic RAM because of
the contents of both the memories changes with time.
5. In dynamic memory, CCD stands for __________

a) Charged Count Devices
b) Change Coupled Devices
c) Charge Coupled Devices
d) Charged Compact Disk
View Answer
Answer: b
Explanation: In dynamic memory, CCD stands for Charge Coupled Devices.
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6. Volatile memory refers to __________

a) The memory whose loosed data is achieved again when power to the memory circuit is removed
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b) The memory which looses data when power to the memory circuit is removed
c) The memory which looses data when power to the memory circuit is applied
d) The memory whose loosed data is achieved again when power to the memory circuit is applied
View Answer
Answer: b
Explanation: Volatile means ‘liable to change rapidly’ and volatile memory refers to the memory which
looses data rapidly when power to the memory circuit is removed. Thus, it looks after it’s data as long as
it is powered. Non-volatile means ‘not volatile’ and non-volatile memory refers to the memory which
retains the data even if there is a break in the power supply.
7. Non-volatile memory refers to __________

a) The memory whose loosed data is retained again when power to the memory circuit is
removed/applied
b) The memory which looses data when power to the memory circuit is removed
c) The memory which looses data when power to the memory circuit is applied
d) The memory whose loosed data is achieved again when power to the memory circuit is applied
View Answer
Answer: a
Explanation: Volatile means ‘liable to change rapidly’ and volatile memory refers to the memory which
looses data rapidly when power to the memory circuit is removed. Thus, it looks after it’s data as long as
it is powered. Non-volatile means ‘not volatile’ and non-volatile memory refers to the memory which
retains the data even if there is a break in the power supply.
8. The example of non-volatile memory device is __________

a) Magnetic Core Memory
b) Read Only Memory
c) Random Access Memory
d) Both Magnetic Core Memory and Read Only Memory
View Answer
Answer: d
Explanation: Non-volatile means ‘not volatile’ and non-volatile memory refers to the memory which
retains the data even if there is a break in the power supply. The examples of non-volatile memory
devices are Magnetic Core Memory & ROM because both have capability to retain the data.
9. Based on material used for construction, memory devices are classi ieds into ________ categories.
a) 2
b) 3
c) 4
d) 5
View Answer
Answer:a
Explanation: Based on material used for construction, memory devices are classi ieds into two
categories, viz., Magnetic and Semiconductor memory. Magnetic recording is the process of storing data
magnetically. Hard disk, loppy disk, magnetic tape are the examples of magnetic recording process.
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10. Magnetic recording is the process of __________

a) Storing data symmetrically
b) Storing data sequentially
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c) Storing data magnetically

d) Both storing data symmetrically and
View Answer
Answer: c
Explanation: Based on material used for construction, memory devices are classi ieds into two
categories, viz., Magnetic and Semiconductor memory. Magnetic recording is the process of storing data
magnetically. Hard disk, loppy disk, magnetic tape are the examples of the magnetic recording process.
11. Magnetic drum is a storage medium using __________

a) The surface of a jumping magnetic drum
b) The surface of a rotating magnetic drum
c) The surface of a stopped magnetic drum
d) The surface of a moving magnetic drum
View Answer
Answer: b
Explanation: Magnetic drum is a storage medium using the surface of a rotating magnetic drum which
have tendency to hold the data.
12. Magnetic core is the digital memory in which data is stored magnetically in individual cores operated
by __________
a) Up and down select wires
b) Row and column select wires
c) Serial and parallel select wires
d) Up and Serial select wires
View Answer
Answer: b
Explanation: Magnetic core is the digital memory in which data is stored magnetically in individual cores
operated by row and column select wires, with data obtained from sense wire.
13. By which technology, semiconductor memories are constructed?

a) PLD
b) LSI
c) VLSI
d) Both LSI and VLSI
View Answer
Answer: d
Explanation: Generally, semiconductor memories are constructed using Large Scale Integration (LSI) or
Very Large Scale Integration (VLSI) because these are made up of NMOS, CMOS, BJT etc.
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This set of Digital Electronic Circuits Questions & Answers for campus interviews focuses on
“Introduction of Memory Devices-5”.
1. When two or more devices try to write data in a bus simultaneously, is known as ______________
a) Bus collisions
b) Address multiplexing
c) Address decoding
d) Bus contention
View Answer
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Answer: d
Explanation: Bus contention is an undesirable state of the bus of a computer, in which more than one
memory mapped device or the CPU is attempting to place output values onto the bus at once.
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2. A memory is a collection of ____________

a) Unit cells
b) Storage cells
c) Data cells
d) Binary cells
View Answer
Answer: b
Explanation: A memory is a collection of storage cells with associated circuits needed to transfer
information.
3. To transfer the information from input to output and vice versa, the cells used are ____________
a) Storage cells
b) Data cells
c) Unit cells
d) Both data and unit cells
View Answer
Answer: a
Explanation: To transfer the information from input to output and vice versa, the cells used are called
storage cells. The storage cells stores data in the form of binary information.
4. The data stored in a group of bits is called ____________

a) Nibble
b) Word
c) Byte
d) Address
View Answer
Answer: b
Explanation: The data stored in a group of bits is called word. Usually, a word is a group of 16-bits or 2-
bytes.
5. Each word consist of a sequence of ____________

a) Letters
b) Binary numbers
c) Hexadecimal numbers
d) Gray codes
View Answer
Answer: b
Explanation: Each word consist of a sequence of 0s and 1s (i.e. binary numbers). Usually, a word is a
group of 16-bits or 2-bytes.
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6. Each word stored in a memory location is represented by ____________

a) RAM
b) ROM
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c) Storage class
d) Address
View Answer
Answer: d
Explanation: Each word stored in a memory location is represented by address. Usually, a word is a
group of 16-bits or 2-bytes.
7. The group of each 8-bit is called ____________

a) Nibble
b) Flag
c) Byte
d) Word
View Answer
Answer: c
Explanation: 1 byte = 8-bit, 4-bits = 1 nibble and 16-bits = 1 word.
8. The capacity of a memory unit is ____________

a) The number of binary input stored
b) The number of words stored
c) The number of bytes stored
View Answer
Answer: c
Explanation: The total number of bytes that can be stored, is the maximum capacity of a memory unit.
However, memory unit is the smallest unit of a processor.
9. The communication between memory and its environment is achieved through ____________
a) Control lines
b) Data input/output lines
c) Address selection lines
View Answer
Answer: d
Explanation: Firstly, the data input is needed to transfer the information and it is passed through the
address lines and then controlled by control lines. The control lines are responsible for the timing and
control of the signals sent and received.
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10. One of the most important speci ications on magnetic media is the ____________
a) Polarity reversal rate
b) Tracks per inch
c) Data transfer rate
d) Rotation speed
View Answer
Answer: c
Explanation: The rate of data transfer depends on the properties of magnetic media.

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Digital Circuits Questions and Answers – Read

Only Memory (ROM) – 1
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Read
Only Memory (ROM) – 1”.
11/5/2020 deld.html
1. Which of the following has the capability to store the information permanently?
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM
View Answer
Answer: b
Explanation: ROM (Read Only Memory) has the capability to store the information permanently. RAM
provides random access to memory. Storage cells are responsible for the transfer of data from and into
the memory.
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2. ROM has the capability to perform _____________

a) Write operation only
b) Read operation only
c) Both write and read operation
d) Erase operation
View Answer
Answer: b
Explanation: ROM means “Read Only Memory”. Hence, it has capability to perform read operation only.
No write or erase operation could be performed in the ROM.
3. Since, ROM has the capability to read the information only then also it has been designed, why?
a) For controlling purpose
b) For loading purpose
c) For booting purpose
d) For erasing purpose
View Answer
Answer: c
Explanation: ROM means “Read Only Memory”. Hence, it has capability to perform read operation only.
No write or erase operation could be performed in the ROM. It has designed to provide the computer
with resident programmes and for booting purpose.
4. The ROM is a ___________

a) Sequential circuit
b) Combinational circuit
c) Magnetic circuit
d) Static circuit
View Answer
Answer: b
Explanation: ROM is a combination of different ICs. So, it is a combinational circuit.
It depends on present input and not past states.
5. ROM is made up of ___________

a) NAND and OR gates
b) NOR and decoder
c) Decoder and OR gates
d) NAND and decoder
View Answer
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Answer: c
Explanation: ROM (Read Only Memory) has the capability to store the information permanently. ROM is
made up of decoder and OR gates within a single IC package.
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6. Why are ROMs called non-volatile memory?

a) They lose memory when power is removed
b) They do not lose memory when power is removed
c) They lose memory when power is supplied
d) They do not lose memory when power is supplied
View Answer
Answer: b
Explanation: Volatile memory stores data as long as it is powered. ROMs are called non-volatile memory
because of they do not lose memory when power is removed.
7. In ROM, each bit is a combination of the address variables is called ___________

a) Memory unit
b) Storage class
c) Data word
d) Address
View Answer
Answer: d
Explanation: In ROM, each bit combination that comes out of the output lines is called data word. Usually,
a word consists of 16-bits or 2-bytes.
8. Which is not a removable drive?

a) Zip
b) Hard disk
c) Super Disk
d) Jaz
View Answer
Answer: c
Explanation: Hard disk is present inside a computer. So, it is not a removable drive.
9. In ROM, each bit combination that comes out of the output lines is called ___________
a) Memory unit
b) Storage class
c) Data word
d) Address
View Answer
Answer: c
Explanation: In ROM, each bit combination that comes out of the output lines is called data word. Usually,
a word consists of 16-bits or 2-bytes.
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10. VLSI chip utilizes ___________

a) NMOS
b) CMOS
c) BJT
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View Answer
Answer: d
Explanation: Very Large Scale Integration (VLSI) (ranging from 10,000 to 100,000 gates per IC) is a
memory chip which is made up of NMOS, CMOS, BJT, and BiCMOS.
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This set of tricky Digital Electronic/Circuits questions and answers focuses on “Read Only Memory(ROM)
– 2”.
1. The MOS technology based semiconductor ROMs are classi ied into _____ categories.
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: b
Explanation: The MOS technology based semiconductor ROMs are classi ied into three categories: Mask
ROM, PROM,& EPROM. PROM stands for Programmable Read Only Memory in which the ROM can be
externally programmed by the user. EPROM stands for Erasable Programmable Read Only Memory,
where the ROM and be cleared and re-programmed.
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2. MOS ROM is constructed using __________

a) FETs
b) Transistors
c) MOSFETs
d) BJTs
View Answer
Answer: c
Explanation: MOS ROM is made up of MOSFETs. MOSFETs are Metal Oxide Semiconductor Field Effect
Transistors.
3. The full form of EEPROM is __________

a) Erasable Electrically Programmable ROMs
b) Electrically Erasable Programmable ROMs
c) Electrically Erasable Programming ROMs
d) Electrically Erasable Programmed ROMs
View Answer
Answer: b
Explanation: The full form of EEPROM is Electrically Erasable Programmable ROMs. In EPROM (Erasable
Programmable ROMs), the ROM is cleared by exposing it to UV radiation and also it’s a tedious process.
Whereas, in EEPROM, the ROM can be cleared electrically and thus is less time consuming and more
ef icient.
4. Which of the following best describes EPROMs?

a) EPROMs can be programmed only once
b) EPROMs can be erased by UV
c) EPROMs can be erased by shorting all inputs to the ground
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d) EPROMs can be erased electrically

View Answer
Answer: b
Explanation: EPROM (Erasable Programmable ROMs), the ROM is cleared by exposing it to UV radiation
and also it’s a tedious process. Whereas, in EEPROM, the ROM can be cleared electrically and thus is less
time consuming and more ef icient.
5. The Width of a processor’s data path is measured in bits. Which of the following are common data
paths?
a) 8 bits
b) 12 bits
c) 16 bits
d) 32 bits
View Answer
Answer: a
Explanation: In generalised form, the data paths are of 8 bits. The data path, also known as data bus, is
the channel through which the processor sends and receives data.
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6. What type of memory is not directly addressable by the CPU and requires special software called EMS
(expanded memory speci ication)?
a) Extended
b) Expanded
c) Base
d) Conventional
View Answer
Answer: b
Explanation: Expanded memory is not directly addressable by the CPU. Expanded memory is the
additional memory which is incorporated beyond the parent memory limit of the processor.
7. Which bus is used for input and output in case of microprocessor operation?
a) Address bus
b) System bus
c) Control bus
d) Data bus
View Answer
Answer: c
Explanation: The input and output are used to control the function of a microprocessor. Hence, the
control bus is used to transfer the input and output signal from microprocessor to external peripherals
and or from external peripherals to microprocessor.
8. What is the major difference between DRAM and SRAM?

a) Dynamic RAMs are always active; static RAMs must reset between data read/write cycles
b) SRAMs can hold data via a static charge, even with power off
c) The only difference is the terminal from which the data is removed—from the FET Drain or Source
d) DRAMs must be periodically refreshed
View Answer
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Answer: d
Explanation: DRAMs must be periodically refreshed so that it can store the new information. DRAMs are
slower compared to SRAMs as the access time for SRAM is less than that of DRAM.
9. Which of the following is not a part of Hard disk?

a) Platter
b) Read/Write
c) Valve
d) Spindle
View Answer
Answer: c
Explanation: A valve is a device that regulates, directs or controls the low of a luid (gases, liquids,
luidized solids, or slurries) by opening, closing, or partially obstructing various passageways. So, it is not
a part of hard disk.
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10. Which ROM can be erased by an electrical signal?

a) ROM
b) Mask ROM
c) EPROM
d) EEPROM
View Answer
Answer: d
Explanation: In EPROM (Erasable Programmable ROMs), the ROM is cleared by exposing it to UV
radiation and also it’s a tedious process. Whereas, in EEPROM, the ROM can be cleared electrically and
thus is less time consuming and more ef icient.
11. In the loppy drive, data is written to and read from the disk via a magnetic _____ head mechanism.
a) Cluster
b) Read/Write
c) Cylinder
d) Recordable
View Answer
Answer: b
Explanation: A loppy disk is a removable disk used for storing data via magnetic facilities. In the loppy
drive, data is written to and read from the disk via a magnetic read/write head mechanism.
12. What does the term “random access” mean in terms of memory?
a) Any address can be accessed in systematic order
b) Any address can be accessed in any order
c) Addresses must be accessed in a speci ic order
d) Any address can be accessed in reverse order
View Answer
Answer: b
Explanation: “Random access” mean which can be accessed randomly and in other words any address
can be accessed in any order.
13. Which type of ROM has to be custom built by the factory?

a) EEPROM
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b) Mask ROM
c) EPROM
d) PROM
View Answer
Answer: b
Explanation: All types of ROM are programmable and can be programmed as per requirement but the
mask ROM is always programmed for speci ic application and it can’t be reprogrammed. PROM stands
for Programmable Read Only Memory in which the ROM can be externally programmed by the user.
EPROM stands for Erasable Programmable Read Only Memory, where the ROM and be cleared and re-
programmed.
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14. The computer’s main memory is __________

a) Hard drive and RAM
b) CD-ROM and hard drive
c) RAM and ROM
d) CMOS and hard drive
View Answer
Answer: c
Explanation: The computer’s main memory is RAM and ROM because all the storage related operation
are performed by the data present in RAM/ROM. RAM stands for Random Access Memory where any
address can accessed in any order. ROM stands for Read Only Memory wherefrom data can only be read.
15. A major disadvantage of the mask ROM is that ____________

a) It is time consuming to change the stored data when system requirements change
b) It is very expensive to change the stored data when system requirements change
c) It cannot be reprogrammed if stored data needs to be changed
d) It has an extremely short life expectancy and requires frequent replacement
View Answer
Answer: c
Explanation: A major disadvantage of the mask ROM is that it cannot be reprogrammed if stored data
needs to be changed. PROM stands for Programmable Read Only Memory in which the ROM can be
externally programmed by the user. EPROM stands for Erasable Programmable Read Only Memory,
where the ROM and be cleared and re-programmed.
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1000+ Multiple Choice Questions and Answers.

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This set of Digital Electronic/Circuits Aptitude Test focuses on “Read Only Memory(ROM)-3”.
1. ROM may be programmed in _____ ways.

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: ROM may be programmed in two different ways: (i) Mask Programming & (ii) PROM. Mask
Programming is done by the manufacture. Whereas, PROM(Programmable ROM) is programmed by the
user.
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2. Which programming is done during manufacturing process?

a) Mask Programming
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b) PROM
c) Both PROM and mask programming
d) EPROM
View Answer
Answer: a
Explanation: Mask ROM is permanently programmed during the manufacturing process. Whereas,
PROM(Programmable ROM) is programmed by the user.
3. A photographic negative is called a ____________

a) Photo
b) Negative
c) Mask
d) Virtual image
View Answer
Answer: c
Explanation: A photographic negative is called a mask is used to control the electrical connections on the
chip.
4. Mask programming is also known as __________

a) EPROM
b) PROM
c) Custom programming
d) Both PROM and EPROM
View Answer
Answer: c
Explanation: Mask programming is also known as custom programming. Mask ROM is permanently
programmed during the manufacturing process. Whereas, PROM(Programmable ROM) is programmed
by the user.
5. The total storage capacity of 16 * 8 ROM is __________

a) 8 bits
b) 16 bits
c) 128 bits
d) 64 bits
View Answer
Answer: c
Explanation: ROM stands for Read Only Memory in which data is stored permanently and wherefrom
data can only be read and rarely modi ied. The total storage capacity of 16 * 8 ROM is 128 bits (i.e. 16 * 8
= 128).
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6. Which IC is a typical MSI/TTL based?

a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
View Answer
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Answer: a
Explanation: MSI/TTL stands for Medium Scale Integration of Transistor-Transistor Logic. IC 74187 is a
typical MSI/TTL based.
7. IC 74187 is of __________
a) 512 bits
b) 1024 bits
c) 256 bits
d) 68 bits
View Answer
Answer: b
Explanation: IC 74187 is of 1024 bits because it is organised as 256 * 4. Thus, it has 256 rows and 4
columns.
8. How many rows and columns are present in IC 74187?

a) 128, 3
b) 128, 4
c) 256, 3
d) 256, 4
View Answer
Answer: d
Explanation: IC 74187 is organised as 256 * 4, hence it has 256 rows and 4 columns.
IC 74187 is of 1024 bits because it is organized as 256 * 4.
9. Which of the following IC is of 256 bit?

a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
View Answer
Answer: c
Explanation: IC 74188 is of 256 bits. Since, it is organised as 32 * 8 = 256. Thus, it has 32 rows and 8
columns.
10. Which IC is known as bipolar ROM?

a) IC 74187
b) IC 74189
c) IC 74188
d) IC 74186
View Answer
Answer: c
Explanation: IC 74188 is known as bipolar ROM since it is made up of TTL logic.
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11. How many address location a bipolar ROM has?

a) 16
b) 32
c) 64
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d) 8
View Answer
Answer: b
Explanation: Bipolar ROM means IC 74188 and it is organized as 32 * 8. Thus, it has 32 rows and 8
columns. So, it has 32 address locations and each of which has 8 bits of storage.
12. Which of the following is known as MOS static ROM?

a) TMS 45276
b) TMS 45278
c) TMS 45279
d) TMS 45275
View Answer
Answer: a
Explanation: TMS 45276 is known as MOS static ROM and it is made up of MOSFETs.
13. TMS 45276 is of __________

a) 32 KB
b) 56 KB
c) 8 bits
d) 4 bytes
View Answer
Answer: a
Explanation: TMS 45276 is known as MOS static ROM and it is made up of MOSFETs. In ROM, the data
remains even when the power is switched off. TMS 45276 is of 32 KB.
14. Which of the following has the capability to store the highest bits of data?
a) TMS 45276
b) IC 74188
c) IC 74187
d) IC 74185
View Answer
Answer: a
Explanation: TMS 45276 has the capability to store the highest bits of data because of 32768 * 8 =
12,62,144 organization.
15. What does CS mean in a chip?

a) Storing Capacity
b) Custom Select
c) Chip Select
d) Custom Storage
View Answer
Answer: c
Explanation: CS means chip select and with the help of CS a chip is activated/deactivated. It is used for
enabling or disabling the function of the chip.
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16. ROMs are used to __________

a) Store bootstrap program
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b) Character generation
c) Code conversion
View Answer
Answer: d
Explanation: ROM stands for Read Only Memory in which data is permanently stored, even when the
power is turned off. It is used to store bootstrap program, character generation and code conversion.
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Programmable Read Only Memory – 1
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“Programmable Read Only Memory -1”.
1. The time from the beginning of a read cycle to the end of tACS/tAA is called as ____________
a) Write enable time
b) Data hold
c) Read cycle time
d) Access time
View Answer
Answer: d
Explanation: The time from the beginning of a read cycle to the end of tACS/tAA is called as access time.
It is the time in which data is fetched from the storage.
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2. Why did PROM introduced?

a) To increase the storage capacity
b) To increase the address locations
c) To provide lexibility
d) To reduce the size
View Answer
Answer: c
Explanation: In order to provide some lexibility in the possible applications of ROM, PROM is introduced.
PROM stands for Programmable ROM, in which the ROM is programmed by the user.
3. Which of the following is programmed electrically by the user?

a) ROM
b) EPROM
c) PROM
d) EEPROM
View Answer
Answer: c
Explanation: Programmable ROMs can be programmed electrically by the user but can’t be
reprogrammed. EEPROMs can be electrically erased and re-programmed by the user.
4. PROMs are available in ___________

a) Bipolar and MOSFET technologies
b) MOSFET and FET technologies
c) FET and bipolar technologies
d) MOS and bipolar technologies
View Answer
Answer: d
Explanation: PROMs (Programmable ROMs) can be programmed electrically by the user but can’t be
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reprogrammed. PROMs are available in both bipolar and MOS (Metal Oxide Semiconductor) technologies.
5. The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is
___________
a) 4096
b) 16384
c) 32768
d) 8129
View Answer
Answer: b
Explanation: 1 address can store 8 bits. Therefore, total capacity of a memory having n addresses = 8 * n.
Therefore, for 2048 addresses,
total capacity of a memory = 2048 * 8 = 16384 bits.
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6. How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word
length of eight bits?
a) Eight
b) Two
c) One
d) Four
View Answer
Answer: a
Explanation: RAM stands for Random Access Memory in which any memory address can be accessed in
any order. It requires word of length 8 bits. So, one word needs of 1 bit and 8 bit requires 8 bits.
7. Which of the following best describes the fusible-link PROM?

a) Manufacturer-programmable, reprogrammable
b) Manufacturer-programmable, one-time programmable
c) User-programmable, reprogrammable
d) User-programmable, one-time programmable
View Answer
Answer: d
Explanation: The fusible-link PROM is user programmable and one time programmable. It means that a
written program can not be reprogrammed. EPROMs can be erased and re-programmed.
8. How can ultraviolet erasable PROMs be recognized?

a) There is a small window on the chip
b) They will have a small violet dot next to the #1 pin
c) Their part number always starts with a “U”, such as in U12
d) They are not readily identi iable, since they must always be kept under a small cover
View Answer
Answer: a
Explanation: An ultraviolet erasable PROMs have small window on the chip with black marked. Such type
of PROMS are called EPROMS which are cleared by exposing it to UV radiation. They are re-
programmable.
9. Which part of a Flash memory architecture manages all chip functions?

a) Program verify code
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b) Floating-gate MOSFET
c) Command code
d) Input/Output pins
View Answer
Answer: b
Explanation: MOSFET technology is the best one in the manufacturing of chip because it has high
lexibility and storage capacity. Thus, Floating-Gate MOSFET part of a Flash Memory architecture
manages all chip functions.
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10. How much locations an 8-bit address code can select in memory?
a) 8 locations
b) 256 locations
c) 65,536 locations
d) 131,072 locations
View Answer
Answer: b
Explanation: An 8 bit address code requires 32 memory locations and it can hold maximum upto 32 * 8
= 256 locations = 28.
11. What is a fusing process?

a) It is a process by which data is passed to the memory
b) It is a process by which data is read through the memory
c) It is a process by which programs are burnout to the diode/transistors
d) It is a process by which data is fetched through the memory
View Answer
Answer: c
Explanation: Fusing is a process by which programs are burnout to the diode/transistors and it can not
be reprogrammed if any error occurs.
12. Fusing process is ___________

a) Reversible
b) Irreversible
c) Synchronous
d) Asynchronous
View Answer
Answer: b
Explanation: Since, any program cannot be reprogrammed in a PROM, so this process is irreversible as
PROMs are programmed using the Fusing process. Fusing is a process by which programs are burnout
to the diode/transistors and it can not be reprogrammed if any error occurs.
13. The cell type used inside a PROM is ___________

a) Link cells
b) Metal cells
c) Fuse cells
d) Electric cells
View Answer
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Answer: c
Explanation: The cell type used inside a PROM is fuse cells by which a program is burnout. Fusing is a
process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any
error occurs.
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14. How many types of fuse technologies are used in PROMs?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: b
Explanation: Fusing is a process by which programs are burnout to the diode/transistors and it can not
be reprogrammed if any error occurs. Three types of fuse technologies are used in PROMs and these
are: (i) Metal links, (ii) Silicon links, & (iii) p-n junctions.
15. Metal links are made up of ___________

a) Polycrystalline
b) Magnesium sulphide
c) Nichrome
d) Silicon dioxide
View Answer
Answer: c
Explanation: Metal links are made up of Nichrome materials.
Answers.

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Programmable Read Only Memory – 2
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This set of Digital Electronic/Circuits Problems focuses on “Programmable Read Only Memory-2”.
1. Silicon links are made up of _____________

a) Polycrystalline silicon
b) Polycrystalline magnesium
c) Nichrome
d) Silicon dioxide
View Answer
Answer: a
Explanation: Metal links are made up of Nichrome materials. Silicon links are made up of polycrystalline
silicon.
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2. During programming p-n junction is _____________

a) Avalanche reverse biased
b) Avalanche forward biased
c) Zener reverse biased
d) Zener reverse biased
View Answer
Answer: a
Explanation: The sudden heavy low of electrons in the reverse direction and heat cause aluminium ions
to migrate. So, during programming p-n junction is avalanche reversed biased.
3. The full form of FAMOS is _____________

a) Floating Gate Avalanche Injection MOS
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b) Float Gate Avalanche Injection MOS

c) Floating Gate Avalanche Induction MOS
d) Float Gate Avalanche Induction MOS
View Answer
Answer: a
Explanation: The full form of FAMOS is Floating Gate Avalanche Injection MOS. It is a loating gate
transistor in which the trapped electrons is responsible for the dropping of the voltage.
4. PROM is programmed by _____________

a) EPROM programmer
b) EEPROM programmer
c) PROM programmer
d) ROM programmer
View Answer
Answer: c
Explanation: PROM is programmed by plugging it into a special device called PROM programmer. The
ROM cannot be clear and hence PROM is a one-time programmable device.
5. The PROM starts out with _____________

a) 1s
b) 0s
c) Null
d) Both 1s and 0s
View Answer
Answer: b
Explanation: PROM is a one-time programmable device, which is programmed by the user. The PROM
starts out with all 0s. These current pulses blow the fuse links, thus creating the desire pattern.
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6. For implementation of PROM, which IC is used?

a) IC 74187
b) IC 74186
c) IC 74185
d) IC 74184
View Answer
Answer: b
Explanation: For implementation of PROM, IC 74186 is used. IC 74186 is of 512 bits (62 * 8 = 512). Thus,
it has 62 rows and 8 columns.
7. IC 74186 is of ______________
a) 1024 bits
b) 32 bits
c) 512 bits
d) 64 bits
View Answer
Answer: c
Explanation: IC 74186 is of 512 bits (62 * 8 = 512). Thus, it has 62 rows and 8 columns.
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8. How many memory locations are addressed using 18 address bits?

a) 165,667
b) 245,784
c) 262,144
d) 212,342
View Answer
Answer: c
Explanation: For n address bits, the memory location will consist of 2n bits. Using 18 address bits, 2^18 =
262,144 (= 256 K) words are addressed.
9. How many address bits are needed to operate a 2K * 8-bit memory?

a) 10
b) 11
c) 12
d) 13
View Answer
Answer: b
Explanation: For n address bits, the memory location will consist of 2n bits. Thus, for 2K, only 11 address
bits are required, because 211 = 2K.
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10. What is the bit storage capacity of a ROM with a 1024 × 8 organization?
a) 1024
b) 4096
c) 2048
d) 8192
View Answer
Answer: d
Explanation: For n address bits, the memory location will consist of 2n bits. 1024 = 210. So, 210 * 23 =
1024 * 8 = 8192 bit.
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Erasable Programmable Read Only Memory
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Erasable
Programmable Read Only Memory”.
1. EPROM uses an array of _______________

a) p-channel enhancement type MOSFET
b) n-channel enhancement type MOSFET
c) p-channel depletion type MOSFET
d) n-channel depletion type MOSFET
View Answer
Answer: b
Explanation: EPROMs are Erasable Programmable ROMs which can be erased using UV radiation and re-
programmed. EPROM uses an array of n-channel enhancement type MOSFET with an insulated gate
structure.
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2. The EPROM was invented by ______________

a) Wen Tsing Chow
b) Dov Frohman
c) Luis O Brian
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d) J P Longwell
View Answer
Answer: b
Explanation: The EPROM was invented by Dov Frohman of Intel in 1971. EPROMs are Erasable
Programmable ROMs which can be erased using UV radiation and re-programmed.
3. Address decoding for dynamic memory chip control may also be used for ______________
a) Chip selection and address location
b) Read and write control
c) Controlling refresh circuits
d) Memory mapping
View Answer
Answer: a
Explanation: Address decoding for dynamic memory chip control may also be used for chip selection
and address location. Chip Selection enables or disables the functioning of the chip.
4. Which of the following describes the action of storing a bit of data in a mask ROM?
a) A 0 is stored by connecting the gate of a MOS cell to the address line
b) A 0 is stored in a bipolar cell by shorting the base connection to the address line
c) A 1 is stored by connecting the gate of a MOS cell to the address line
d) A 1 is stored in a bipolar cell by opening the base connection to the address line
View Answer
Answer: c
Explanation: The action of storing a bit of data in a mask ROM is that when a 1 is stored by connecting
the gate of a MOS cell to the address line. Mask ROMs are programmed by the manufacturer and are
custom made as per the user.
5. The check sum method of testing a ROM ______________

a) Allows data errors to be pinpointed to a speci ic memory location
b) Provides a means for locating and correcting data errors in speci ic memory locations
c) Indicates if the data in more than one memory location is incorrect
d) Simply indicates that the contents of the ROM are incorrect
View Answer
Answer: d
Explanation: If checking of a sum method goes wrong, it simply indicates that the contents of the ROM
are incorrect.
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6. The initial values in all the cells of an EPROM is ______________

a) 0
b) 1
c) Both 0 and 1
d) Alternate 0s and 1s
View Answer
Answer: b
Explanation: The initial values in all the cells of a EPROM is 1.
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7. To store 0 in such a cell, the loating point must be ______________

a) Reprogrammed
b) Restarted
c) Charged
d) Power off
View Answer
Answer: c
programmed. To store 0 in the cell of an EPROM, the loating point must be charged.
8. The major disadvantage of RAM is?

a) Its access speed is too slow
b) Its matrix size is too big
c) It is volatile
d) High power consumption
View Answer
Answer: c
Explanation: RAM is volatile memory. Thus, RAM stores the data as long as it is powered on and once the
power goes out, it loses its data.
9. Which one of the following is used for the fabrication of MOS EPROM?
a) TMS 2513
b) TMS 2515
c) TMS 2516
d) TMS 2518
View Answer
Answer: c
programmed. TMS 2516 is a MOS EPROM device.
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10. How many addresses a MOS EPROM have?

a) 1024
b) 512
c) 2516
d) 256
View Answer
Answer: c
programmed. MOS EPROM (i.e. TMS 2516) has 2048 (2^11 = 2048) addresses.
11. To read from the memory, the select input and the power down/program input must be ______________
a) HIGH
b) LOW
c) Sometimes HIGH and sometimes LOW
d) Alternate HIGH and LOW
View Answer
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Answer: b
Explanation: To read from the memory, the select input and the power down/program input must be
LOW.
12. ROMs retain data when ______________

a) Power is on
b) Power is off
c) System is down
View Answer
Answer: d
Explanation: ROM retains the data when power is off/on/down because it has to read the data from
memory only and it is done in every condition. It is non-volatile memory.
13. Suppose that a certain semiconductor memory chip has a capacity of 8K × 8. How many bytes could
be stored in this device?
a) 8,000
b) 65,536
c) 8,192
d) 64,000
View Answer
Answer: c
Explanation: 8K = 8 * 1024 = 8192.
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14. When a RAM module passes the checker board test it is ______________
a) Able to read and write only 0s
b) Faulty
c) Probably good
d) Able to read and write only 1s
View Answer
Answer: c
Explanation: When a RAM module passes the checker board test it is probably good. It is a volatile
memory. Thus, RAM stores the data as long as it is powered on and once the power goes out, it loses its
data.
15. What is the difference between static RAM and dynamic RAM?
a) Static RAM must be refreshed, dynamic RAM does not
b) There is no difference
c) Dynamic RAM must be refreshed, static RAM does not
d) SRAM is slower than DRAM
View Answer
Answer: c
Explanation: Dynamic RAM must be refreshed because it made up of capacitor, and capacitor required
refresh. Static RAM made up of lip lop and it doesn’t required a refresh.
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Answers.

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Digital Circuits Questions and Answers – Random

Access Memory – 1
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This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Random
Access Memory – 1”.
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1. What is access time?

a) The time taken to move a stored word from one bit to other bits after applying the address bits
b) The time taken to write a word after applying the address bits
c) The time taken to read a stored word after applying the address bits
d) The time taken to erase a stored word after applying the address bits
View Answer
Answer: c
Explanation: The access time is the time taken to read a stored word after applying the address bits in a
MOS EPROM. It is the time required to fetch data from the memory.
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2. What are the typical values of tOE?

a) 10 to 20 ns for bipolar
b) 25 to 100 ns for NMOS
c) 12 to 50 ns for CMOS
View Answer
Answer: d
Explanation: The access time is the time taken to read a stored word after applying the address bits in a
MOS EPROM. It is the time required to fetch data from the memory. The typical values of tOE (i.e. access
time) are 10 to 20 ns for bipolar, 25 to 100 ns for NMOS and 12 to 50 ns for CMOS.
3. Which of the following is not a type of memory?

a) RAM
b) FPROM
c) EEPROM
d) ROM
View Answer
Answer: c
Explanation: EEPROM (Electrical Erasable Programmable ROM) is not a type of memory because it is
used for erasing purpose only. Through EEPROM, data can be erased electrically, thereby consuming less
time.
4. The chip by which both the operation of read and write is performed __________
a) RAM
b) ROM
c) PROM
d) EPROM
View Answer
Answer: a
Explanation: A Random Access Memory (RAM) is a volatile chip memory in which both the read and
write operations can be performed. Since it is volatile, therefore it stores data as long as power is on.
5. RAM is also known as __________

a) RWM
b) MBR
c) MAR
d) ROM
View Answer
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Answer: a
Explanation: A Random Access Memory (RAM) is a volatile chip memory in which both the read and
write operations can be performed. Since it is volatile, therefore it stores data as long as power is on.
RAM is also known as RWM (i.e. Read Write Memory).
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6. If a RAM chip has n address input lines then it can access memory locations upto __________
a) 2(n-1)
b) 2(n+1)
c) 2n
d) 22n
View Answer
Answer: c
Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is also
known as RWM (i.e. Read Write Memory). If a RAM chip has n address input lines then it can access
memory locations upto 2n.
7. The n-bit address is placed in the __________

a) MBR
b) MAR
c) RAM
d) ROM
View Answer
Answer: b
Explanation: The n-bit address is placed in the Memory Address Register (MAR) to select one of 2n
memory locations. It stores the address of the instruction which is to be executed next.
8. Which of the following control signals are selected for read and write operations in a RAM?
a) Data buffer
b) Chip select
c) Read and write
d) Memory
View Answer
Answer: c
Explanation: Read and write are control signals that are used to enable memory for read and write
operations respectively.
9. Computers invariably use RAM for __________

a) High complexity
b) High resolution
c) High speed main memory
d) High lexibility
View Answer
Answer: c
known as RWM (i.e. Read Write Memory). Computers invariably use RAM for their high high-speed main
memory and then use backup or slower-speed memories to hold auxiliary data.
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10. How many types of RAMs are?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: There are two types of RAM and these are static and dynamic. Static RAM(SRAM) is faster
than dynamic RAM(DRAM) as the access time for DRAM is more compared to that of SRAM.
11. Static RAM employs __________

a) BJT or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
View Answer
Answer: d
Explanation: Static RAM employs bipolar or MOS lip- lops because both the semiconductor has storing
capacity. Thus, it’s access time is less and it is faster in operation.
12. Dynamic RAM employs __________

a) Capacitor or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
View Answer
Answer: a
Explanation: Dynamic RAM employs a capacitor or MOSFET. Thus, it’s access time is more and it is slower
in operation.
13. Which one of the following is volatile in nature?

a) ROM
b) EROM
c) PROM
d) RAM
View Answer
Answer: d
known as RWM (i.e. Read Write Memory). RAMs are volatile because the stored data will be lost once the
d.c. power applied to the lip- lops is removed.
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14. The magnetic core memories have been replaced by semiconductor RAMs, why?
a) Semiconductor RAMs are highly lexible
b) Semiconductor RAMs have highest storing capacity
c) Semiconductor RAMs are smaller in size
View Answer
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Answer: d
known as RWM (i.e. Read Write Memory). The magnetic core memories have been replaced by
semiconductor RAMs because of smaller in size, high storing capacity as well as lexibility.
15. The data written in lip- lop remains stored as long as __________
a) D.C. power is supplied
b) D.C. power is removed
c) A.C. power is supplied
d) A.C. power is removed
View Answer
Answer: a
Explanation: Since lip- lops are made up of semiconductor materials. So, it can’t accept A.C. source and
the data written in lip- lop remains stored as long as the dc power is maintained.
Answers.

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Access Memory – 2
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This set of tough Digital Electronic/Circuits Questions focuses on “Random Access Memory-2”.
1. The memory capacity of a static RAM varies from ____________

a) 32 bit to 64 bit
b) 64 bit to 1024 bit
c) 64 bit to 1 Mega bit
d) 512 bit to 1 Mega bit
View Answer
Answer: c
Explanation: Static RAM(SRAM ) is faster than dynamic RAM(DRAM) as the access time for DRAM is
more compared to that of SRAM. The memory capacity of a static RAM varies from 64 bits to 1 Mega bit.
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2. The input data bit is written into the cell by setting ____________
a) The lip- lop for 1
b) Resetting the lip- lop
c) The lip- lop for HIGH
d) Both the lip- lop for 1 and resetting the lip- lop
View Answer
Answer: d
Explanation: The input data bit (1 or 0) is written into the cell by setting the lip- lop for 1 and the
resetting the lip- lop for a 0 when the R/W’ line is low, R/W is active-low pin.
3. When the READ/(WRITE)’ line is HIGH then the lip- lop is ____________
a) Activated
b) Deactivated
c) Unaffected
d) Both activated and deactivated
View Answer
Answer: c
Explanation: When the READ/(WRITE)’ line is HIGH then the lip- lop is unaffected since it’s an active
low pin. It means that the stored bit (data) is gated to the data out line.
4. The lip- lop in static memory cell can be constructed using ____________
a) Capacitor or MOSFET
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b) FET or JFET
c) Capacitor or BJT
d) BJT or MOSFET
View Answer
Answer: d
Explanation: The lip- lop in the static memory cell can be constructed using Bipolar Junction Transistor
(BJT) and MOSFETs because of it’s storing capability. Also, it’s access time is less and it is faster in
operation.
5. Which of the following IC is TTL based static RAM?

a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
View Answer
Answer: b
Explanation: The lip- lop in the static memory cell can be constructed using Bipolar Junction Transistor
(BJT) and MOSFETs because of it’s storing capability. Also, it’s access time is less and it is faster in
operation. In IC 7489, TTL is used which is static RAM.
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6. IC 7489 is of ____________
a) 32 bit
b) 64 bit
c) 512 bit
d) 1024 bit
View Answer
Answer: b
Explanation: The arrangement of IC 7489 is 16 * 4 = 64 bits. Thus, it has 16 columns and 4 rows.
7. Data is written in IC 7489 through ____________

a) Chip select
b) Enable
c) Data input
d) Memory enable
View Answer
Answer: c
Explanation: Data can be written into the memory via the data inputs by supplying an address to the
SELECT inputs and holding both the memory enable and write enable LOW.
8. The irst practical form of Random Access Memory (RAM) was the ____________
a) Cathode tube
b) Data tube
c) Memory tube
d) Select tube
View Answer
Answer: c
Explanation: Data can be written into the memory via the data inputs by supplying an address to the
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SELECT inputs and holding both the memory enable and write enable LOW since it’s an active-low pin.
9. Magnetic-core memory was invented in ____________

a) 1946
b) 1948
c) 1947
d) 1945
View Answer
Answer: c
Explanation: Magnetic-core memory was invented in 1947 and developed up until the mid-1970s. It
became a widespread form of random-access memory, relying on an array of magnetized rings. RAM is a
volatile memory, therefore it stores data as long as power is on. RAM is also known as RWM (i.e. Read
Write Memory).
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10. Which of the following RAM is volatile in nature?

a) SRAM
b) DRAM
c) EEPROM
d) Both SRAM and DRAM
View Answer
Answer: d
known as RWM (i.e. Read Write Memory). Both static and dynamic RAM are considered volatile, as their
state is lost or reset when power is removed from the system.
11. Which one of the following IC is of 4KB?

a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
View Answer
Answer: d
Explanation: IC 2114 is of 4KB and it is a static RAM. Both static and dynamic RAM are considered
volatile, as their state is lost or reset when power is removed from the system.
12. Which of the following IC implements the static MOS RAM?

a) TMS 4015
b) TMS 4014
c) TMS 4016
d) TMS 2114
View Answer
Answer: c
Explanation: The IC TMS 4016 is a 2KB static MOS RAM. There are eleven address inputs available to
select the 2014 locations.
13. What types of arrangements a TMS 4016 has?

a) 1024 * 4
b) 1024 * 8
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c) 2048 * 4
d) 2048 * 8
View Answer
Answer: d
Therefore, arrangements in TMS 4016 = 2048 * 8 = 2KB.
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14. How many address inputs are available in TMS 4016?

a) 10
b) 9
c) 12
d) 11
View Answer
Answer: d
15. In TMS 4016, the data in/data out are ______________

a) Unidirectional
b) Parallel
c) Serial
d) Bidirectional
View Answer
Answer: d
Explanation: In TMS 4016, the data in/data out are bidirectional terminal. It means that the input/output
can be transmitted or received through the same terminal.
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Access Memory – 3
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This set of tough Digital Electronic/Circuits questions and answers focuses on “Random Access Memory-
3”.
1. Dynamic RAM is more preferable than static RAM, why?

a) DRAM is of the lowest cost, lowest density
b) DRAM is of the highest cost, reduced size
c) DRAM is of the lowest cost, highest density
d) DRAM is more lexible and lowest storage capacity
View Answer
Answer: c
Explanation: The Dynamic Random Access Memory is the lowest cost, highest density random access
memory available. Nowadays, computers use DRAM for main memory. However, it’s access time is more
compared to SRAM.
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2. The memory size of DRAM is ____________

a) 1 to 100 MB
b) 512 to 1024 MB
c) 64 to 512 MB
d) 16 to 256 MB
View Answer
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Answer: d
Explanation: The Dynamic Random Access Memory is the lowest cost, highest density random access
memory available. Nowadays, computers use DRAM for main memory. However, it’s access time is more
compared to SRAM. The memory size of DRAM lies between 16 to 256 MB.
3. The DRAM stores its binary information on __________

a) MOSFET
b) Transistor
c) Capacitor
d) BJT
View Answer
Answer: c
Explanation: Capacitor has high storing capability only, so DRAM stores its binary information in the
form of electric charges on capacitors. However, DRAM takes more time time to access data.
4. Most modern operating systems employ a method of extending RAM capacity, known as __________
a) Magnetic memory
b) Virtual memory
c) Storage memory
d) Static memory
View Answer
Answer: b
Explanation: Most modern operating systems employ a method of extending RAM capacity, known as
virtual memory. Virtual memory is seen as part of main memory but is actually a secondary memory.
5. DRAM uses of integrated MOS capacitors as _______ instead of a lip- lop.

a) Storage cell
b) Memory cell
c) Dynamic cell
d) Static cell
View Answer
Answer: b
Explanation: DRAM uses of integrated MOS capacitors as memory cell instead of a lip- lop. The
advantage of this cell is that it allows very large memory arrays to be constructed on a chip at a lower
cost per bit than in static memories.
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6. What is the disadvantage of MOS capacitor in DRAM?

a) It can’t hold the data till a long period
b) It doesn’t holds the charge till a long period
c) It is highly densed
d) It is not lexible
View Answer
Answer: b
Explanation: The disadvantage of MOS capacitor in DRAM is that it can’t hold the stored charge over a
long period of time and it has to be refreshed every few millisecond. Thus, DRAM is slow in operation.
7. The dynamic RAM offers __________

a) High power consumption, large storage capacity
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b) Reduced power consumption, large storage capacity

c) Reduced power consumption, short storage capacity
d) High power consumption, short storage capacity
View Answer
Answer: b
Explanation: The dynamic RAM offers reduced power consumption and large storage capacity in a single
memory chip. With the availability of such high packing density memory ICs, the capacity of memory will
continue to grow. However, it’s access time is more and thus operation is slow.
8. The main memory of a PC is made of __________

a) Cache
b) Dynamic RAM
c) Static RAM
d) Both cache and dynamic RAM
View Answer
Answer: d
Explanation: The main memory of a PC is made of cache and DRAM. DRAM offers reduced power
consumption and large storage capacity in a single memory chip.
9. Virtual memory consists of __________

a) SRAM
b) DRAM
c) Magnetic memory
d) Main Memory
View Answer
Answer: a
Explanation: Most modern operating systems employ a method of extending RAM capacity, known as
virtual memory which consists of SRAM.
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10. Dynamic RAM is used as main memory in a computer system as __________

a) It has a lower cell density
b) It needs refreshing circuitry
c) Consumes less power
d) Has higher speed
View Answer
Answer: d
Explanation: Dynamic RAM is used as main memory in a computer system as it has higher speed due to
the presence of MOSFET technology. However, it’s access time is more compared to SRAM and operation
is slow.
11. Cache memory acts between __________

a) RAM and ROM
b) CPU and RAM
c) CPU and Hard Disk
d) CPU and ROM
View Answer
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Answer: b
Explanation: In a computer, cache memory acts between CPU and RAM.
12. Which characteristic of RAM memory makes it not suitable for permanent storage?
a) Unreliable
b) Too slow
c) Too bulky
d) It is volatile
View Answer
Answer: d
Explanation: RAM is volatile. Therefore, it stores data only as long as the d.c power is on.
13. Why do a DRAM employ address multiplexing technique?

a) To reduce the number of memory locations
b) To increase the number of memory locations
c) To reduce the number of address lines
d) To increase the number of address lines
View Answer
Answer: c
Explanation: A Dynamic RAM usually employs a technique called address multiplexing to reduce the
number of address lines and thus the number of input/output pins on the IC package.
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14. An address multiplexing in DRAM is of _____ bits.

a) 10240
b) 15289
c) 16384
d) 17654
View Answer
Answer: c
Explanation: A Dynamic RAM usually employs a technique called address multiplexing to reduce the
number of address lines and thus the number of input/output pins on the IC package. Address
multiplexing has 214 = 16384 bits.
15. What is a sense ampli ier?

a) It is an ampli ier which converts ac current into dc current
b) It is an ampli ier which lowers the input voltage
c) It is an ampli ier which increases the input voltage
d) It is an ampli ier which converts the low voltage to a suf icient voltage
View Answer
Answer: d
Explanation: A sense ampli ier for each column is necessary to convert from the low voltage and low
energy to a suf icient level on the I/O data line.
To practice tough questions and answers on all areas of Digital Electronic Circuits, here is complete set of
1000+ Multiple Choice Questions and Answers.
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Access Memory – 4
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This set of Basic Digital Electronic/Circuits Interview questions and answers focuses on “Random Access
Memory-4”.
1. DRAM is fabricated by using IC __________

a) 2114
b) 7489
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c) 4116
d) 2776
View Answer
Answer: c
Explanation: DRAM is Dynamic RAM which takes more access time compared to SRAM and is thus,
slower in operation comparatively. Although, in general it offers high speed and is used in most
computers nowadays. DRAM is fabricated by using IC 4116.
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2. IC 4116 is of ______ storage memory.

a) 16 KB
b) 32 KB
c) 64 MB
d) 2 KB
View Answer
Answer: a
Explanation: IC 4116 is a DRAM of 16 KB storage memory. It requires three supply voltages (+5V, -5V,
and +12V) to operate the IC unit.
3. How many supply voltage IC 4116 requires to operate the IC unit?

a) 3
b) 2
c) 1
d) 4
View Answer
Answer: a
Explanation: IC 4116 is a DRAM of 16 KB storage memory. It requires three supply voltages (+5V, -5V,
and +12V) to operate the IC unit.
4. The full form of PSRAM is __________

a) Plugged Static RAM
b) Plugged Stored RAM
c) Pseudo Stored RAM
d) Pseudo Static RAM
View Answer
Answer: d
Explanation: The full form of PSRAM is Pseudo Static RAM. It is a dynamic RAM which is implemented as
a SRAM.
5. Pseudo static RAM is a __________

a) Static RAM
b) Dynamic RAM
c) Cache
d) ROM
View Answer
Answer: b
Explanation: The full form of PSRAM is Pseudo Static RAM. It is a dynamic RAM having built-in fresh logic,
which is implemented as an SRAM.
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6. When PSRAM is performing internal refresh __________

a) The read operation is performed
b) The write operation is performed
c) It can not be accessed for read or write
d) The voltage goes HIGH
View Answer
Answer: c
Explanation: The full form of PSRAM is Pseudo Static RAM. It is a dynamic RAM having built-in fresh logic,
which is implemented as a SRAM. So, it can not be accessed for read or write during the refresh
operation.
7. RAMs are utilized in the computer as __________

a) Scratch-pad
b) Buffer
c) Main memory
View Answer
Answer: d
Explanation: RAMs are utilized in the computer as a scratch-pad, buffer and main memories. These are
the applications of RAMs. Mostly, these RAMs are DRAMs as they provide high speed.
8. The advantages of RAMs are __________

a) Non destructive read out
b) Fast operating speed
c) Low power dissipation
View Answer
Answer: d
Explanation: The advantages of RAM are Non-destructive read out, Fast operating speed and Low power
dissipation.
9. Which one is more economical?

a) ROM
b) RAM
c) EROM
d) PROM
View Answer
Answer: b
Explanation: RAM is more economical than ROM because MOS memories are more economical than the
magnetic core for small and medium sized systems.
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10. Which one is self-compatible?

a) ROM
b) RAM
c) EROM
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d) PROM
View Answer
Answer: b
Explanation: As semiconductor memories enjoy common interface and technology between sensing and
decoding circuitry and the storage element itself, so RAMs are self-compatible. Also, they provide high
speed and fast operation.
11. The memory which is used for storing programs and data currently being processed by the CPU is
called __________
a) PROM
b) Main Memory
c) Non-volatile memory
d) Mass memory
View Answer
Answer: a
Explanation: PROM has the capability to store the data due to the presence of MOSFET which is
processed by the CPU. It is one-time programmable by the user.
12. CD-ROM is a __________

a) Memory register
b) Magnetic memory
c) Semiconductor memory
d) Non-volatile memory
View Answer
Answer: d
Explanation: CD-ROM is a non-volatile memory. Once a program is uploaded in it then it can’t be erasable.
Thus, it stores the data permanently.
13. A place which is used as storage location in a computer __________

a) A bit
b) A record
c) An address
d) A byte
View Answer
Answer: c
Explanation: A storage location of a computer is an address/memory location, used to store instructions
and data.
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14. Which of the following is not a primary storage device?

a) Optical disk
b) Magnetic tape
c) Magnetic disk
d) RAM
View Answer
Answer: d
Explanation: RAM (i.e. Random Access Memory) is not a primary storage device.
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Programmable Logic Array
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“Programmable Logic Array”.
1. What is memory decoding?

a) The process of Memory IC used in a digital system is overloaded with data
b) The process of Memory IC used in a digital system is selected for the range of address assigned
c) The process of Memory IC used in a digital system is selected for the range of data assigned
d) The process of Memory IC used in a digital system is overloaded with data allocated in memory cell
View Answer
Answer: b
Explanation: The Memory IC used in a digital system is selected or enabled only for the range of
addresses assigned to it and this process is called memory decoding. It decodes the memory to be
selected for a speci ic address.
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2. The irst step in the design of memory decoder is __________

a) Selection of a EPROM
b) Selection of a RAM
c) Address assignment
d) Data insertion
View Answer
Answer: c
Explanation: Memory decoder decodes the memory to be selected for a speci ic address. The irst step in
the design of memory decoder is address assignment in non-overlapped manner.
3. How many address bits are required to select memory location in Memory decoder?
a) 4 KB
b) 8 KB
c) 12 KB
d) 16 KB
View Answer
Answer: c
Explanation: Memory decoder decodes the memory to be selected for a speci ic address. Since, the given
EPROM and RAM are of 4 KB (4 * 1024 = 4096) capacity, it requires 12 address bit to select one of the
4096 memory locations.
4. How memory expansion is done?

a) By increasing the supply voltage of the Memory ICs
b) By decreasing the supply voltage of the Memory ICs
c) By connecting Memory ICs together
d) By separating Memory ICs
View Answer
Answer: c
Explanation: Memory ICs can be connected together to expand the number of memory words or the
number of bits per word.
5. IC 4116 is organised as _________

a) 512 * 4
b) 16 * 1
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c) 32 * 4
d) 64 * 2
View Answer
Answer: c
Explanation: IC 4116 is organised as 16 * 1 K which has capability to store 16 KB.
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6. To construct 16K * 4-bit memory, how many 4116 ICs are required?
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: d
Explanation: Since, IC 4116 is organised as 16K * 1, which can store about 16KB data. So, four ICs are
required for 16K * 4 memory implementation.
7. How many 1024 * 1 RAM chips are required to construct a 1024 * 8 memory system?
a) 4
b) 6
c) 8
d) 12
View Answer
Answer: c
Explanation: One 1024 * 1 RAM chips is of 1-bit. SO, for construction of 1024 * 8 RAM chip of 8-bits, it
will require 8 chips.
8. How many 16K * 4 RAMs are required to achieve a memory with a capacity of 64K and a word length
of 8 bits?
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: d
Explanation: 16K * 4 = 64K RAM is of 64K. Therefore, for a word of length 8-bits,
64 * 8 = 512K RAM required. Thus, number of 16K * 4 RAMs = 512/64 = 8.
9. The full form of PLD is _________

a) Programmable Load Devices
b) Programmable Logic Data
c) Programmable Logic Devices
d) Programmable Loaded Devices
View Answer
Answer: c
Explanation: The full form of PLD is Programmable Logic Devices. It is a collection of gates, lip- lops and
registers on a single chip.
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10. PLD contains a large number of _________

a) Flip- lops
b) Gates
c) Registers
View Answer
Answer: d
Explanation: Programmable Logic Devices is a collection of a large number of gates, lip- lops, registers
that are interconnected on the chip. Thus, it is used for designing logic circuits.
11. Logic circuits can also be designed using _________

a) RAM
b) ROM
c) PLD
d) PLA
View Answer
Answer: c
Explanation: Programmable Logic Devices is a collection of large number of gates, lip- lops, registers
that are interconnected on the chip. Thus, it is used for designing logic circuits.
12. In PLD, there are provisions to perform interconnections of the gates internally, because of _________
a) High reliability
b) High conductivity
c) The desired logic implementation
d) The desired output
View Answer
Answer: c
that are interconnected on the chip. In PLD, there are provisions to perform interconnections of the
gates internally so that the desired logic can be implemented.
13. Why antifuses are implemented in a PLD?

a) To protect from high voltage
b) To increase the memory
c) To implement the programmes
d) As a switching devices
View Answer
Answer: c
that are interconnected on the chip. Programming is accomplished by using antifuses in a PLD and it is
fabricated at the cross points of the gates.
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14. How many types of PLD is?

a) 2
b) 3
c) 4
d) 5
View Answer
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Answer: a
Explanation: There are two types of PLD, viz., devices with ixed architecture and devices with a lexible
architecture. The main categories of PLDs are PROM, PAL and PLA.
15. PLA refers to _________

a) Programmable Loaded Array
b) Programmable Array Logic
c) Programmable Logic Array
d) Programmed Array Logic
View Answer
Answer: c
Explanation: PLA refers to Programmable Logic Array. It is a type of PLD having programmable AND and
OR gates.
Answers.

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Programmable Array Logic
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“Programmable Array Logic”.
1. The inputs in the PLD is given through ____________

a) NAND gates
b) OR gates
c) NOR gates
d) AND gates
View Answer
Answer: d
Explanation: The inputs in the PLD is given through AND gate followed by inverting & non-inverting
buffer. PLDs are Programmable Logic Devices consisting of logic gates, lip- lops and registers connected
together on a single chip. Thus, it can be categorised into PROM, PAL and PLA.
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2. PAL refers to ____________

a) Programmable Array Loaded
b) Programmable Logic Array
c) Programmable Array Logic
d) Programmable AND Logic
View Answer
Answer: c
Explanation: PAL refers to Programmable Array Logic consisting of programmable AND gates and ixed
OR gates.
3. Outputs of the AND gate in PLD is known as ____________

a) Input lines
b) Output lines
c) Strobe lines
d) Control lines
View Answer
Answer: b
Explanation: Outputs of the AND gate in PLD is known as output lines.
4. PLA contains ____________

a) AND and OR arrays
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b) NAND and OR arrays

c) NOT and AND arrays
d) NOR and OR arrays
View Answer
Answer: a
Explanation: Programmable Logic Array is a type of ixed architecture logic devices with programmable
AND gates followed by programmable OR gates. It is a kind of PLD.
5. PLA is used to implement ____________

a) A complex sequential circuit
b) A simple sequential circuit
c) A complex combinational circuit
d) A simple combinational circuit
View Answer
Answer: c
Explanation: Since, PLA is the combination of programmable AND and OR gates. So, it is used to
implement complex combinational circuit.
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6. A PLA is similar to a ROM in concept except that ____________

a) It hasn’t capability to read only
b) It hasn’t capability to read or write operation
c) It doesn’t provide full decoding to the variables
d) It hasn’t capability to write only
View Answer
Answer: c
Explanation: A PLA is similar to a ROM in concept except that it doesn’t provide full decoding to the
variables and doesn’t generate all the minterms as in the ROM. Programmable Logic Array is a type of
ixed architecture logic devices with programmable AND gates followed by programmable OR gates. It is
a kind of PLD.
7. For programmable logic functions, which type of PLD should be used?

a) PLA
b) PAL
c) CPLD
d) SLD
View Answer
Answer: b
Explanation: Since PAL consists of programmable AND gates and ixed OR gates and also circuitry
working is less.
8. The complex programmable logic device contains several PLD blocks and __________
a) A language compiler
b) AND/OR arrays
c) Global interconnection matrix
d) Field-programmable switches
View Answer
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Answer: c
Explanation: The complex programmable logic device contains several PLD blocks and a global
interconnection matrix by which it communicates through several devices. It is also known as Field-
Programmable Gate Arrays (FPGAs).
9. Which type of device FPGA are?

a) SLD
b) SROM
c) EPROM
d) PLD
View Answer
Answer: d
Explanation: Field-Programmable Gate Arrays (FPGAs) are reprogrammable silicon chips. In contrast to
processors that you ind in your PC, programming an FPGA rewires the chip itself to implement your
functionality rather than run a software application. Thus, FPGAs are PLD devices.
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10. The difference between a PAL & a PLA is ____________

a) PALs and PLAs are the same thing
b) The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a
programmable AND plane
c) The PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a
programmable AND plane
d) The PAL has more possible product terms than the PLA
View Answer
Answer: b
Explanation: The main difference between a PAL & PLA is that PLA has a programmable OR plane and a
programmable AND plane, while the PAL only has a programmable AND plane and a ixed OR plane.
11. If a PAL has been programmed once ____________

a) Its logic capacity is lost
b) Its outputs are only active HIGH
c) Its outputs are only active LOW
d) It cannot be reprogrammed
View Answer
Answer: d
Explanation: PAL only has a programmable AND plane and a ixed OR plane. Since, PAL is dynamic in
nature. So, it can’t be reprogrammed.
12. The FPGA refers to ____________

a) First programmable Gate Array
b) Field Programmable Gate Array
c) First Program Gate Array
d) Field Program Gate Array
View Answer
Answer: b
Explanation: The FPGA refers to Field Programmable Gate Array. Field-Programmable Gate Arrays
(FPGAs) are reprogrammable silicon chips. In contrast to processors that you ind in your PC,
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programming an FPGA rewires the chip itself to implement your functionality rather than run a software
application. Thus, FPGAs are PLD devices.
13. The full form of VLSI is ____________

a) Very Long Single Integration
b) Very Least Scale Integration
c) Very Large Scale Integration
d) Very Long Scale Integration
View Answer
Answer: c
Explanation: The full form of VLSI is Very Large Scale Integration in which FPGA is implemented.
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14. In FPGA, vertical and horizontal directions are separated by ____________

a) A line
b) A channel
c) A strobe
d) A lip- lop
View Answer
Answer: b
Explanation: The FPGA refers to Field Programmable Gate Array. Field-Programmable Gate Arrays
(FPGAs) are reprogrammable silicon chips. Vertical and horizontal directions is separated by a channel
in an FPGA which determines the location of the output.
15. Applications of PLAs are _____________

a) Registered PALs
b) Con igurable PALs
c) PAL programming
View Answer
Answer: d
Explanation: Applications of PLAs are as mentioned above and these are performed by using an extra
lip- lop with PAL.
Answers.

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Introduction to Hardware Description Language
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“Introduction to hardware description language”.
1. The full form of HDL is _________________

a) Higher Descriptive Language
b) Higher De inition Language
c) Hardware Description Language
d) High Descriptive Language
View Answer
Answer: c
Explanation: The full form of HDL is Hardware Description Language.
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2. The full form of VHDL is _____________

a) Very High Descriptive Language
b) Verilog Hardware Description Language
c) Variable De inition Language
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d) None of the Mentioned

View Answer
Answer: b
Explanation: The full form of VHDL is Verilog Hardware Description Language.
3. VHSIC stands for _____________

a) Very High Speed Integrated Circuits
b) Very Higher Speed Integration Circuits
c) Variable High Speed Integrated Circuits
d) Variable Higher Speed Integration Circuits
View Answer
Answer: a
Explanation: VHSIC stands for Very High Speed Integrated Circuits.
4. VHDL is being used for _____________

a) Documentation
b) Veri ication
c) Synthesis of large digital design
View Answer
Answer: d
Explanation: The full form of VHDL is Verilog Hardware Description Language. The acronym of VHDL
itself captures the entire theme of the language and it describes the hardware in the same manner as
does the schematic. So, it is used as documentation, veri ication and synthesis of large digital designs.
5. The use of VHDL can be done in _____ ways.

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: b
Explanation: The VHDL has three coding styles are: (i) data low, (ii) structural, (iii) behavioural.
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6. At high frequencies when the sampling interval is too long in a frequency counter _____________
a) The counter works ine
b) The counter undercounts the frequency
c) The measurement is less precise
d) The counter over lows
View Answer
Answer: d
Explanation: Let the sampling time be 1 sec. This means the counter will count the number of pulses
from the unknown signal for 1sec duration and would display it after 1 sec. thus if the signal is of 800 Hz,
at the end of 1 sec, counter would have counted up to 800. Thus, in case of high frequencies and high
sampling time, counter might count beyond its limit and over lows.
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7. The output frequency related to the sampling interval of a frequency counter as _____________
a) Directly with the sampling interval
b) Inversely with the sampling interval
c) More precision with longer sampling interval
d) Less precision with longer sampling interval
View Answer
Answer: c
Explanation: Sampling interval means a particular frequency range in which the device operates
correctly. Thus, more precision is produced with longer sampling interval.
8. In an HDL application of a stepper motor, what is done next after an up/down counter is built?
a) Build the sequencer
b) Test it on a simulator
c) Test the decoder
d) Design an intermediate integer variable
View Answer
Answer: b
Explanation: Simulator is a software which is used in the testing of the stepper motor using up/down
counter.
9. In a digital clock application, the basic frequency must be divided down as _____________
a) 1 Hz
b) 60 Hz
c) 100 Hz
d) 1000 Hz
View Answer
Answer: a
Explanation: Minimum count is 1 sec and time = 1/freq. So, t = 1/1 = 1Hz.
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10. What does the data signal do in the keypad application?

a) The row and column encoded data
b) The ring encoded data
c) The freeze locator data
d) The ring counter data
View Answer
Answer: a
Explanation: The data signal arrange the information with the help of data low in row and column
manner. It encodes the data to be sent.
11. When a key is pressed, what does the ring counter in the HDL keypad application do?
a) Count to ind the row
b) Freeze
c) Count to ind the column
d) Start the D lip- lop
View Answer
Answer: a
Explanation: The data signal arrange the information with the help of data low in row and column
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manner. It encodes the data to be sent. When a key is pressed the ring counter in the HDL scans the
information provided by the user and counts to ind the row.
12. A step which should be followed in project management is known as _____________

a) Overall de inition
b) System documentation
c) Synthesis and testing
d) System integration
View Answer
Answer: b
Explanation: System documentation is the second step of project management in which a result of the
system is noted simultaneously.
13. In the keypad application, the preset state of the ring counter de ine _____________
a) The NANDing of the columns
b) The NANDing of the rows
c) The proper output of the column encoder
d) The proper output of the row encoder
View Answer
Answer: d
Explanation: When a key is pressed the ring counter in the HDL scans the information provided by the
user and counts to ind the row. The preset state of the ring counter de ine the proper output of the row
encoder.
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14. A major block which is not a part of an HDL frequency counter _____________
a) Timing and control unit
b) Decoder/display
c) Display register
d) Bit shifter
View Answer
Answer: d
Explanation: Bit shifter is part of a register in which bit shifting takes place bit-by-bit either left or right.
15. A stepper motor HDL application must include _____________

a) Sequencers and multiplexers
b) Types and bits
c) Counters and decoders
d) Variables and processes
View Answer
Answer: c
Explanation: A stepper motor (also referred to as step or stepping motor) is an electromechanical device
achieving mechanical movements through the conversion of electrical pulses. A stepper motor HDL
application must include counters and decoders for position control. It is tested on the simulator.
Answers.
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Multivibrators
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“Multivibrators”.
1. A multivibrator is an electronic circuit used to implement ____________

a) Oscillator
b) Timer
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c) Flip- lop
View Answer
Answer: d
Explanation: A multivibrator is an electronic circuit used to implement a variety of simple two-state
systems and two state systems are an oscillator, timer, lip- lop. It produces an output when triggered.
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2. Multivibrators are characterized by ____________

a) Registers
b) Capacitors
c) Transistors
View Answer
Answer: d
Explanation: A multivibrator is an electronic circuit used to implement a variety of simple two-state
systems and two state systems are an oscillator, timer, lip- lop. It produces an output when triggered.
Multivibrators are characterized by amplifying devices (transistors) and cross coupled devices (registers,
capacitors).
3. How many types of multivibrators are?

a) 2
b) 4
c) 5
d) 3
View Answer
Answer: d
Explanation: There are three types of multivibrator circuits depending on the circuit operation: (i)
Astable, (ii) Bistable, and (iii) Monostable. Astable multivibrator is internally triggered, whereas the other
two types are externally triggered.
4. Astable multivibrator is ________ in any state.

a) Stable
b) Unstable
c) Saturated
d) Both Stable & Saturated
View Answer
Answer: b
Explanation: Astable multivibrator, in which the circuit is not stable in either state i.e. it continually
switches from one state to the other. It is internally triggered and does not have any stable state.
5. Monostable multivibrator is/has ________ state.

a) Stable
b) Unstable
c) One stable and another unstable
d) Independent
View Answer
11/5/2020 deld.html
Answer: b
Explanation: Monostable multivibrator, in which one of the states is stable, but the other state is unstable
(transient). A trigger pulse causes the circuit to enter the unstable state. After entering the unstable state,
the circuit will return to the stable state after a set time.
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6. Bistable multivibrator is ________ in any state.

a) Stable
b) Unstable
c) Saturated
d) Independent
View Answer
Answer: a
Explanation: Bistable multivibrator is a type of multivibrator having two stable states. The circuit is stable
in either state. It can be lipped from one state to the other by an external trigger pulse.
7. Bistable circuit is also known as ____________

a) Latch
b) Gate
c) Flip- lop
d) Bidirectional circuit
View Answer
Answer: c
Explanation: Bistable multivibrator circuit has capability to store 1-bit of information. So, it is also known
as lip- lop. Like Flip- lop, Bistable circuit also has 2 states.
8. Astable circuit acts as a/an ____________

a) Ampli ier
b) Oscillator
c) Relaxation oscillator
d) Multiplexer
View Answer
Answer: c
Explanation: Astable circuit continually switches from one state to the other. It keeps oscillating between
unstable states. Hence, it functions as a relaxation oscillator.
9. In an astable multivibrator, the amplifying elements are ____________

a) FET
b) JFET
c) OP-AMP
View Answer
Answer: d
Explanation: Astable multivibrators are made with FET, JFET, OP-AMP or other types of ampli ier. Astable
circuit continually switches from one state to the other. It keeps oscillating between unstable states.
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10. Monostable multivibrator can also be termed as ____________

a) Full astable multivibrator
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b) Half astable multivibrator

c) Half bistable multivibrator
d) Full bistable multivibrator
View Answer
Answer: b
Explanation: Since, astable multivibrator is unstable and changes their states continually (It means that it
can have both the states), whereas in monostable multivibrator, one of the states is stable, but the other
state is unstable. SO Monostable Multivibrator is also known as Half-Astable Multivibrator.
11. The classic multivibrator circuit is known as ____________

a) Metal-coupled multivibrator
b) Plate-coupled multivibrator
c) Parallel-plate coupled multivibrator
d) Alternate-plate coupled multivibrator
View Answer
Answer: b
Explanation: The classic multivibrator circuit (also called a plate-coupled multivibrator) is irst described
by Henri Abraham and Eugene Bloch.
Answers.
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DELD UNIT 2
Matoshri College of Engineering and Research Center Nasik

Department of Computer Engineering
Digital Elecronics and Logic Design (DELD)
UNIT - II
Class : S.E.Comp Subject : DELD
Sr. Correct
Question Option A Option B Option C Option D Marks
No. Option
Current Voltage Voltage
Current
controlled controlled controlled
1 Transistor is a controlled A 1
voltage current voltage
current device.
device. device. device.
high input low input low input high input
impedance impedance impedance impedance
A digital logic device used as a buffer should have what input/output
2 and high and high and low and low D 2
characteristics?
output output output output
impedance impedance impedance impedance
3 What is the standard TTL noise margin? 5.0 V 0.2 V 0.8 V 0.4 V D 2
0.0 V to
4 The range of a valid LOW input is: 0.0 V to 0.4 V 0.4 V to 0.8 V 0.0 V to 1.8 V B 2
2.8 V
When an IC has two rows of parallel connecting pins, the device is a phase
5 a QFP a DIP CMOS B 1
referred to as: splitter
Which digital IC package type makes the most efficient use of printed
6 SMT TO can flat pack DIP A 1
circuit board space?
7 The digital logic family which has minimum power dissipation is TTL RTL DTL CMOS D 2
8 Which of the following is the fastest logic TTL ECL CMOS LSI B 2
9 The digital logic family which has the lowest propagation delay time is ECL TTL CMOS PMOS A 2
Open collector Tri state

10 Which TTL logic gate is used for wired ANDing Totem Pole ECL gates A 2
output output
Less than Thrice of
11 CMOS circuits consume power Equal to TTL Twice of TTL B 2
TTL TTL
lower
positive higher zero voltage
12 In a positive logic system, logic state 1 corresponds to voltage B 1
voltage voltage level level
level
Page 1
DELD UNIT 2
The commercially available 8-input multiplexer integrated circuit in the

13 7495 74153 74154 74151 B 2
TTL family is
14 The logic 0 level of a CMOS logic device is approximately 1.2 volts 0.4 volts 0volts 5volts C 2
15 Which ofthe following is a universal logic gate? OR XOR AND NAND D 1
greater of smaller of
How is the noise margin of a logic family VDD – VOH VIL – VOL
16 VOH – VOL VIH – VIL. C 2
defi ned? and VOL – and VOH –
GND VIH
What parameter causes the main limit power
d.c. input output input
17 on fan-out of CMOS logic in high-speed supply A 2
current current capacitance
applications? voltage.
power-
The number of standard loads that the output of the gate can drive
18 Fan-in Fan-Out noise-margin dissipiatio B 2
with out impairment of its normal operation is
n
all the
minization many
any logic
techniques digital
it is used by function can
are computers
19 A NAND gate is called a universal logic element because everybody be realized B 2
applicable use NAND
by NAND
for optimum gates.
gates alone
NAND gate
realization
power-
Measure of power consumed by the gate when fully driven by all
20 Fan-in Fan-Out noise-margin dissipiatio D 2
its inputs is
n
21 Fan-out is specified in terms of voltage current watt unit load D 2
22 Which of the following logic family has highest fan-out DTL CMOS RTL TTL B 2
23 Which of following consume minimum power TTL RTL DTL CMOS D 1
24 Among the logic families, low power dissipation is in DTL CMOS RTL TTL B 1
25 The temperature in which the performance of the IC is effective Operating Fan-Out Normal power- A 1
Temprature temrature dissipiatio
26 The nominal value of the dc supply voltage for TTL (transistor-transistor 0v 5v 10v 15v B 1
logic) devices is
power-
The average transition delay time for the signal to propagate from Propogation
27 Fan-Out noise-margin dissipiatio A 2
input to output when the signals change in value. It is expressed in ns is Delay
n
the number of inputs connected to the gate without any degradation in Propogation power-
28 Fan-Out Fan- in C 2
the Delay dissipiatio
29 Which of the following logic gives the complementary outputs? ECL TTL CMOS PMOS A 2
Page 2
DELD UNIT 2
30 The maximum noise voltage added to an input signal of a digital circuit Fan-in Fan-Out noise-margin power- C 2
31 that
Amongdoes
the logic families, Slowest logic family is TTL RTL DTL dissipiatio
CMOS D 1
32 Operating temperature of the IC vary from 0 to70 celsius 0to35celsius 0to 50celsius 0to70celsi A 1
1. Open collector output 2. Totem-Pole Output 3. Tri-state output are the us of
None
33 TTL LOGIC RTL LOGIC CMOS LOGIC A 1
type of this
34 If the channel is initially doped lightly with p-type impurity a conducting Depletion Enhancemen Both Mode None of A 1
channel
If the region beneath the gate is left initially uncharged the gate field mode t mode
Enhancemen this
Depletion
must induce a t mode None of
35 mode Both Mode B 2
channel before current can flow. Thus the gate voltage enhances the this
operation MOS operation of
channel current and sucha device is said to operate in the MOS
gate- to- gate- to- gate- to- None of
36 The n- channel MOS conducts when its A 2
source voltage source source this
37 The p- channel MOS conducts when its gate- to- gate- to- gate- to- None of C 2
source voltage source source this
high
The fan-out of a MOS-logic gate is higher than that of TTL gates because low input high input low output
38 output D 2
of its impedance impedance impedance
impedance
Charging time Discharging Output Input

39 Which factor does not affect CMOS loading? C 2
associated time capacitance capacitanc
with the associated of gating
the load edigital
of the
40 Logic gates are the basic elements that make a Analog system Basic System D 1
system system
EXCLUSIVE
Which of the following gate is a two-level logic gate OR gate NAND gate
41 OR gate NOT C 1
Among the logic families, the family which can be used at very high
TTLAS
42 frequency greater than 100 MHz in a 4 bit CMOS ECL TTLLS C 1
consume provide
have lower can be used
least maximum
NAND. gates are preferred over others because these fabrication to make any
43 electronic density in B 2
area gate
power a chip.
The fan Out of a 7400 NAND gate is 2TTL 5TTL 8TTL 10TTL
44 D 2
Unijunctio
45 Which transistor element is used in CMOS logic? FET MOSFET Bipolar B 2
n
Page 3
DELD UNIT 2
large
CMOS circuits are extensively used for ON-chip computers mainly low power high noise
46 packing low cost. C 2
because of their extremely dissipation. immunity.
density.
VNH =
VNL = VNH = VNL =
VOH(min)
47 Which equation is correct? VIL(max) + VOH(min) + VOH(min) – D 2
–
VOL(max) VIH(min) VIH(min)
VIH(min)
minimum
lower the higher the maximum
frequency
48 The greater the propagation delay, the maximum maximum frequency is A 2
is
frequency frequency unaffected
unaffected
49 For a CMOS gate, which is the best speed-power product? 1.4 Pj 1.6 pJ 2.4 pJ 3.3 pJ A 2
VOH and
VOH(min) VOH drops
VOH exceeds VOH(min)
50 In a TTL circuit, if an excessive number of load gate inputs are connected, drops below below B 2
VOH(min) are
VOH VOH(min)
unaffected
51 Which is not a MOSFET terminal? Gate Drain Source Base D 2
an open- a bipolar an emitter-
a tristate
52 An open-drain gate is the CMOS counterpart of collector TTL junction coupled A 2
TTL gate
gate transistor logic gate
metal-oxide
semiconduct unijunctio
bipolar field-effect
or field- n
53 The active switching element used in all TTL circuits is the junction transistor A 2
effect transistor
transistor (BJT (FET
transistor (UJ)
(MOSFET
base,
emitter,
JBT totem-pole
54 One output structure of a TTL gate is often referred to as a diode collector C 2
arrangement arrangement
arrangeme
nt
a pull-down a pull-up no output an output
55 An open-collector output requires B 2
resistor resistor resistor resistor
56 Which is not an output state for tristate logic? HIGH LOW High-Z Low-Z D 2
Page 4
DELD UNIT 2
commercia
industrial millitary educational
57 TTL is alive and well, particularly in lapplicatio C 2
applications applications applications
ns
A TTL NAND gate with IIL(max) of –1.6 mA per input drives eight TTL
58 –12.8 Ma –8 mA –1.6 mA –25.6 mA A 4
inputs. How much current does the drive output sink?
A standard TTL circuit with a totem-pole output can sink, in the LOW
59 16 Ma 20 mA 24 Ma 28mA A 4
state (IOL(max)),
open- tristate
It is best not to leave unused TTL inputs unconnected (open) because of noise low-current
60 collector constructi A 2
TTL's sensitivity requirement
outputs on
61 Which logic family combines the advantages of CMOS and TTL? BiCMOS TTL/CMOS ECL TTL/MOS A 2
Emitter-
Differential Totem-
62 Which is not part of emitter-coupled logic (ECL)? Bias circuit follower D 2
amplifier pole circuit
circuit
diode TTL
63 PMOS and NMOS circuits are used largely in MSI functions LSI functions B 2
functions functions
64 The nominal value of the dc supply voltage for TTL and CMOS is 3V 5V 10 V 12 V B 2
If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static
65 (noncharging) HIGH output state, the power dissipation (PD) of the gate 5.5 Mw 5mW 5.5 W 1.1mW A 4
is
competitive three times slower than twice that

66 The switching speed of CMOS is now A 2
with TTL that of TT TTL of TTL
not sensitive
more
to
67 One advantage TTL has over CMOS is that TTL is less expensive faster widely B 2
electrostatic
available
discharge
12-volt 5-volt
68 TTL operates from a 9-volt suppl 3-volt supply D 1
supply supply
the same
less power more power no power
69 A CMOS IC operating from a 3-volt supply will consume power as a A 2
than a TTL IC than a TTL IC at all
TTL IC
DIP and SOIC
DIP SOIC
70 CMOS IC packages are available in configuration None of this C 2
configuration configuration
s
Page 5
DELD UNIT 2
The terms "low speed" and "high speed," applied to logic circuits, refer to propagation clock
71 rise time fall time C 2
the delay time speed
dc supply dc supply ac supply ac supply
72 The power dissipation, PD, of a logic gate is the product of the B 2
voltage and voltage and voltage and voltage
73 How many different logic level ranges for TTL 1 2 3 4 D 1
Metal-oxide semiconductor field-effect transistors (MOSFETs) are the PMOS
74 CMOS circuits TTL ECL circuits A 2
active switching elements in circuits
none of
75 ECL IC technology is……………….than TTL technology. faster slower equal A 1
this
both low neither
power low power
low power
76 A major advantage of ECL logic over TTL and CMOS is high speed dissipation dissipation B 1
dissipation
and high nor high
speed speed
TTL, ECL, TTL, ECL, TTL, ECL,
77 Digital technologies being used now-a-days are DTL and EMOS CMOS and CMOS and CMOS and B 2
RTL DTL DTL
78 Which of the following is the fastest logic TTL ECL CMOS PMOS B 2
Open collector Tri state
79 Which TTL logic gate is used for wired ANDing Totem Pole ECL gates A 2
output output
Less than Thrice of
80 CMOS circuits consume power Equal to TTL Twice of TTL B 1
TTL TTL
large
CMOS circuits are extensively used for ON-chip computers mainly low power high noise
81 packing low cost. C 2
because of their extremely dissipation immunity
density
Dual edge Dual edge Dual edge
Dual edge
triggered D triggered D triggered
82 The MSI chip 7474 is triggered JK C 2
flip-flop flip-flop JK flip-flop
flip-flop (TTL).
(CMOS). (TTL). (CMOS).
83 The logic 0 level of a CMOS logic device is approximately 1.2 volts 0.4 volts 5 volts 0 volts D 2
Page 6
DELD UNIT 2
These devices
use Schottky
transistors
The S
and diodes to The gate The S
denotes a
prevent them transistors denotes the
slow
from going are silicon fact that a
version of
into (S), and the single gate is
the device,
saturation; gates present in
84 which is a A 4
this results in therefore the IC rather
What is unique about TTL devices such as the 74SXX? consequen
faster turn-on have lower than the
ce of its
and turn-off values of usual
higher
times, which leakage package of
power
translates into current. 2–6 gates.
rating.
higher
frequency
operation.
85 Which of the following logic families has the shortest propagation delay? CMOS BiCMOS ECL 74SXX C 1
because they
can be
so they don’t because they damaged by
86 Why must CMOS devices be handled with care? all of above C 2
get dirty break easily static
electricity
discharge
Page 7
DELD UNIT 2
Unused
All unused AND and
They should inputs NAND
be left should be inputs
disconnected All unused connected to should be
so as not to gates should an unused tied to
produce a load be output; this VCC
on any of the connected will ensure through a
87 What should be done to unused inputs on TTL gates? D 2
other circuits together and compatible 1k
and to tied to V loading on resistor;
minimize through a 1 both the unused
power loading k resistor. unused OR and
on the voltage inputs and NOR
source. unused inputs
outputs. should be
grounded.
Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and
88 ICCH = 10 mA and ICCL = 23 mA. What is the power dissipation for the 50 Mw 82.5 mW 115 mW 165 mW B 4
chip?
89 Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate? YES No A 1
wide range
very high very high
90 What is the major advantage of ECL logic? of operating very low cost A 2
speed power
voltage
long long
propagation propagation
As a general rule, the lower the value of the speed–power product, the none of
91 delay and high delay and Both B 2
better the device because of its: above
power low power
consumption consumption
Page 8
DELD UNIT 2
54XX has
a
54XX has a narrower
wider power power
What is the difference between the 54XX and 74XX series of TTL logic 54XX is supply and supply
92 54XX is faster. C 2
gates? slower. expanded and
temperature contracted
range.
temperatu
re range.
93 What is the range of invalid TTL output voltage? 0.0–0.4 V 0.4–2.4 V 2.4–5.0 V 0.0–5.0 V B 2
source,
sink, source source, sink sink, source
94 An open collector output can ________ current, but it cannot ________. sink A 2
current current voltage
voltage
to reduce the
effects of
to reduce noise,
to block dc,
Why is a decoupling capacitor needed for TTL ICs and where should it be noise, connect NONE OF
95 connect to C 2
connected connect to between ABOVE
input pins
input pins power
supply and
ground
good noise low poor noise
low noise
immunity, propagation immunity,
margin, low
negative time, high- positive
output voltage
logic, high- frequency supply
swing,
frequency response, voltage
Which of the following summarizes the important features of emitter- negative
96 capability, low power operation, A 2
coupled logic (ECL)? voltage
low power consumption, good low-
operation, fast,
dissipation, and high frequency
and high
and short output operation,
power
propagation voltage and low
consumption
time swings power
to provide to provide to provide
to provide Vcc
97 Why is a pull-up resistor needed for an open collector gate? ground for the HIGH the LOW C 2
for the IC
the IC voltage voltage
Page 9
DELD UNIT 2
to
to increase the to decrease to increase decrease
Why is a pull-up resistor needed when connecting TTL logic to CMOS
98 output LOW the output the output the output C 2
logic?
voltage LOW voltage HIGH voltage HIGH
voltage
a circuit any gate
a conditioning connected that is a TTL
circuit between the operational any TTL
connected driver and amplifier circuit
between a load to designed to that is an
99 The word "interfacing" as applied to digital electronics usually means: B 2
standard TTL condition a condition input
NAND gate signal so signals buffer
and a standard that it is between stage
TTL OR gate compatible NMOS
with the load transistors
10%,
The rise time (tr) is the time it takes for a pulse to rise from its ________
10%, 90%, 90%, 10%, 20%, 80%, 70.7%,
100 point up to its ________ point. The fall time (tf) is the length of time it takes A 4
90%, 10% 10%, 90% 80%, 20% 70.7%,
to fall from the ________ to the ________ point.
10%
The term buffer/driver signifies the ability to provide low output
101 TRUE FALSE B 2
currents to drive light loads.
represent
positive and
negative
represent MOS-type
are
MOSFET devices,
enhancement
devices which can be
-type CMOS
utilizing either operated
devices used
P-channel or N- from None of
102 PMOS and NMOS ________. to produce a A 4
channel differential the above
series of
devices power
high-speed
exclusively supplies and
logic known
within a given are
as 74HC
gate compatible
with
operational
amplifiers
Page 10
DELD UNIT 2
At high
frequencie
s, the gate
will only
be able to
deliver
At high 70.7 % of
frequencies, rated
charging and power
discharging and
At low At high the gate charging
frequencies, At frequencies, capacitance and
low the gate will will draw a dischargin
Why is the operating frequency for CMOS devices critical for
103 frequencies, only be able heavy g the gate C 2
determining power dissipation?
power to deliver current from capacitanc
dissipation 70.7 % of the power e will
increases. rated power. supply and draw a
thus heavy
increase current
power from the
dissipation. power
supply
and thus
increase
power
dissipation
.
noise power propagatio
104 Ten TTL loads per TTL driver is known as: fan-out B 2
immunity dissipation n delay
a CMOS a TTL a CMOS
inverting tristate noninverting a CMOS
The problem of different current requirements when CMOS logic circuits bilateral inverting bilateral buffer or
105 D 4
are driving TTL logic circuits can usually be overcome by the addition of: switch buffer switch inverting
between the between the between the buffer
stages stages stages
Page 11
DELD UNIT 2
cannot, can,
together, if together,
the outputs should, in together
are in series, they can
can, in parallel, opposite certain handle
sometimes states applications larger
106 B 4
higher current excessively may require load
Totem-pole outputs ________ be connected ________ because ________.
is required high higher currents
currents can output and
damage one voltage higher
or both output
devices voltages
reduces
input prevents creates
allows faster
107 The high input impedance of MOSFETs: current and dense low-noise B 2
switching
power packing reactions
dissipation
source
The output current capability of a single 7400 NAND gate when HIGH is
108 source current sink current IOH current of A 2
called _____
IOH
The time needed for an output to change from the result of an input noise propagation
109 fan-out rise time C 2
change is known as: immunity delay
The problem of interfacing IC logic families that have different supply tristate decoupling pull-down
110 Level-shifter A 2
voltages (VCC's) can be solved by using a: shifter capacitor resistor
What is the advantage of using low-power Schottky (LS) over standard more power less power cost is
111 cost is less B 2
TTL logic? dissipation dissipation more
when the
A level when the
A level shifter supply
shifter is supply
112 When is a level-shifter circuit needed in interfacing logic? is always voltages D 2
never voltages are
needed. are
needed. the same
different
provide provide are never
are always on
113 A TTL totem-pole circuit is designed so that the output transistors: linear phase voltage on D 2
together
splitting regulation together
114 The most common TTL series ICs are: E-MOSFET 7400 QUAD AC00 B 1
Which family of devices has the characteristic of preventing saturation
115 TTL ECL MOS IIL B 2
during operation?
116 How many 74LSTTL logic gates can be driven from a 74TTL gate? 10 20 30 40 B 2
Page 12
DELD UNIT 2
The HCT
he HCT
series is
series is
not input
The HCT input and
What is the difference between the 74HC00 series and the 74HCT00 The HCT and
117 series is output C 4
series of CMOS logic? series is faster. output
slower. voltage
voltage
compatible
compatible
with TTL.
with TTL.
Why are the maximum value of VOL and the minimum value of VOH
It doesn't
used to determine the noise margin rather than the typical values for
These are These are These are matter
these parameters?
118 worst-case normal best-case what A 2
conditions. conditions. conditions. values are
used.
119 What is the standard TTL noise margin? 5.0 V 0.0 V 0.8 V 0.4 V D 2
Which logic family is characterized by a multiemitter transistor on the None of
120 ECL CMOS TTL C 2
input? the above
adding a fixed
voltage- avoiding this adding an adding an
he problem of the VOH(min) of a TTL IC being too low to drive a CMOS divider bias condition external pull- external
121 circuit and meet the CMOS requirement of VIH(min) is usually easily resistive and only down pull-up D 4
overcome by: network at the using TTL to resistor to resistor to
output of the drive TTL ground VCC
TTL device
less
more power more power less power power
How does the 4000 series of CMOS logic compare in terms of speed and dissipation dissipation dissipation dissipation
122 D 2
power dissipation to the standard family of TTL logic? and slower and faster and faster and
speed speed speed slower
speed
tie them tie them None of
123 What should be done with unused inputs to a TTL NAND gate? let them float C 2
LOW HIGH the above
Which of the following logic families has the highest maximum clock
124 S-TTL AS-TTL HS-TTL HCMOS B 2
frequency?
Page 13
DELD UNIT 2
The input
gates of
the FETs
When the are
frequency predomina
reaches the The higher ntly
critical the number capacitive,
value, the of gates and as the
Each CMOS gate will attached to signal
input gate has only be the output, frequency
a specific capable of the more increases
propagation delivering frequently the
time and this 70% of the they will capacitive
limits the normal have to be loading
125 Why is the fan-out of CMOS gates frequency dependent? D 4
number of output serviced, also
different gates voltage and thus increases,
that can be consequently reducing the thereby
connected to the output frequency at limiting
the output of a power will which each the
CMOS gate. be one-half will be number of
of normal; serviced loads that
this defines with an may be
the upper input signal. attached
operating to the
frequency. output of
the
driving
gate.
Page 14
DELD UNIT 2
A pull-up
resistor
must be
used
A 5 V Zener
As long as between
diode must
the CMOS the TTL
be placed
supply output-
across the
A dropping voltage is 5 CMOS
inputs of the
resistor must V, they can input
TTL gates in
be used on the be node and
order to
126 What must be done to interface TTL to CMOS? CMOS 12 V interfaced; Vcc; the D 2
protect them
supply to however, the value of
from the
reduce it to 5 fan-out of RP will
higher
V for the TTL. the TTL is depend on
output
limited to the
voltages of
five CMOS number of
the CMOS
gates. CMOS
gates.
gates
connected
to the
node.
Nothing. The
The Schottky- Using
What causes low-power Schottky TTL to use less power than the 74XX 74XX series A larger
127 clamped NAND C 2
series TTL? uses less value resistor
transistor gates
power.
Page 15
DELD UNIT 2
The 7400
series was
originally
developed
by Texas
Instrumen
The 5400
ts. The
series are
The 5400 5400
military The 7400
series are series was
grade and series are an
military grade brought
What are the major differences between the 5400 and 7400 series of allow for a improvement
128 and require out by B 2
ICs? wider range over the
tighter supply National
of supply original
voltages and Semicondu
voltages and 5400s.
temperatures. ctors after
temperature
TI's
s.
patents
expired,
as a
second
supply
source.
The devices
All tools, test
should be
The devices equipment,
stored and
should not be and metal
shipped in All of the
129 Which of the following statements apply to CMOS devices? inserted into workbenches D 2
antistatic above.
circuits with should be
tubes or
the power on. tied to earth
conductive
ground.
foam.
Which of the logic families listed below allows the highest operating
130 74AS ECL HCMOS 54S B 2
frequency?
What is the increase in switching speed between 74LS series TTL and
131 5 10 50 100 B 2
74HC/HCT (High-Speed CMOS)?
emitter-
electron- energy- NONE OF
132 What does ECL stand for? coupled B 2
coupled logic; coupled logic; ABOVE
logic;
Page 16
DELD UNIT 2
The
devices
use
Schottky
transistors
and
diodes to
The S
prevent
The gate denotes the The S
them from
transistors are fact that a denotes a
going into
silicon (S), and single gate is slow version
saturation;
the gates present in of the device,
133 What is unique about TTL devices such as the 74S00? this D 4
therefore have the IC rather which is a
results in
lower values of than the consequence
faster turn
leakage usual of its higher
on and
current. package of power rating.
turn off
2–6 gates.
times,
which
translates
into
higher
frequency
operation.
emitter-
coupled
logic
emitter- current- transistor-
he bipolar TTL logic family that was developed to increase switching (ECL) and
134 coupled logic mode logic transistor D 2
speed by preventing transistor saturation is: transistor-
(ECL). (CML). logic (TTL).
transistor
logic
(TTL).
0.0 V and 0.4 0.0 V and 0.5 0.0V and
135 In TTL the noise margin is between 0.4 V and 0.8 V. A 2
V. V. 0.8 V.
What is the transitive voltage for the voltage input of a CMOS operating
136 1V 5V 10V 15V B 2
from 10V supply
137 The highest noise margin is offered by CMOS TTL ECL BICMOS B 2
Page 17
DELD UNIT 2
What is the transitive voltage for the voltage input of a CMOS operating
138 1V 5V 10V 20V B 2
from 10V supply ?
139 The digital logic family which has the lowest propagation delay time is ECL TTL CMOS PMOS A 2
Lower
Positive Higher Zero voltage
140 In a positive logic system, logic state 1 corresponds to voltage B 2
voltage voltage level level
level
Which of the following logic families is well suited for high-speed
141 TTL ECL MOS CMOS B 2
operations ?
142 Which of the following is the fastest logic? ECL TTL MOS CMOS A 1
143 he digital logic family which has the lowest propagation delay time is ECL TTL CMOS PMOS c 2
144 A binary digit is called a Bit Byte Number Character A 1
145
Noise
immunity is
the amount Operating
of noise speed is
Propagation
which can be Fan-in of a the
delay is the
applied to gate is maximum
time required
Which of the following statements is wrong ? the input of always equal frequency
for a gate to
146 a gate to fan-out of at which C 4
change its state
without the same gate digital
causing the data can
gate to be applied
change state to a gate
Which table shows the logical state of a digital circuit output for every
possible combination of logical states in the inputs ? Routing ASCII
147 Function table Truth table table table B 1
148 The digital logic family which has minimum power dissipation is TTL ECL MOS CMOS D 1
Page 18
DELD UNIT 4

UNIT - IV
Sr. Correct
No. Option
1 Which of the following is not a form of multivibrator? Astable. Monostable. Tristable. Bistable. C 1
The Q
A J-K flip-flop has two control inputs. What happens to the Q output on
The Q output The Q The Q output
the active edge of the clock if both control inputs are asserted
2 toggles to the output is set output is remains A 2
simultaneously?
other state. to 1. reset to 0. unchanged
.
3 TRUE False A 1
A master/slave bistable is formed using two bistable connected in series.
An astable has two metastable states and produces the function of a

4 TRUE False A 1
digital oscillator
In synchronous counters the clock input of each of the bistables are

5 TRUE False A 1
connected together so that each changes state at the same time.
1: When the maximum clock rate is quoted for a logic family, then it Multiplexe
6 shift register flip-flop counter B 1
applies to a r
2: The number of flip-flops required in a modulo N counter is
7 log2 (N) + 1 log2(N-1) log2 (N) N log2 (N) C 2
3: Flip-flop outputs are always same as

Independent
8 Complimentary The same previous A 1
of each other
input
4: How many gates (minimum) are needed for a 3-bit up-counter using
9 6 3 2 1 C 2
standard binary and using T lip-lops ? Assume unlimited fan-in.
Synchronous Directed Either (a) or
10 5: The clear data and present input of the JK lip-lop are known as None of these C 1
inputs inputs (b)
Page 1
DELD UNIT 4
Same as a
A decade
mode-5 Ripple
counter A mod-7
11 A mod-2 counter followed by a mod-5 counter is counter carry A 1
counter
followed by a Counter
mod- 2 counter
What is the maximum counting speed of a 4-bit binary counter which is
12 1 MHz 10 MHz 100 MHz 8 MHz B 2
composed of flip-flops with a propagation delay of 25 ns ?
Go to state 0
and stay
Change its Go to state 1
8: A JK flip-lop has its J input connected to logic level 1 and its input to there
13 state at each and stay Retain its D 2
the Q output. A clock pulse is fed to its clock input. The flip-lop will now
clock pulse there previous
state
Q will flip
Q will flip from
9: Consider an RS lip-lops with both inputs set to 0. If a momentary '1' is from 0 to 1 Q will flip Q will flip
14 0 to 1 and then D 2
applied at the input S,then the output and then from 1 to 0 from 0 to 1
back to 0
back to 0
Present
outputs
Past outputs Both present
Present inputs only
15 The output of a sequential circuit depends on only and past C 2
only
inputs
Stepping J-K flip-

16 The ring counter is analogous to Toggle switch Latch C 1
switch flop
Reduce the Asynchron
number of ous input
Improve Improve
17 12: In a digital counter circuit feedback loop is introduced to input pulses and C 1
distortion stability
to reset the output
counter pulses
Change its Go to state 1 Go to state 0 Retain its
A J-K lip-lop has its J-input connected to logic level 1 and its input to the
18 state at each and stay and stay present A 2
Q output pulse is fed to its clock input the flip-flop will now
clock pulse there there state
Page 2
DELD UNIT 4
Which of the following conditions must be met to avoid race around None of
19 Δ t < tp < T T > Δt > tp 2 tp < Δt < T B 2
problem ? these
Match List I with List II and select the correct answer form the codes
given below the list List I
A. A shift register can be

B. A multiplexer
C. A decoder can List II
20 1.for parallel to serial conversion 312 231 132 12 3 C 4
2.to generate memory can be used chip select
3.for parallel to serial conversion
CODES:
ABC
With the use of an electronic counter six capsules are to be filled in

21 bottles automatically. In such a counter what will be the number of flip- 3 12 6 8 C 2
flops required ?
A parallel-
A serial-in A serial-in
Both (a) and in parallel-
22 A pulse train can be delayed by a finite number of clock periods using serial-out shift parallel-out D 1
(b) out shift
register shift register
register
23 How many illegitimate states has synchronous mod-6 counter ? 3 2 1 6 A 1
2 input XORs 2 input
NOR gates
2 input ANDs and 4 input NORs and
24 A 2 bit binary multiplier can be implemented using and shift B 2
only AND gates one XNOR
registers
only gate
Ripple
up-down parallel-
25 A ring counter is same as shift register carry C 1
counter counter
Counter
Combinational Sequential Both (a) and None of
26 The dynamic hazard problem occurs in C 1
circuit alone circuit only (b) these
n n-1
27 A n-stage ripple counter will count up to 2 2 n 2n-1 A 1
Page 3
DELD UNIT 4
Tell how
Synchroniz
much time
e events in
Tell the time of has elapsed Carry parllel
28 The clock signals are used in sequential logic circuits to various D 2
the day since the data signals
parts of
system was
system
turned on
Encoder
Demultiple
Decoder/demu
29 74L5138 chip functions as Multiplexer xer A 1
ltiplexer
A sequential circuit outputs a ONE when an even number (> 0) of one's

None of
30 are input; otherwise the output is ZERO. The minimum number of states 0 1 2 C 2
these
required is
Serial to Parallel to
Digital delay
31 A shift register can be used for parallel serial All of these D 1
line
conversion conversion
Transfer Shift
32 Popular application of flip-flop are Counters All of these D 2
register registers
Q type flip-flop
For which of the following flip-flops, the output is clearly defined for all
33 R-S flip-lop J-K flip-lop D flip-flop C 2
combinations of two inputs ?
Successive
When a large number of analog signals are to be converted an analog Ripple carry Dual stop Forward
34 approxima D 2
multiplexer is used. In this case most suitable A.D. converter will be counter type type counter type
tion type
35 To build a mod-19 counter the number of flip-flops required is 3 5 7 9 B 2
One stable
Two quasi Two stable and one None of
36 The astable multivibrator has A 2
stable states states quasi-stable these
state
How many bits are required to encode all twenty six letters, ten symbols,
37 5 6 10 48 B 2
and ten numerals ?
The functional difference between S-R flip-flop and J-K flip-flop is that J- is faster than S- Has a feed- Accepts both Both (a)
38 C 1
K flip-flop R flip-flop back path inputs 1 and (b)
Page 4
DELD UNIT 4
High state
39 In a positive edge triggered JK flip-flop, a low J and low K produces No change Low state None of these A 1
Master
When an inverter is placed between both inputs of an SR flip-flop, then
40 JK flip-flop D flip-flop SR flip-flop slave JK B 2
resulting flip-lop is
flip-flop
A 2 MHz signal is applied to the input of a J-K lip-lop which is operating
41 1 MHz 2 MHz 6 MHz 8 MHz D 2
in the 'toggle' mode. The frequency of the signal at the output will be
A SR flip-flop An SR flip-
A T flip-flop
Two D flip-
42 The master slave JK lip-flop is effectively a combination of and a T flip- lfop and a D
and a D flip- A 2
flops
flop flip-flop flop
Generally
External clock they
It is more Both (a) and
43 It is difficult to design asynhronous sequential circuit because is to be involve D 2
complex (b)
provided stability
problem
Frequency to Voltage to
Comparator Demultiplexe
44 A stable multivibrator is used as voltage frequency A 2
circuit r
converter converter
45 How many flip-flop are needed to divide the input frequency by 64 ? 2 5 6 8 C 1
J and K
clock input J and K
41: In a ripple counter using edge triggered JK flfp-flops, the pulse input clock input of inputs of
46 of one flip- inputs of all C 1
is applied to the all flip-flops one flip-
flops flip-flops
flop
The number of clock pulses needed to shift one byte of data from input
47 10 12 16 32 C 2
to the output of a 4-bit shift register is
JK flip-flop
is
acronym
JK flip flop There is a JK flip-flop
of
48 The main difference between JK and RS flip-flop is that needs a clock feedback in accepts both C 2
Junction
pulse JK lip-lop inputs as 1
cathode
multivibra
tor
Page 5
DELD UNIT 4
Which of the following unit will choose to transform decimal number to

49 Encoder Decoder Multiplexer Counter A 1
binary code ?
The flip-flops which operate in synchronism with external clock pulses Synchronous Asynchronou Either of the None of
50 A 1
are known as flip-flop s flip-flop above these
Master-
51 Which of the following flip-flop is free from race-around problem ? Q flip-flop T flip-flop SR flip-flop slave JK D 2
flip-flop
Master
If the input J is connected through K input of J-K, then flip-flop will T type flip-
52 D type flip-flop S-R flip-flop slave JK A 2
behave as a flop
flip-flop
If a clock with time period 'T' is used with n stage shift register, then (2n+1)T
53 nT sec (n-1)T sec n/T sec B 2
output of final stage will be delayed by sec
set of temporary
capacitor used storage unit
set to paper
to register within the part of the
tapes and
54 Register is a input CPU having main C 1
cards put in
instructions in dedicated or memory
a file
a digital general
computer purpose use
55 The number of flip-flops required in a decade counter is 3 4 8 10 B 1
Ring
Ring counter Twisted ring
Twisted ring counter
56 If in a shift resistor Q0 is fed back to input the resulting counter is with N : 1 with 2N : 1 C 1
with N : 1 scale with 2 N :
scale scale
1 scale
A 8-bit serial in / parallel out shift register contains the value “8”, _____
clock signal(s) will be required to shift the value completely out of the
57 1 2 4 8 D 2
register.
Input and
Current Current state
State variable, clock
58 In a sequential circuit the next state is determined by ________ and _______ state, flip- and external D 2
current state signal
flop output input
applied
The divide-by-60 counter in digital clock is implemented by using two Mod-50, Mod-10, Mod-50,
59 Mod-6, Mod-10 A 2
cascading counters: Mod-10 Mod-50 Mod-6
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the
60 True FALSE A 2
previous output state is maintained.
Page 6
DELD UNIT 4
The minimum time for which the input signal has to be maintained at the Pulse
Pulse
61 input of flip-flop is called ______ of the flip-flop. Set-up time Hold time Stability B 2
Interval time
time (PST)
62 74HC163 has two enable input pins which are _______ and _________ ENP, ENT ENI, ENC ENP, ENC ENT, ENI A 4
____________ is said to occur when multiple internal variables change due Race Hold and
63 Clock Skew Hold delay B 2
to change in one input variable condition Wait
Clear
Synchronous, input
Preset input
Asynchronous (CLR),
64 The _____________ input overrides the ________ input (PRE), Clear A 4
, synchronous asynchronou Preset
input (CLR)
s input
(PRE)
Mod-5 Mod-8 Mod-10
65 A decade counter is __________. Mod-3 counter D 2
counter counter counter
State of
transmissi
Remains in on line is
It is set to logic It is set to
66 In asynchronous transmission when the transmission line is idle, _________ previous not used B 2
low logic high
state to start
transmissi
on
67 A Nibble consists of _____ bits 2 4 8 16 B 1
68 The output of this circuit is always ________. 1 0 A Abar C 1
69 Excess-8 code assigns _______ to “-8” 1110 1100 1000 0 D 1
Vout / Vin = - Vout / Rf = - Rf / Vin = - Rf / Vin =
70 The voltage gain of the Inverting Amplifier is given by the relation ________ A 2
Rf / Ri Vin / Ri Ri / Vout Ri / Vout
None of
Local User Least Upper
71 LUT is acronym for _________ Look Up Table given A 2
Terminal Time Period
options
AND, NAND, OR, AND, NOT, NOR, NOT, OR,
72 The three fundamental gates are ___________ D 1
XOR NAND XOR AND
The size of
the
The The The size of
The total amount of memory that is supported by any digital system address
73 organization structure of decoding D 2
depends upon ______ bus of the
of memory memory unit
microproc
essor
Page 7
DELD UNIT 4
LIFO Flash Bust Flash

74 Stack is an acronym for _________ FIFO memory B 2
memory Memory Memory
75 Addition of two octal numbers “36” and “71” results in ________ 213 123 127 345 C 2
Clear
Preset input
76 ___________ is one of the examples of synchronous inputs. J-K input EN input Input A 2
(PRE)
(CLR)
__________occurs when the same clock signal arrives at different times at
None of
different clock inputs due to
77 Race condition Clock Skew Ripple Effect given B 2
propagation delay
options
Consider an up/down counter that counts between 0 and 15, if external
input(X) is “0” the counter counts
upward (0000 to 1111) and if external input (X) is “1” the counter
78 counts downward (1111 to 0000), now 0 1101 1011 1111 B 1
suppose that the present state is “1100” and X=1, the next state of the
counter will be ___________
Current Previous Previous

In a state diagram, the transition from a current state to the next state is Current state
79 state and state and state and A 1
determined by and the inputs
outputs inputs outputs
State
Next state State
80 ________ is used to simplify the circuit that determines the next state. State diagram assignmen D 2
table reduction
t
clock signal(s) will be required to shift the value completely out of the
81 1 2 4 8 D 1
register.
Assume that a 4-bit serial in/serial out shift register is initially clear. We
wish to store the nibble 1100. What
82 will be the 4-bit pattern after the second clock pulse? (Right-most bit 1100 11 0 1111 C 2
first.)
None of
Local User Least Upper
83 LUT is acronym for _________ Look Up Table given A 2
Terminal Time Period
options
Sum of
Associative Product of
84 The diagram given below represents __________ Demorgans law product D 2
law sum form
form
Page 8
DELD UNIT 4
It does not
It does not
Sets to clear show
The operation of J-K flip-flop is similar to that of the SR flip-flop except Doesn’t have accept
85 when both J transition on A 1
that the J-K flip-flop ___________ an invalid state asynchron
= 0 and K = 0 change in
ous inputs
pulse
Parallel
Serial data to Parallel data Serial data to
86 A multiplexer with a register circuit converts _________ data to B 1
parallel to serial serial
parallel
PAL that is
Non- programmed Reprogra
Very large
87 A GAL is essentially a ________. reprogrammab only by the mmable D 2
PAL
le PAL manufacture PAL
r
None of
Sequential FAST Mode
88 in ____________, all the columns in the same row are either read or written. MOS Access given C 2
Access Page Access
options
89 How many flip-flops are required to produce a divide-by-32 device? 2 5 6 4 B 2
A reduced state table has 18 rows. The minimum number of flip flops
90 18 9 5 4 C 2
needed to implement the sequential machine is
ease of
Advantage of synchronous sequential circuits over asynchronous ones is avoiding lower better
faster
91 problems hardware noise A 1
operation
due to requirement immunity
hazard
The characteristic equation of a JK flip flop is Qn+1=J.Qn+K.Q Qn+1=J.Q’n+ Qn+1=(J+K
92 Qn+1=QnJ.K B 1
n K’.Qn )Qn
THE
OUTPUT
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE
THE FLOP- OF FLIP-
SET TO LOGIC ZERO ------- Q=0 AND Q=1 AND
93 FLOP IS FLOP D 2
Q‟=1 Q‟=0
TRIGGERED REMAINS
UNCHANG
ED
Page 9
DELD UNIT 4
In ________ Q output of the last flip-flop of the shift register is connected to

the data input of the first Meally Johnson Ring
94 Moore machine D 2
flip-flop of the shift register. machine counter counter
5-BIT JOHNSON COUNTER SEQUENCES THROUGH ____ STATES

95 7 10 32 25 B 2
clock signal(s) will be required to shift
96 1 2 4 8 D 1
the value completely out of the register.
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT

WILL BE THE VALUE OF
97 REGISTER AFTER THREE CLOCK PULSES? 2 4 6 8 D 1
Serial in /
The alternate solution for a multiplexer and a register circuit is _________ Parallel in / Serial in / Parallel in /
Serial Out
98 Serial out shift Parallel out Parallel out A 1
shift
register shift register shift register
register
Parallel
A multiplexer with a register circuit converts _________ Serial data to Parallel data Serial data to
99 data to B 2
parallel
A synchronous decade counter will have _______ flip-flops
100 3 4 7 10 B 2
In ________ outputs depend only on the current state. State State
Moore
101 Mealy machine Reduction Assignmen B 1
Machine
table t table
The state
diagram
The Both the
Given the state diagram of an up/down counter, we can find ________ shows
The next state previous next and
only the
102 of a given state of a previous A 1
inputs/out
present state given states of a
puts of a
present state given state
given
states
Page 10
DELD UNIT 4
A SINGLE
ONLY A
THE HOURS COUNTER IS IMPLEMENTED USING __________ MOD-10 MOD-10 DECADE
SINGLE MOD-
103 AND MOD-6 AND MOD-2 COUNTER D 2
12 COUNTER
COUNTERS COUNTERS AND A
IS REQUIRED
FLIP-FLOP
The design and implementation of synchronous counters start from

_________ state
104 Truth table k-map state table D 2
diagram
NEGATIVE
POSITIVE-
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A PULSE -EDGE
GATED FLIP- EDGE
105 ___________ TRIGGERED TRIGGERE D 2
FLOPS TRIGGERED
FLIP-FLOPS D FLIP-
FLIP-FLOPS
FLOPS
Clear
Preset input
(PRE)
(CLR)
Preset
Low-to-high High-to-low
A positive edge-triggered flip-flop changes its state when ________________ Enable input input
107 transition of transition of A 1
(EN) is set (PRE) is
clock clock
set
Flip flops are also called _____________ Bi-stable Bi-stable
Bi-stable Bi-stable
108 multivibrator singlevibra C 1
dualvibrators transformer
s tors
A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY
THE USER AND NOT BY
109 THE MANUFACTURER. TRUE FALSE A 2
THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED

TO FORM A 16-INPUT
110 MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT AND OR NAND XOR B 2
__________ GATE
Page 11
DELD UNIT 4
2 INPUTS 3 INPUTS 3 INPUTS

A particular half adder has 2 INPUTS AND
111 AND 2 AND 1 AND 2 B 2
1 OUTPUT
OUTPUT OUTPUT OUTPUT
A full-adder has a Cin = 0. What are the sum (<PRIVATE
"TYPE=PICT;ALT=sigma"> ) and the carry (Cout) = 1, Cout
112 = 0, Cout = 0 = 0, Cout = 1 = 1, Cout = 0 B 2
when A = 1 and B = 1? =1
The sequence of states that are implemented by a n-bit Johnson counter

is 2n (n n2 (n
2n (2 raise
113 n+2 (n plus 2) multiplied raise to B 2
to power n)
by 2) power 2)
clock signal(s) will be required to shift
114 1 2 4 8 D 1
the value completely out of the register.
PAL that is
Non- programmed Reprogra
A GAL is essentially a ________. Very large
115 reprogrammab only by the mmable D 2
PAL
le PAL manufacture PAL
r
State of
transmissi
In asynchronous transmission when the transmission line is idle, _________ Remains in on line is
It is set to logic It is set to
116 previous not used B 1
low logic high
state to start
transmissi
on
Serial in /
The alternate solution for a demultiplexer-register combination circuit is Parallel in / Serial in / Parallel in /
Serial Out
117 _________ Serial out shift Parallel out Parallel out B 1
shift
register
Serial in /
Parallel in / Serial in / Parallel in /
The alternate solution for a multiplexer and a register circuit is _________ Serial Out
118 Serial out shift Parallel out Parallel out A 2
shift
register
Page 12
DELD UNIT 4
State State
Moore
119 In ________ outputs depend only on the current state. Mealy machine Reduction Assignmen B 2
Machine
table t table
Propagation Input
The changes Delay is zero Hold time
The changes in
in the data at (Output is is zero (no
the data at the
A transparent mode means ____________ the inputs of immediately need to
120 inputs of the A 4
the latch are changed maintain
latch are seen
not seen at when clock input after
at the output
the output signal is clock
applied) transition)
__________occurs when the same clock signal arrives at different times at

None of
different clock inputs due to
121 Race condition Clock Skew Ripple Effect given B 2
propagation delay.
options
Clear
122 ___________ is one of the examples of asynchronous inputs. J-K input S-R input D input Input D 1
(CLR)
Bi-stable devices remain in either of their _________ states unless the
123 inputs force the device to switch its state Ten Eight Three Two D 1
Reconfigurati Ripple Ripple

RCO Stands for _________ Reconfiguratio
124 on Clock Counter Clock D 2
n Counter
Output Output Output
Output
Preset
clock clock
set
The low to high or high to low transition of the clock is considered to be
126 a(n) ________ State Edge Trigger One-shot B 2
In asynchronous digital systems all the circuits change their state with
127 respect to a common clock TRUE FALSE B 1
Page 13
DELD UNIT 4
If the S and R inputs of the gated S-R latch are connected together using
a ______gate then there is only a
128 single input to the latch. The input is represented by D instead of S or R AND OR NOT XOR C 1
(A gated D-Latch)
Input is
129 If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop 0 1 Invalid B 1
invalid
3-to-8 decoder can be used to implement Standard SOP and POS Boolean
130 TRUE FALSE A 2
expressions
Decimal-
4-to-16 BCD-to-
131 The _______ Encoder is used as a keypad encoder. 2-to-8 encoder to-BCD D 1
encoder Decimal
Priority
(n-1) to (2n-
132 The simplest and most commonly used Decoders are the ______ Decoders n to 2n (n-1) to 2n n to 2n-1 A 1
1)
A Karnaugh map is similar to a truth table because it presents all the
possible values of input variables and the
133 TRUE False A 2
resulting output of each value.
The decimal “17” in BCD will be represented as _________10001(right opt

134 11101 11011 10111 11110 C 1
is not given)
Q2 :=Q1 OR X OR Q3 Q2:= Q1 $ X $ Q2:= Q1 # X Q2:= Q1 & X Q2:= Q1 !
135 B 2
The above ABEL expression will be Q3 # Q3 & Q3 X ! Q3
Synchrono
Above is the circuit diagram of _______ Asynchronous Asynchronou Synchronous
136 us down- A 2
up-counter s down- up-counter
counter
counter
2 floating- 4 floating- 6 floating-
The high density FLASH memory cell is implemented using ______________ 1 floating-gate
137 gate MOS gate MOS gate MOS A 1
MOS transistor
transistors transistors transistors
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is
LOW. The nibble 0111 is
138 1110 111 1000 1001 D 1
waiting to be entered on the serial data-input line. After two clock
pulses, the shift register is storing ________.
At T0 the value stored in a 4-bit left shift was “1”. What will be the value
139 of register after three clock pulses? 2 4 6 8 D 2
Page 14
DELD UNIT 4
State of
transmissi
Remains in on line is
In asynchronous transmission when the transmission line is idle, _________ It is set to logic It is set to
140 previous not used B 2
low logic high
state to start
transmissi
on
Parallel
A multiplexer with a register circuit converts ____ Serial data to Parallel data Serial data to
141 data to B 2
parallel
State
________ is used to simplify the circuit that determines the next state. Next state State
142 State diagram assignmen D 1
table reduction
t
State State
In ________ outputs depend only on the combination of current state and Moore
143 Mealy machine Reduction Assignmen A 1
inputs Machine
table t table
Clear
Synchronous, input
Preset input
The _____________ input overrides the ________ input Asynchronous, (CLR),
144 (PRE), Clear A 1
synchronous asynchronou Preset
input (CLR)
s input
(PRE)
Clear
145 ___________ is one of the examples of asynchronous inputs. J-K input S-R input D input Input 2
(CLR)
Preset
clock clock
set
In asynchronous digital systems all the circuits change their state with
147 respect to a common clock TRUE False B 1
For a gated D-Latch if EN=1 and D=1 then Q(t+1) = _________

148 0 1 Q(t) Invalid B 2
Page 15
DELD UNIT 4
It does not
It does
Sets to clear show
The operation of J-K flip-flop is similar to that of the SR flip-flop except Doesn’t have not accept
149 when both J transition on A 4
that the J-K flip-flop ___________ an invalid state asynchron
= 0 and K = 0 change in
ous inputs
pulse
If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-
Input is
150 flop 0 1 Invalid C 2
invalid
The sequence of states that are implemented by a n-bit Johnson counter
2 raise to n raise to
151 is n+2 2n B 2
power n power 2
________
of a ROM is the time it takes
for the data to appear at the Data
152 Write Time Recycle Time Refresh Time Access Time D 1
Output of the ROM chip after an
address is applied at the address
input lines
In _______ the Q output of the last flip-flop of the shift register is
connected to the data input of the first flipflop. Moore Meally
153 Johnson counterRing counter 1
machine machine
At T0 the value stored in a 4-bit left shift was “1”. What will be the value
154 of register after three clock pulses? 2 4 6 8 D 2
Serial in /
Parallel in / Serial in / Parallel in /
Serial Out
155 The alternate solution for a multiplexer and a register circuit is Serial out shift Parallel out Parallel out A 2
shift
register
A multiplexer with a register circuit converts _________ Parallel
Serial data to Parallel data Serial data to
156 data to B 2
parallel
The design and implementation of synchronous counters start from state
157 Truth table k-map state table D 1
________ diagram
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A NEGATIVE
POSITIVE-
___________ PULSE -EDGE
GATED FLIP- EDGE
158 TRIGGERED TRIGGERE D 1
FLOPS TRIGGERED
FLIP-FLOPS D FLIP-
FLIP-FLOPS
FLOPS
Page 16
DELD UNIT 4
Clear
Preset input
(PRE)
(CLR)
Preset
clock clock
set
Bi-stable Bi-stable
Flip flops are also called _____________ Bi-stable Bi-stable
161 multivibrator singlevibra C 1
dualvibrators transformer
s tors
The sequence of states that are implemented by a n-bit Johnson counter 2n (n n2 (n
2n (2 raise
162 is n+2 (n plus 2) multiplied raise to B 1
to power n)
by 2) power 2)
Propagation Input
The changes Delay is zero Hold time
The changes in
in the data at (Output is is zero (no
the data at the
the inputs of immediately need to
163 A transparent mode means _____________ inputs of the A 2
the latch are changed maintain
latch are seen
not seen at when clock input after
at the output
the output signal is clock
applied) transition)
Clear
___________ is one of the examples of asynchronous inputs.
164 J-K input S-R input D input Input D 2
(CLR)
Preset
clock clock
set
If the S and R inputs of the gated S-R latch are connected together using
a ______gate then there is only a
166 single input to the latch. The input is represented by D instead of S or R AND OR NOT XOR C 2
(A gated D-Latch)
Input is
167 If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop 0 1 Invalid 1
invalid
Page 17
DELD UNIT 4
The state
diagram
Both the
The previous shows
The next state next and
state of a only the
168 Given the state diagram of an up/down counter, we can find ________ of a given previous A 1
given inputs/out
present state states of a
present state puts of a
given state
given
states
NEGATIVE
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A POSITIVE-
PULSE -EDGE
___________ GATED FLIP- EDGE
169 TRIGGERED TRIGGERE D 2
FLOPS TRIGGERED
FLIP-FLOPS D FLIP-
FLIP-FLOPS
FLOPS
In ________ Q output of the last flip-flop of the shift register is connected to
Meally Johnson Ring
170 the data input of the first Moore machine D 2
machine counter counter
flip-flop of the shift register.
A counter is implemented using three (3) flip-flops, possibly it will have
________ maximum output
171 3 7 8 15 C 2
status.
We have a digital circuit. Different parts of circuit operate at different

clock frequencies (4MHZ, 2MHZ
and 1MHZ), but we have a single clock source having a fix clock Using S-R Flop-
172 D-flipflop J-K flip-flop T-Flip-Flop C 1
frequency (4MHZ), we can get help by Flop
___________
If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop Input is
173 0 1 Invalid B 1
invalid
If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip- Input is
174 0 1 Invalid C 1
flop invalid
THE
OUTPUT
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE
THE FLOP- OF FLIP-
SET TO LOGIC ZERO Q=0 AND Q=1 AND
175 FLOP IS FLOP C 2
_________ Q‟=1 Q’=0
TRIGGERED REMAINS
UNCHANG
ED
Page 18
DELD UNIT 4
If an S-R latch has a 1 on the S input and a 0 on the R input and then the S
176 input goes to 0, the latch will set reset invalid clear A 2
be
For a positive edge-triggered J-K flip-flop with both J and K HIGH, the
outputs will______ if the clock goes HIGH.
177 toggle set reset not change A 2
The D latch The D flip-

The D latch The D flip-
is used for flop has a
178 What is the difference between a D latch and a D flip-flop? has a clock flop has an D 2
faster clock
input. enable input.
operation. input.
Counts high
Counts no. of and low None of
A frequency counter ______________ Counts pulse
179 clock pulses range of given B 2
width
in 1 second given clock options
pulse
Page 19
DELD UNIT 1

UNIT - I
Sr. Correct
No. Option
Unit No:-1 Number Systems and Logic Design Techniques
1 The Gray code for decimal number 6 is equivalent to 1100 1001 101 110 C 1
2 The 2s compliment form (Use 6 bit word) of the number 1010 is 111100 110110 110111 1011 B 2
3 AB+(A+B)’ is equivalent to A Ex-Nor B A Ex OR B (A+B)A (A+B)B A 2
4 The hexadecimal number equivalent to (1762.46)8 is 3F2.89 3F2.98 2F3.89 2F3.98 B 1
One input is One input is Two input All input
5 A three input NOR gate gives logic high output only when D 1
high low are low are LOW
None of
6 The absorption law in Boolean algebra say that X+X=X X.Y=X x+x.y=x C 2
the above
7 Logic X-OR operation of (4ACO)H & (B53F)H results AACB 0000 ABCD FFFF D 2
8 What is decimal equivalent of (11011.1000)2 ? 22 22.2 20.2 27.5 D 1
Sign 2's 1's All of the
9 The negative numbers in the binary system can be represented by A 1
magnitude complement complement above
Signed 1’s 2’s
None of
10 Negative numbers cannot be represented in magnitude complement complement D 1
the above
form form form
11 The answer of the operation (10111)2*(1110)2 in hex equivalence is 150 241 142 1.01E+08 C 2
12 The Hexadecimal number equivalent of (4057.06)8 is 82F.027 82F.014 82F.937 83F.014 B 1
13 The NAND gate output will be low if the two inputs are 00 01 10 11 D 1
14 A binary digit is called a Bit Character Number Byte A 1
15 What is the binary equivalent of the decimal number 368 101110000 110110000 111010000
1.11E+08 A 1
10111011
16 What is the binary equivalent of the Octal number 367 11110111 011100111 110001101 A 1
1
17 What is the binary equivalent of the Hexadecimal number 368 1111101000 1101101000 1101111000 1.11E+09 B 1
18 What is the binary equivalent of the decimal number 1011 1111110111 1111000111 1111110011 1.11E+09 C 1
Page 1
DELD UNIT 1
19 The gray code equivalent of (1011)2 is 1101 1010 1111 1110 D 1

20 The decimal equivalent of hex number 1A53 is 6793 6739 6973 6379 B 1
21 ( 734)8 =( )16 C1D DC1 1CD 1DC D 1
22 The simplification of the Boolean expression (A'BC')'+ (AB'C)' is 0 1 A BC B 2
23 The hexadecimal number ‘A0’ has the decimal value equivalent to 80 256 100 160 D 1
25 The Boolean expression A.B+ A.B+ A.B is equivalent to A+B A'.B (A + B)' A.B A 2
26 The 2’s complement of the number 1101101 is 101110 111110 110010 10011 D 1
27 When simplified with Boolean Algebra (x + y)(x + z) simplifies to x x + x(y + z) x(1 + yz) x + yz D 2
The code where all successive numbers differ from their preceding
28 Binary code. BCD. Excess – 3. Gray. D 1
number by single bit is
29 -8 is equal to signed binary number 10001000 OOOO1000 10000000 11000000 A 2
OR gate and NOR gate NOR gate NAND
30 DeMorgan’s first theorem shows the equivalence of Exclusive OR and Bubbled and NAND gate and B 1
gate. AND gate. gate. NOT gate
9’s
When signed numbers are used in binary arithmetic, then which one of Sign- 1’s 2’s
31 compleme A 1
the following notations would have unique representation for zero. magnitude. complement. complement.
nt.
32 The decimal equivalent of Binary number 11010 is 26 36 16 23 A 1
33 1’s complement representation of decimal number of -17 by using 8 bit 1110 1110 1101 1101 1100 1100 0001 0001 A 1
34 representation
The is of decimal number 26 is
excess 3 code 0100 1001 01011001 1000 1001 01001101 B 1
35 How many AND gates are required to realize Y = CD+EF+G 4 5 3 2 D 1
36 The hexadecimal number for (95.5)10 is (5F.8) 16 (9A.B) 16 ( 2E.F) 16 ( 5A.4) 16 A 1
37 The octal equivalent of (247) 10 is ( 252) 8 (350) 8 ( 367) 8 ( 400) 8 C 1
none of
38 The number 140 in octal is equivalent to (96)10 . ( 86) 10 (90) 10 . A 1
these.
39 The NOR gate output will be low if the two inputs are 11 01 10 All D 1
none of
40 Convert decimal 153 to octal. Equivalent in octal will be (231)8 ( 331) 8 ( 431) 8 . A 1
these.
41 The decimal equivalent of ( 1100)2 is 12 16 18 20 A 1
none of
42 The binary equivalent of (FA)16 is 1010 1111 1111 1010 10110011 B 1
these
How many two-input AND and OR gates are required to realize None of
43 2,2 2,3 3,3 A 1
Y=CD+EF+G these
Page 2
DELD UNIT 1
44 The excess-3 code of decimal 7 is represented by 1100 1001 1011 1010 D 1

When an input signal A=11001 is applied to a NOT gate serially, its
45 00111 00110 10101 11001 B 2
output signal is
46 The result of adding hexadecimal number A6 to 3A is DD E0 F0 EF B 1
A universal logic gate is one, which can be used to generate any logic
47 OR AND XOR NAND D 1
function. Which of the following is a universal logic gate?
To
To map the maximize
To minimize
Reducing the given the terms
the terms in
48 Karnaugh map is used for the purpose of electronic Boolean of a given C 1
a Boolean
circuits used. logic a Boolean
expression.
function. expression
.
49 The 2’s complement of the number 1101110 is 0010001 0010001 0010010 None C 1
50 The decimal equivalent of Binary number 10101 is 21 31 26 28 A 1
How many two input AND gates and two input OR gates are required to
51 1,1 4,2 3,2 2,3 A 1
realize Y = BD+CE+AB
52 Which of following are known as universal gates NAND & NOR AND & OR. XOR & OR.
None. A 1
53 Convert the octal number 7401 to Binary. 1.111E+11 1.1111E+11 1.111E+11
1.11E+11 A 1
54 Find the hex sum of (93)16 + (DE)16 . (171)16 (271)16 (179)16
(181)16 A 1
1110 (OR
55 Perform 2’s complement subtraction of (7)10 − (11)10 . 1100 (OR -4) 1101 (OR -5) 1011 (OR -3) A 1
-6)
56 What is the Gray equivalent of (25)10 01101 110101 10110 10101 D 1
57 Simplify the Boolean expression F = C(B + C)(A + B + C). C BC ABC A+BC A 2
Simplify the following expression into sum of products using Karnaugh A'B+C' D+ A'B'+C' D'+ A'B'+C' D+ A'B+C' D'+
58 A 4
map F(A,B,C,D) = (1,3,4,5,6,7,9,12,13) A'D+BC' A'D'+B'C' A'D+BC' A'D'+BC'
( A + B'
59 Simplify F = (ABC)'+( AB)'C+ A'BC'+ A(BC)'+ AB'C. ( A' + B' +C' ) ( A' + B +C ) ( A + B +C ) A 4
+C' )
11001.010
60 Determine the binary numbers represented by 25.5 11001.1 011011.101 10101.110 A 1
1
61 Conversion of decimal number 10.625 into binary number: 1010.101 1110.101 1001.11 1001.101 A 1
Conversion of fractional number 0.6875 into its equivalent binary
62 0.1011 0.1111 0.10111 0.0101 A 1
number:
Page 3
DELD UNIT 1
Perform the following subtractions using 2’s complement method.

63 00001 00010 00011 11110 A 3
01000 – 01001
64 Subtraction of 01100-00011 using 2’s complement method. : 1001 1000 1010 0110 A 3
ABC D' + A' B' ABC D + A B ABC D' +
Minimize the logic functionY(A,B,C,D) = m(0,1,2,3,5,7,8,9,11,14) . Using A' B' + B' C' +
65 + B' C' + B' D+ + B' C' + B' A' B' + B' A 4
Karnaugh map. B' D+ A'D
A'D D+ A'D C' + B' D
Simplify the given expression to its Sum of Products (SOP) form Y = (A + AC+ BC+ A'B + BC+ A'B + A' AC+ A'B +
66 AC+ BC+ A'B A 4
B)(A + (AB)')C + A'(B+C')+ A'B+ ABC A' C' C' A' C'
(1010010.
10101011)
(1010010.1010 (1010010.10 (1010010.10
2;
Convert the decimal number 82.67 to its binary, hexadecimal and octal 1011)2; 101011)2; 101011)2;
67 (52.AB)16 ; A 1
equivalents (52.AB)16 ; (52.AB)16 ; (52.AB)16 ;
(122.526)8 (122.526)9 (122.526)10
(122.526)1
1
(100100 )2 OR (000100 )2 Both (A) and None of

68 Add 20 and (-15) using 2’s complement. A 3
(+4)10 OR (-4)10 (B) the above
69 Add 648 and 487 in BCD code. 1135. 1136 1235 1138 A 3
(10111.100110 (10101.1001 (10001.1001 (10111.10
70 (23.6)10 = (X)2 FIND X A 1
0)2 100)2 100)2 00011)2
(41.88F5C28)16 (42.88F5C28 (42.88F5C
71 (65.535)10 =(X)16 FIND X (41.88F5C)16. A 1
. )16. )16.
11010000
72 Convert the decimal number 430 to Excess-3 code: 110110001 110110000 110110011 A 1
1
73 Convert the binary number 10110 to Gray code: 11101. 11001. 10101. 11100 A 1
Minimize the following logic function using K-maps F(A,B,C,D) = A B' C' + C' D + C' D + B'D + A B' C' + B'D A B' C' + C'
74 A 4
m(1,3,5,8,9,11,15) + d(2,13) B'D + AD AD + AD D + B'D
75 Convert (2222)10 in Hexadecimal number. 8AE 8BE 93C FFF A 1
Quotient - Quotient - Quotient -
Quotient -1001
1000 1001 1001
76 Divide ( 101110) 2 by ( 101)2. Remainder - A 4
Remainder - Remainder - Remainder
001
001 011 -000
F=[(B+D’)+
F=[(B+D’)+(B+ F=[(B+D’)+(B F=[(B+D’)+(B
Minimise the logic function (POS Form) F A,B,C,D) = PI M (1, 2, 3, 8, 9, (B+C’)’(‘A’
77 C’)’(A’+C’)+(A’ +C’)’(‘A’+C’)+ +C’)’(‘A’+C’)+ A 4
10, 11,14)× d (7, 15) +C’)+(A’+B
+B)]’ (A’+B)]’ (A’+B)]’
)]’
Page 4
DELD UNIT 1
78 Perform following subtraction (i) 11001-10110 using 1’s complement 00011 00111 00010 10011 A 3
79 Perform following subtraction(ii) 11011-11001 using 2’s complement 00010 00111 00011 10011 A 3
Reduce the following equation using k-map Y = (ABC)'+ A(CD)'+ AB'+
80 B'+(AD)' B' (AD)' B'+AD A 4
ABCD'+ (AB)'C
= = (A+B' = =
Write the expression for Boolean function F (A, B, C) = m (1,4,5,6,7) in
81 (A+B+C)(A+B' +C)(A+B' +C' (A+B+C)(A+B (A+B+C)(A A 4
standard POS form.
+C)(A+B' +C' ) ) ' +C) +B' +C' )
Convert the decimal number 45678 to its hexadecimal equivalent
82 (B26E)16 (A26E)16 (B26B)16 (B32E)16 A 1
number.
83 Convert (177.25)10 to octal. (261.2)8 (260.2)8 (361.2)8 (251.2)8 A 1
Reduce the following equation using k-map Y = B C' D'+ A' B C' D+ A B C' BC’ + BD +
84 BC’ + BD BC’ + BD+A BC’ + BD + AC A 4
D+ A' B C D+ A B C D AD
10110010.10 01001101.00
85 8-bit 1’s complement form of –77.25 is 1001101.01 10110010 B 2
11 10
2’s
In computers, subtraction is generally carried out by 9’s 10’s 1’s
86 compleme D 1
complement complement complement
nt
87 The 2s compliment form (Use 6 bit word) of the number 1010 is 111100 110110 110111 1011 B 1
10101111
88 The answer of the operation (10111)2*(1110)2 in hex equivalence is 150 241 142 C 2
0
89 The decimal number equivalent of (4057.06)8 is 2095.75 2095.075 2095.937 2095.094 D 1
90 The gray code equivalent of (1011)2 is 1101 1010 1110 1111 D 1
01001001.110 11001001.11 10110110.01 10110110.
91 12-bit 2’s complement of –73.75 is C 2
0 00 00 1100
92 The 2’s complement of the number 1101101 is 101110 111110 110010 10011 D 1
93 The hexadecimal number equivalent to (1762.46)8 is 3F2.89 3F2.98 2F3.89 2F3.98 B 1
94 What is decimal equivalent of BCD 11011.1100 ? 22.0 22.2 20.2 21.2 B 2
11110000
95 What is the binary equivalent of the decimal number 368 101110000 110110000 111010000 A 1
0
97 The decimal equivalent of hex number 1A53 is 6793 6739 6973 6379 B 1
(001011111
Both (A) and None of
98 (2FAOC)16 is equivalent to (195 084)10 010 0000 B 1
(B) these
1100)2
Page 5
DELD UNIT 1
99 The octal equivalent of hexadecimal (A.B)16 is 47.21 12.74 12.71 17.21 B 1

100 Logic X-OR operation of (4ACO)H & (B53F)H results AACB 0000 FFFF ABCD C 1
101 The simplified form of the Boolean expression (X+Y+XY)(X+Z) is X + Y + ZX + Y XY – YZ X + YZ XZ + Y C 2
The output of a logic gate is 1 when all its inputs are at logic 0. the gate is An AND or A NOR or
102 A NAND or an XOR
An OR or an XNOR D 1
either XOR an XNOR
calculating
1's
adding 1's adding 1 compleme
subtracting
103 2's complement of any binary number can be calculated by complement to 1's nt and B 1
1 from 1's
twice complement inverting
complement.
Most
significant
bit
to
to convert convert
from one to encode to decode from
104 Sum-of-Weights method is used __________ A 1
number data data serial to
system to other parralel
data
105 The complement of a variable is always 1 0 inverse None C 1
106 The difference of 111 - 001 equals 100 111 001 110 D 2
The Unsigned Binary representation can only represent positive binary Both (A) and None of
107 TRUE FALSE A 1
numbers (B) Above
which of the following rules states that if one input of an AND gate is
108 A +1 =1 A +A =A A.A = A A.1= A C 1
always 1, the output is equal to the other input?
109 Which of the number is not a representative of hexadecimal system 1234 ABCD 1001 DEFH D 1
110 Which one of the following is NOT a valid rule of Boolean algebra? A = A' AA = A A+1=1 A+0=A A 1
2^3 (2 2^0 (2 2^1 (2
In the binary number ' 10011 ' the weight of the most significant digit is 2^4(2 raise
111 raise to raise to raise to A 1
____ to power 4)
power 3) power 0) power 1)
112 The binary value ' 1010110 ' is equivalent to decimal __________ 86 87 88 89 A 1
113 2's complement of hexadecimal number B70A is B70B B709 48F6 48F5 C 1
114 2's complement of 5 is 1101 1011 1010 1100 B 1
115 The 4-bit 2's complement representation of ' -7 ' is _____________ 111 1111 1001 110 C 1
Page 6
DELD UNIT 1
If we multiply ' 723 ' and ' 34 ' by representing them in floating point
116 notation i.e. By first, converting them in floating point representation 24.582 2.4582 24582 0.24582 A 2
and then multiplying them, the value of mantissa of result will be ________
The output of the expression F=A+B+C will be Logic ________ when A=0, 10
117 Undefined One Zero B 2
B=1, C=1. the symbol ' + ' here represents OR Gate. (binary)
all inputs are all inputs are any input is any input
118 A NAND gate's output is LOW if C 1
LOW HIGH LOW is HIGH
NOT Gate AND Gate OR Gate
OR Gate and
119 NOR gate is formed by connecting _________ and then OR and then OR and then C 1
then NOT Gate
Gate Gate AND Gate
120 The AND Gate performs a logical __________function Addition Subtraction Multiplication Division C 1
The Extended ASCII Code (American Standard Code for Information
121 2-bit 7-bit 8-bit 16-bit C 1
Interchange) is a _____ code
122 The OR gate performs Boolean ___________. subtraction division addition D 1
multiplication
All the
All of the Any of the Any of the
123 The output of an AND gate is one when _______ inputs are A 1
inputs are one input is one input is zero
zero
all
all inputs are any input any input
124 A NOR's gate output is HIGH if inputs are D 1
HIGH is HIGH is LOW
LOW
two AND three AND two AND two
gates, two OR gates, two gates, one AND
125 A logic circuit with an output X = A(Bar)BC+AB(Bar) consists of ________. C 1
gates, two OR gates, OR gate, two gates, one
inverters one inverter inverters OR gate
126 the boolean expression AB'CD'is a sumterm a product term a literal term always 1 B 1
two ORs two ANDs an
a 4-input
127 The boolean expression X = AB + CD represents ANDed ORed exclusive- C 1
AND gate
together together Or
The expression _________ is an example of Commutative Law for AB+C = A(B+C) =
128 AB=BA A+B=B+A C 2
Multiplication. A+BC B(A+C)
Page 7
DELD UNIT 1
three AND
three AND
To implement the expression AB(bar)CD+ ABC(bar)D+ ABCD (bar), it gates and three AND one
129 gates and A 1
takes one OR gate and four gates AND gate
three inverters
inverters
130 the boolean expression A + B' + C is a sum term a literal a product compleme A 1
F(A,B,C)
F(A,B,C) = F(A,B,C) = =
The minterm expansion for F(A,B,C) = (A + B + C)(A + B' + C')(A' + B + F (A,B,C) =
131 Summation Summation Summatio A 2
C')(A' + B' + C) is Pi M(0,3,5,6)
m(0,3,5,6) m(0,3,5,6) n
m(1,2,4,7)
132 (A+B).(A+C) = ___________ B+C A+BC AB+C AC+B B 1
Product of Sum of
133 A'B +A'BC'+AC is an example of ________ B 1
sum form product form Demorgans Associativ
law e law
A'B + AC' + (A' + B + both (a)
134 An example of SOP expression is A + B(C + D) B 1
AB'C C)(A + B' + C) nad (b)
A = 1, B
Determine the values of A, B, C, and D that make the sum term A(bar) + A = 1, B = 0, A = 1, B = A = 0, B =
135 = 0, C = 1, B 2
B+C(bar)+D equal to zero. C = 0, D = 0 0, C = 1, D = 0 1, C = 0, D = 0
D=1
(A' + B)(A' + (A + B)(A (A + B)(A' none of
136 The bolean expression A + BC equals B 2
C) + C) + C) the above
Demorgan's
137 A.(B + C) = A.B + A.C is the expression of _________________ Commutative Distributive Associativ C 1
Law
Law Law e Law
Demorgan's
138 A.(B.C) = (A.B).C is an expression of __________ Distributive Commutative Associativ D 1
Law
Law Law e Law
139 How many binary bits are necessary to represent 748 different numbers? 7 10 9 8 B 1
140 The correct binary equivalent for DFA16 is: 1111011001012110111101010111010111010

011011011011 B 1
Which of the following Boolean expressions represents the
141 DeMorganized version of (A′ +B + C + D) ′ (A′ +B) (C′ D) (A′ B). (C′ + D)A′ + B′ + C + D C 1
the expression ((A + B′ ) + CD′ ) ′
142 A Nibble consists of _____ bits 2 4 8 16 B 1
143 Excess-8 code assigns _______ to “-8” 1110 1100 1000 0000 D 1
OR, AND, NOT, NOR, NOT, OR,
144 The three fundamental gates are ___________ AND, NAND, XOR D 1
NAND XOR AND
Page 8
DELD UNIT 1
The size of
the
The The The size of
The total amount of memory that is supported by any digital system address
145 organization structure of decoding D 1
depends upon ______ bus of the
of memory memory unit
microproc
essor
146 Addition of two octal numbers “36” and “71” results in ________ 213 123 127 345 C 4
Base 10
147 In which of the following base systems is 123 not a valid number? Base 16 Base8 Base 3 D 1
1000
148 Storage of 1 KB means the following number of bytes 964 1024 1064. D 2
What is the octal equivalent of the binary number:
149 10111101 675 275 572 573. B 1
10101.001
150 The binary code of (21.125)10 is 10100.001 10101.010 10100.111 A 1
all the
minization
any logic many
techniques
function can digital
it is used by are
151 A NAND gate is called a universal logic element because be realized computers B 1
everybody applicable
by NAND use NAND
for optimum
gates alone gates.
NAND gate
realization
useful over
always more
Digital computers are more widely used as compared to analog less expensive wider ranges easier to
152 accurate and C 1
computers, because they are of problem maintain.
faster
types
it is not
possible to
floating point
it is slower perform of no
Most of the digital computers do not have floating point hardware hardware is
153 than floating specific A 1
because costly
software point reason.
addition by
hardware
154 The number 1000 would appear just immediately after FFFF (hex) 1111 7777 (octal) All of the D 1
(binary) above.
Page 9
DELD UNIT 1
155 (1(10101)2 is (37)10 ( 69)10 (41 )10 — (5)10 A 1
The number of Boolean functions that can be generated by n variables is n n n-1 n

156 2 22 2 —2 B 1
equal to
Consider the representation of six-bit numbers by two’s complement,
one’s Sign and Two’s
complement, or by sign and magnitude: In which representation is there Two’s magnitude complement All three
157 overflow from complement and one’s and one’s representa D 2
the addition of the integers 011000 and 011000? only complement complement tions.
only only
logic 0 and 1 logic 0 and, - logic 0

are 1 are logic 0 voltage
represented represented voltage level level is
158 Positive logic in a logic circuit is one in which by 0 and by negative is higher lower D 1
positive and positive than logic 1 than logic
voltage voltages voltage level 1 voltage
respectively respectively level.
OR gate EXCLUSIVE
159 Which of the following gate is a two-level logic gate NAND gate NOT gate. C 1
OR gate
all the
all the inputs inputs and
to the gates all the inputs either of the outputs
160 An AND gate will function as OR if D 1
are “1” are ‘0’ inputs is “1” are
compleme
nted.
161 An OR gate has 6 inputs. The number of input words in its truth table are 6 32 64 128 C 1
Page 10
DELD UNIT 1
have lower consume provide

can be used
fabrication least maximum
162 NAND. gates are preferred over others because these to make any B 1
area electronic density in
gate
power a chip.
1 at any input 1 at any 0 any input 0 at any

163 In case of OR gate, no matter what the number of inputs, a A 1
causes the input causes causes the input
164 Excess-3 code is known as Weighted code Cyclic Self- Algebraic C 1
Indicate which of the following three binary additions are correct?
1.1011 + 1010 = 10101
165 II. 1010 + 1101 = 10111 I and II II and III III only II and I D 3
III. 1010 + 1101 = 11111
X=X–Y+1
166 X – = Y + 1 means X = –X – Y – 1 X = –X + Y + 1 X= X – Y – 1 A 1
167 A binary digit is called a Bit Byte Number Character A 1
22.0
168 What is decimal equivalent of BCD 11011.1100 ? 22.2 20.2 21.2 B 1
The ASCII code for letter A is 1100011
169 1111111 1000001 0010011 C 1
1100
170 The Gray code for decimal number 6 is equivalent to 1001 0101 0110 C 1
The decimal equivalent of hex number 1A53 is 6793
171 6739 6973 6379 B 1
Page 11
DELD UNIT 3

UNIT - III
Sr. Correct
No. Option
In the following question, match each of the items A, B and C on the left
with an approximation item on the right
A. Shift register can be used 1. for code conversion A B C
A B C A B C
B. A multiplexer can be used 2. to generate memory slipto select A B C
1 C. A decoder can be used 3. for parallel to serial conversion 5 4 2 B 4
3 4 1 1 3 5
4. as many to one switch 1 2 3
5. for analog to digital conversion
A standard SOP form has __________ terms that have all the variables in the
2 SUM SUB Mult DIV A 1
domain of the expression.
3 How many data select lines are required for selecting eight inputs? 1 2 3 4 C 2
A circuit to
Half of an Half of a none of
4 Half adder circuit is ______? add two bits B 2
AND gate NAND gate above
together
sum of all carry from (
The full adder adds the Kth bits of two numbers to the difference of sum of
previous bits K - 1 )TH bit
5 the previous previous C 2
bits bit
The number of two input multiplexers required to construct a 210 input

multiplexer is,
6 31 10 127 1023 D 2
A small dot or circle printed on top of an IC indicates

Pin 14
7 Vcc Gnd Pin 1 D 1
Page 1
DELD UNIT 3
Which of the following adders can add three or more numbers at a time ? Carry-save-
Carry-look- adder
8 Parallel adder Full adder B 2
ahead adder
D.
gives an
output when
all input
signals are
is a memory is a -ve OR is a linear
9 An AND circuit present B 2
circuit gate circuit
simultaneous
ly
HIGH, LOW, both of the neither of

10 What are the three output conditions of a three-state buffer? 1, 0, float C 2
float above the above
when two
or more
when two or
when all when all outputs
more outputs
outputs are outputs are are
11 When is it important to use a three-state buffer? are connected A 2
normally normally connected
to the same
HIGH LOW to two or
input
more
inputs
MULTIPLEXE DEMULTIPLE
12 The device which changes from serial data to parallel data is COUNTER FLIP-FLOP C 2
R XER
DEMULTIPL
13 A device which converts BCD to Seven Segment is called MULTIPLEXER ENCODER DECODER D 2
EXER
14 How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? 1 2 4 8 C 2
Demultiple
15 A device which converts BCD to Seven Segment is called Encoder Decoder Multiplexer B 2
xer
accepts one accepts accepts accepts
input and many inputs many inputs one input
16 A multiplexer is a logic circuit that C 2
gives several and gives and gives and gives
output many output one output one output
Page 2
DELD UNIT 3
2n-1
17 In order to implement a n variable switching function, a MUX must have 2n inputs 2n+1 inputs 2n-1 inputs A 2
inputs
Design
18 Logic gates with a set of input and outputs is arrangement of Combinational Logic circuit Register A 2
circuits
circuit
AND and OR NAND and NAND
19 A latch is constructed using two cross-coupled AND gates D 2
gates NOR gates gates
A combinational logic circuit which sends data coming from a single Demultiple
20 Decoder Encoder Multiplexer D 2
source to two or more separate destinations is xer
Combination A/D
21 Data can be changed from special code to temporal code by using Shift registers Counters A 2
al circuits converters
Demultiple
22 A device which converts BCD to Seven Segment is called Encoder Decoder Multiplexer
xer
23 The gray code equivalent of (1011)2 is 1101 1010 1110 1111 B 2
Odd parity of word can beconveniently tested by
XOR gate
24 OR gate AND gate NOR gate D 2
Which one of the following will give the sum of full adders as output ?
Three bit
Three point Three bit Three bit
25 parity D 2
majority circuit comparator counter
checker
The number of full and half-adders required to add 16-bit numbers is
4 half-
8 half-adders, 1 half-adder, 16 half-
26 adders, 12 B 2
8 full-adders 15 full- adders, 0 full-
full-adders
adders adders
A one-to-four line demultiplexer is to be implemented using a memory.

How many bits must each word have ?
1 bit 8 bits
27 2 bits 4 bits A 2
Page 3
DELD UNIT 3
What logic function is produced by adding an inverter to the output of an

AND gate ?
28 NAND NOR XOR OR A 1
Route the data Select data

from single from several Perform
input to one of inputs and serial to
All of
29 A demultiplexer is used to many outputs route it to parallel A 1
these
single output conversion
How many full adders are required to construct an m-bit parallel adder ?
m/2
30 m-1 m m+1 B 1
both (a)
combinational sequential None of
31 Parallel adders are and (b) B 1
logic circuits logic circuits these
The digital multiplexer is basically a combination logic circuit to perform
the operation
32 AND-AND OR-OR AND-OR OR-AND C 2
How many lines the truth table for a four-input NOR gate would contain
to cover all possible input combinations ?
33 4 8 12 16 D 2
How many truth tables can be made from one function table ?
34 1 2 3 ANY NO B 2
Page 4
DELD UNIT 3
operates at
the same
speed as
A comparison between serial and parallel adder reveals that serial order is more
parallel
35 is slower is faster complicate A 2
adder
d
What is the largest number of data inputs which a data selector with
two control inputs can have ?
36 2 4 6 8 B 1
If a logic gates has four inputs, then total number of possible input
combinations is
37 4 8 16 32 C 1
nput
combination
input
at that time present
If a logic gates has four inputs, then total number of possible input input combination
and the output
combinations is combination at and the
38 previous and the A 2
the time previous
input previous
output
combination output
A combinational logic circuit which generates a particular binary word

Decoder
or number is Multiplexer Demultiple
39 Encoder A 1
xer
Which of the following circuit can be used as parallel to serial converter ?

Digital
Demultiplexe Decoder
40 Multiplexer counter A 2
r
Page 5
DELD UNIT 3
Carry-
In which of the following adder circuits, the carry look ripple delay is
look-
eliminated ? Half adder Full adder Parallel
41 ahead C 2
adder
adder
is called so
because a
full adder needs two
All of
involves two input and
42 Adders adds 2 bits these D 2
half-adders generates
two output
Cyclic Self-
Algebraic
Weighted code redundancy complementi
43 Excess-3 code is known as code. C 1
code ng code
44 The number of control lines for 32 to 1 multiplexer is 4 16 5 6 C 2
45 The selector inputs to an arithmetic-logic unit (ALU) determine the: selection of arithmetic data word clock B 2
46 What are the two types of basic adder circuits? the IC and
half adder or logic
half adder selection
asynchronou frequency
one's A 2
The inverter OR-gate and AND gate are called deeision-making elements full adder and parallel s and compleme
bytes,high character,l
47 words,high bytes,low A 2
because they can recognize some input while disregarding others. A gate ow
Which one of the following set of gates are best suited for 'parity'
checking and 'parity' generation. EX-NOR or NOR
AND, OR, NOT
48 EX-OR gates NAND gates gates B 2
gates
HIGH, LOW, both of the neither of

49 What are the three output conditions of a three-state buffer? 1, 0, float C 2
float above the above
Page 6
DELD UNIT 3
when two
or more
when two or
when all when all outputs
more outputs
outputs are outputs are are
50 When is it important to use a three-state buffer? are connected A 2
normally normally connected
to the same
HIGH LOW to two or
input
more
inputs
51 How many inputs are required for a 1-of-10 BCD decoder? 4 8 10 1 A 1
single input, odd parity
decimal to
52 Most demultiplexers facilitate which of the following? multiple ac to dc to even B 1
hexadecimal
outputs parity
parallel-to-
code parity data
53 One application of a digital multiplexer is to facilitate: serial data C 1
conversion checking generation
conversion
best suited
for detecting
double-bit
best suited for
errors that
detecting
occur during NONE OF
Select one of the following statements that best describes the parity single-bit
54 the A AND B THE A 2
method of error detection: errors in
transmission ABOVE
transmitted
of codes
codes.
from one
location to
another.
accepts
data
accepts data
accepts data inputs
uses one inputs from
inputs from from
display to multiple
one line and several
present two lines and
55 A multiplexed display: passes this lines and B 1
or more passes this
data to multiplexe
pieces of data to
multiple s this
information multiple
output lines input data
output lines
to four
BCD lines
Page 7
DELD UNIT 3
In which of the following gates, the output is 1, if and only if at least one
56 NOR AND OR NAND C 1
input is 1?
Propagation Charging
57 The time required for a gate or inverter to change its state is called Rise time Decay time C 1
time time
The time required for a pulse to change from 10 to 90 percent of its Propagation Operating
58 Rise time Decay time A 1
maximum value is called time speed
Binary level
The maximum frequency at which digital data can be applied to gate is Operating Propagation Charging
59 transaction A 1
called speed speed time
period
What is the minimum number of two-input NAND gates used to perform
60 one two three Four C 2
the function of two input OR gate ?
Odd parity of word can beconveniently tested by XOR gate
61 OR gate AND gate NOR gate D 1
Three bit
Which one of the following will give the sum of full adders as output ? Three point Three bit Three bit
62 parity D 1
majority circuit comparator counter
checker
1 half-adder, 16 half- 4 half-
The number of full and half-adders required to add 16-bit numbers is 8 half-adders,
63 15 full- adders, 0 full- adders, 12 B 1
8 full-adders
adders adders full-adders
The time required for a pulse to decrease from 90 to 10 per cent of its Binary level
Propagatio
64 maximum value is called Rise time Decay time transition B 1
n delay
period
Which of the following gates would output 1 when one input is 1 and
65 other input is 0 ? OR gate AND gate NAND gate AND gate D 1
Noise
Operating
immunity is
speed is
the amount
the
Propagation of noise Fan-in of a
maximum
delay is the which can be gate is
frequency
Which of the following statements is wrong ? time required applied to always equal
66 at which C 1
for a gate to the input of to fan-out of
digital
change its state a gate the same gate
data can
without
be applied
causing the
to a gate
gate to
change state
Page 8
DELD UNIT 3
67 Which of the following expressions is not equivalent to X ' ? X NAND X X NOR X X NAND 1 X NOR 1 D 1
Which of the following gates are added to the inputs of the OR gate to
68 convert it to the NAND gate ? NOT AND OR XOR A 1
The EXCLUSIVE NOR gate is equivalent to which gate followed by an

69 OR gate AND NAND XOR D 1
inverter ?
A one-to-four line demultiplexer is to be implemented using a memory.
70 1 BIT 2 BITS 4 BITS 8 BITS A 1
How many bits must each word have ?
71 AND gate ? NAND NOR XOR OR A 1
NAND
72 Which of the following gates is known as coincidence detector ? AND GATE OR GATE NOT GATE A 1
GATE
73 possible combination of logical states in the inputs ? Function table Truth table Routing table ASCII table B 1
74 A positive AND gate is also a negative NAND gate NOR gate AND GATE OR GATE D 1
Select data
Route the data Perform
from several
from single serial to
75 A demultiplexer is used to inputs and All of these A 1
input to one of parallel
route it to
many outputs conversion
single output
MOS
Switches Switches
transistors None of
76 An OR gate can be imagined as connected in connected in B 1
connected in these
series parallel
series
Which combination of gates does not allow the implementation of an OR gates and OR gates and
OR gates and NAND
77 arbitrary boolean function? exclusive OR NOT gates A 1
AND gates only gates only
gate only only
78 m/2 m-1 m m+1 B 2
combinational sequential both (a) and None of

79 Parallel adders are A 1
logic circuits logic circuits (b) these
Page 9
DELD UNIT 3
The digital multiplexer is basically a combination logic circuit to perform

80 AND-AND OR-OR AND-OR OR-AND C 1
the operation
High if
Low if all of High if all of
High if all of its only of its
81 The output of NOR gate is its inputs its inputs are C 1
inputs are high inputs is
are low low
low
How many lines the truth table for a four-input NOR gate would contain
82 4 8 12 16 D 1
to cover all possible input combinations ?
A toggle operation cannot be performed using a single
83 NOR gate AND gate NAND gate XOR gate B 1
Which table shows the electrical state of a digital circuit's output for
84 every possible combination of electrical states in the inputs ? Function table Truth table Routing table ASCII table A 1
What is the minimum number of 2 input NAND gates required to

implement the function
85 6 5 4 3 C 1
F = (x'+y') (z+w)
How many truth tables can be made from one function table ? Any
86 One Two Three B 1
numbers
operates at
the same is more
A comparison between serial and parallel adder reveals that serial order
87 is slower is faster speed as complicate A 1
parallel d
adder
What is the largest number of data inputs which a data selector with two
88 2 4 8 16 B 1
control inputs can have ?
89 combinations is 4 8 16 32 C 1
input
input combination present
input combination at that time output
A combinational circuit is one in which the output depends on the
90 combination at and the and the and the A 1
the time previous previous previous
output input output
combination
Page 10
DELD UNIT 3
to select 1
out of N to
input data to transit perform
to decode
91 The function of a multiplexer is sources and data on N serial to B 1
information
to transmit lines parallel
it to single conversion
channel
A combinational logic circuit which generates a particular binary word Demultiple
92 Decoder Multiplexer Encoder A 1
or number is xer
Demultiplexe Digital
93 Which of the following circuit can be used as parallel to serial converter ? Multiplexer Decoder A 1
r counter
Carry-
In which of the following adder circuits, the carry look ripple delay is Parallel look-
94 Half adder Full adder C 1
eliminated ? adder ahead
adder
Is called so
needs two
Adders because a
input and
95 adds 2 bits full adder All of these A 1
generates
involves two
two output
half-adders
96 How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? 1 2 4 8 C 1

Cannot be
For the device shown here, let all D inputs be LOW, both S inputs be
97 LOW HIGH Don't Care determine A 1
HIGH, and the input be LOW. What is the status of the Y output?
d
98 Convert BCD 0001 0010 0110 to binary. 1111110 1111000 1111101 1111111 A 2
99 Convert BCD 0001 0111 to binary. 10101 10001 10010 11000 C 2
100 How many data select lines are required for selecting eight inputs? 1 2 3 4 C 1
How many 1-of-16 decoders are required for decoding a 7-bit binary
101 5 6 7 8 D 1
number?
The implementation of simplified sum-of-products expressions may be
easily implemented into actual logic circuits using all universal ________
102 AND/OR NAND NOR OR/AND B 1
gates with little or no increase in circuit complexity. (Select the response
for the blank space that will BEST make the statement true.)
Page 11
DELD UNIT 3
Actual Boolean
Karnaugh circuit trial algebra
Boolean
mapping and error and actual
Which of the following statements accurately represents the two BEST algebra and
103 and circuit evaluation circuit A 1
methods of logic circuit simplification? Karnaugh
waveform and trial and
mapping
analysis waveform error
analysis evaluation
Overlappin
Corners in
Which of the following combinations cannot be combined into K-map Corners in the Diagonal g
104 the same C 2
groups? same row corners combinati
column
ons
A defective IC A solar A
As a technician you are confronted with a TTL circuit board containing chip that is bridge defective
An open
dozens of IC chips. You have taken several readings at numerous IC drawing between the output IC
input on the
105 chips, but the readings are inconclusive because of their erratic nature. excessive inputs on chip that C 2
first IC chip
Of the possible faults listed, select the one that most probably is causing current from the first IC has an
on the board
the problem. the power chip on the internal
supply board open to V cc
106 Which gate is best used as a basic comparator? NOR OR Exclusive-OR AND C 1
demultiplexe parity
107 The device shown here is most likely a ________. comparator multiplexer C 2
r generator
For the device shown here, assume the D input is LOW, both S inputs are All but are All but are
108 All are HIGH. All are LOW. A 1
HIGH, and the input is HIGH. What is the status of the outputs? LOW. HIGH.
preprogra
analog a set of bit mmed
109 In VHDL, macrofunctions is/are: digital circuits. D 1
circuits. vectors. TTL
devices.
110 Which of the following expressions is in the product-of-sums form? (A + B )(C + D ) (AB )(CD ) AB (CD ) AB + CD A 2
Page 12
DELD UNIT 3
The
No signal maximum
All logic
The delay must pass number of
circuits are
times are through gates that
reduced to
Which of the following is an important feature of the sum-of-products greatly more than any signal
111 nothing more A 1
form of expressions? reduced two gates, must pass
than simple
over other not through is
AND and OR
forms. including reduced
operations.
inverters. by a factor
of two.
An output gate is connected to four input gates; the circuit does not
function. Preliminary tests with the DMM indicate that the power is
applied; scope tests show that the primary input gate has a pulsing Logic
112 Current tracer Logic probe Oscilloscope A 1
signal, while the interconnecting node has no signal. The four load gates analyzer
are all on different ICs. Which instrument will best help isolate the
problem?
A > B = 0, A < A > B = 1, A < A > B = 0,
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a A > B = 1, A < B
113 B = 1, A = B = B = 0, A = B = A < B = 1, C 4
comparator. What are the output levels? = 0, A < B = 1
0 0 A=B=1
The dim
indication
The dim
on the logic
indication is
The output of probe The gate
A logic probe is placed on the output of a gate and the display indicator a result of a
the gate indicates may be a
114 is dim. A pulser is used on each of the input terminals, but the output bad ground A 1
appears to be that the tristate
indication does not change. What is wrong? connection
open. supply device.
on the logic
voltage is
probe.
probably
low.
Page 13
DELD UNIT 3
a DON'T
a HIGH CARE
a HIGH for
output on a LOW condition
each input
the truth output for all for all
truth table
115 Each "1" entry in a K-map square represents: table for all possible possible A 1
condition that
LOW input HIGH input input
produces a
combination conditions. truth table
HIGH output.
s. combinati
ons.
variables variables
variables within the within the
within the variables loop that loop that
loop that that remain appear in appear
116 Looping on a K-map always results in the elimination of: appear only in unchanged both only in C 2
their within the complemente their
complemented loop. d and uncomple
form. uncompleme mented
nted form. form.
Give the
Program a design to a
What will a design engineer do after he/she is satisfied that the design Put it in a flow Perform a
117 chip and test technician to B 2
will work? chart vector test
it verify the
design
There is a
signal loss
to all gates
on the
Only the There is a The affected
node, and
output of the signal loss to node will be
118 What is the indication of a short on the input of a load gate? the D 1
defective gate all gates on stuck in the
affected
is affected. the node. LOW state.
node will
be stuck
in the
LOW state.
Page 14
DELD UNIT 3
a
binary coded
119 In HDL, LITERALS is/are: digital systems. scalars. numbering B 1
decimals.
system.
120 Which of the following expressions is in the sum-of-products form? (A + B )(C + D ) (AB )(CD ) AB (CD ) AB + CD D 1
121 The carry propagation can be expressed as ________. Cp = AB Cp = A + B B 1

using the
input lines
for data
tying all tying all tying all data-
selection
122 A decoder can be used as a demultiplexer by ________. enable pins data-select select lines D 1
and an
LOW lines LOW HIGH
enable
line for
data input
How many 4-bit parallel adders would be required to add two binary
123 1 2 3 4 C 1
numbers each representing decimal numbers up through 30010?
Karnaugh
The maps
Variable
Karnaugh provide a
A Karnaugh complements
map visual
map can be can be
eliminates approach
124 Which statement below best describes a Karnaugh map? used to eliminated D 1
the need for to
replace by using
using NAND simplifyin
Boolean rules. Karnaugh
and NOR g Boolean
maps.
gates. expression
s.
None. All
A certain BCD-to-decimal decoder has active-HIGH inputs and active-
125 0 3 9 outputs C 1
LOW outputs. Which output goes LOW when the inputs are 1001?
are HIGH.
A full-adder has a Cin = 0. What are the sum and the carry (Cout) when A = 0, Cout = = 1, Cout = 1,
126 = 0, Cout = 0 B 1
= 1 and B = 1? 1 =0 C out = 1
127 When adding an even parity bit to the code 110010, the result is ________. 1110010 110010 1111001 1101 A 1
One 4-
One 4-input One 4-input
Which of the following combinations of logic gates can decode binary One 4-input input AND
128 AND gate, NAND gate, D 1
1101? AND gate gate, one
one OR gate one inverter
inverter
Page 15
DELD UNIT 3
The
The node affected
Only the
There is a may be stuck node will
What is the indication of a short to ground in the output of a driving output of the
129 signal loss to in either the be stuck B 1
gate? defective gate
all load gates. HIGH or the in the
is affected.
LOW state. HIGH
state.
How many outputs would two 8-line-to-3-line encoders, expanded to a
130 3 4 5 6 B 1
16-line-to-4-line encoder, have?
all of the
131 A half-adder does not have ________. carry in carry out two inputs A 1
above
data = 0001 data =
data = 1101 data = 1101
________ is a correct combination for an ODD-parity data transmission 0101 1010 1111
132 1011 0010 A 1
system. parity
parity = 1 parity = 0
=1 parity = 0
A circuit that can convert one of ten numerical keys pressed on a priority demultiple
133 decoder multiplexer A 1
keyboard to BCD is a ________. encoder xer
The ________ prefix on IC's indicates a broader operating temperature
134 54 2N 74 TTL A 1
range, and the devices are generally used by the military.
go HIGH, still be
go LOW,
react as if since full good, if
because there
the open voltage only the
135 When an open occurs on the input of a TTL device, the output will ________. is no current B 1
input were a appears good
in an open
HIGH across an inputs are
circuit
open used
The largest truth table that can be implemented directly with an 8-line-
136 3 rows 4 rows 8 rows 16 rows C 1
to-1-line MUX has ________.
when a
which of two errors in errors in binary
137 Parity generation and checking is used to detect ________. numbers is binary data arithmetic in counter B 1
greater transmission computers counts
incorrectly
138 Except for ________, STD_LOGIC may have the following values. 'z' 'U' '?' 'L' C 1
A gate that could be used to compare two logic levels and provide a HIGH
139 XOR gate XNOR gate NAND gate NOR gate B 1
output if they are equal is a(n) ________.
Page 16
DELD UNIT 3
VHDL is very strict in the way it allows us to assign and compare ________ LOGIC_VECT
140 objects designs arrays A 1
such as signals, variables, constants, and literals. ORS
The AND-OR-INVERT gates are designed to simplify implementation of DeMorgan's
141 POS logic NAND logic SOP logic B 1
________. theorem
show
be able to
whether the probably not
identify
identify the gate is be able to
142 The output of a gate has an internal short; a current tracer will ________. the A 1
defective gate shorted to locate the
defective
V cc or problem
load node
ground
exclusive- exclusive-
143 Parity generators and checkers use ________ gates. exclusive-AND exclusive-OR B 1
OR/NOR NAND
test the
display to
turn off the turn off the
turn off the assure all
The 7447A is a BCD-to-7-segment decoder with ripple blanking input display for any display for
144 display for segments A 1
and output functions. The purpose of these lines is to ________. nonsignificant leading or
any zero are
digit trailing zeros
operationa
l
One reason for using the sum-of-products form is that it can be
145 NOR NAND AND DOOR B 1
implemented using all ________ gates without much difficulty.
go HIGH,
go LOW, be
react as if since full
because there unpredicta
the open voltage
146 When an open occurs on the input of a CMOS gate, the output will ________. is no current ble; it may D 2
input were a appears
in an open go HIGH
HIGH across an
circuit or LOW
open
To subtract a signed number (the subtrahend) from another signed complemented complemente always never
147 number (the minuend) in the 2's complement system, the minuend is only if it is d only if it is complemente compleme D 2
________. positive negative d nted
In an odd-parity system, the data that will produce a parity bit = 1 is data = data = data = All of the
148 D 2
________. 1010011 1111000 1100000 above
have
The addition of two signed numbers in the 2's complement system can have the
149 be positive be negative opposite C 2
cause overflow. For overflow to occur both numbers must ________. same sign
signs
Page 17
DELD UNIT 3
give an
overall
allow any
eliminate the produce the picture of
circuit to be
need for simplest how the
implemented
150 A Karnaugh map will ________. tedious sum-of- signals A 2
with just
Boolean products flow
AND and OR
simplifications expression through
gates
the logic
circuit
the
the number
number of
An 8-bit binary number is input to an odd parity generator. The parity the number is of 1s in the the number
151 1s in the D 2
bit will equal 1 only if ________. odd number is is even
number is
odd
even
to the
cascading
to the outputs A = B to a
Two 4-bit comparators are cascaded to form an 8-bit comparator. The inputs of the
from the least logic high, A
152 cascading inputs of the most significant 4 bits should be connected least ground A 1
significant 4- < b and a > B
________. significant 4-
bit comparator to a logic low
bit
comparator
When Karnaugh mapping, we must be sure to use the ________ number of
153 maximum minimum median Karnaugh B 1
loops.
154 The final output of a POS circuit is generated by ________. an AND an OR a NOR a NAND A 2
After each circuit in a subsection of a VHDL program has been ________,
155 designed tested engineered produced B 1
they can be combined and the subsection can be tested.
The ________ series of IC's are pin, function, and voltage-level compatible
156 ALS CMOS HCT 2N C 2
with the 74 series IC's.
The ________ circuit produces a HIGH output whenever the two inputs are exclusive- exclusive- exclusive-
157 exclusive-AND C 2
equal. NAND NOR OR
A 4-bit adder has the following inputs: C0 = 0, A1 = 0, A2 = 1, A3 = 0, A4 = 1,
158 1100 10101 11000 11 C 2
B1 = 0, B2 = 1, B3 = 1, B4 = 1. The output will be ________.
IF/THEN/EL
159 The ________ statement evaluates the variable status. IF/THEN CASE ELSIF A 2
SE
STD_VECT
160 In VHDL, data can be each of the following types except ________. BIT BIT_VECTOR STD_LOGIC D 2
OR
When grouping cells within a K-map, the cells must be combined in
161 2's 1, 2, 4, 8, etc. 4's 3's B 1
groups of ________.
Page 18
DELD UNIT 3
The ________ circuit produces a HIGH output whenever the two inputs are exclusive- inexclusive
162 exclusive-AND exclusive-OR C 1
unequal. NOR -OR
Occasionally, a particular logic expression will be of no consequence in
spurious, spurious,
the operation of a circuit, such as in a BCD-to-decimal converter. These don't care, 1's, duplicate,
163 AND's, OR's, 1's, 0's, A 2
result in ________ terms in the K-map and can be treated as either ________ 0's, simplify 1's, 0's, verify
eliminate simplify
or ________, in order to ________ the resulting term.
A good rule of thumb for determining the pin numbers of dual-in-line
None of the Can not
164 package IC chips would be to place the notch to your right and pin #1 TRUE FALSE B 2
above predict
will always be in the lower right corner.
The carry output of each adder in a ripple adder provides an additional None of the Can not
165 TRUE FALSE A 1
sum output bit. above predict
Truth tables are great for listing all possible combinations of None of the Can not
166 TRUE FALSE A 1
independent variables. above predict
A square in the top row of a K-map is considered to be adjacent to its None of the Can not
167 TRUE FALSE A 1
corresponding square in the bottom row. above predict
To implement the full-adder sum functions, two exclusive-OR gates can None of the Can not
168 TRUE FALSE A 1
be used. above predict
The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder with active- None of the Can not
169 TRUE FALSE B 2
low outputs is 1110. As a result, output line 7 is driven LOW. above predict
When decisions demand two possible actions, the IF/THEN/ELSE None of the Can not
170 TRUE FALSE A 2
control structure is used. above predict
None of the Can not
171 TTL stands for transistor-technology-logic. TRUE FALSE B 1
above predict
The 54 prefix on ICs indicates a broader operating temperature range, None of the Can not
172 TRUE FALSE A 2
generally intended for military use. above predict
None of the Can not
173 This is an example of a POS expression: TRUE FALSE A 2
above predict
None of the Can not
174 The abbreviation for an exclusive-OR gate is XOR. TRUE FALSE A 2
above predict
In an even-parity system, the parity bit is adjusted to make an even None of the Can not
175 TRUE FALSE A 2
number of one bits. above predict
In an even-parity system, the following data will produce a parity bit = 1. None of the Can not
176 TRUE FALSE B 2
data = 1010011 above predict
The following combination is correct for an ODD parity data None of the Can not
177 TRUE FALSE A 1
transmission system: data = 011011100 and parity = 0 above predict
The XOR gate will produce a HIGH output if only one but not both of the None of the Can not
178 TRUE FALSE A 1
inputs is HIGH. above predict
Page 19
DELD UNIT 3
When decisions demand one of many possible actions, the ELSIF control None of the Can not
179 TRUE FALSE A 1
structure is used. above predict
The K-map provides a "graphical" approach to simplifying sum-of- None of the Can not
180 TRUE FALSE A 1
products expressions. above predict
Even parity is the condition of having an even number of 1s in every None of the Can not
181 TRUE FALSE A 1
group of bits. above predict
None of the Can not
182 The look-ahead carry method suffers from propagation delays. TRUE FALSE B 1
above predict
A pull-up resistor is a resistor used to keep a given point in a circuit None of the Can not
183 TRUE FALSE A 1
HIGH when in the active state. above predict
None of the Can not
184 A data selector is also called a demultiplexer. TRUE FALSE B 1
above predict
A digital circuit that converts coded information into a familiar or non- None of the Can not
185 TRUE FALSE B 1
coded form is known as an encoder. above predict
An exclusive-OR gate will invert a signal on one input if the other is None of the Can not
186 TRUE FALSE A 1
always HIGH. above predict
The following combination is correct for an EVEN parity data None of the Can not
187 TRUE FALSE B 2
transmission system: data = 100111100 and parity = 0 above predict
The CASE control structure is used when an expression has a list of None of the Can not
188 TRUE FALSE A 2
possible values. above predict
An encoder in which the highest and lowest value input digits are None of the Can not
189 TRUE FALSE B 2
encoded simultaneously is known as a priority encoder. above predict
None of the Can not
190 Three select lines are required to address four data input lines. TRUE FALSE B 2
above predict
Single looping in groups of three is a common K-map simplification None of the Can not
191 TRUE FALSE B 2
technique. above predict
In true sum-of-products expressions, the inversion signs cannot cover None of the Can not
192 TRUE FALSE A 2
more than single variables in a term. above predict
A combinatorial logic circuit has memory characteristics that None of the Can not
193 TRUE FALSE B 2
"remember" the inputs after they have been removed. above predict
Page 20
((MARKS)) (1/2/3...) 1
((QUESTION)) There are ______ cells in a 4-variable K-map.
((OPTION_A)) 12
((OPTION_B)) 16
((OPTION_C)) 18
((OPTION_D)) 8
((CORRECT_CHOICE)) B
(A/B/C/D)
((EXPLANATION)) There are 16 = (24) cells in a 4-variable K-map.

(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Product-of-Sums expressions can be implemented using

___________
((OPTION_A)) 2-level OR-AND logic circuits
((OPTION_B)) 2-level NOR logic circuits
((OPTION_C)) 2-level XOR logic circuits
((OPTION_D)) Both 2-level OR-AND and NOR logic circuits
((CORRECT_CHOICE)) D
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) In case of XOR/XNOR simplification we have to look for the

following _______________
Diagonal Adjacencies
((OPTION_A))
Offset Adjacencies
((OPTION_B))
Straight Adjacencies
((OPTION_C))
Both diagonal and offset adjacencies
((OPTION_D))
(A/B/C/D)
((EXPLANATION)) In case of XOR/XNOR simplification we have to look for the

(OPTIONAL) following diagonal and offset adjacencies. XOR gives output 1
when odd number of 1s are present in input while XNOR gives
output 1 when even number of 1s or all 0s are present in input.
((MARKS)) (1/2/3...) 1
((QUESTION)) Which of the examples below expresses the commutative law of

multiplication?
((OPTION_A)) A+B=B+A
((OPTION_B)) A•B=B+A
((OPTION_C)) A • (B • C) = (A • B) • C
((OPTION_D)) A•B=B•A
(A/B/C/D)
((EXPLANATION)) The commutative law of multiplication is (A * B) = (B * A).

(OPTIONAL) The commutative law of addition is (A + B) = (B + A).
((MARKS)) (1/2/3...) 1
((QUESTION)) Each “1” entry in a K-map square represents
((OPTION_A)) A HIGH for each input truth table condition that produces a HIGH
output
((OPTION_B)) A HIGH output on the truth table for all LOW input combinations
((OPTION_C)) A LOW output for all possible HIGH input conditions
((OPTION_D)) A DON’T CARE condition for all possible input truth table
combinations
((CORRECT_CHOICE)) A
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Looping on a K-map always results in the elimination of

__________
((OPTION_A)) Variables within the loop that appear only in their complemented
form
((OPTION_B)) Variables that remain unchanged within the loop
((OPTION_C)) Variables within the loop that appear in both complemented and
uncomplemented form
((OPTION_D)) Variables within the loop that appear only in their

uncomplemented form
((CORRECT_CHOICE)) C
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Odd parity of word can be conveniently tested by ___________
((OPTION_A)) OR gate
((OPTION_B)) AND gate
((OPTION_C)) NAND gate
((OPTION_D)) XOR gate
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Binary coded decimal is a combination of __________
((OPTION_A)) Two binary digits

((OPTION_B)) Three binary digits
((OPTION_C)) Four binary digits
((OPTION_D)) Five binary digits
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) A three digit decimal number requires ________ for

representation in the conventional BCD format.
((OPTION_A)) 3 bits
((OPTION_B)) 6 bits
((OPTION_C)) 12 bits
((OPTION_D)) 24 bits
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
(MARKS)) (1/2/3...) 1
((QUESTION)) The excess-3 code for 597 is given by __________
((OPTION_A)) 100011001010
((OPTION_B)) 100010100111
((OPTION_C)) 010110010111
((OPTION_D)) 010110101101
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) The decimal equivalent of the excess-3 number

110010100011.01110101 is
((OPTION_A)) 970.42
((OPTION_B)) 1253.75
((OPTION_C)) 861.75
((OPTION_D)) 1132.87
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) What is a multiplexer?
((OPTION_A)) It is a type of decoder which decodes several inputs and gives one
output
((OPTION_B)) A multiplexer is a device which converts many signals into one
((OPTION_C)) It takes one input and results into many output
((OPTION_D)) It is a type of encoder which decodes several inputs and gives one
output
(A/B/C/D)
((EXPLANATION)) A multiplexer (or MUX) is a device that selects one of several

(OPTIONAL) analog or digital input signals and forwards the selected input into
a single line, depending on the active select lines.
((MARKS)) (1/2/3...) 1
((QUESTION)) Which combinational circuit is renowned for selecting a single
input from multiple inputs & directing the binary information to
output line?
((OPTION_A)) Data Selector
((OPTION_B)) Data distributor
((OPTION_C)) Both data selector and data distributor
((OPTION_D)) DeMultiplexer
(A/B/C/D)
((EXPLANATION)) Data Selector is another name of Multiplexer. A multiplexer (or

(OPTIONAL) MUX) is a device that selects one of several analog or digital
input signals and forwards the selected input into a single line,
depending on the active select lines.
((MARKS)) (1/2/3...) 1
((QUESTION)) What is the function of an enable input on a multiplexer chip?
((OPTION_A)) To apply Vcc
((OPTION_B)) To connect ground
((OPTION_C)) To active the entire chip
((OPTION_D)) To active one half of the chip
(A/B/C/D)
((EXPLANATION)) Enable input is used to active the chip, when enable is high the
(OPTIONAL) chip works (ACTIVE), when enable is low the chip does not work
(MEMORY). However, Enable can be Active-High or Active-
Low, indicating it is active either when it is connected to VCC or
GND respectively.
((MARKS)) (1/2/3...) 1
((QUESTION)) In a multiplexer, the selection of a particular input line is

controlled by ___________
((OPTION_A)) Data controller
((OPTION_B)) Selected lines
((OPTION_C)) Logic gates
((OPTION_D)) Both data controller and selected lines
(A/B/C/D)
((EXPLANATION)) Enable input is used to active the chip, when enable is high the
(OPTIONAL) chip works (ACTIVE), when enable is low the chip does not work
(MEMORY). However, Enable can be Active-High or Active-
Low, indicating it is active either when it is connected to VCC or
GND respectively.
((MARKS)) (1/2/3...) 1
((QUESTION)) The enable input is also known as ___________
((OPTION_A)) Select input
((OPTION_B)) Decoded input
((OPTION_C)) Strobe
((OPTION_D)) Sink
(A/B/C/D)
((EXPLANATION)) Explanation: The enable input is also known as strobe which is

(OPTIONAL) used to cascade two or more multiplexer ICs to construct a
multiplexer with a larger number of inputs. Enable input activates
the multiplexer to operate.
((MARKS)) (1/2/3...) 1
((QUESTION)) A combinational circuit is one in which the output depends on the

____________
((OPTION_A)) Input combination at the time
((OPTION_B)) Input combination and the previous output

((OPTION_C)) Input combination at that time and the previous input combination
((OPTION_D)) Present output and the previous output
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) What is data routing in a multiplexer?
((OPTION_A)) It spreads the information to the control unit
((OPTION_B)) It can be used to route data from one of several source to

destination
((OPTION_C)) It is an application of multiplexer
((OPTION_D)) Both it can be used to route data and it is an application of

multiplexer
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) How many outputs are present in a BCD decoder?
((OPTION_A)) 4
((OPTION_B)) 8
((OPTION_C)) 10
((OPTION_D)) 16
(A/B/C/D)
((EXPLANATION)) BCD to Decimal decoder has 10 number of outputs because the

(OPTIONAL) decimal digit’s range is from 0 to 9.
((MARKS)) (1/2/3...) 1
((QUESTION)) Which digital system translates coded characters into a more

useful form?
((OPTION_A)) Encoder
((OPTION_B)) Display
((OPTION_C)) Counter
((OPTION_D)) Decoder
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) How many inputs are required for a 1-of-10 BCD decoder?
((OPTION_A)) 4
((OPTION_B)) 8
((OPTION_C)) 10
((OPTION_D)) 16
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) A code converter is a logic circuit that _____________
((OPTION_A)) Inverts the given input

((OPTION_B)) Converts into decimal number
((OPTION_C)) Converts data of one type into another type
((OPTION_D)) Converts to octal
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Use the weighting factors to convert the following BCD numbers
to binary ___________
0101 0011 & 0010 0110 1000
((OPTION_A)) 01010011 001001101000
((OPTION_B)) 11010100 100001100000
((OPTION_C)) 110101 100001100
((OPTION_D)) 101011 001100001
(A/B/C/D)
((EXPLANATION)) Firstly, convert every 4 sets of binary to decimal from the given:
(OPTIONAL) 0101=5, 0011=3. Then convert 53 to binary, which will give
110101. Again, do the same with the next 4 set of binary digits.
((MARKS)) (1/2/3...) 1
((QUESTION)) Code is a symbolic representation of ___________
((OPTION_A)) Discrete information
((OPTION_B)) Continuous information
((OPTION_C)) Decimal information into binary
((OPTION_D)) Binary information into decimal
(A/B/C/D)
((EXPLANATION)) Codes can be anything like numbers, letter or words, written in

(OPTIONAL) terms of group of symbols.
((MARKS)) (1/2/3...) 1
((QUESTION)) All the comparisons made by comparator is done using

____________
((OPTION_A)) 1 circuit
((OPTION_B)) 2 circuit
((OPTION_C)) 3 circuit
((OPTION_D)) 4 circuit
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) One that is not the outcome of magnitude comparator is

____________
((OPTION_A)) a>b
((OPTION_B)) a–b
((OPTION_C)) a<b
((OPTION_D)) a=b
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Which one is a basic comparator?
((OPTION_A)) XOR
((OPTION_B)) XNOR
((OPTION_C)) AND
((OPTION_D)) NAND
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Comparators are used in ____________
((OPTION_A)) Memory
((OPTION_B)) CPU
((OPTION_C)) Motherboard
((OPTION_D)) Hard drive
(A/B/C/D)
((EXPLANATION)) Because all the arithmetic and logical operations are performed in
(OPTIONAL) the ALU(Arithmetic Logic Unit) part of the CPU.
((MARKS)) (1/2/3...) 1
((QUESTION)) How many types of digital comparators are?
((OPTION_A)) 4
((OPTION_B)) 3
((OPTION_C)) 2
((OPTION_D)) 1
(A/B/C/D)
((EXPLANATION)) There are two main types of Digital Comparator available and
(OPTIONAL) these are: Identity Comparator & Magnitude Comparator. Identity
Comparator checks only the equality of the inputs and thus has
one output terminal. While Magnitude Comparator checks for
greater than, less than as well as equality of the inputs, and thus
has 3 output terminals.
((MARKS)) (1/2/3...) 1
((QUESTION)) Which of the following combinations of logic gates can decode

binary 1101?
((OPTION_A)) One 4-input AND gate
((OPTION_B)) One 4-input AND gate, one inverter
((OPTION_C)) One 4-input AND gate, one OR gate
((OPTION_D)) One 4-input NAND gate, one inverter
(A/B/C/D)
((EXPLANATION)) For decoding any number output must be high for that code and
(OPTIONAL) this is possible in One 4-input NAND gate, one inverter option
only. A decoder is a combinational circuit that converts binary
data to n-coded data upto 2n outputs.
((MARKS)) (1/2/3...) 1
((QUESTION)) 3 bits full adder contains ________
((OPTION_A)) 3 combinational inputs
((OPTION_B)) 4 combinational inputs
((OPTION_C)) 6 combinational inputs
((OPTION_D)) 8 combinational inputs
(A/B/C/D)
((EXPLANATION)) Full Adder is a combinational circuit with 3 input bits and 2
(OPTIONAL) output bits CARRY and SUM. Three bits full adder requires 23 =
8 combinational circuits.
Which of the following respectively represent commutative law,
Associative law and Distributive law ?
A.(B C)=(A.B).C
A.(B+C)=A.B+A.C
A + B = B + A
A. I,III, and II
B. II, I and III
C. III, II and I
D. III, I and II
ANSWER: D
The number of canonical expressions that can be developed over a 3-valued

boolean algebra is
A. 8
B. 16
C. 32
D. 256
ANSWER: D
Simplified form of the boolean expression (X + Y + XY) (X + Z) is

A. X + Y + Z
B. XY + YZ
C. X + YZ
D. XZ + Y
ANSWER: A
A switching function is symmetric with respect to a set of literals if

and only if the function remains unchanged after
A. Two of these literals are interchanged
B. Any permutation of the literals
C. All the literals are changed in anticlockwise order
D. All the literals are changed in clockwise order
ANSWER: B
The voltages in digital electronics are continuously variable.
A. True
B. False
Answer:B
One hex digit is sometimes referred to as a(n):

A. byte
B. nibble
C. grouping
D. instruction
Answer:B
The minimal cover for the maimal compatibility classes {ae, acd, ad, bd}
is
A. ae, acd, ad '
B. acd, ad, bd
C. ae, acd, bd
D. ae, ad, bd
ANSWER: D
Which of the following expression remove hazard from : xy + zx ' ?

A. xy+zx'
B. xy+zx '+wyz
C. xy+zx'+yz
D. xy + zx' + wz
ANSWER: C
What is the form of the boolean expressions AB+ B'C' =Y?

A. Product-of-sums
B. Sum-of-products
C. Karnaugh map
D. Matrix
ANSWER: B
How many boolean functions of three variables f(x, y, z) have the

property that f(x, y, z) = (f(x, y, z)) ?
A. 8
B. 6
C. 64
D. 26
ANSWER: B
A graphical display of the fundamental products in a truth-table is known

as
A. Mapping
B. Graphing
C. T-map
D. karnaugh-map
ANSWER: D
Which is typically the longest: bit, byte, nibble, word?
A. Bit
B. Byte
C. Nibble
D. Word
Answer:D
How many binary digits are required to count to 10010?

A. 7
B. 2
C. 3
D. 100
Answer:A
Consider following switching function:

f(w, x, y, z) = w'x' + w'x y'+ wx'z'+ wxy
For this function, which of the following is list of essential prime
impicants ?
A. w' x', w' y', x' y', wxy, wyz
B. wxy, wyz'
C. w' x', w' y', x' z'
D. w' x', w' y', x' z, wxy'
ANSWER: C
If set x = {a, b, c, d}, then number of binary operations that can be

defined on x is
A. 42
B. 24
C. 216
D. 416
ANSWER: C
The minimum number of NAND gates required to implement the Boolean
function. A + AB' + AB'C is equal to
A. zero
B. 1
C. 4
D. 7
ANSWER: A
Which of the following logic expression is incorrect?

A. 1 ⊕ 0 = 1
B. 1 ⊕ 1 ⊕ 0 =1
C. 1 ⊕ 1 ⊕ 1 = 1
D. 1 ⊕ 1 = 0
ANSWER: B
In which of the following gates, the output is 1, if and only if at least

one input is 1?
A. NOR
B. AND
C. OR
D. NAND
ANSWER: C
What is the minimum number of two-input NAND gates used to perform the
function of two input OR gate ?
A. one
B. two
C. three
D. four
ANSWER: C

A. OR gate
B. AND gate
C. NOR gate
D. XOR gate
ANSWER: D
A. Three point majority circuit
B. Three bit parity checker
C. Three bit comparator
D. Three bit counter
ANSWER: D

A. 8 half-adders, 8 full-adders
B. 1 half-adder, 15 full-adders
C. 16 half-adders, 0 full-adders
D. 4 half-adders, 12 full-adders
ANSWER: B
The time required for a pulse to decrease from 90 to 10 per cent of its
maximum value is called
A. Rise time
B. Decay time
C. Binary level transition period
D. Propagation delay
ANSWER: B
Which of the following gates would output 1 when one input is 1 and other
input is 0 ?
A. OR gate
B. AND gate
C. NAND gate
D. both (a) and (c)
ANSWER: D
The sum of 11101 + 10111 equals ________.
When using even parity, where is the parity bit placed?
A. Before the MSB

B. After the LSB
C. In the parity word
D. After the odd parity bit
Answer:A
Which of the following is an invalid BCD code?
A. 0011
B. 1101
C. 0101
D. 1001
Answer:B
Convert the Gray code 1011 to binary.
A. 1011
B. 1010
C. 0100
D. 1101
Answer:D
Determine the decimal equivalent of the signed binary number 11110100 in
1's complement.
A. 116
B. –12
C. –11
D. 128
Answer:C
Which of the following statements is wrong ?

A. Propagation delay is the time required for a gate to change its state
B. Noise immunity is the amount of noise which can be applied to the
input of a gate without causing the gate to change state
C. Fan-in of a gate is always equal to fan-out of the same gate
D. Operating speed is the maximum frequency at which digital data can be
applied to a gate
ANSWER: C
Which of the following expressions is not equivalent to X ' ?

A. X NAND X
B. X NOR X
C. X NAND 1
D. X NOR 1
ANSWER: D
convert it to the NAND gate ?
A. NOT
B. AND
C. OR
D. XOR
ANSWER: A

inverter ?
A. OR
B. AND
C. NAND
D. XOR
ANSWER: D
A one-to-four line demultiplexer is to be implemented using a memory. How

many bits must each word have ?
A. 1 bit
B. 2 bits
C. 4 bits
D. 8 bits
ANSWER: A

AND gate ?
A. NAND
B. NOR
C. XOR
D. OR
ANSWER: A
Which of the following gates is known as coincidence detector ?

A. AND gate
B. OR gate
C. NOT gate
D. NAND gate
ANSWER: A
possible combination of logical states in the inputs ?
A. Function table
B. Truth table
C. Routing table
D. ASCII table
ANSWER: B
A positive AND gate is also a negative

A. NAND gate
B. NOR gate
C. AND gate
D. OR gate
ANSWER: D
A demultiplexer is used to
A. Route the data from single input to one of many outputs
B. Perform serial to parallel conversion
C. Both (a) & (b)
D. Select data from several inputs and route it to single output
ANSWER: C
An OR gate can be imagined as
A. Switches connected in series
B. Switches connected in parallel
C. MOS transistors connected in series
D. None of these
ANSWER: B
Which combination of gates does not allow the implementation of an

arbitrary boolean function?
A. OR gates and AND gates only
B. OR gates and exclusive OR gate only
C. OR gates and NOT gates only
D. NAND gates only
ANSWER: B
A. m/2
B. m-1
C. m
D. m+1
ANSWER: B
Parallel adders are

A. combinational logic circuits
B. sequential logic circuits
C. both (a) and (b)
D. None of these
ANSWER: A
The digital multiplexer is basically a combination logic circuit to

perform the operation
A. AND-AND
B. OR-OR
C. AND-OR
D. OR-AND
ANSWER: C
The output of NOR gate is

A. High if all of its inputs are high
B. Low if all of its inputs are low
C. High if all of its inputs are low
D. High if only of its inputs is low
ANSWER: C
How many lines the truth table for a four-input NOR gate would contain to
cover all possible input combinations ?
A. 4
B. 8
C. 12
D. 16
ANSWER: D

A. NOR gate
B. AND gate
C. NAND gate
D. XOR gate
ANSWER: B
every possible combination of electrical states in the inputs ?
A. Function table
B. Truth table
C. Routing table
D. ASCII table
ANSWER: A
What is the minimum number of 2 input NAND gates required to implement

the function
F = (x'+y') (z+w)
A. 6
B. 5
C. 4
D. 3
ANSWER: C
A. One
B. Two
C. Three
D. Any numbers
ANSWER: B
A. is slower
B. is faster
C. operates at the same speed as parallel adder
D. is more complicated
ANSWER: A
A. 2
B. 4
C. 8
D. 16
ANSWER: B
combinations is
A. 4
B. 8
C. 16
D. 32
ANSWER: C

A. input combination at the time
B. input combination and the previous output
C. input combination at that time and the previous input combination
D. present output and the previous output
ANSWER: A
he function of a multiplexer is
A. to decode information
B. to select 1 out of N input data sources and to transmit it to single
channel
C. to transit data on N lines
D. to perform serial to parallel conversion
ANSWER: B
A combinational logic circuit which generates a particular binary word or

number is
A. Decoder
B. Multiplexer
C. Encoder
D. Demultiplexer
ANSWER: A
Which of the following circuit can be used as parallel to serial

converter ?
A. Multiplexer
B. Demultiplexer
C. Decoder
D. Digital counter
ANSWER: A
eliminated ?
A. Half adder
B. Full adder
C. Parallel adder
D. Carry-look-ahead adder
ANSWER: C
Adders
A. adds 2 bits
B. is called so because a full adder involves two half-adders
C. needs two input and generates two output
D. All of these
ANSWER: D
The inverter OR-gate and AND gate are called deeision-making elements
because they can recognize some input while disregarding others. A gate
recognize a word when its output is
A. words,high
B. bytes,low
C. bytes,high
D. character,low
ANSWER: A
checking and 'parity' generation.
A. AND, OR, NOT gates
B. EX-NOR or EX-OR gates
C. NAND gates
D. NOR gates
ANSWER: B
An AND circuit
A. is a memory circuit
B. gives an output when all input signals are present simultaneously
C. is a -ve OR gate
D. is a linear circuit
ANSWER: B
Which of the following adders can add three or more numbers at a time ?
A. Parallel adder
B. Carry-look-ahead adder
C. Carry-save-adder
D. Full adder
ANSWER: C
What is the difference between binary coding and binary-coded decimal?
A. BCD is pure binary.

B. Binary coding has a decimal format.
C. BCD has no decimal format.
D. Binary coding is pure binary.
Answer:D
Digital electronics is based on the ________ numbering system.
A. decimal
B. octal
C. binary
D. hexadecimal
Answer:C
An informational signal that makes use of binary digits is considered to

be:
A. solid state
B. digital
C. analog
D. non-oscillating
Answer:B
The 1's complement of 10011101 is ________.
A. 01100010
B. 10011110
C. 01100001
D. 01100011
Answer: A
In the decimal numbering system, what is the MSD?
A. The middle digit of a stream of numbers

B. The digit to the right of the decimal point
C. The last digit on the right
D. The digit with the most weight
Answer:D
Which of the following statements does NOT describe an advantage of

digital technology?
A. The values may vary over a continuous range.

B. The circuits are less affected by noise.
C. The operation can be programmed.
D. Information storage is easy.
Answer:A
What are the symbols used to represent digits in the binary number
system?
A. 0,1
B. 0,1,2
C. 0 through 8
D. 1,2
Answer:A
NAND gate produces output HIGH, when
A. all the time

B. when any input is LOW
C. when any input is HIGH
D. when all inputs are HIGH
Answer:B
Any number with an exponent of one is equal to:
A. zero.
B. one.
C. two.
D. that number.
Answer:D
Determine the values of A, B, C, and D that make the sum term equal to
zero.
A.A = 1, B = 0, C = 0, D = 0
B.A = 1, B = 0, C = 1, D = 0
C.A = 0, B = 1, C = 0, D = 0
D.A = 1, B = 0, C = 1, D = 1
Answer:B
Which of the following expressions is in the sum-of-products (SOP) form?

A.(A + B)(C + D)
B.(A)B(CD)
C.AB(CD)
D.AB + CD
Answer:D
One of De Morgan's theorems states that . Simply stated, this means that
logically there is no difference between:
A.a NOR and an AND gate with inverted inputs
B.a NAND and an OR gate with inverted inputs
C.an AND and a NOR gate with inverted inputs
D.a NOR and a NAND gate with inverted inputs
Answer: B
The commutative law of Boolean addition states that A + B = A × B.

A.True
B.False
Answer:B
The systematic reduction of logic circuits is accomplished by:

A.using Boolean algebra
B.symbolic reduction
C.TTL logic
D.using a truth table
Answer: A
An AND gate with schematic "bubbles" on its inputs performs the same
function as a(n)________ gate.
A.NOT
B.OR
C.NOR
D.NAND
Answer:C
For the SOP expression , how many 1s are in the truth table's output
column?
A.1
B.2
C.3
D.5
Answer:C
A truth table for the SOP expression has how many input combinations?
A.1
B.2
C.4
D.8
Answer:D
How many gates would be required to implement the following Boolean

expression before simplification? XY + X(X + Z) + Y(X + Z)
A.1
B.2
C.4
D.5
Answer:D
Determine the values of A, B, C, and D that make the product term equal
to 1.
A.
A = 0, B = 1, C= 0, D = 1
B.
A = 0, B = 0, C = 0, D = 1
C.
A = 1, B = 1, C = 1, D = 1
D.
A = 0, B = 0, C = 1, D = 0
Answer:A
Minterms are also called

A. standard sum
B. standard product
C. standard division
D. standard subtraction
ANSWER: B
Maxterms are also called

A. standard sum
B. standard product
ANSWER: A
What is the primary motivation for using Boolean algebra to simplify
logic expressions?
A.It may make it easier to understand the overall function of the
circuit.
B.It may reduce the number of gates.
C.It may reduce the number of inputs required.
D.all of the above
Answer:B

expression after simplification? XY + X(X + Z) + Y(X + Z)
A.1
B.2
C.4
D.5
Answer:C
AC + ABC = AC
A.True
B.False
Answer:A
Which Boolean algebra property allows us to group operands in an

expression in any order without affecting the results of the operation
[for example, A + B = B + A]?
A.associative
B.commutative
C.Boolean
D.distributive
Answer:B
When grouping cells within a K-map, the cells must be combined in groups
of ________.
A.2s
B.1, 2, 4, 8, etc.
C.4s
D.3s
Answer:B
Use Boolean algebra to find the most simplified SOP expression for F =
ABD + CD + ACD + ABC + ABCD.
A.F = ABD + ABC + CD
B.F = CD + AD
C.F = BC + AB
D.F = AC + AD
Answer:A

the operation of a circuit, such as a BCD-to-decimal converter. These
result in ________terms in the K-map and can be treated as either
________ or ________, in order to ________ the resulting term.
A.don't care, 1s, 0s, simplify
B.spurious, ANDs, ORs, eliminate
C.duplicate, 1s, 0s, verify
D.spurious, 1s, 0s, simplify
Answer:A
The NAND or NOR gates are referred to as "universal" gates because

either:
A.can be found in almost all digital circuits
B.can be used to build all the other types of gates
C.are used in all countries of the world
D.were the first gates to be integrated
Answer:B
Convert hexadecimal value 16 to decimal.
A. 22
B. 16
C. 10
D. 20
Answer:A
Convert decimal number 187 to 8-bit binary.

A. 10111011
B. 11011101
C. 10111101
D. 10111100
Answer:A
Convert binary 111111110010 to hexadecimal.

A. EE2
B. FF2
C. 2FE
D. FD2
Answer:B
Which of the following respectively represent commutative law,
Associative law and Distributive law ?
A.(B C)=(A.B).C
A.(B+C)=A.B+A.C
A + B = B + A
A. I,III, and II
B. II, I and III
C. III, II and I
D. III, I and II
ANSWER: D
The number of canonical expressions that can be developed over a 3-valued

boolean algebra is
A. 8
B. 16
C. 32
D. 256
ANSWER: D
Simplified form of the boolean expression (X + Y + XY) (X + Z) is

A. X + Y + Z
B. XY + YZ
C. X + YZ
D. XZ + Y
ANSWER: A
A switching function is symmetric with respect to a set of literals if

and only if the function remains unchanged after
A. Two of these literals are interchanged
B. Any permutation of the literals
C. All the literals are changed in anticlockwise order
D. All the literals are changed in clockwise order
ANSWER: B
Convert binary number 01011 to decimal.
A. 11
B. 35
C. 15
D. 10
Answer:A
Convert the binary number 1001.00102 to decimal.

A. 90.125
B. 9.125
C. 125
D. 12.5
Answer:B
The voltages in digital electronics are continuously variable.

A. True
B. False
Answer:B
One hex digit is sometimes referred to as a(n):

A. byte
B. nibble
C. grouping
D. instruction
Answer:B
Convert 59.7210 to BCD.

A. 111011
B. 01011001.01110010
C. 1110.11
D. 0101100101110010
Answer:B
Convert 8B3F Hexadecimal to binary.

A. 35647
B. 011010
C. 1011001111100011
D. 1000101100111111
Answer:D
The minimal cover for the maimal compatibility classes {ae, acd, ad, bd}
is
A. ae, acd, ad '
B. acd, ad, bd
C. ae, acd, bd
D. ae, ad, bd
ANSWER: D
Which of the following expression remove hazard from : xy + zx ' ?

A. xy+zx'
B. xy+zx '+wyz
C. xy+zx'+yz
D. xy + zx' + wz
ANSWER: C
What is the form of the boolean expressions AB+ B'C' =Y?

A. Product-of-sums
B. Sum-of-products
C. Karnaugh map
D. Matrix
ANSWER: B
How many boolean functions of three variables f(x, y, z) have the

property that f(x, y, z) = (f(x, y, z)) ?
A. 8
B. 6
C. 64
D. 26
ANSWER: B
A graphical display of the fundamental products in a truth-table is known

as
A. Mapping
B. Graphing
C. T-map
D. karnaugh-map
ANSWER: D
Which is typically the longest: bit, byte, nibble, word?
A. Bit
B. Byte
C. Nibble
D. Word
Answer:D
Convert decimal 64 to binary.

A. 01010010
B. 01000000
C. 00110110
D. 01001000
Answer:B
Convert hexadecimal value C1 to binary.
A. 11000001
B. 1000111
C. 111000100
D. 111000001
Answer:A
Convert 178 octal number to decimal.

A. 51
B. 82
C. 57
D. 15
Answer:D
Convert 010111100 binary number to octal.

A. 172
B. 272
C. 174
D. 274
Answer:D
How many binary digits are required to count to 10010?

A. 7
B. 2
C. 3
D. 100
Answer:A
The BCD number for decimal 347 is ________.

A. 1100 1011 1000
B. 0011 0100 0111
C. 0011 0100 0001
D. 1100 1011 0110
Answer:B
The binary number for octal 458 is ________.

A. 100010
B. 100101
C. 110101
D. 100100
Answer:B
Consider following switching function:

f(w, x, y, z) = w'x' + w'x y'+ wx'z'+ wxy
For this function, which of the following is list of essential prime
impicants ?
A. w' x', w' y', x' y', wxy, wyz
B. wxy, wyz'
C. w' x', w' y', x' z'
D. w' x', w' y', x' z, wxy'
ANSWER: C
If set x = {a, b, c, d}, then number of binary operations that can be

defined on x is
A. 42
B. 24
C. 216
D. 416
ANSWER: C
The minimum number of NAND gates required to implement the Boolean

function. A + AB' + AB'C is equal to
A. zero
B. 1
C. 4
D. 7
ANSWER: A
Which of the following logic expression is incorrect?

A. 1 ⊕ 0 = 1
B. 1 ⊕ 1 ⊕ 0 =1
C. 1 ⊕ 1 ⊕ 1 = 1
D. 1 ⊕ 1 = 0
ANSWER: B
In which of the following gates, the output is 1, if and only if at least

one input is 1?
A. NOR
B. AND
C. OR
D. NAND
ANSWER: C
What is the minimum number of two-input NAND gates used to perform the
function of two input OR gate ?
A. one
B. two
C. three
D. four
ANSWER: C

A. OR gate
B. AND gate
C. NOR gate
D. XOR gate
ANSWER: D
A. Three point majority circuit
B. Three bit parity checker
C. Three bit comparator
D. Three bit counter
ANSWER: D

A. 8 half-adders, 8 full-adders
B. 1 half-adder, 15 full-adders
C. 16 half-adders, 0 full-adders
D. 4 half-adders, 12 full-adders
ANSWER: B
The time required for a pulse to decrease from 90 to 10 per cent of its
maximum value is called
A. Rise time
B. Decay time
C. Binary level transition period
D. Propagation delay
ANSWER: B
Which of the following gates would output 1 when one input is 1 and other
input is 0 ?
A. OR gate
B. AND gate
C. NAND gate
D. both (a) and (c)
ANSWER: D
The sum of 11101 + 10111 equals ________.
A. 110011
B. 100001
C. 110100
D. 100100
Answer:C
Convert 10011010 binary number to decimal.
A. 154
B. 155
C. 153
D. 157
Answer:A
The decimal number 188 is equal to the binary number ________.
A. 10111100
B. 0111000
C. 1100011
D. 1111000
Answer:A
Convert 001101011 binary number to octal.
A. 153
B. 351
C. 253
D. 352
Answer:A
A binary number's value changes most drastically when the ________ is

changed.
A. MSB
B. frequency
C. LSB
D. duty cycle
Answer:A
Convert decimal 213 to binary.
A. 11001101
B. 11010101
C. 11011111
D. 10010111
Answer:B
The decimal number for octal 748 is ________.
A. 74
B. 60
C. 22
D. 62
Answer:B
The sum of the two BCD numbers, 0011 + 0011, is ________.
A. 0110
B. 0111
C. 0011
D. 1100
Answer:A
Convert binary 01001110 to decimal.
A. 4E
B. 78
C. 76
D. 116
Answer:B
Which is not a word size?
A. 64
B. 28
C. 16
D. 8
Answer:B
The octal numbering system:

A. simplifies tasks
B. groups binary numbers in groups of 4
C. saves time
D. simplifies tasks and saves time
Answer :D
When using even parity, where is the parity bit placed?
A. Before the MSB

B. After the LSB
C. In the parity word
D. After the odd parity bit
Answer:A
Which of the following is an invalid BCD code?
A. 0011
B. 1101
C. 0101
D. 1001
Answer:B
Convert the Gray code 1011 to binary.
A. 1011
B. 1010
C. 0100
D. 1101
Answer:D
Determine the decimal equivalent of the signed binary number 11110100 in
1's complement.
A. 116
B. –12
C. –11
D. 128
Answer:C
Which of the following statements is wrong ?

A. Propagation delay is the time required for a gate to change its state
B. Noise immunity is the amount of noise which can be applied to the
input of a gate without causing the gate to change state
C. Fan-in of a gate is always equal to fan-out of the same gate
D. Operating speed is the maximum frequency at which digital data can be
applied to a gate
ANSWER: C
Which of the following expressions is not equivalent to X ' ?

A. X NAND X
B. X NOR X
C. X NAND 1
D. X NOR 1
ANSWER: D
convert it to the NAND gate ?
A. NOT
B. AND
C. OR
D. XOR
ANSWER: A

inverter ?
A. OR
B. AND
C. NAND
D. XOR
ANSWER: D
A one-to-four line demultiplexer is to be implemented using a memory. How

many bits must each word have ?
A. 1 bit
B. 2 bits
C. 4 bits
D. 8 bits
ANSWER: A

AND gate ?
A. NAND
B. NOR
C. XOR
D. OR
ANSWER: A
Which of the following gates is known as coincidence detector ?

A. AND gate
B. OR gate
C. NOT gate
D. NAND gate
ANSWER: A
possible combination of logical states in the inputs ?
A. Function table
B. Truth table
C. Routing table
D. ASCII table
ANSWER: B
A positive AND gate is also a negative

A. NAND gate
B. NOR gate
C. AND gate
D. OR gate
ANSWER: D
A demultiplexer is used to
A. Route the data from single input to one of many outputs
B. Perform serial to parallel conversion
C. Both (a) & (b)
D. Select data from several inputs and route it to single output
ANSWER: C
An OR gate can be imagined as

A. Switches connected in series
B. Switches connected in parallel
C. MOS transistors connected in series
D. None of these
ANSWER: B
Which combination of gates does not allow the implementation of an

arbitrary boolean function?
A. OR gates and AND gates only
B. OR gates and exclusive OR gate only
C. OR gates and NOT gates only
D. NAND gates only
ANSWER: B
A. m/2
B. m-1
C. m
D. m+1
ANSWER: B
Parallel adders are

A. combinational logic circuits
B. sequential logic circuits
C. both (a) and (b)
D. None of these
ANSWER: A
The digital multiplexer is basically a combination logic circuit to

perform the operation
A. AND-AND
B. OR-OR
C. AND-OR
D. OR-AND
ANSWER: C
The output of NOR gate is

A. High if all of its inputs are high
B. Low if all of its inputs are low
C. High if all of its inputs are low
D. High if only of its inputs is low
ANSWER: C
How many lines the truth table for a four-input NOR gate would contain to
cover all possible input combinations ?
A. 4
B. 8
C. 12
D. 16
ANSWER: D

A. NOR gate
B. AND gate
C. NAND gate
D. XOR gate
ANSWER: B
every possible combination of electrical states in the inputs ?
A. Function table
B. Truth table
C. Routing table
D. ASCII table
ANSWER: A
What is the minimum number of 2 input NAND gates required to implement
the function
F = (x'+y') (z+w)
A. 6
B. 5
C. 4
D. 3
ANSWER: C
A. One
B. Two
C. Three
D. Any numbers
ANSWER: B
A. is slower
B. is faster
C. operates at the same speed as parallel adder
D. is more complicated
ANSWER: A
A. 2
B. 4
C. 8
D. 16
ANSWER: B
combinations is
A. 4
B. 8
C. 16
D. 32
ANSWER: C

A. input combination at the time
B. input combination and the previous output
C. input combination at that time and the previous input combination
D. present output and the previous output
ANSWER: A
he function of a multiplexer is
A. to decode information
B. to select 1 out of N input data sources and to transmit it to single
channel
C. to transit data on N lines
D. to perform serial to parallel conversion
ANSWER: B
A combinational logic circuit which generates a particular binary word or
number is
A. Decoder
B. Multiplexer
C. Encoder
D. Demultiplexer
ANSWER: A
Which of the following circuit can be used as parallel to serial

converter ?
A. Multiplexer
B. Demultiplexer
C. Decoder
D. Digital counter
ANSWER: A
eliminated ?
A. Half adder
B. Full adder
C. Parallel adder
D. Carry-look-ahead adder
ANSWER: C
Adders
A. adds 2 bits
B. is called so because a full adder involves two half-adders
C. needs two input and generates two output
D. All of these
ANSWER: D
The inverter OR-gate and AND gate are called deeision-making elements
because they can recognize some input while disregarding others. A gate
recognize a word when its output is
A. words,high
B. bytes,low
C. bytes,high
D. character,low
ANSWER: A
checking and 'parity' generation.
A. AND, OR, NOT gates
B. EX-NOR or EX-OR gates
C. NAND gates
D. NOR gates
ANSWER: B
An AND circuit
A. is a memory circuit
B. gives an output when all input signals are present simultaneously
C. is a -ve OR gate
D. is a linear circuit
ANSWER: B
Which of the following adders can add three or more numbers at a time ?
A. Parallel adder
B. Carry-look-ahead adder
C. Carry-save-adder
D. Full adder
ANSWER: C
What is the difference between binary coding and binary-coded decimal?
A. BCD is pure binary.

B. Binary coding has a decimal format.
C. BCD has no decimal format.
D. Binary coding is pure binary.
Answer:D
Digital electronics is based on the ________ numbering system.
A. decimal
B. octal
C. binary
D. hexadecimal
Answer:C
An informational signal that makes use of binary digits is considered to

be:
A. solid state
B. digital
C. analog
D. non-oscillating
Answer:B
The 1's complement of 10011101 is ________.
A. 01100010
B. 10011110
C. 01100001
D. 01100011
Answer: A
In the decimal numbering system, what is the MSD?
A. The middle digit of a stream of numbers

B. The digit to the right of the decimal point
C. The last digit on the right
D. The digit with the most weight
Answer:D
Which of the following statements does NOT describe an advantage of

digital technology?
A. The values may vary over a continuous range.

B. The circuits are less affected by noise.
C. The operation can be programmed.
D. Information storage is easy.
Answer:A
What are the symbols used to represent digits in the binary number
system?
A. 0,1
B. 0,1,2
C. 0 through 8
D. 1,2
Answer:A
NAND gate produces output HIGH, when
A. all the time

B. when any input is LOW
C. when any input is HIGH
D. when all inputs are HIGH
Answer:B
Any number with an exponent of one is equal to:
A. zero.
B. one.
C. two.
D. that number.
Answer:D
Determine the values of A, B, C, and D that make the sum term equal to
zero.
A.A = 1, B = 0, C = 0, D = 0
B.A = 1, B = 0, C = 1, D = 0
C.A = 0, B = 1, C = 0, D = 0
D.A = 1, B = 0, C = 1, D = 1
Answer:B
Which of the following expressions is in the sum-of-products (SOP) form?

A.(A + B)(C + D)
B.(A)B(CD)
C.AB(CD)
D.AB + CD
Answer:D
One of De Morgan's theorems states that . Simply stated, this means that
logically there is no difference between:
A.a NOR and an AND gate with inverted inputs
B.a NAND and an OR gate with inverted inputs
C.an AND and a NOR gate with inverted inputs
D.a NOR and a NAND gate with inverted inputs
Answer: B
The commutative law of Boolean addition states that A + B = A × B.

A.True
B.False
Answer:B
The systematic reduction of logic circuits is accomplished by:

A.using Boolean algebra
B.symbolic reduction
C.TTL logic
D.using a truth table
Answer: A
An AND gate with schematic "bubbles" on its inputs performs the same
function as a(n)________ gate.
A.NOT
B.OR
C.NOR
D.NAND
Answer:C
For the SOP expression , how many 1s are in the truth table's output
column?
A.1
B.2
C.3
D.5
Answer:C
A truth table for the SOP expression has how many input combinations?
A.1
B.2
C.4
D.8
Answer:D

expression before simplification? XY + X(X + Z) + Y(X + Z)
A.1
B.2
C.4
D.5
Answer:D
Determine the values of A, B, C, and D that make the product term equal
to 1.
A.
A = 0, B = 1, C= 0, D = 1
B.
A = 0, B = 0, C = 0, D = 1
C.
A = 1, B = 1, C = 1, D = 1
D.
A = 0, B = 0, C = 1, D = 0
Answer:A
Minterms are also called

A. standard sum
B. standard product
ANSWER: B
Maxterms are also called

A. standard sum
B. standard product
ANSWER: A
What is the primary motivation for using Boolean algebra to simplify
logic expressions?
A.It may make it easier to understand the overall function of the
circuit.
B.It may reduce the number of gates.
C.It may reduce the number of inputs required.
D.all of the above
Answer:B

expression after simplification? XY + X(X + Z) + Y(X + Z)
A.1
B.2
C.4
D.5
Answer:C
AC + ABC = AC
A.True
B.False
Answer:A
Which Boolean algebra property allows us to group operands in an

expression in any order without affecting the results of the operation
[for example, A + B = B + A]?
A.associative
B.commutative
C.Boolean
D.distributive
Answer:B
When grouping cells within a K-map, the cells must be combined in groups
of ________.
A.2s
B.1, 2, 4, 8, etc.
C.4s
D.3s
Answer:B
Use Boolean algebra to find the most simplified SOP expression for F =
ABD + CD + ACD + ABC + ABCD.
A.F = ABD + ABC + CD
B.F = CD + AD
C.F = BC + AB
D.F = AC + AD
Answer:A

the operation of a circuit, such as a BCD-to-decimal converter. These
result in ________terms in the K-map and can be treated as either
________ or ________, in order to ________ the resulting term.
A.don't care, 1s, 0s, simplify
B.spurious, ANDs, ORs, eliminate
C.duplicate, 1s, 0s, verify
D.spurious, 1s, 0s, simplify
Answer:A
The NAND or NOR gates are referred to as "universal" gates because

either:
A.can be found in almost all digital circuits
B.can be used to build all the other types of gates
C.are used in all countries of the world
D.were the first gates to be integrated
Answer:B
Sr.
No. Question
1 The _______ operator represents complementary function.
For converting from SOP to standard SOP ____ each term with term formed by
2 Oring missing term and its complement.
3 From the truth table below, determine the standard SOP expression.
An OR gate with "bubbles" on its inputs performs the same functions as

4 ________ gate.
5 Minterm is each individual term in _____ form.
6 The expression Y=AB+(A+B)(ĀB+BB) is simplified as Y= _____
7 Find the equivalent of ∑m(2,4,7).
8 The expression Y=∑m(0,1) can also be represented as Y=______
The output of an OR gate with three inputs, A, B, and C, is LOW when

9 ________.
10 Which of the examples below expresses the commutative law of multiplication?
11 Which is the correct logic function for this PAL diagram?
12 Derive the Boolean expression for the logic circuit shown below:
The Boolean expression is logically equivalent to which

13 single gate?
The AND function can be used to ________ and the OR function can be used
14 to ________ .
15 Which of the following gates is described by the expression X=ABCD ?
16 How many truth table entries are necessary for a four-input circuit?
17 Find the complement of ABC.
18 EX-OR gate is ______ gate.

19 How many AND gates are required to implement Y=AB+CDE
20 IC 7404 is a 14 pin TTL Intergatrated Circuit with ____inverters inside.
21 The expression Y=ABC+ABC is in which form?
22 0110 represnts which combination?
23 Mapping the standard SOP expression
The truth table for the SOP expression has how many input
24 combinations?
25 The maxterm A+B+C is represented as ____.

26 expression after simplification? XY + X(X + Z) + Y(X + Z)
The Standard POS expression Y=(A+B+C)(A+B+C)(A+B+C) is also expressed

27 as Y=______.
28 The logic expression for a NOR gate is ________.
Use Boolean algebra to find the most simplified SOP expression

29 for F = ABD + CD +ACD + ABC + ABCD.
30 The NAND or NOR gates are referred to as "universal" gates because either:
31 Don’t Care Condition is_____.
32 The basic types of programmable arrays are made up of ________.
33 How many AND gates are found in a 7408 IC?
Converting the Boolean expression LM + M(NO + PQ) to SOP form, answer is

34 ________.
35 What is the difference between a 7400 and a 7411 IC?

Option A Option B Option C Option D
NOT NOR NAND EXNOR
OR AND NAND NOT
NAND NOR NOT OR
POS SOP SOP and POS NOP
A+B ĀB B AB
∑M(0,1,3,5,6) ∏m(0,1,3,5,6) ∑m(0,1,3,5,6) ∏m(0,1,3,5,6)
A B+A B AB+AB A B+A B A B+A B
A = 0, B = 0, C = 0 A = 0, B = 0, C = 1 A = 0, B = 1, C = 1 A=1 , B=1 ,C=1

A+B=B+A AB = BA AB = B + A AB = A × B
NAND NOR AND OR
enable or disable,
enable, disable disable, enable enable or disable detect, invert
OR AND NOR NAND
4 16 8 12
ABC A+B+C ABC A+B+C
Derived Basic Universal Complementary

1 2 3 4
2 4 8 6
Standard SOP Standard POS SOP and POS POS
ABCD ABCD ABCD ABCD
A B C D
1 2 4 8
M4 m4 M3 m3
1 2 4 5
∑M(0,6,2) ∏m(0,6,2) ∑m(7,1,5) ∏M(7,1,5)

F = ABD + ABC + C
D F = CD + AD F = BC + AB F = AC + AD
can be used to build all can be found in almost are used in all were the first gates to
the other types of gates all digital circuits countries of the world be integrated
0 or 1 0 1 Impedance
AND gates and OR

AND gates OR gates NAND and NOR gates gates
1 2 3 4
LM + MNOPQ L + MNO + MPQ LM + M + NO + MPQ LM + MNO + MPQ
7400 has two four- 7400 has four two-input 7400 has two four- 7400 has four two-
input NAND gates; NAND gates; 7411 has input AND gates; 7411 input AND gates; 7411
7411 has three three- three three-input AND has three three-input has three three-input
input AND gates gates NAND gates NAND gates
Answe Difficulty
r Marks Level Explanation
NOT represents inversion or
A 1 1 complementary
According to rule the term is to be

B 1 1 ANDed
D 1 1 Outputs which are 1 are taken for
Draw the truth table and then verify

A 1 1 it.
B 1 1 Minterm is for SOP.
Use Rules : AB+AB=AB , BB=B,

C 2 1 AĀ=0 ,A+1=1
Given function contains minterms

and hence answer should have
B 1 1 remainig as maxterms
First two combinations are to be

A 1 1 considered for this
As OR gate is having its ouput 1 even

if any of the input is 1 therefore 1st
A 1 1 option.
As cumulative law of multiplication
B 1 1 therefore second option
X sign indicates valid input considred

C 4 4 for this example.
A 1 1 Trace the diagram according to gates.
As given expression is equivalent to

A 1 1 ABC
Depending upon application both can

C 1 1 be used
Observing the expression , it is

D 1 1 product and then inversion
B 1 1 As 2^4=16
To find the complement invert each

B 1 1 variable and operator also.
A 1 1 As it is formed from other basic

C 1 1 One for AB and two for CDE.
As 7404 structure contains 6 NOT

D 1 1 gates i.e Inverters
A 1 1 As both terms contains all variables.
C 1 1 As it is represented in Minterms.
Observe the expresssion and then see

B 4 4 the Kmaps.
As three variables in the expression

D 2 2 therefore its 2^3=8.
ABC=011 amd minterm is ABCand

C 1 1 therefore maxterm is A+B+C
B 2 2 Use Rule 1+A=1.
Find out from table and as its

maxterm answer will have for
A 2 2 example A+B+C as 0,0,0 and which
From truth table we will have the
D 1 1 answer D
A 2 2 Use rule 1+A=1 for simplification.
NAND and NOR are used for

A 1 1 buliding all other types of gates.
A 1 1 Don’t Care has either 0 or 1 state.
Programmable arrays are

D 2 2 combination of both AND and OR
As according to structure only 4 gates

D 1 1 are their.
D 1 1 Only SOP so solve brackets.
B 2 2 According to manufacturer.
Unit 3rd Combinational Logic
Sr.
No. Question
1 IC74LS83 is __________.
2 Which among the following is the disadvantage of Half Adder?
3 Full Adder is used to add_____.
4 In Full Adder(A,B,C) , Sum = Ex or of ______.

5 In Half Adder the expression for Carry is ______
6 Which among the following is not true?
7 Half Subtractor is a Combinational Circuit with ___ inputs and _____ outputs.
8 In Half Subtractor (A,B) the Difference = ?
9 Full Subtractor is a Combinational Circuit with ___ inputs and ___ output.
10 The n-Bit Parallel Adder is used to add_____.

11 In BCD Adder , BCD cannot be greater than _____.
______is a combinational circuit , designed to compare two n-bit binary words

12 applied at its input.
13 IC 7485 is a _____.
1- Bit Binary Comparator is a Combinational Circuit with ____ inputs and ___
14 outputs
15 One of the output of one bit binary comparator is____.
16 BCD Subtraction can be calculated using which one among the following?
The 9's Complement of BCD number can be obtained by Subtracting it

17 from___.
18 While designing BCD Adder , which among the following are considered?
19 In Look Ahead Carry , Carry Generate =?
20 Look Ahead Carry eliminates the problem due to _____ .
21 The Pi in Look Ahead Carry is called as_____.
22 In Full Subtractor the Difference is EX OR of _____.
Disadvantage of Half Subtractor is that it can perform subtraction of ___ binary

23 bits.
24 How many 7485 IC will be required to design 24 bit magnitude comparator?

25 Which among the following is not the output of IC 7485?
26 8-bit magnitude comparator can be designed using ____ 7485.
27 BCD Subtractor using 10's Complement Method needs ___ 7483.
In the even parity system , the added parity bit will make total number of 1's an
28 ___ number.
29 ______ is a Logic Circuit which generates parity bits for even or odd parity.
30 Odd Parity Generator for 3 bit binary words will give output as ______.
31 The _______ circuit will check parity of word and produce its output.
32 IC 74180 is ________.
33 Expression for Carry Out in Full Adder is ______.
34 _______ are the Ouputs of IC 74180.
A Combinational Circuit in BCD Adder is used to check if Sum is ____ or

35 Carry= ____.
36 Which are the Cascading Input of IC 74180?
37 What is the Expression for the output A=B in 2 bit Binary Comparator?
Which are thefollowing are the inputs to the Combinational Circuit of BCD
38 adder using 4 bit binary adder?
In Half Subtractor Circuit , for the inputs 0 , 1 the Difference= ____ and
39 Borrow=____.
40 IC 7483 is having ___ and ___ as its outputs.
The output of Parity Checker Circuit is denoted by parity error output and
41 which is =0 when ____.
42 Sum and Carry both are 1 for A=__,B=__ and C=___ in Full Adder.
43 Cascading of two 74283 for 8 bit additions can be done using ______.
In Full Subtractor Circuit , Difference and Borrow are 1 for which of the
44 inputs?
45 Which are the Parity Input of IC 74180?
46 What is the Expression for the output A>B in 1 bit Binary Comparator?
47 How many 4 bit binary adders are required for designing 4-bit BCD Adder.
The output of Parity Checker Circuit is denoted by parity error output and
48 which is =1 when ____.
49 Even Parity Generator for 3 bit binary words will give output as ______.
In the odd parity system , the added parity bit will make total number of 1's an
50 ___ number.
51 How many 7485 IC will be required to design 5 bit magnitude comparator?
52 How many 74180 IC will be required to use it as 10 bit even parity generator?
53 Which component can be used to route multiple data over a single line
How many minimum number of NAND gate are required for realizing a 4 X 1
54 mux
55 ______ is also acts like a digitally controlled single pole, multiple way switch
56 If n=4 hence the nunmber of select lines m required by the multiplxer is _____.
57 The IC no for 4:1 MUX with output same as input is ____.
58 Which pin of 16:1 MUX is connected to logic low level.

59 16:1 MUX have _____ number of select lines
60 ______ performs parallel to series conversion
61 The IC no for 2:1 MUX with output same as input is ____.
62 The IC no for 2:1 MUX with inverted ouput is ______.
63 74151A IC is a 8:1 Multiplexer with output as ____.
_____ number of select lines are required for selecting the data pins when two
64 8:1 MUX are cascaded.
State which type of MUX can be used for implementing the given function :
65 Y= A'B'C' + AB'C + ABC
66 _____ device is used to distribute the received input over several outputs.
Which device can be used at the receiving end in the time division multiplexing
67 system
Which digital system has " n " number of input lines and "m" number of output
68 lines.
Which of the following are the types of encoders: i) Priority ii)
69 Decimal to BCD iii) Octal to Binary iv) Decimal to BCD
70 Which encoder is used when two or more input lines are " 1" at the same
71 74148 is ____ of priority encoder.
72 Octal to Binary Encoder has _____ input lines and _____ output lines.
73 In ______ select inputs are absent.
74 Common anode and common cathode are the _____ types of display
75 In non multilexed sidplay the typical segment current is _____ mA.
76 In multiplexed display the segment current is raised to about _____ mA.
The decoder / driver IC used for driving the common cathode display is
77 ______.
Active low open collector output and maximum voltage 30V and max current
78 sinking capability 40 mA are the specification of IC no ______.
Active low open collector output, maximum voltage 15V and max current 40
79 mA are the specification of IC no ______.
Active high open collector output, pull up resistor 2KW and maximum current
80 604 mA are the specification of IC____.
81 The IC 7485 is known as________ comparator.
82 The function of MUX is :
A combinationql logic circuit which generates a particular binary word or number is
83 _______
84 Which of the following circuit can be used as serial to parallel convertor?
85 A 'n' variable function can be realized with ______ select line MUX
A logic circuit which is used to change a BCD number to an equivalent decimal number
86 is _____.
87 Demux can be used to realize
88 The max number of outputs for a decoder with 6-bit daat word would be
A 4 X 2 encoder uses the following priorities I1 I3 I0 I2 ( highest to lowest ) if the
89 encoded bits are Y1 Y0 What is the expression for Y1 (MSB)
90 A DEMUX is used to
91 A X:Y decoder can be constructed using how many A:B decoder with enable
Match the following : i) MUX 1) Sequential memory ii) DEMUX
2) converts decimal to binary iii) shift registers 3) data selector
92 iv) Encoder 4) routes out many data output with single input
Match the following : i) Encoder 1) one to many ii) DEMUX
93 2) Some to many iii) Decoder 3) Many to some
94 The number of functions that can be realized by a decoder is restricted by
Match the following : i) Encoder 1) HUB ii) DEMUX
95 2) interrupt services iii) PLA 3) Minimizations
96 A multiplexer having 32-bit data input lines needs ____ select lines
97 MUX is used as data selector to select ______ out of many data inputs.
4 bit parallel addder 4 bit parallel subtractor 8 bit parallel adder 8 bit parallel subtractor
Addition of two and
Addition of two bits is Addition of three bits is Addition of three bits three bits both not
not possible. not possible. is possible. possible.
Two one bit numbers Two one bit numbers Two two bit numbers
and carry Two two bit numbers and carry and carry
A and B A and C B and C A , B and C

AB A B AB'
Half Adder adds two Full Adder can not be
Full Adder can be single bit numbers used as basic buliding Full Adder adds two
designed using Half without considering block for 4 bit BCD single bit numbers and
Adder Carry. Adder IC such as 7483 also considers carry.
two,one two,three two,two one,two
A EXOR B A B AB
three,two two,two three,one three,three

two n-bit binary three n-bit binary
two binary numbers numbers numbers BCD numbers
15 9 8 4
Adder Subtractor Digital Comparator Divisor

4 bit Magnitude 8 bit Magnitude 2 bit Magnitude 1 bit Magnitude
Comparator Comparator Comparator Comparator
two,three three,three two,two three,two
A<B A!=B A>=B A<=B
6's Complement 7's Complement 8's Complement 9's Complement
6 7 9 10
Carry Sum Sum and Carry Borrow
AiBi Ai EXOR Bi Ai Bi
interstage carry delay borrow delay addtion inputs

Carry Propogation
Carry Produced Carry Propogate Delay Carry Problem
A,B,Bin A,B A,Bin B
one two three four
4 5 6 7
A>B A=B A<B A!-B
one two three four
2 3 4 5
even odd random either even or odd
Sequence Generator Parity Generator Parity Maker Parity Sequencer
EX OR of 3 bit binary ANDing of 3 bit Binary EX NOR of 3 bit ORing of 3 bit Binary
words Words binary words Words
Parity Checker Parity Generator Parity Maker Parity Sequencer

A Parity
A Parity Sequencer A Parity Detector A Parity Removal Generator/Checker
AB+AC+BC EX OR of A,B,C AB'+A'C+BC' A'B+A'C+B'C
∑Even ∑Even and ∑Odd ∑Odd ∑A to H
less than 9 ,0 less than 9 ,1 greater than 9 ,0 greater than 9 ,1
A to H EVEN ODD EVEN and ODD

EX OR of A1 , B1 and ANDof A1 , B1 and NAND of A1 , B1 and EX NOR of A1 , B1
A0,B0 A0,B0 A0,B0 and A0,B0
Cout and Output of Cin ,Cout and Output
Cout Output of First Adder first Adder of first Adder
0,0 1,1 1,0 0,1
Difference,Borrow Sum,Carry Sum,Borrow Difference,Carry
Error is present there is no error error may be their error is to be removed
1,1,1 1,0,1 1,1,0 0,0,1
Cin of one and Cout of

Cin of both IC's only Cout of both IC's Only other A0-A3 and B0-B3
(0,0,1),(0,1,0),(1,0,1) (0,0,1),(0,1,0),(1,1,1) (0,0,1),(0,1,1),(1,1,1) (1,0,1),(0,1,0),(1,1,1)

A to H EVEN ODD EVEN and ODD
AB AB' AB+AB' A'B
one three two four
Error is present there is no error error may be their error is to be removed
EX OR of 3 bit binary ANDing of 3 bit Binary EX NOR of 3 bit ORing of 3 bit Binary
words Words binary words Words
even odd random either even or odd
two one three four
one two three four

Encoder Multiplexer Decoder Demultiplexer
1 2 5 7
Mulitplexer Ecoder Decoder Demultiplexer
1 2 3 4
74157 74153 74352 74158
S E' E D
2 3 4 1
Mulitplexer Encoder ADC DAC
74158 74150 74157 74151A
74158 74150 74157 74150
same as input inverted output complementary otuput no output
4 2 3 6
8:1 MUX 2:1 MUX 4:1 MUX 16:1 MUX
Demultiplexer Multiplexer Amplifier OP- Amplifier

Mulitplexer Decoder Demultiplexer Encoder
Encoder Multiplexer Decoder Demultiplexer
1 and 2 1 2 All
Priority Decimal to BCD Octal to Binary Hexadecimal to Binary
Decimal to BCD Octal to Binary BCD to Decimal Binary to Octal
8,3 3,8 2,8 8.2
Demultiplexer Decoder Multiplexer Encoder
BCD to seven segment Seven segment to BCD both a and b None
10 30 20 40
10 30 20 40
7448 / 74248 7447 / 74247 both a and b None
7446 / 74246 7447 / 74247 7448 / 74248 7446 / 7448
7447 / 74246 7448 / 74247 7449 / 74248 7447 / 7448
7448 / 74246 7447 / 74247 7448 / 74248 7446 / 7448

4-bit 2-bit 3-bit 1-bit
to select 1 out of N input
to perform serial to
to decode information data sources and to transit to transit data on N lines
parallel conversion
it to single channel
Decoder Multiplexer Encoder Demultiplexer
Digital Counters Multiplexer Demultiplexer Decoder

n n-1 both a and b none
Decoder Encoder Multiplexer Code Convertor
Counter Shift Registers Combinational Circuits Display systems

64 6 24 256
I1 + I3' I0 I1 + I3 I1 + I2 + I3 None of these
route the data from select data from several

perform serial to parallel
single input to one of input and route it to single All of these
conversion
many output output
Y/B X/A X/B Y/A
i-3, ii-4, iii-1, iv-2 i-4, ii-3, iii-1, iv-2 i-3, ii-4, iii-2, iv-1 i-1, ii-2, iii-3, iv-4
i-1, ii-2, iii-3 i-3, ii-1, iii-2 i-1, ii-2, iii-3 None of these
fanout capacity number of gates both a and b None of these
i-2, ii-1, iii-3 i-3, ii-1, iii-2 i-1, ii-3, iii-2 None of these
5 3 4 2
one two three four
Answe Difficulty
r Marks Level Explanation
A 1 1 IC74LS83 is 4 bit parallel adder.
Addition of three bits is not possible
with Half Adder as is adds only two
B 1 1 bits.
Full Adder adds two one bit numbers
A 2 2 and carry.
Sum is Ex or of A , B and C in Full
D 2 2 Adder
A 1 1 In Half Adder Carry is AB
Full Adder can be used as basic

buliding block for 4 bit BCD Adder
C 2 2 IC such as 7483
Half Subtractor is a Combinational
Circuit with two inputs and two
C 1 1 outputs.
In Half Subtractor (A,B) the
A 1 1 Difference = A EXOR B
Full Subtractor is a Combinational
Circuit with three inputs and two
A 1 1 output.
The n-Bit Parallel Adder is used to
B 2 2 add two n-bit binary numbers.
B 1 1 BCD cannot be greater than 9.
Digital Comparator is a
combinational circuit , designed to
C 1 1 compare two n-bit binary words
IC 7485 is a 4 bit Magnitude
A 1 1 Comparator.
1- Bit Binary Comparator is a
Combinational Circuit with two
A 1 1 inputs and three outputs.
One of the output of one bit binary
A 1 1 comparator is A<B.
BCD Subtraction can be calculated
D 1 1 using 9's Complement Method
The 9's Complement of BCD number
can be obtained by Subtracting it
C 1 1 from 9 .
C 1 1 BCD Adder considers Sum and
In Look Ahead Carry , Carry
A 1 1 Generate = AiBi
Look Ahead Carry eliminates the
A 1 1 problem due to interstage carry delay
The Pi in Look Ahead Carry is called
B 1 1 as Carry Propogate.
In Full Subtractor the Difference is
A 1 1 EX OR of A,B,Bin.
Disadvantage of Half Subtractor is
that it can perform subtraction of two
B 1 1 binary bits.
6, 7485 IC will be required to design
C 4 4 24 bit magnitude comparator.
D 2 2 A!=B is not the ouput of IC 7485
8-bit magnitude comparator can be
B 1 1 designed using two7485.
BCD Subtractor using 10's
C 2 2 Complement Method needs four
In the even parity system , the added
parity bit will make total number of
A 1 1 1's an even number.
Parity Generator is a Logic Circuit
which generates parity bits for even
B 1 1 or odd parity.
Odd Parity Generator for 3 bit binary
words will give output as EX OR of 3
A 2 2 bit binary words.
The Parity Checker circuit will check
A 1 1 parity of word and produce its output.
IC 74180 is Parity Generator /
D 1 1 Checker.
Expression for Carry Out in Full
A 2 2 Adder is AB+AC+BC.
∑Even and ∑Odd are the Ouputs of
B 1 1 IC 74180.
A Combinational Circuit in BCD
Adder is used to check if Sum is
D 2 2 greater than 9 or Carry=1.
EVEN and ODD , both are
D 1 1 Cascading Inputs of IC 74180.
A=B is EX NOR of A1 , B1 and
D 4 2 A0,B0 in 2 bit comparator.
Cout and Output of first Adder are
the two inputs to the Combinational
C 2 2 Circuit.
In Half Subtractor Circuit , for the
inputs 0 , 1 the Difference=1 and
B 1 1 Borrow=1.
IC 7483 is having Sum and Carry as
B 1 1 its outputs.
The output of Parity Checker Circuit
is denoted by parity error output and
B 1 1 which is =1 when there is no error.
Sum and Carry both are 1 for
A 1 1 A=1,B=1 and C=1 in Full Adder.
Cascading of two 74283 for 8 bit
additions can be done using Cin of
C 1 1 one and Cout of other.
In Full Subtractor Circuit , Difference
and Borrow are 1 for following
B 2 2 inputs: (0,0,1),(0,1,0),(1,1,1)
A 1 1 A to H are Parity Inputs of IC 74180.
Expression for the output A>B in 1
B 2 2 bit Binary Comparator is AB'.
two, 4 bit binary adders are required
C 1 1 for designing 4 bit BCD Adder.
The output of Parity Checker Circuit
is denoted by parity error output and
A 1 1 which is =1 when error is present.
Even Parity Generator for 3 bit binary
words will give output as EX OR of 3
A 2 2 bit binary words.
In the even parity system , the added
parity bit will make total number of
B 1 1 1's an odd number.
One 7485 IC will be required to
B 1 1 design 5 bit magnitude comparator.
One, 74180 IC will be required to use
A 1 1 it as 10 bit even parity generator.
B 1 Easy
D 1
A 1
2m= n thus, if m=2 then 22 = 4 ie
B 1
value of n
74153 because 74352 is 4:1 mux
with inverted opuput and 74157,
B 1
74158 are 2:1 mux with o/p same as
i/p and inverted o/p resp.
the enable pin of MUX IC is a
B 1
bubbled one ie denoting E'
B 1
A 1
C 1
A 1
C 1
three select lines i.e. S0 S1 S2 and the
A 1 enable pin act as the 4th select line as
E' is used for cascading purpose.
Y= A'B'C'+ AB'C + ABC represented
in their SOP Minterms form we get
A'B'C'= 000, AB'C= 101, ABC= 111.
A 1
thus, the data input pin 0,5,7 will be
selected and can be implemented
using 8:1 MUX
A 1
C 1
A 1
D 1
A 1
B 1
A 1
B 1
C 1
C 1
D 1
Because 7447 / 74247 is the common
A 1
cathode IC of display
A 1
B 1
C 1
A 1
B 1
A 1
B 1
C 1
A 1
C 1
D 1
C 2
A 1
A 2
A 2
B 2
B 2
A 2
A 1
A 1
((MARKS)) (1/2/3...) 1
((QUESTION)) 32:1 multiplexer has ________ number of select lines
((OPTION_A)) 2
((OPTION_B)) 3
((OPTION_C)) 5
((OPTION_D)) 8
(A/B/C/D)
((EXPLANATION)) 2 select lines = number of inputs

(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) A multiplexer has ________
((OPTION_A)) One input & several output
((OPTION_B)) Several inputs & several outputs
((OPTION_C)) One input & one output
((OPTION_D)) Several inputs & one output
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) How many gates would be required to implement the following

Boolean expression after simplification? XY + X(X + Z) + Y(X + Z)
1
((OPTION_A))
2
((OPTION_B))
4
((OPTION_C))
5
((OPTION_D))
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) How many full adders are required to construct an m-bit parallel
adder ?
((OPTION_A)) m/2
((OPTION_B)) m+1
((OPTION_C)) m
((OPTION_D)) m-1
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) In the Karnaugh map shown below, which of the loops shown
represents a legal grouping?
((OPTION_A)) A
((OPTION_B)) B
((OPTION_C)) C
((OPTION_D)) D
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
Which sequential circuits generate the feedback path due to the cross-
coupled connection from output of one gate to the input of another gate?
A. Synchronous
B. Asynchronous
C. Both
D. None of the above
ANSWER: B
What is/are the crucial function/s of memory elements used in the

sequential circuits?
A. Storage of binary information
B. Specify the state of sequential
C. Both a & b
ANSWER: C
How are the sequential circuits specified in terms of time sequence?

A. By Inputs
B. By Outputs
C. By Internal states
D. All of the above
ANSWER: D
The behaviour of synchronous sequential circuit can be predicted by

defining the signals at ______.
A. discrete instants of time
B. continuous instants of time
C. sampling instants of time
D. at any instant of time
ANSWER: A
Which memory elements are utilized in an asynchronous & clocked

sequential circuits respectively?
A. Time- delay devices & registers
B. Time- delay devices & flip-flops
C. Time- delay devices & counters
D. Time-delay devices & latches
ANSWER: B
Why do the D-flipflops receives its designation or nomenclature as 'Data

Flipflops' ?
A. Due to its capability to receive data from fliflop
B. Due to its capability to store data in flipflop
C. Due to its capability to transfer the data into flipflop
D. All of the above
ANSWER: C
The characteristic equation of D-flipflop implies that _____.

A. the next state is dependent on previous state
B. the next state is dependent on present state
C. the next state is independent of previous state
D. the next state is independent of present state
ANSWER: D
Which circuit is generated from D-flipflop due to addition of an inverter
by causing reduction in the number of inputs?
A. Gated JK- latch
B. Gated SR- latch
C. Gated T- latch
D. Gated D- latch
ANSWER: D
What is the bit storage binary information capacity of any flipflop?

A. 1 bit
B. 2 bits
C. 16 bits
D. infinite bits
ANSWER: A
What is/are the directional mode/s of shifting the binary information in

a shift register?
A. Up-Down
B. Left - Right
C. Front - Back
D. All of the above
ANSWER: B
Which time interval specify the shifting of overall contents of the shift
registers?
A. Bit time
B. Shift time
C. Word time
D. Code time
ANSWER: C
Which type of shift register is renowned as 'bit bucket brigade circuit'

by presenting the input data and applying the clock pulse for the
movement of bits across the storage elements?
A. Serial In - Serial Out (SISO)
B. Serial In - Parallel Out (SIPO)
C. Parallel In - Parallel Out (PIPO)
D. Parallel In - Serial Out (PISO)
ANSWER: A
Which kind of dynamic shift register has a provision of repeating the

code continuously by connecting its output back to the serial input?
A. PIPO Register
B. SISO Register
C. Multi-mode Shift Register
D. Reintrant Shift Register
ANSWER: D
A counter is fundamentally a _________ sequential circuit that proceeds

through the predetermined sequence of states only when input pulses are
applied to it.
A. register
B. memory unit
C. flipflop
D. arithmatic logic unit
ANSWER: A
Which property of unit distance counters has the potential to overcome

the consequences of multi-bit change flashing that arises in almost all
conventional binary and decimal counters?
A. one bit change per unit change
B. two bits change per unit change
C. three bits change per unit change
D. four bits change per unit change
ANSWER: A
What contributes to the triggering of clock pulse inputs for all the
flipflops excluding the first flipflop in a ripple counter?
A. Incoming Pulses
B. Output Transistion
C. Double Clock Pulses
D. All of the above
ANSWER: B
What is the required relationship between number of flipflops and the

timing signals in Johnson Counter?
A. No. of flipflops = 1/2 x No. of timing signals
B. No. of flipflops = 2/3 x No. of timings signals
C. No. of flipflops = 3/4 x No. of timing signals
D. No. of flipflops = 4 x No. of timing signals
ANSWER: A
In moore model outputs are functions of

A. present state
B. input state
C. next state
D. both a and b
ANSWER: A
Memory elements in clocked sequential circuits are called

A. latches
B. flipflop
C. signals
D. gates
ANSWER: B
Design procedure of sequential circuit is based on

A. 7steps
B. 8steps
C. 9steps
D. 10steps
ANSWER: C
In a digital counter circuit feedback loop is introduced to

A. Improve distortion
B. Improve stability
C. Reduce the number of input pulses to reset the counter
D. Asynchronous input and output pulses
ANSWER: C

bottles automatically. In such a counter what will be the number of flip-
flops required ?
A. 3
B. 12
C. 6
D. 8
ANSWER: C
A pulse train can be delayed by a finite number of clock periods using

A. A serial-in serial-out shift register
B. A serial-in parallel-out shift register
C. Both (a) and (b)
D. A parallel-in parallel-out shift register
ANSWER: D
How many illegitimate states has synchronous mod-6 counter ?

A. 3
B. 2
C. 1
D. 6
ANSWER: A
A 2 bit binary multiplier can be implemented using

A. 2 input ANDs only
B. 2 input XORs and 4 input AND gates only
C. 2 input NORs and one XNOR gate
D. NOR gates and shift registers
ANSWER: B
A ring counter is same as

A. up-down counter
B. parallel-counter
C. shift register
D. Ripple carry Counter
ANSWER: C
The dynamic hazard problem occurs in

A. Combinational circuit alone
B. Sequential circuit only
C. Both (a) and (b)
D. None of these
ANSWER: C
The clock signals are used in sequential logic circuits to

A. Tell the time of the day
B. Tell how much time has elapsed since the system was turned on
C. Carry parllel data signals
D. Synchronize events in various parts of system
ANSWER: D
74L5138 chip functions as
A. Decoder/demultiplexer
B. Encoder
C. Multiplexer
D. Demultiplexer
ANSWER: A
A sequential circuit outputs a ONE when an even number (> 0) of one's are
input; otherwise the output is ZERO. The minimum number of states
required is
A. 0
B. 1
C. 2
D. None of these
ANSWER: C
A shift register can be used for

A. Digital delay line
B. Serial to parallel conversion
C. Parallel to serial conversion
D. All of these
ANSWER: D
Popular application of flip-flop are

A. Transfer register
B. Shift registers
C. Counters
D. All of these
ANSWER: D
For which of the following flip-flops, the output is clearly defined for
all combinations of two inputs ?
A. Q type flip-flop
B. R-S flip-lop
C. J-K flip-lop
D. D flip-flop
ANSWER: C
When a large number of analog signals are to be converted an analog

multiplexer is used. In this case most suitable A.D. converter will be
A. Ripple carry counter type
B. Dual stop type
C. Forward counter type
D. Successive approximation type
ANSWER: D
To build a mod-19 counter the number of flip-flops required is

A. 3
B. 5
C. 7
D. 9
ANSWER: B
The astable multivibrator has

A. Two quasi stable states
B. Two stable states
C. One stable and one quasi-stable state
D. None of these
ANSWER: A
and ten numerals ?
A. 5
B. 6
C. 10
D. 48
ANSWER: B
The functional difference between S-R flip-flop and J-K flip-flop is that
J-K flip-flop
A. is faster than S-R flip-flop
B. Has a feed-back path
C. Accepts both inputs 1
D. Both (a) and (b)
ANSWER: C
In a positive edge triggered JK flip-flop, a low J and low K produces

A. No change
B. Low state
C. High state
D. None of these
ANSWER: A

A. JK flip-flop
B. D flip-flop
C. SR flip-flop
D. Master slave JK flip-flop
ANSWER: B
A 2 MHz signal is applied to the input of a J-K lip-lop which is

operating in the 'toggle' mode. The frequency of the signal at the output
will be
A. 1 MHz
B. 2 MHz
C. 6 MHz
D. 8 MHz
ANSWER: D
The master slave JK lip-flop is effectively a combination of

A. A SR flip-flop and a T flip-flop
B. An SR flip-lfop and a D flip-flop
C. A T flip-flop and a D flip-flop
D. Two D flip-flops
ANSWER: A
It is difficult to design asynhronous sequential circuit because

A. External clock is to be provided
B. It is more complex
C. Both (a) and (b)
D. Generally they involve stability problem
ANSWER: D
A stable multivibrator is used as

A. Comparator circuit
B. Demultiplexer
C. Frequency to voltage converter
D. Voltage to frequency converter
ANSWER: A
How many flip-flop are needed to divide the input frequency by 64 ?

A. 2
B. 5
C. 6
D. 8
ANSWER: C
In a ripple counter using edge triggered JK flfp-flops, the pulse input

is applied to the
A. clock input of all flip-flops
B. clock input of one flip-flops
C. J and K inputs of all flip-flops
D. J and K inputs of one flip-flop
ANSWER: D
The number of clock pulses needed to shift one byte of data from input to
the output of a 4-bit shift register is
A. 10
B. 12
C. 16
D. 32
ANSWER: C
The main difference between JK and RS flip-flop is that

A. JK flip flop needs a clock pulse
B. There is a feedback in JK lip-lop
C. JK flip-flop accepts both inputs as 1
D. JK flip-flop is acronym of Junction cathode multivibrator
ANSWER: C

binary code ?
A. Encoder
B. Decoder
C. Multiplexer
D. Counter
ANSWER: A
The flip-flops which operate in synchronism with external clock pulses

are known as
A. Synchronous flip-flop
B. Asynchronous flip-flop
C. Either of the above
D. None of these
ANSWER: A
Which of the following flip-flop is free from race-around problem ?

A. Q flip-flop
B. T flip-flop
C. SR flip-flop
D. Master-slave JK flip-flop
ANSWER: D
If the input J is connected through K input of J-K, then flip-flop will

behave as a
A. D type flip-flop
B. T type flip-flop
C. S-R flip-flop
ANSWER: B
If a clock with time period 'T' is used with n stage shift register, then
output of final stage will be delayed by
A. nT sec
B. (n-1)T sec
C. n/T sec
D. (2n+1)T sec
ANSWER: B
Register is a
A. set of capacitor used to register input instructions in a digital
computer
B. set to paper tapes and cards put in a file
C. temporary storage unit within the CPU having dedicated or general
purpose use
D. part of the main memory
ANSWER: C
The number of flip-flops required in a decade counter is

A. 3
B. 4
C. 8
D. 10
ANSWER: B
Which of the following is asynchronous input of SR flip-flop

A. S
B. R
C. PRESET
D. CLOCK
ANSWER: C
Which of the following is synchronous input of SR flip-flop?

A. S
B. R
C. PRESET
D. CLOCK
ANSWER: D
On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2

= 1, and Q3 = 1. On the sixth clock pulse, the sequence is ________.
A.Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
B.Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0
C.Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1
D.Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1
Answer:C
What is a shift register that will accept a parallel input, or a

bidirectional serial load and internal shift features, called?
A.tristate
B.end around
C.universal
D.conversion
Answer:C
On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2

= 1, and Q3 = 0. On the fourth clock pulse, the sequence is ________.
A.Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1
B.Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0
C.Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
D.Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0
Answer:A
A bidirectional 4-bit shift register is storing the nibble 1101. Its

input is HIGH. The nibble 1011 is waiting to be entered on the serial
data-input line. After three clock pulses, the shift register is storing
________.
A.1101
B.0111
C.0001
D.1110
Answer:B

________.
A.1101
B.0111
C.0001
D.1110
Answer:B
How can parallel data be taken out of a shift register simultaneously?

A.Use the Q output of the first FF.
B.Use the Q output of the last FF.
C.Tie all of the Q outputs together.
D.Use the Q output of each FF.
Answer:D
What is meant by parallel load of a shift register?
A.All FFs are preset with data.
B.Each FF is loaded with data, one at a time.
Answer:A
What does the output enable do on the 74395A chip?

A.It determines when data can be loaded.
B.It forces all outputs to go HIGH.
C.It forces all outputs to go LOW.
D.It activates the three-state buffer.
Answer:D
To operate correctly, starting a ring shift counter requires:

A.clearing all the flip-flops
B.presetting one flip-flop and clearing all others
C.clearing one flip-flop and presetting all others
D.presetting all the flip-flops
Answer:B
In a 6-bit Johnson counter sequence there are a total of how many states,
or bit patterns?
A.2
B.6
C.12
D.24
Answer:C
A modulus-12 ring counter requires a minimum of ________.

A.10 flip-flops
B.12 flip-flops
C.6 flip-flops
D.2 flip-flops
Answer:B
The group of bits 11001 is serially shifted (right-most bit first) into a
5-bit parallel output shift register with an initial state 01110. After
three clock pulses, the register contains ________.
A.01110
B.00001
C.00101
D.00110
Answer:C
Assume that a 4-bit serial in/serial out shift register is initially

clear. We wish to store the nibble 1100. What will be the 4-bit pattern
after the second clock pulse? (Right-most bit first.)
A.1100
B.0011
C.0000
D.1111
Answer:C
A serial in/parallel out, 4-bit shift register initially contains all 1s.
The data nibble 0111 is waiting to enter. After four clock pulses, the
register contains ________.
A.0000
B.1111
C.0111
D.1000
Answer:C
A sequence of equally spaced timing pulses may be easily generated by

which type of counter circuit?
A.ring shift
B.clock
C.Johnson
Answer:A
An 8-bit serial in/serial out shift register is used with a clock

frequency of 2 MHz to achieve a time delay (td) of ________.
A. 16s
B. 8s
C. 4s
D. 2s
Answer:C
The bit sequence 10011100 is serially entered (right-most bit first) into
an 8-bit parallel out shift register that is initially clear. What are
the Q outputs after four clock pulses?
A.10011100
B.11000000
C.00001100
D.11110000
Answer:B
If an 8-bit ring counter has an initial state 10111110, what is the state
after the fourth clock pulse?
A.11101011
B.00010111
C.11110000
D.00000000
Answer:D
How would a latch circuit be used in a microprocessor system?

A.as transportation for Intel employees
B.for a group of data that is the same
C.as a set of common connections for transfer of data
Answer:C
A 4-bit shift register that receives 4 bits of parallel data will shift
to the ________ by ________ position(s) for each clock pulse.
A.right, one
B.right, two
C.left, one
D.left, three
Answer:A
How many clock pulses will be required to completely load serially a 5-
bit shift register?
A.2
B.3
C.4
D.5
Answer:D
How is a strobe signal used when serially loading a shift register?

A.to turn the register on and off
B.to control the number of clocks
C.to determine which output Qs are used
D.to determine the FFs that will be used
Answer:B
What are the three output conditions of a three-state buffer?

A.HIGH, LOW, float
B.1, 0, float
C.both of the above
D.neither of the above
Answer:C
The primary purpose of a three-state buffer is usually:

A.to provide isolation between the input device and the data bus
B.to provide the sink or source current required by any device connected
to its output without loading down the output device
C.temporary data storage
D.to control data flow
Answer:A
What is the difference between a ring shift counter and a Johnson shift
counter?
A.There is no difference.
B.A ring is faster.
C.The feedback is reversed.
D.The Johnson is faster.
Answer:C
What is a recirculating register?

A.serial out connected to serial in
B.all Q outputs connected together
C.a register that can be used over again
Answer:A
When is it important to use a three-state buffer?

A.when two or more outputs are connected to the same input
B.when all outputs are normally HIGH
C.when all outputs are normally LOW
D.when two or more outputs are connected to two or more inputs
Answer:A

Answer:C
A.right, one
B.right, two
C.left, one
D.left, three
Answer:C

bit shift register?
A.2
B.3
C.4
D.5
Answer:D

input is LOW. The nibble 0111 is waiting to be entered on the serial
data-input line. After two clock pulses, the shift register is storing
________.
A.1110
B.0111
C.1000
D.1001
Answer:D
In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and

D3 = 0. After three clock pulses, the data outputs are ________.
A.1110
B.0001
C.1100
D.1000
Answer:B
The group of bits 10110111 is serially shifted (right-most bit first)

into an 8-bit parallel output shift register with an initial state
11110000. After two clock pulses, the register contains ________.
A.10111000
B.10110111
C.11110000
D.11111100
Answer:D
By adding recirculating lines to a 4-bit parallel-in, serial-out shift

register, it becomes a ________, ________, and ________-out register.
A.parallel-in, serial, parallel
B.serial-in, parallel, serial
C.series-parallel-in, series, parallel
D.bidirectional in, parallel, series
Answer:A
What type of register would have a complete binary number shifted in one
bit at a time and have all the stored bits shifted out one at a time?
A.parallel-in, parallel-out
B.parallel-in, serial-out
C.serial-in, parallel-out
D.serial-in, serial-out
Answer:C
When an 8-bit serial in/serial out shift register is used for a 20 s

time delay, the clock frequency is ________.
A.40 kHz
B.50 kHz
C.400 kHz
D.500 kHz
Answer:C
Ring shift and Johnson counters are:

A.synchronous counters
B.aynchronous counters
C.true binary counters
D.synchronous and true binary counters
Answer:A
What is the difference between a shift-right register and a shift-left

register?
B.the direction of the shift
Answer:B
What is a transceiver circuit?

A.a buffer that transfers data from input to output
B.a buffer that transfers data from output to input
C.a buffer that can operate in both directions
Answer:C
A 74HC195 4-bit parallel access shift register can be used for ________.
A.serial in/serial out operation
B.serial in/parallel out operation
C.parallel in/serial out operation
D.all of the above
Answer:D
Which type of device may be used to interface a parallel data format with
external equipment's serial format?
A.key matrix
B.UART
C.memory chip
D.series in, parallel out
Answer:B
What is the function of a buffer circuit?

A.to provide an output that is inverted from that on the input
B.to provide an output that is equal to its input
C.to clean up the input
D.to clean up the output
Answer:B
What is the preset condition for a ring shift counter?

A.all FFs set to 1
B.all FFs cleared to 0
C.a single 0, the rest 1
D.a single 1, the rest 0
Answer:D
Which is not characteristic of a shift register?

A.Serial in/parallel in
B.Serial in/parallel out
C.Parallel in/serial out
D.Parallel in/parallel out
Answer:A
To keep output data accurate, 4-bit series-in, parallel-out shift

registers employ a ________.
A.divide-by-4 clock pulse
B.sequence generator
C.strobe line
D.multiplexer
Answer:C
With a 50 kHz clock frequency, six bits can be serially entered into a
shift register in ________.
A.12s
B.120s
C.12ms
D.120ms
Answer:B
Another way to connect devices to a shared data bus is to use a ________.

A.circulating gate
B.transceiver
C.bidirectional encoder
D.strobed latch
Answer:B
To serially shift a nibble (four bits) of data into a shift register,

there must be ________.
A.one clock pulse
B.four clock pulses
C.eight clock pulses
D.one clock pulse for each 1 in the data
Answer:B
Computers operate on data internally in a ________ format.

A.tristate
B.universal
C.parallel
D.serial
Answer:C
or bit patterns?
A.1
B.2
C.4
D.8
Answer:D
In which sequential circuit output depends on present state and inputs.

a.Moore model
b.Mealy model
c.In both cases
d.Neither a nor b
Answer:b
how many sequential model are available?

a.Moore model
b.Mealy model
c.both
d.Neither a nor b
Answer:c
stata table is a representation of describing the operation of a which

circuit.
a.Synchronous circuit
b.Asynchronous circuit
c.In both cases
d.Neither a nor b
Answer:a
which sequential circuit has required more delay to generate output ?.

a.Moore model
b.Mealy model
c.In both cases
d.Neither a nor b
Answer:b
In a state diagram the circuit is represented by a --------

a.graph
b.chart
c.block
d.table
Answer:a
In which sequential circuit output can be unstable.

a.Moore model
b.Mealy model
c.In both cases
d.Neither a nor b
Answer:b
In which sequential circuit required more hardware to generate output .

A.Moore model
B.Mealy model
C.In both cases
D.Neither a nor b
Answer:A
which sequential circuit is easy to design .

a.Moore model
b.Mealy model
c.In both cases
d.Neither a nor b
Answer:a
when sequence generator move into the unused state and not come back into
used state so this condition known as
a.Race condition
b.Toggle condition
c.Race around condition
d.Lockout condition
Answer:d
Those state which are not available in sequence known as

a.Unwanted state
b.Unavailable state
c.Unused state
d.Used state
Answer:c
Those state which are available in sequence known as

a.wanted state
b.available state
c.Unused state
d.Used state
Answer:d
in which method sequence come back into used state.

a.Without bushing
b.With bushing
c.both
d.neither a nor b
Answer:b
((MARKS)) (1/2/3...) 1
((QUESTION)) ASM is a-----------.
((OPTION_A)) chart
((OPTION_B)) graph
((OPTION_C)) table
((OPTION_D)) circuit
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) ASM contain how many basic blocks
((OPTION_A)) 1
((OPTION_B)) 2
((OPTION_C)) 3
((OPTION_D)) none
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Which type of boxes are available in ASM.
((OPTION_A)) state
((OPTION_B)) decision
((OPTION_C)) conditional
((OPTION_D)) all of them
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Which type of box it is in ASM.
((OPTION_A)) state
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Which type of box it is in ASM.
((OPTION_A)) state
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) This ASM represent which circuit diagram.
((OPTION_A)) mod 4 counter
((OPTION_B)) 2 bit up counter
((OPTION_C)) 2 bit down counter
((OPTION_D)) Mod 6 counter
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Which chart depends on clock?
((OPTION_A)) ASM chart
((OPTION_B)) Flow chart
((OPTION_C)) Both
((OPTION_D)) None of above
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 2
((QUESTION)) This ASM represent which circuit diagram.
00
01
0 1
M
10
0 1
M
11
((OPTION_A)) Mod 4 counter
((OPTION_B)) 2 bit up counter
((OPTION_C)) 2 bit up/down counter
((OPTION_D)) Mod 6 counter
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) ASM chart resembles with
((OPTION_A)) Map
((OPTION_B)) Flow chart
((OPTION_C)) Data
((OPTION_D)) Operation
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) ASM stands for
((OPTION_A)) algorithmic state machine
((OPTION_B)) algorithmic solid machine
((OPTION_C)) arithmetic state machine
((OPTION_D)) arithmetic solid machine
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Control sequence state is indicated by
((OPTION_A)) State box
((OPTION_B)) Decision box
((OPTION_C)) Conditional box
((OPTION_D)) Data box
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) ASM chart is composed of
((OPTION_A)) 2 Elements
((OPTION_B)) 3 Elements
((OPTION_C)) 4 Elements
((OPTION_D)) 5 Elements
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
Which sequential circuits generate the feedback path due to the cross-
coupled connection from output of one gate to the input of another gate?
A. Synchronous
B. Asynchronous
C. Both
ANSWER: B
What is/are the crucial function/s of memory elements used in the

sequential circuits?
A. Storage of binary information
B. Specify the state of sequential
C. Both a & b
ANSWER: C
How are the sequential circuits specified in terms of time sequence?

A. By Inputs
B. By Outputs
C. By Internal states
D. All of the above
ANSWER: D
The behaviour of synchronous sequential circuit can be predicted by

defining the signals at ______.
A. discrete instants of time
B. continuous instants of time
C. sampling instants of time
D. at any instant of time
ANSWER: A
Which memory elements are utilized in an asynchronous & clocked

sequential circuits respectively?
A. Time- delay devices & registers
B. Time- delay devices & flip-flops
C. Time- delay devices & counters
D. Time-delay devices & latches
ANSWER: B
Why do the D-flipflops receives its designation or nomenclature as 'Data

Flipflops' ?
A. Due to its capability to receive data from fliflop
B. Due to its capability to store data in flipflop
C. Due to its capability to transfer the data into flipflop
D. All of the above
ANSWER: C
The characteristic equation of D-flipflop implies that _____.

A. the next state is dependent on previous state
B. the next state is dependent on present state
C. the next state is independent of previous state
D. the next state is independent of present state
ANSWER: D
Which circuit is generated from D-flipflop due to addition of an inverter

by causing reduction in the number of inputs?
A. Gated JK- latch
B. Gated SR- latch
C. Gated T- latch
D. Gated D- latch
ANSWER: D
What is the bit storage binary information capacity of any flipflop?

A. 1 bit
B. 2 bits
C. 16 bits
D. infinite bits
ANSWER: A
What is/are the directional mode/s of shifting the binary information in

a shift register?
A. Up-Down
B. Left - Right
C. Front - Back
D. All of the above
ANSWER: B
Which time interval specify the shifting of overall contents of the shift
registers?
A. Bit time
B. Shift time
C. Word time
D. Code time
ANSWER: C
Which type of shift register is renowned as 'bit bucket brigade circuit'

by presenting the input data and applying the clock pulse for the
movement of bits across the storage elements?
A. Serial In - Serial Out (SISO)
B. Serial In - Parallel Out (SIPO)
C. Parallel In - Parallel Out (PIPO)
D. Parallel In - Serial Out (PISO)
ANSWER: A
Which kind of dynamic shift register has a provision of repeating the

code continuously by connecting its output back to the serial input?
A. PIPO Register
B. SISO Register
C. Multi-mode Shift Register
D. Reintrant Shift Register
ANSWER: D
A counter is fundamentally a _________ sequential circuit that proceeds

through the predetermined sequence of states only when input pulses are
applied to it.
A. register
B. memory unit
C. flipflop
D. arithmatic logic unit
ANSWER: A
Which property of unit distance counters has the potential to overcome

the consequences of multi-bit change flashing that arises in almost all
conventional binary and decimal counters?
A. one bit change per unit change
B. two bits change per unit change
C. three bits change per unit change
D. four bits change per unit change
ANSWER: A
What contributes to the triggering of clock pulse inputs for all the
flipflops excluding the first flipflop in a ripple counter?
A. Incoming Pulses
B. Output Transistion
C. Double Clock Pulses
D. All of the above
ANSWER: B
What is the required relationship between number of flipflops and the

timing signals in Johnson Counter?
A. No. of flipflops = 1/2 x No. of timing signals
B. No. of flipflops = 2/3 x No. of timings signals
C. No. of flipflops = 3/4 x No. of timing signals
D. No. of flipflops = 4 x No. of timing signals
ANSWER: A
In moore model outputs are functions of

A. present state
B. input state
C. next state
D. both a and b
ANSWER: A
Memory elements in clocked sequential circuits are called

A. latches
B. flipflop
C. signals
D. gates
ANSWER: B
Design procedure of sequential circuit is based on

A. 7steps
B. 8steps
C. 9steps
D. 10steps
ANSWER: C
In a digital counter circuit feedback loop is introduced to

A. Improve distortion
B. Improve stability
C. Reduce the number of input pulses to reset the counter
D. Asynchronous input and output pulses
ANSWER: C

bottles automatically. In such a counter what will be the number of flip-
flops required ?
A. 3
B. 12
C. 6
D. 8
ANSWER: C
A pulse train can be delayed by a finite number of clock periods using

A. A serial-in serial-out shift register
B. A serial-in parallel-out shift register
C. Both (a) and (b)
D. A parallel-in parallel-out shift register
ANSWER: D
How many illegitimate states has synchronous mod-6 counter ?
A. 3
B. 2
C. 1
D. 6
ANSWER: A
A 2 bit binary multiplier can be implemented using

A. 2 input ANDs only
B. 2 input XORs and 4 input AND gates only
C. 2 input NORs and one XNOR gate
D. NOR gates and shift registers
ANSWER: B
A ring counter is same as

A. up-down counter
B. parallel-counter
C. shift register
D. Ripple carry Counter
ANSWER: C
The dynamic hazard problem occurs in

A. Combinational circuit alone
B. Sequential circuit only
C. Both (a) and (b)
D. None of these
ANSWER: C
The clock signals are used in sequential logic circuits to

A. Tell the time of the day
B. Tell how much time has elapsed since the system was turned on
C. Carry parllel data signals
D. Synchronize events in various parts of system
ANSWER: D
74L5138 chip functions as

A. Decoder/demultiplexer
B. Encoder
C. Multiplexer
D. Demultiplexer
ANSWER: A
A sequential circuit outputs a ONE when an even number (> 0) of one's are
input; otherwise the output is ZERO. The minimum number of states
required is
A. 0
B. 1
C. 2
D. None of these
ANSWER: C
A shift register can be used for

A. Digital delay line
B. Serial to parallel conversion
C. Parallel to serial conversion
D. All of these
ANSWER: D
Popular application of flip-flop are

A. Transfer register
B. Shift registers
C. Counters
D. All of these
ANSWER: D
For which of the following flip-flops, the output is clearly defined for
all combinations of two inputs ?
A. Q type flip-flop
B. R-S flip-lop
C. J-K flip-lop
D. D flip-flop
ANSWER: C
When a large number of analog signals are to be converted an analog

multiplexer is used. In this case most suitable A.D. converter will be
A. Ripple carry counter type
B. Dual stop type
C. Forward counter type
D. Successive approximation type
ANSWER: D
To build a mod-19 counter the number of flip-flops required is

A. 3
B. 5
C. 7
D. 9
ANSWER: B
The astable multivibrator has

A. Two quasi stable states
B. Two stable states
C. One stable and one quasi-stable state
D. None of these
ANSWER: A
and ten numerals ?
A. 5
B. 6
C. 10
D. 48
ANSWER: B
The functional difference between S-R flip-flop and J-K flip-flop is that
J-K flip-flop
A. is faster than S-R flip-flop
B. Has a feed-back path
C. Accepts both inputs 1
D. Both (a) and (b)
ANSWER: C
In a positive edge triggered JK flip-flop, a low J and low K produces

A. No change
B. Low state
C. High state
D. None of these
ANSWER: A
A. JK flip-flop
B. D flip-flop
C. SR flip-flop
ANSWER: B
A 2 MHz signal is applied to the input of a J-K lip-lop which is

operating in the 'toggle' mode. The frequency of the signal at the output
will be
A. 1 MHz
B. 2 MHz
C. 6 MHz
D. 8 MHz
ANSWER: D
The master slave JK lip-flop is effectively a combination of

A. A SR flip-flop and a T flip-flop
B. An SR flip-lfop and a D flip-flop
C. A T flip-flop and a D flip-flop
D. Two D flip-flops
ANSWER: A
It is difficult to design asynhronous sequential circuit because

A. External clock is to be provided
B. It is more complex
C. Both (a) and (b)
D. Generally they involve stability problem
ANSWER: D
A stable multivibrator is used as

A. Comparator circuit
B. Demultiplexer
C. Frequency to voltage converter
D. Voltage to frequency converter
ANSWER: A
How many flip-flop are needed to divide the input frequency by 64 ?

A. 2
B. 5
C. 6
D. 8
ANSWER: C
In a ripple counter using edge triggered JK flfp-flops, the pulse input

is applied to the
A. clock input of all flip-flops
B. clock input of one flip-flops
C. J and K inputs of all flip-flops
D. J and K inputs of one flip-flop
ANSWER: D
The number of clock pulses needed to shift one byte of data from input to
the output of a 4-bit shift register is
A. 10
B. 12
C. 16
D. 32
ANSWER: C
The main difference between JK and RS flip-flop is that
A. JK flip flop needs a clock pulse
B. There is a feedback in JK lip-lop
C. JK flip-flop accepts both inputs as 1
D. JK flip-flop is acronym of Junction cathode multivibrator
ANSWER: C

binary code ?
A. Encoder
B. Decoder
C. Multiplexer
D. Counter
ANSWER: A
The flip-flops which operate in synchronism with external clock pulses

are known as
A. Synchronous flip-flop
B. Asynchronous flip-flop
C. Either of the above
D. None of these
ANSWER: A
Which of the following flip-flop is free from race-around problem ?

A. Q flip-flop
B. T flip-flop
C. SR flip-flop
D. Master-slave JK flip-flop
ANSWER: D
If the input J is connected through K input of J-K, then flip-flop will

behave as a
A. D type flip-flop
B. T type flip-flop
C. S-R flip-flop
ANSWER: B
If a clock with time period 'T' is used with n stage shift register, then
output of final stage will be delayed by
A. nT sec
B. (n-1)T sec
C. n/T sec
D. (2n+1)T sec
ANSWER: B
Register is a
A. set of capacitor used to register input instructions in a digital
computer
B. set to paper tapes and cards put in a file
C. temporary storage unit within the CPU having dedicated or general
purpose use
D. part of the main memory
ANSWER: C
The number of flip-flops required in a decade counter is

A. 3
B. 4
C. 8
D. 10
ANSWER: B
Which of the following is asynchronous input of SR flip-flop

A. S
B. R
C. PRESET
D. CLOCK
ANSWER: C
Which of the following is synchronous input of SR flip-flop?

A. S
B. R
C. PRESET
D. CLOCK
ANSWER: D
On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2

= 1, and Q3 = 1. On the sixth clock pulse, the sequence is ________.
A.Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
B.Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0
C.Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1
D.Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1
Answer:C
What is a shift register that will accept a parallel input, or a

bidirectional serial load and internal shift features, called?
A.tristate
B.end around
C.universal
D.conversion
Answer:C
On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2

= 1, and Q3 = 0. On the fourth clock pulse, the sequence is ________.
A.Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1
B.Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0
C.Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
D.Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0
Answer:A

________.
A.1101
B.0111
C.0001
D.1110
Answer:B

________.
A.1101
B.0111
C.0001
D.1110
Answer:B
How can parallel data be taken out of a shift register simultaneously?
A.Use the Q output of the first FF.
B.Use the Q output of the last FF.
C.Tie all of the Q outputs together.
D.Use the Q output of each FF.
Answer:D
What is meant by parallel load of a shift register?

A.All FFs are preset with data.
B.Each FF is loaded with data, one at a time.
Answer:A
What does the output enable do on the 74395A chip?

A.It determines when data can be loaded.
B.It forces all outputs to go HIGH.
C.It forces all outputs to go LOW.
D.It activates the three-state buffer.
Answer:D

A.clearing all the flip-flops
B.presetting one flip-flop and clearing all others
C.clearing one flip-flop and presetting all others
D.presetting all the flip-flops
Answer:B
or bit patterns?
A.2
B.6
C.12
D.24
Answer:C
A modulus-12 ring counter requires a minimum of ________.

A.10 flip-flops
B.12 flip-flops
C.6 flip-flops
D.2 flip-flops
Answer:B
The group of bits 11001 is serially shifted (right-most bit first) into a
5-bit parallel output shift register with an initial state 01110. After
three clock pulses, the register contains ________.
A.01110
B.00001
C.00101
D.00110
Answer:C
Assume that a 4-bit serial in/serial out shift register is initially

clear. We wish to store the nibble 1100. What will be the 4-bit pattern
after the second clock pulse? (Right-most bit first.)
A.1100
B.0011
C.0000
D.1111
Answer:C
A serial in/parallel out, 4-bit shift register initially contains all 1s.
The data nibble 0111 is waiting to enter. After four clock pulses, the
register contains ________.
A.0000
B.1111
C.0111
D.1000
Answer:C
A sequence of equally spaced timing pulses may be easily generated by

which type of counter circuit?
A.ring shift
B.clock
C.Johnson
Answer:A
An 8-bit serial in/serial out shift register is used with a clock

frequency of 2 MHz to achieve a time delay (td) of ________.
A. 16s
B. 8s
C. 4s
D. 2s
Answer:C
The bit sequence 10011100 is serially entered (right-most bit first) into
an 8-bit parallel out shift register that is initially clear. What are
the Q outputs after four clock pulses?
A.10011100
B.11000000
C.00001100
D.11110000
Answer:B
If an 8-bit ring counter has an initial state 10111110, what is the state
after the fourth clock pulse?
A.11101011
B.00010111
C.11110000
D.00000000
Answer:D

Answer:C
A.right, one
B.right, two
C.left, one
D.left, three
Answer:A

bit shift register?
A.2
B.3
C.4
D.5
Answer:D
How is a strobe signal used when serially loading a shift register?

A.to turn the register on and off
B.to control the number of clocks
C.to determine which output Qs are used
D.to determine the FFs that will be used
Answer:B
What are the three output conditions of a three-state buffer?

A.HIGH, LOW, float
B.1, 0, float
C.both of the above
D.neither of the above
Answer:C
The primary purpose of a three-state buffer is usually:

A.to provide isolation between the input device and the data bus
B.to provide the sink or source current required by any device connected
to its output without loading down the output device
C.temporary data storage
D.to control data flow
Answer:A
What is the difference between a ring shift counter and a Johnson shift
counter?
B.A ring is faster.
C.The feedback is reversed.
D.The Johnson is faster.
Answer:C
What is a recirculating register?

A.serial out connected to serial in
B.all Q outputs connected together
C.a register that can be used over again
Answer:A
When is it important to use a three-state buffer?

A.when two or more outputs are connected to the same input
B.when all outputs are normally HIGH
C.when all outputs are normally LOW
D.when two or more outputs are connected to two or more inputs
Answer:A

Answer:C
A.right, one
B.right, two
C.left, one
D.left, three
Answer:C
bit shift register?
A.2
B.3
C.4
D.5
Answer:D

input is LOW. The nibble 0111 is waiting to be entered on the serial
data-input line. After two clock pulses, the shift register is storing
________.
A.1110
B.0111
C.1000
D.1001
Answer:D
In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and

D3 = 0. After three clock pulses, the data outputs are ________.
A.1110
B.0001
C.1100
D.1000
Answer:B
The group of bits 10110111 is serially shifted (right-most bit first)

into an 8-bit parallel output shift register with an initial state
11110000. After two clock pulses, the register contains ________.
A.10111000
B.10110111
C.11110000
D.11111100
Answer:D
By adding recirculating lines to a 4-bit parallel-in, serial-out shift

register, it becomes a ________, ________, and ________-out register.
A.parallel-in, serial, parallel
B.serial-in, parallel, serial
C.series-parallel-in, series, parallel
D.bidirectional in, parallel, series
Answer:A
What type of register would have a complete binary number shifted in one
bit at a time and have all the stored bits shifted out one at a time?
A.parallel-in, parallel-out
B.parallel-in, serial-out
C.serial-in, parallel-out
D.serial-in, serial-out
Answer:C
When an 8-bit serial in/serial out shift register is used for a 20 s

time delay, the clock frequency is ________.
A.40 kHz
B.50 kHz
C.400 kHz
D.500 kHz
Answer:C

A.synchronous counters
B.aynchronous counters
C.true binary counters
D.synchronous and true binary counters
Answer:A
What is the difference between a shift-right register and a shift-left

register?
B.the direction of the shift
Answer:B
What is a transceiver circuit?

A.a buffer that transfers data from input to output
B.a buffer that transfers data from output to input
C.a buffer that can operate in both directions
Answer:C
A 74HC195 4-bit parallel access shift register can be used for ________.
A.serial in/serial out operation
B.serial in/parallel out operation
C.parallel in/serial out operation
D.all of the above
Answer:D
Which type of device may be used to interface a parallel data format with
external equipment's serial format?
A.key matrix
B.UART
C.memory chip
D.series in, parallel out
Answer:B
What is the function of a buffer circuit?

A.to provide an output that is inverted from that on the input
B.to provide an output that is equal to its input
C.to clean up the input
D.to clean up the output
Answer:B
What is the preset condition for a ring shift counter?

A.all FFs set to 1
B.all FFs cleared to 0
C.a single 0, the rest 1
D.a single 1, the rest 0
Answer:D
Which is not characteristic of a shift register?

A.Serial in/parallel in
B.Serial in/parallel out
C.Parallel in/serial out
D.Parallel in/parallel out
Answer:A
To keep output data accurate, 4-bit series-in, parallel-out shift

registers employ a ________.
A.divide-by-4 clock pulse
B.sequence generator
C.strobe line
D.multiplexer
Answer:C
With a 50 kHz clock frequency, six bits can be serially entered into a
shift register in ________.
A.12s
B.120s
C.12ms
D.120ms
Answer:B
Another way to connect devices to a shared data bus is to use a ________.

A.circulating gate
B.transceiver
C.bidirectional encoder
D.strobed latch
Answer:B
To serially shift a nibble (four bits) of data into a shift register,

there must be ________.
A.one clock pulse
B.four clock pulses
C.eight clock pulses
D.one clock pulse for each 1 in the data
Answer:B
Computers operate on data internally in a ________ format.

A.tristate
B.universal
C.parallel
D.serial
Answer:C
or bit patterns?
A.1
B.2
C.4
D.8
Answer:D
In which sequential circuit output depends on present state and inputs.

a.Moore model
b.Mealy model
c.In both cases
d.Neither a nor b
Answer:b
how many sequential model are available?

a.Moore model
b.Mealy model
c.both
d.Neither a nor b
Answer:c
stata table is a representation of describing the operation of a which

circuit.
a.Synchronous circuit
b.Asynchronous circuit
c.In both cases
d.Neither a nor b
Answer:a
which sequential circuit has required more delay to generate output ?.

a.Moore model
b.Mealy model
c.In both cases
d.Neither a nor b
Answer:b
In a state diagram the circuit is represented by a --------

a.graph
b.chart
c.block
d.table
Answer:a
In which sequential circuit output can be unstable.

a.Moore model
b.Mealy model
c.In both cases
d.Neither a nor b
Answer:b
In which sequential circuit required more hardware to generate output .

A.Moore model
B.Mealy model
C.In both cases
D.Neither a nor b
Answer:A
which sequential circuit is easy to design .

a.Moore model
b.Mealy model
c.In both cases
d.Neither a nor b
Answer:a
when sequence generator move into the unused state and not come back into
used state so this condition known as
a.Race condition
b.Toggle condition
c.Race around condition
d.Lockout condition
Answer:d
Those state which are not available in sequence known as

a.Unwanted state
b.Unavailable state
c.Unused state
d.Used state
Answer:c
Those state which are available in sequence known as

a.wanted state
b.available state
c.Unused state
d.Used state
Answer:d
in which method sequence come back into used state.
a.Without bushing
b.With bushing
c.both
d.neither a nor b
Answer:b
((MARKS)) (1/2/3...) 1
((QUESTION)) Which type of PLD should be used to program basic logic functions?
((OPTION_A)) SLD
((OPTION_B)) CPLD
((OPTION_C)) PAL
((OPTION_D)) PLA
((CORRECT_CHOICE))
C
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) PLA stands for
((OPTION_A)) Programmable Logic Array
((OPTION_B)) Programming Logic Algorithm
((OPTION_C)) Programmable Logic Analysis
((OPTION_D)) Process Localization Algorithm
((CORRECT_CHOICE))
A
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) PLA circuit falls in which circuit category
((OPTION_A)) Sequential Logic Circuit.
((OPTION_B)) Combinational Logic Circuit
((OPTION_C)) Both (1) and (2)
((OPTION_D)) Neither (1) nor (2)

((CORRECT_CHOICE))
B
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Which type of PLD should be used to program basic logic functions?
((OPTION_A)) CPLD
((OPTION_B)) PAL
((OPTION_C)) PLA
((OPTION_D)) PROM
((CORRECT_CHOICE))
B
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Programmable logic array is a
((OPTION_A)) Two Level OR-OR Device
((OPTION_B)) Two Level AND-AND Device
((OPTION_C)) Two Level OR-AND Device
((OPTION_D)) Two Level AND-OR Device
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) PLA is programmed to realize any
((OPTION_A)) Ex-OR logic expression

((OPTION_B)) Product of sum logic expression
((OPTION_C)) Sum of Product logic expression
((OPTION_D)) None of the above
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Fuses in Programmable logic array are
((OPTION_A)) Volatile memory that are programmed to make a connection only
((OPTION_B)) Volatile memory that are programmed to make a connection or not
((OPTION_C)) Non-volatile memory that are programmed to make a connection or

not
((OPTION_D)) Non-volatile memory that are not programmed to make a connection
only
((CORRECT_CHOICE))
C
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) The complex programmable logic device (CPLD) contains several
PLD blocks and:
((OPTION_A)) field-programmable switches
((OPTION_B)) A global interconnection matrix
((OPTION_C)) AND/OR arrays

((OPTION_D)) a language compiler
((CORRECT_CHOICE))
B
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Once a PAL has been programmed:
((OPTION_A)) Its outputs are only active HIGHs
((OPTION_B)) It cannot be reprogrammed
((OPTION_C)) Its outputs are only active LOWs
((OPTION_D)) Its logic capacity is lost
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) PLD Stands for
((OPTION_A)) Programmable Logic Device
((OPTION_B)) Process Location Derive
((OPTION_C)) Performance Logic Device
((OPTION_D)) Programming Local Derive
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Which among the following statement/s is/are not an/the advantage/s
of Programmable Logic Devices(PLDs)?
((OPTION_A)) Short design cycle
((OPTION_B)) Increased space requirement
((OPTION_C)) Increased switching speed

((OPTION_D)) All of the above
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) How many logic gates can be implemented in the circuit by

complex programmable logic devices(CPLDs)?
((OPTION_A)) 10
((OPTION_B)) 100
((OPTION_C)) 1000
((OPTION_D)) 10000
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) Which among the following are used in programming array logic
(PAL) for reducing the loading on inputs?
((OPTION_A)) Input buffers
((OPTION_B)) Output buffers
((OPTION_C)) OR matrix
((OPTION_D)) AND matrix
(A/B/C/D)
((EXPLANATION))
(OPTIONAL)
((MARKS)) (1/2/3...) 1
((QUESTION)) A combinational PLD with a fixed AND array and a programmable
OR array is called a
((OPTION_A)) PLD
((OPTION_B)) PROM
((OPTION_C)) PAL
((OPTION_D)) PLA
(A/B/C/D)
((EXPLANATION)) ROM – Fixed AND array and fixed OR array

(OPTIONAL) PROM – Fixed AND array and Programmable OR array
PAL – Programmable AND array and fixed OR array
PLA – Programmable AND array and programmable OR array
State box without decision and conditional box is
A. asm block
B. defined block
C. simple block
D. both a and b
ANSWER: C
ASM chart resembles to

A. map
B. data
C. flowchart
D. operation
ANSWER: C
Control sequence's state is indicated by

A. state box
B. decision box
C. data box
D. conditional box
ANSWER: A
Control information gives knowledge about the

A. command signals
B. data
C. metadata
D. operation
ANSWER: A
If system is performing no function then it is in

A. clear state
B. initial state
C. enable state
D. reset state
ANSWER: B
ASM chart has

A. 4 exits
B. 3 exits
C. 2 exits
D. any no exits
ANSWER: D
ASM chart is composed of

A. 2 elements
B. 3 elements
C. 4 elements
D. 5 elements
ANSWER: B
Second level of design with mux has register holding

A. present state
B. input
C. next state
D. output
ANSWER: A
All inputs are synchronized with

A. master clock
B. clock pulses
C. counter
D. latch
ANSWER: B
In method of one flipflop per state no of flip-flops set to 1 is/are

A. 1
B. 2
C. 3
D. 4
ANSWER: A
State box of ASM chart represents

A. condition
B. clock
C. state
D. pulse
ANSWER: C
If excitation is not to be used then flipflop used is

A. JK
B. RS
C. T
D. D
ANSWER: D
One that is not present in list of state table is

A. present state
B. input
C. next state
D. previous state
ANSWER: D
In method of one flipflop per state all flip-flops except one are set to
A. 1
B. 0
C. x
D. y
ANSWER: B
Binary information is classified into

A. data
B. control information
C. metadata
D. both a and b
ANSWER: D
Difference in conventional flowchart and asm chart lies in

A. master clock
B. flow
C. time relationship
D. clock
ANSWER: C
Logic design consists of

A. 1 part
B. 2 parts
C. 3 parts
D. 4 parts
ANSWER: B
Design with multiplexers, is method consisting of
A. 1 level
B. 2 levels
C. 3 levels
D. 4 levels
ANSWER: C
Sequential circuit is also called

A. state
B. encoder
C. flipflop
D. state machine
ANSWER: D
ASM chart takes entire block as

A. 1 unit
B. 2 unit
C. 3 unit
D. 4 unit
ANSWER: A
ASM chart is very same to

A. state diagram
B. flowchart
C. data box
D. operation
ANSWER: A
To continue count E must be

enabled
reset
stopped
cleared
ANSWER: D
At E=1 register R will be

enabled
reset
stopped
cleared
ANSWER: D
Rounded corners of conditional box differentiate it from

A. state box
B. decision box
C. data box
D. conditional box
ANSWER: A
For going to next state flipflop is set to

1
0
y
dont cares
ANSWER: A
Control implementation method is

A. practical
B. impractical
C. enabled
D. cleared
ANSWER: B
Single flipflop can be cleared to

A. 1
B. 0
C. x
D. y
ANSWER: B
States not used are treated as

1
0
y
dont cares
ANSWER: D
First level of design with mux determines registers'

A. present state
B. input
C. next state
D. output
ANSWER: C
No of inputs and outputs in a state table are

A. equal
B. same
C. unequal
D. not present
ANSWER: A
One that is a digital component is

A. latch
B. encoder
C. flipflop
D. processor
ANSWER: B
Third level of design with mux consists of

A. demux
B. mux
C. encoder
D. decoder
ANSWER: D
ASM stands for

A. algorithmic state machine
B. algorithmic solid machine
C. arithmetic state machine
D. arithmetic solid machine
ANSWER: A
In ASM design flip-flops are considered to be

A. negative edge triggered
B. negative level triggered
C. positive edge triggered
D. negative level triggered
ANSWER: C
ASM chart has

A. 4 entrances
B. 3 entrances
C. 2 entrances
D. 1 entrances
ANSWER: D
Discrete element of information is

A. data
B. control information
C. metadata
D. operation
ANSWER: A
To specify sequence of algorithm method used is

A. map
B. data
C. flowchart
D. operation
ANSWER: C
State box is a shape of

A. square
B. rectangle
C. rhombus
D. pentagon
ANSWER: B
Conditional box is of shape of

A. square
B. rectangle
C. oval
D. pentagon
ANSWER: C
One that is not a digital component is

A. decoder
B. encoder
C. flipflop
D. mux
ANSWER: C
With every clock pulse count is

A. decremented
B. stopped
C. incremented
D. enabled
ANSWER: C
Signal that starts operation is indicated by

A. INITIAL
B. GO
C. BEGIN
D. START
ANSWER: D
Box that tells effect of input on control subsystem is called

A. state box
B. decision box
C. data box
D. conditional box
ANSWER: B
To satisfies any two condition gate used is

A. OR
B. NOT
C. NAND
D. AND
ANSWER: C
Timings for registers are controlled by

A. master clock
B. slave clock
C. serial clock
D. parallel clock
ANSWER: A
One that is not element of ASM chart is

A. state box
B. decision box
C. data box
D. conditional box
ANSWER: C
One that is not a type of register

A. storage
B. shift register
C. counter
D. latch
ANSWER: D
Large maps are used if flip-flops and inputs become greater than
A. 2
B. 3
C. 5
D. 8
ANSWER: C
Change of state in ASM chart is performed in

A. control logic
B. slave clock
C. metadata
D. processor
ANSWER: A
Sequential operations in digital system are described by

A. map
B. ASM chart
C. flowchart
D. graph
ANSWER: B
ASM is a-----------.
a.chart
b.graph
c.table
d.circuit
Answer:a
ASM contain how many basic contain.

a.1
b.2
c.3
d.none
Answer:c
Which type of boxes are available in ASM.

a.state
b.decision
c.conditional
d.all of them
Answer:d
Which type of boxe it is in ASM.

a.state
b.decision
c.conditional
d.all of them
Answer:c
which chart depends on clock?

a.ASM chart
b.Flow chart
c.Both
d.None of above
Answer:a
Which type of PLD should be used to program basic logic functions?

A. PLA
B. PAL
C. CPLD
D. SLD
ANSWER: B
The content of a simple programmable logic device (PLD) consists of:

A. fuse-link arrays
B. thousands of basic logic gates
C. advanced sequential logic functions
D. thousands of basic logic gates and advanced sequential logic functions
ANSWER: D
Once a PAL has been programmed:

A. it cannot be reprogrammed.
B. its outputs are only active HIGHs
C. its outputs are only active LOWs
D. its logic capacity is lost
ANSWER: A
The complex programmable logic device (CPLD) contains several PLD blocks
and:
A. field-programmable switches
B. AND/OR arrays
C. a global interconnection matrix
D. a language compiler
ANSWER: C
PLAs, CPLDs, and FPGAs are all which type of device?

A. SLD
B. PLD
C. EPROM
D. SRAM
ANSWER: B
PAL stands for

A. portable array logic
B. programmable advanced logic
C. programmable array logic
D. portable advanced logic
ANSWER: C
The difference between a PLA and a PAL is:

A. the PLA has a programmable OR plane and a programmable AND plane,
while the PAL only has a programmable AND plane
B. the PAL has a programmable OR plane and a programmable AND plane,
while the PLA only has a programmable AND plane
C. the PAL has more possible product terms than the PLA
D. PALs and PLAs are the same thing.
ANSWER: A
The OR array in a PAL is ________.

A. fixed
B. programmable
C. nonexistent; there is no OR array in a PAL
D. floating
ANSWER: A
Simple Programmable Logic Devices (SPLDs) are also regarded as

_____________.
A. Programmable Array Logic (PAL)
B. Generic Array Logic (GAL)
C. Programmable Logic Array (PLA)
D. All of the above
ANSWER: D
Which among the following is/are not suitable for in-system programming?
A. EPROM
B. EEPROM
C. Flash
D. All of the above
ANSWER: A
Which among the following are used in programming array logic (PAL) for
reducing the loading on inputs?
A. Input buffers
B. Output buffers
C. OR matrix
D. AND matrix
ANSWER: A
PROM stands for

A. Permanent Read Only Memory
B. Portable Read Only Memory
C. Programmable Read Only Memory
D. Plugin Read Only Memory
ANSWER: C
PLD stands for

A. portable large device
B. portable logic device
C. programmable large device
D. programmable logic device
ANSWER: D
A binary parallel adder produces arithmetic sum in

A. serial
B. parallel
C. sequence
D. both a and b
ANSWER: B
ROM is a
A. Non volatile memory
B. secondary memory
C. volatile memory
D. small memory
ANSWER: A
Rom can be programmed in

A. 2 ways
B. 3 ways
C. 4 ways
D. 5 ways
ANSWER: A
If two numbers are not equal then binary variable will be

A. 0
B. 1
C. a
D. b
ANSWER: A
In a ROM each bit combination input variable is called

A. cell
B. block
C. Address
D. memory
ANSWER: C
The difference between a PLA and a PAL is:
A. The PLA has a programmable OR plane and a programmable AND plane,
while the PAL only has a programmable AND plane.
B. The PAL has a programmable OR plane and a programmable AND plane,
while the PLA only has a programmable AND plane.
C. The PAL has more possible product terms than the PLA.
D. PALs and PLAs are the same thing.
Answer:A
PALs tend to execute ________ logic.

A. SAP
B. SOP
C. PLA
D. SPD
Answer:B
A GAL is essentially a ________.

A. non-reprogrammable PAL
B. PAL that is programmed only by the manufacturer
C. very large PAL
D. reprogrammable PAL
Answer:D
Each programmable array logic (PAL) gate product is applied to an OR gate

and, if combinational logic is desired, the product is ORed and then:
A.the polarity fuse is restored
B.sent to an inverter for output
C.sent immediately to an output pin
D.passed to the AND function for output
Answer:B
________ are used at the inputs of PAL/GAL devices in order to prevent
input loading from a large number of AND gates.
A. Simplified AND gates
B. Fuses
C. Buffers
D. Latches
Answer:C
What is another name for digital circuitry called sequential logic?

A. logic macrocell
B. logic array
C. flip-flop memory circuitry
D. inverter
Answer:C
The final step in the device programming sequence is ________.

A. compiling
B. downloading
C. simulation
D. synthesis
Answer:B
A circuit that implements a combinational logic function by storing a

list of output values that correspond to all possible input combinations
is a(n) ________.
A. output logic macrocell
B. look-up table
C. parallel logic expander
D. logic element
Answer:B
By adding an OR gate to a simple programmable logic device (SPLD) the

foundation for a(n) ________ is made possible.
A. PAL
B. PLA
C. CPLD
D. EEPROM
Answer:A
A PAL16L8 has:
A. 10 inputs and 8 outputs.
B. 8 inputs and 8 outputs.
C. 16 inputs and 16 outputs.
D. 16 inputs and 8 outputs.
Answer:A
The macrocells in a PAL/GAL are located ________.

A. after the programmable AND arrays
B. ahead of the programmable AND arrays
C. at the input terminals
D. at the output terminals
Answer:A
The content of a simple programmable logic device (PLD) consists of:

A. fuse-link arrays
B. thousands of basic logic gates
C. advanced sequential logic functions
D. thousands of basic logic gates and advanced sequential logic functions
Answer:D
What does a dot mean when placed on a PLD circuit diagram?
A. A point that is programmable
B. A point that cannot change
C. An intersection of logic blocks
D. An input or output point
Answer:B
Which of the following is true?

A. Altera uses PAL architecture and Xilinx uses PLA architecture.
B. Altera uses PLA architecture and Xilinx uses PAL architecture.
C. Altera and Xilinx both use PAL architecture.
D. Altera and Xilinx both use PLA architecture.
Answer:A
Which is not a type of PLD?

A. SPLD
B. HPLD
C. CPLD
D. FPGA
Answer:B
Product terms are the outputs of which type of gate within a PLD array?
A. OR
B. XOR
C. AND
D. flip-flop
Answer:C
College Code: 4043
College Name: Sinhgad Academy of Engineering, Pune
Class: SEComputer:
Subject: Digital Electronics and Logic Design
Sr.No Unit No. Question Option A

1 1 How many full adders are required to construct an m-bit parallel
m/2 adder ?
2 1 Which of the following statements accurately represents the Boolean
two BEST
algebra
methods
and Karnaugh
of logic c
3 1 Which gate is best used as a basic comparator? NOR
4 1 The digital multiplexer is basically a combination logic circuit
AND-AND
to perform the operation
5 1 The output of a ____circuit at any instant of time is dependent
Combinational
only on the inputs present a
6 1 Two bit comparator is------circuit. Combinational
7 1 The decoder circuit does not have the --input. Select
8 1 How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? 1
9 1 How many data select lines are required for selecting eight inputs? 1
10 1 The carry propagation can be expressed as ________. Cp =((A))B
11 1 When adding an even parity bit to the code 110010, the result 1110010
is
12 1 What is the function of an enable input on a multiplexer chip?
To apply Vcc(+5V)
13 1 binary code that progresses such that only one bit changesnine's-complement
between two successive
code codes
14 1 The full adder adds the Kth bits of two numbers to the difference of the previous bits
15 1 The Ex-NOR is sometimes called the ________. parity gate
16 1 Gray code is Reflective Code
17 1 The number of full and half-adders required to add 16-bit8numbers
half-adders,
is 8 full-adders
18 1 The function of a multiplexer is to decode information
19 1 Which of the following circuit can be used as parallel to serial
Multiplexer
converter ?
20 1 The IC 74138 is a Multiplexer
21 1 A 32:1 multiplexer has ----number of select lines. 2
22 1 Perform the followling addition in 8-4-2-1 BCD (48) + (58). 0001 0000 0010
23 1 The gates required to build a half adder are EX-OR gate and OR gate
24 1 The number of inputs and outputs in a full adder are 2 and 1
25 1 IC 74153 is a 4:1 mux
26 1 A decoder can be used as a demultiplexer by ________ tying all enable pins LOW
27 1 An encoder in which the highest and lowest value input digitsTRUE are encoded simultaneously
28 1 Single looping in groups of three is a common K-map simplification
TRUE technique
29 1 The following combination is correct for an EVEN parity dataTRUE transmission system:data =
30 1 In binary subtrctor 0 - 1 = 1 WITH BORROW
31 1 The relation between n output lines and m select lines is 2m
32 1 Sum output of full adder is sum= a (b Exor c in )
33 1 A full subtractor can be constructed using --- half subtractor
1,1 and ---- OR gate
34 1 for 16:1 mux if S3 S2 S1 S0 = 1011 then Y = D10
35 1 DeMorgan’s first theorem shows the equivalence of OR gate and Exclusive OR gate
36 1 The simplest equation which implements the K-map in Figure X = 4-6AC+B is:
37 1 The binary value “1010110” is equivalent to decimal __________ 86
38 1 A standard POS form has __________ terms that have all Sumthe variables in the domain of
39 1 The AND Gate performs a logical __________function Addition
40 1 The output of an AND gate is one when ______ All of the inputs are one
41 1 The systematic reduction of logic circuits is accomplished usingby: Boolean algebra
42 1 A SOP expression is equal to ______________ All the variables in domain of ex
43 1 A non-standard POS is converted into a standard POS by A+A'=1
using the rule _____
44 1 The binary numbers A = 1100 and B = 1001 are applied A to>theB inputs
= 1, Aof< aBcomparator.
= 0, A < B =W
45 1 Two bit comparator is------circuit. combinational
46 1 Two 16:1 and one 2:1 multiplexer can be connected to form 16:1a Multiplexer
------
47 1 Perform the followling addition in 8-4-2-1 BC((D)) (48) +0001 (58) 0000 0010
48 1 The combinational circuit in BCD adder produces an add0command , <9 6 if the carry is-----
49 1 Convert BCD 0001 0010 0110 to binary 1111110
50 1 ________ is a correct combination for an ODD-parity data datatransmission
= 1101 1011 system
parity = 1
51 2 On a master-slave flip-flop, when is the master enabled? when the gate is LOW
52 2 Which table shows the logical state of a digital circuit output Function
for every tablepossible combinatio
53 2 A J-K flip-flop is in a "no change" condition when ________. J = 1, K = 1
54 2 In sequential circuits the output states depends upon ----------past inputs
55 2 -----Flip flop can be used to provide delay in the circuts. SR
56 2 For JK flip flop with J=1, K=0, the output after clock pulse will be 0
57 2 The output of SR flip flop when S=1, R=0 is 1
58 2 The preset and clear inputs are used in flip flop circuits ---- to reduce the power consumptio
59 2 Race around condition occurs in a JK FF when---- both the inputs are 0
60 2 latch is constructed using two cross-coupled AND and OR gates
61 2 How can parallel data be taken out of a shift register simultaneously?
Use the Q output of the first FF
62 2 sequence of equally spaced timing pulses may be easily generated ring shiftby which type of count
63 2 How many clock pulses will be required to completely load serially a 25-bit
64 2 In Sequential circuit the output state depend upon Past input State
65 2 How is a J-K flip-flop made to toggle? J=0 , K= 0
66 2 Sequetial circuit used for counting pulses is known as -----Register
67 2 On the fifth clock pulse, a 4-bit Johnson sequence is Q0 =Q0 0, =Q1 1, =Q11, =Q2 0, =Q2
1, =and
0, Q3 =
68 2 What is a shift register that will accept a parallel input, or atristate
bidirectional serial load and int
69 2 A bidirectional 4-bit shift register is storing the nibble 1101. Its input1101 is HIGH. The nibble
70 2 when a flip flop is set ,its output will be --------- Q=0
71 2 On the fifth clock pulse, a 4-bit Johnson sequence is Q0 =Q0 0, =Q1 1, =Q11, =Q2 0, =Q2
1, =and
0, Q3 =
72 2 The bit sequence 0010 is serially entered (right-most bit first)Q3Q2Q1Q0=0000
into a 4-bit parallel out shift
73 2 On the third clock pulse, a 4-bit Johnson sequence is Q0 Q0 = 1,=Q1 1, Q1= 1,=Q2 1, Q2
= 1,=and
1, Q3
Q3==
74 2 A bidirectional 4-bit shift register is storing the nibble 1101.Q3Q2Q1Q0=1101
Its input is HIGH. The nibble
75 2 How can parallel data be taken out of a shift register simultaneously?
Use the Q output of the first FF
76 2 To operate correctly, starting a ring shift counter requires:clearing all the flip-flops
77 2 In a 6-bit Johnson counter sequence there are a total of how many states, 2 or bit patterns?
78 2 A modulus-12 ring counter requires a minimum of ________. 10 flip-flops
79 2 The group of bits 11001 is serially shifted (right-most bit first)
Q4Q3Q2Q1Q0=01110
into a 5-bit parallel output s
80 2 Assume that a 4-bit serial in/serial out shift register is initially
Q3Q2Q1Q0=1100
clear. We wish to store the n
81 2 The bit sequence 10011100 is serially entered (right-most bit 10011100
first) into an 8-bit parallel o
82 2 If an 8-bit ring counter has an initial state 10111110, what is11101011the state after the fourth cloc
83 2 If a logic circuit does not contain any feedback loops, andCombinational
the output is wholly logic circuit
dependent
84 2 A ring counter consisting of five Flip-Flops will have 5 states
85 2 The device which changes from serial data to parallel dataCOUNTER is
86 2 In this logic, output depends not only on the current inputsLogicalbut alsoCircuiton the past input value
87 2 A _________________ is a circuit, which can rememberLogical values Circuit
for a long time or chang
88 2 A ________________ circuit is not suitable in the synchronous Latch circuit design because of
89 2 The different types of flip-flops are R-S
90 2 It is a bi-directional counter capable of counting in either of Upthe Synchronous
direction depending
Counter on the
91 2 A MOD-16 ripple counter is holding the count 10012 . What will 1000 the count be after 31 clo
92 2 The terminal count of a modulus-11 binary counter is ________ 1010
93 2 Synchronous construction reduces the delay time of a counter all flip-flops
to the delayand gates
of:
94 2 Synchronous counters eliminate the delay problems encountered input clock withpulses
asynchronous
are applied
couno
95 2 A 4-bit ripple counter consists of flip-flops, which each have 15 ns a propagation delay from clo
96 2 Which of the following statements best describes the operation The counter
of a synchronous
can count in up-/dow
either
97 2 The parallel outputs of a counter circuit represent the: parallel data word
98 2 If T flip flop function is obtained from a JK flip flop, if ........
J=K=1
99 2 In JK Flip - flop, when J = K = 1 and clock is applied, the notoutput
change Q will .......
100 2 Both inputs of JK flip flop are tied high, the FF behaves like D Flip
........flop
101 2 An universal register ................... accepts serial input
102 2 Master slave configuration is used in FF to .......... increase its clocking rate
103 2 In JK Flip - flop, when J = K = 1 and clock is applied, the notoutput
change Q will .......
104 2 A mod 4 counter will count ....... From 0 - 4
105 The logic level at theDDflip-flop?
2 Which statement BEST describes the operation of a negative-edge-triggered input is
106 2 How many flip-flops are required to produce a divide-by-128 device? 1
107 2 An invalid condition in the operation of an active-HIGH input HIGHs S-Rare latch
applied
occurs simultaneou
when ___
108 2 To completely load and then unload an 8-bit register requires how many 2 clock pulses?
109 2 Why are the S and R inputs of a gated flip-flop said to beThey synchronous?
must occur with the gate.
110 2 comparison between ring and johnson counters indicates that: a ring counter has fewer flip-flop
111 2 What is meant by parallel-loading the register? Shifting the data in all flip-flops s
112 2 Mod-6 and mod-12 counters are most commonly used in:frequency counters
113 2 Which of the following is correct for a gated D-type flip-flop? The Q output is either SET or R
114 2 To overcome the difficulty of race around condition whichJkof the following flip flop is used
115 4 The difference between a PLA and a PAL is: The PLA has a programmable O
116 4 ALM is the acronym for ________. Array Logic Matrix
117 4 PALs tend to execute ________ logic. SAP
118 4 Each programmable array logic (PAL) gate product is applied the polarity
to an OR fusegate
is restored
and, if comb
119 4 _______ are used at the inputs of PAL/GAL devices in order Simplified
to prevent
ANDinputgatesloading fro
120 4 A(n) ________ consists of a programmable array of AND GAL gates that connects to a fixed
121 4 What is another name for digital circuitry called sequentiallogic logic? macrocell
122 4 When did the first PLD appear? More than 10 years ago
123 4 SPLDs, CPLDs, and FPGAs are all which type of device? PAL
124 4 What is the major downfall of microprocessor/DSP systems? Speed—they are too fast
125 4 ASIC stands for: advanced speed integrated circu
126 4 Why have PLDs taken over so much of the market? One PLD does the work of man
127 4 The final step in the device programming sequence is ________.
Compiling
128 4 By adding an OR gate to a simple programmable logic device PAL(SPLD) the foundation for
129 4 Which one of the following is an embedded function of theAND-OR
Stratix II logic
FPGA?
130 4 Field-programmable gate arrays (FGPAs) use ________DRAM, memorynonvolatile
technology, which is _
131 4 A PAL16L8 has: 10 inputs and 8 outputs.
132 4 Now many times can a GAL be erased and reprogrammed? 0
133 4 What does a dot mean when placed on a PLD circuit diagram? A point that is programmable
134 4 GAL is an acronym for ________. Generic Array Logic
135 4 What gives a GAL its flexibility? Its speed
136 4 A macrocell basically contains ________ a programmable AND-OR gate
137 4 What programmable technology is used in FPGA devices? SRAM
138 4 FPGA is the acronym for ________. Flexible Programming [of] Gene
139 4 Which is not a type of PLD? SPLD
140 4 Which type of PLD could be used to program basic logicPLA functions?
141 4 Product terms are the outputs of which type of gate withinOR a PLD array?
142 4 A slice consists of ________. only two logic cells
143 4 What is PROM? SPLD
144 4 A unit of logic in an FPGA that is made up of multiple smaller
bed-of-nails
logic modules and a local p
145 4 Most FPGA logic modules utilize a(n) ________ approach AND to create
array the desired logic fun
146 4 A macrocell is ________ part of a PAL or GAL
147 4 Most complex digital designs include ________. standard logic devices
148 4 The programming technologies that are used in FPGA devices SRAM include SRAM, flash, and
149 4 Full custom ICs can operate at ________ and require thelowest ________.
speed, largest die area
150 4 Design costs for standard cell ASICs are ________ thoselower for MPGAs.
than
151 4 The ________ can generate any possible logic function ofGAL the input variables because it g
152 4 The distinction between CPLDs and FPGAs is ________. well known
153 4 The flexibility of the GAL16V8 is in its ________. AND/OR array
154 4 In a programmable logic device circuit diagram, the inputsatodot each of the OR gates are de
155 4 The SPLD classification includes the ________ PLD devices. earliest
156 4 Four subcategories of ASIC devices are available to create HCPLDs
digital systems. These are PL
157 4 PROM stands for Permanent Read Only Memory
158 4 PLD stands for portable large device
159 4 ROM is a non volatile memory
160 4 EPROM stands for Electrical Programmable Read O
161 4 In a ROM each bit combination input variable is called cell
162 4 An integrated circuits with internal logic gates connected through
A. portable
electronic
large
fuses
device
is called
163 4 Blowing of fuses are referred to as ROM's memory
164 4 PAL stands for portable array logic
165 4 ROM is a two level implementation in sum of maxterms
166 4 What do the Programmable Logic Devices (PLDs) designed Onlyspecially
gates for the combinatio
167 4 Which among the following statement/s is/are not an/the advantage/s
Short designofcycle
Programmable Lo
168 4 What is/are the configurable functions of each and every IOBs
Input connected
operation around the FPG
169 4 Which type of CPLD packaging can provide maximum number PLCCof pins on the package du
170 4 How many logic gates can be implemented in the circuit by complex10 programmable logic
171 4 If the number of nichrome fuse links in PAL are equal to Number
2M xn, thenof inputs
what does 'n' repre
172 4 Which among the following are used in programming arrayInput logicbuffers
(PAL) for reducing the lo
173 3 ASM charts resembles to--- map
174 3 state box without decision and conditional box is--- asm block
175 3 Control information gives knowledge about the command signals
176 3 ASM chart has 4 exits
177 3 Number of basic notations of an ASM are-- 1
178 3 A rectangular box in ASM is ----box state
179 3 ASM chart is composed of--- 2 elements
180 3 Sate box of ASM chart represents---- condition
181 3 Logic desgin consists of --- 1 part
182 3 No of inputs and outputs in a state table are-- equal
183 3 Signal that starts operation is indicated by -- INITIAL
184 3 In VHDL, the mode of a port does not define -- an input
185 3 which VHDL data type can only have a value of '1' and '0'signal
186 3 VHDL can be used for -- synthesis and simulation only
187 3 which is of the following statements is not a concurrent statement
if statement
188 3 which is symbol used for signal assignment ? <=
189 3 __type is the group of elements of same type? Array
190 3 which statement is used to JUMP out of loop statement currently
EXIT in execution?
191 3 ____type of object can have values TRUE and FALSE CONSTANT
192 3 Which are the possible modes of a port? Onlu IN,OUT
193 3 ____declaration specifies only the outer description of a circuit?
Entity
194 3 In VHDL a digital system is modeled as___ module
195 3 STD_LOGIC_1164 is a __in a VHDL IEEElibrary module
196 3 the PROCESSstatement itself is a concurrent
197 3 what is used to bind ta component instance to an entity configuration
architecture pair?
declaration
198 3 In a dataflow modeling statements are executed sequentialy
199 3 The signal written in parenthesis after keyword PROCESS variable
is
200 3 which is an invalid form of wait? wait until time expression
Option B Option C Option D Marks Correct Option
m-1 m m+1 1 C
Karnaugh mapping andcircuit
Actual circuittrial
waveform
Boolean
and erroranalysis
algebra andand
evaluation actual circuit
1waveformA trial and error evaluation
analysis
OR Ex-OR AND 1 C
OR-OR AND-OR OR-AND 1 A
sequential Combinational andNone sequential 1 A
sequential FF None 1 A
data Control Strobe 1 B
2 4 8 1 C
2 3 4 1 C
Cp=A+B Cp =A+B' Cp=A'+B 2 B
1111001 1111001 1101 1 C
to connect groundto active the entiretochip active one half of the 1chip C
8421 code excess-3 code Gray code 2 D
sum of all previous
carrybits
from ( K - 1sum )THofbitprevious bit 1 C
equality gate inverted OR parity gate or the equality 1 gate B
Cyclic Code Non-Weighted code All of these 1 D
1 half-adder, 1516full-adders
half-adders, 0 full-adders
4 half-adders, 12 full-adders 2 B
to select 1 out of
to N
transit
inputdata
dataonsources
Ntolines
perform
and toserial
transmit
to parallel
it to1 single
conversion
channel
B
Demultiplexer Decoder Digital counter 2 A
Demultiplexer BCD adder Comparator 1 B
3 4 5 1 D
0110 0000 0001 0001 0000 0110 0001 0000 0101 2 C
EX-OR gate and EX-OR
NORgate gate and EX-OR
AND gate gate and NAND 1 gate C
1 and 2 3 and 1 2 and 2 1 C
8:1 mux 16:1 mux dual4:1 mux 1 D
tying all data-select
tyinglines
all data-select
LOW using linesthe
HIGH
input lines for 1data selection
D and an enable line for data input
FALSE 1 B
FALSE 1 B
FALSE 2 B
0 1 10 1 A
log2 m log2 n log m 1 A
sum= a Exor b sum=
Exor cbinExor c in sum= a Exor c in 2 B
2,2 1,2 2,1 2 D
D11 D12 D13 1 B
NOR gate and NOR
Bubbled
gateAND
and NAND
gate.
NANDgate.
gate and NOT gate
1 B
X= AB'X X= ABC'+ABC+AB'C NONE 1 A
87 67 55 1 A
Product Min Composite 1 A
Subtraction Multiplication Division 1 C
Any of the inputAny
is one
of the input isAll zerothe inputs are zero 1 A
symbolic reduction
TTL logic using a truth table 1 A
At least one variable
When one in domain
or more ofWhen
product
expression
oneterms
orismore
present.
in theproduct
expression
1 termsDare
in the
equal
expression
to 0. are equal to 1.
((A))A'=0 1+A=1 A+B=B+A 1 B
A > B = 0, A <AB>=B1,=A1,=AB<=B0A= >0,BA==0,BA= <0 B = 1, 2A = B =C1
sequential FF NONE 1 A
32:1 Multiplexer8:1 Multiplexer 64:1 Multiplexer 2 B
0110 0000 0001 0001 0000 0110 0001 0000 0101 2 C
1,>9 1 , =9 1, < 9 2 B
11110 1110010 1111111 1 A
data = 1101 0010 dataparity
= 0001 = 00101dataparity
= 0001
= 1 0101parity2= 1 A
when the gate isboth
HIGHof the aboveneither of the above 1 A
Truth table Routing table ASCII table 1 B
J = 1, K = 0 J = 0, K = 1 J = 0, K = 0 1 D
present inputs None Present as well as past inputs 1 D
D T JK 1 B
1 high impedance. no change. 1 B
0 high impedance. no change. 1 A
to increse speedto set the initial conditions
for sychronization 1 C
both the inputs are
inputs
1 are complementry any condtion is present1 B
AND Exor gates NAND gate 1 D
Use the Q outputTieof
allthe
of the
last Q
FF. outputs
Use thetogether.
Q output of each 1 FF. D
CLOCK Johnson Binary 1 A
3 4 5 1 D
Present input State
Present as well as Past Noneinput
of Above 1 C
J=0 , K=1 J=1 , K=0 J=1 , K=1 1 D
Counter Flip flop NONE 1 B
Q0 = 1, Q1 = Q0 1, Q2= 0,= Q1
1, Q3
= 0,= Q0
Q2
0 = 0, 1, Q1
Q3 = 0, 1 Q2 = 0, 2 Q3 = C1
end around universal conversion 1 C
111 1 1110 2 C
Q=1 Q=00 NONE 2 B
Q0 = 1, Q1 = Q0 1, Q2= 0,= Q1
1, Q3
= 0,= Q0
Q2
0 = 0, 1, Q1
Q3 = 0, 1 Q2 = 0, 2 Q3 = C1
Q3Q2Q1Q0=0010 Q3Q2Q1Q0=1000 Q3Q2Q1Q0=1111 2 C
Q0 = 1, Q1 = Q0 1, Q2= 1,
= Q10, Q3
= 0, = Q2
0Q0==0,0,Q3 Q1==00, Q2 =20, Q3 =A0
Q3Q2Q1Q0=0111 Q3Q2Q1Q0=0001 Q3Q2Q1Q0=1110 2 B
Use the Q outputTieof
allthe
of the
last Q
FF. outputs
Use the Q output of each
together. 2 FF. D
presetting one flip-flop
clearingandoneclearing
flip-flop
presetting
all
and
others
presetting
all the flip-flops
all others
2 B
6 12 24 1 C
12 flip-flops 6 flip-flops 2 flip-flops 1 B
Q4Q3Q2Q1Q0=00001
Q4Q3Q2Q1Q0=00101 Q4Q3Q2Q1Q0=001102 C
Q3Q2Q1Q0=0011 Q3Q2Q1Q0=0000 Q3Q2Q1Q0=1111 2 C
11000000 10001100 11110000 2 A
11001011 11110000 All Zeros 2 D
Sequential logicDelay
circuitlogic circuit ADDER 2 B
10 states 32 states Infinite states. 1 A
MULTIPLEXER DEMULTIPLEXER FLIP-FLOP 1 C
Connected Circuit
Sequential Circuit Parallel Circuit 1 C
Digital Circuit Memory Element Complex Circuit 1 C
Parallel Diagonal Circuit None of the above 1 A
D,T J-K All of the above 1 D
Down SynchronousSynchronous
CounterCounter Both A and B 1 C
1010 1011 1101 1 A
1000 1001 1100 1 A
all flip-flops andagates
singleafter
gatea 3 count a single flip-flop and a gate 1 D
input clock pulsesinputareclock
applied
pulsesonlyinput
are
to not
the
clock
used
lastpulses
stage
to activate
are applied
1any ofsimultaneously
the
D counter stages to each stage
30 ns 45 ns 60 ns 1 D
The counter can Inbegeneral,
reversed,
the counter
but The
mustcan
count
be bereset
sequence
reversed
before cannot
at
counting
2any point
beinreversed,
Cthe
in its
other
counting
once
direction.
itsequence.
has begun, without first resetting the co
clock frequencycounter modulus clock count 1 D
J = K =0 J =1 and K =0 None of the above 1 A
become 0 become 1 race condition 1 D
SR Flip flop T Flip flop None of the above 1 C
accepts parallelgives
outputserial and parallel
is capable
outputof all the above 2 D
reduce power dissipation
eleminate race around improve
condition
its reliability 1 C
become 0 become 1 race condition 2 D
0-5 0-3 None of the above 2 C
The Q output isThe ALWAYS
Q outputidentical
is ALWAYS
The toQ the CLKis ALWAYS
output
identical input
to the DD
if2the input
identical
input
Awhen the D=input.
istoHIGH.
CLK PGT.
4 6 7 1 D
LOWs are applied a LOW simultaneously
is applied atotoHIGH
the
bothS is
input
inputs
applied
while
S and
toa the
HIGH
R1S input is applied
Awhile atoLOWthe Risinput
applied to the R
4 8 16 1 D
They occur independent
All of the above
of the gate.None of the above 1 A
a ring counter has a johnson
an inverted
counterfeedback
ahas
johnson
more
pathcounter
flip-flopshas butan1less
inverted
decoding
Dfeedbackcircuitry
path
Loading data inLoading
two of the dataflip-flops
in allMomentarily
four flip-flopsdisabling
at the samethe
1 synchronous
time C SET and RESET inputs
multiplexed displays
digital clocks power consumption meters 1 C
The output complement
Only one follows
of the inputs
the
Theinput
canwhen
outputbe toggles
HIGH
enable((D))
at
if one
a time.
1of the inputsA is held HIGH
Sr D Master salve 1 D
The PAL has aThe programmable
PAL has more ORPALs
possible
planeand
and product
PLAs
a programmable
are
termsthe2than
sameAND the
thing.
APLA.
plane, while the PLA only has a programmable AND
Arithmetic Logic Asynchronous
Module Local
Adaptive
Modulator Logic Module1 D
SOP PLA SPD 1 B
sent to an inverter
sentfor
immediately
output topassed an output
to the pinAND function 1 forBoutput
Fuses Buffers Latches 1 C
CPLD PAL SPLD 1 C
logic array flip-flop memory circuitryInverter 1 C
More than 20 yearsMoreago than 30 years More
ago than 40 years ago1 C
PLD EPROM SRAM 1 B
Speed—they are Too toomuch
slowflexibility Not enough flexibility 1 B
advanced standard
application
integrated
specific
circuit.
application
integrated speedy
circuit. integrated
1 circuit.
C
The PLDs are cheaper.
Less power is required. All of the above 1 D
downloading simulation synthesis 1 B
PLA CPLD EEPROM 1 A
Programmable Digital
SOP signal processing None of the above 1 C
SRAM, nonvolatile
SRAM, volatile RAM, volatile 2 C
8 inputs and 8 outputs.
16 inputs and 16 outputs.
16 inputs and 8 outputs.1 A
At least 100 At least 1000 Over 10,000 1 B
A point that cannot
An intersection
change of An logicinputblocks
or output point1 B
General Array Logic
Giant Array LogicGeneric Analysis Logic 1 A
Its reprogrammable
Its large
EPROM
logic arrays Its programmable OLMCs 1 D
an OR-gate arrayan AND-OR
and some output
gatelicensed
array
logicand programming
some output logic
1 B
FLASH Antifuse All of the above 1 D
Field Programmable
Field Generic
Programmable
Array Field GateProgrammer's
Array Gate
1 Assembly
C
HPLD CPLD FPGA 1 B
PAL CPLD all the above 1 D
XOR AND flip-flop 1 C
between 2 and up 8 logic
to 16cells
logic cellsa single CLB 1 A
QPLD HPLD PLD 1 D
boundary scanCLB CPLD 1 C
Look-up table OR array AND and OR array 1 B
a type of one-time
an example
programmable
of intellectual
aSPLD
logic array
property
block 1 A
ASIC devices microprocessor/DSP a mix devices
of different hardware 1 categories
D
flash antifuse SRAM and flash 1 A
lowest speed, smallest
highest die
speed,
arealargest
highest die area
speed, smallest 1die area D
about the samehigher
as than none of the above 1 C
SOP PROM LAB 1 C
very small often fuzzy very large 1 C
D flip-flops programmable output EEPROM logic macro cells 1 C
a bus a single line 4 inputs 1 C
smallest largest newest 1 A
full custom GAL FPLDs 1 B
Portable Read Programmable
Only Memory Read D.OnlyPlugin Memory
Read Only Memory1 C
portable logic device
programmable large programmable
device logic device
1 D
A. secondaryvolatile
memory memory small memory 1 A
Electrical Portable
Erasable
ReadProgrammable
Only Memory D. Erasable
Read Only
Portable
MemoryRead
1 OnlyCMemory
block address memory 1 C
portable logic device
programmable large device A. programmable logic 1 deviceD
cells blocks programming 2 D
programmable programmable
advanced logicarray portable
logic advanced logic1 C
sum of minterms product of maxterms product of minterms 1 C
Only flip flops Both a and b None of the above 1 A
Increased spaceIncreased
requirementswitching Allspeed
of the above 1 B
Tristate output Bi-directional
operation I/O All
pin of access
the above 1 D
QFP BGA PGA 1 C
100 1000 10000 1 D
Number of arrays
Number of outputsNumber of product terms 1 D
Output buffers OR matrix AND matrix 1 A
data flowchart operation 1 C
defined block simple block Both A and B 1 C
data metadata operation 1 A
3 exits 2 exits any no exits 1 D
2 3 4 1 C
decision conditional outputNone of the above 1 A
3 elements 4 elements 5 elements 1 B
clock state pulse 1 C
2 parts 3 parts 4 parts 1 B
same unequal not present 1 A
GO BEGIN START 1 D
an output Both a and b the type of bit 1 D
std_logic bit integer 1 C
Synthesis ans documentation
programing None 1 A
signal assignment
condtional signal assignment
selected signal assignment
1 D
:= both of the aboveNone 1 A
Record Both a and b None of the above 1 A
NEXT LOOP END 1 A
BOOLEAN VARIABLE None of the above 2 B
IN, OUT, INOUT CLK None 2 B
Architecture Package Attribute 1 A
entity process All of the above 1 D
package function procedure 2 B
sequential data flow None of the above 1 A
Identifier port map sensitivity list 1 A
concurrently Both a and b None of the above 1 B
constant sensitivity list none 1 C
wait on signal wait for condtion Both A and C 2 D
College Code: 4043
Sinhgad Academy of Engineering,Pune
College Name:

Class: SEComputer:
Subject:
Digital Electronics and Logic Design
Sr.No Unit No. Question

1 1 Assign the proper even parity bit to the code 1100001.
2 1 The base of the hexadecimal system is:
Which of the following expressions is in the sum-of-
3 1
products (SOP) form?
Which of the following is the primary advantage of using
4 1 the BCD code instead of straight binary coding?
A logic circuit that provides a HIGH output for both inputs

5 1
HIGH or both inputs LOW is a
The expression W(X + YZ) can be converted to SOP form
6 1
by applying which law?
How many gates would be required to implement the
7 1 following Boolean expression after simplification?
XY+ X(X + Z) + Y(X + Z)
The NAND or NOR gates are referred to as "universal"
8 1 gates because either:
9 1 Odd parity of word can be conveniently tested by

The number of full and half-adders required to add 16-bit
10 1
numbers is
A one-to-four line demultiplexer is to be implemented
11 1
using a memory. How many bits must each word have ?
Which of the following gates is known as
12 1
coincidence detector ?
How many full adders are required to construct an
13 1
m-bit parallel adder ?
Parallel adders are
14 1
The digital multiplexer is basically a combination logic

15 1 circuit
to perform the operation
Which of the following circuit can be used as parallel to
16 1 serial
converter ?
Which one of the following set of gates are best suited
17 1
for 'parity' checking and 'parity' generation.
A multiplexer has ________
18 1
19 1 32:1 multiplexer has ________ number of select lines
Which device is also called as serial data to parallel data
20 1
converter
21 1 For an N : 1 multiplexer number of select lines are
22 1 IC74 XX 153 is a
23 1 IC7 4 XX 151 is a
24 1 IC74 X 138 is a
25 1 IC74 83 is a
On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0,
26 2 Q1 = 1, Q2 = 1, and Q3 = 1. On the sixth clock pulse, the
sequence is ____
On the third clock pulse, a 4-bit Johnson sequence is Q0 =
27 2 1, Q1 = 1, Q2 = 1, and Q3 = 0. On the fourth clock pulse, the
sequence is _____
How can parallel data be taken out of a shift register
28 2
simultaneously?
29 2
A modulus-12 ring counter requires a minimum of

30 2
________.
A serial in/ parallel out, 4-bit shift register initially contains
31 2 all 1s. The data nibble 0111 is waiting to enter. After four
clock pulses, the register contains ________.
How many clock pulses will be required to completely load
32 2
serially a 5-bit shift register?
How is a strobe/ enable signal used when serially loading a
33 2
shift register?
What is the difference between a ring shift counter and a
34 2
Johnson shift counter?
What type of register would have a complete binary
35 2 number shifted in one bit at a time and have all the stored
bits shifted out one at time?
36 2
37 2 Which is not characteristic of a shift register?

In which sequential circuit output depends on present
38 2 state
and inputs.
State table is a representation of describing the operation
39 2
of a which circuit
Which sequential circuit has required more delay to
40 2
generate output ?
when sequence generator move into the unused state and
41 2
not come back into used state so this condition known as
42 2 Those state which are not available in sequence known as
43 2 In which method sequence come back into used state.
44 2 IC74 76 is a
45 2 IC74 90 is a
46 2 IC7490 is combination of
47 2 IC74 74 is a
A 4-bit synchronous counter uses flip-flops with
48 2 propagation delay times of 15 ns each. The maximum
possible time required for change of state will be
How many flip-flops are required to construct mod 30
49 2
counter
Sequential circuit consist of_____
50 2
In SR Latch , if S=___, R=______& En=____ indeterminate

51 2
state occurs
52 2 How many stable states do flip flops have?
53 2 For JK flipflop J = 0, K=1, the output after clock pulse will be
54 2 SRLatch will operate when EN= _____
55 2 In ___ flip flop output follows the input
56 2 Group of FFs connected together forms____
Preset & clear inputs are used in flip flop ____
57 2
58 2 A 4 bit DOWN counter can count from

The output Qn of a J-K FF is 1. It changes to 0 when a clock
59 2
pulse is applied. The inputs Jn & Kn are_______
The output Qn of a T FF is 1. It changes to 0 when a clock
60 2
pulse is applied. The inputs T is_______
11100001 1100001 1100001 1110101
8 16 2 10
(A + B )(C + D ) (A)B(CD) AB(CD) AB + CD
Fewer bits are required to The relative ease of BCD codes are easily BCD codes are easily
represent a decimal converting converted converted
number with the BCD code to and from decimal. to hexadecimal codes. to straight binary codes.
Ex-NOR gate OR gate Ex-OR gate NAND gate
associative law commutative law distributive law none of the above
1 2 4 5
can be used to build all

can be found in almost all are used in all countries were the first gates to
the other types of
digital circuits of the world be integrated
gates
ORgate AND gate NORgate XOR gate
1 half-adder, 5 full- 16 half-adders, 0 full- 4 half-adders, 12 full-
8 half-adders, 8 full-adders
adders adders adders
1 bit 2 bits 3 bits 4 bits
OR NOT AND NAND
m/ 2 m+1 m m-1
combinational logic circuits sequential logic circuits both (a) and (b) None of these
AND-AND OR-OR OR-AND AND-OR
Multiplexer Demultiplexer Decoder Digital Counter
AND, or NOT gates EX-NOR or EX-ORgates NORgate NAND gate
Several inputs & Several inputs & one

One input & several output One input & one output
several outputs output
2 3 5 8
Decoder Multiplexer Demultiplexer Encoder
2N Log2 N Log10 N 2N
4: 1 multiplexer 8 : 1 multiplexer 3 : 8 decoder 4 bit binary adder
Q0 = 1, Q 1 = 0, Q 2 = 0, Q0 = 1, Q 1 = 1, Q 2 = Q0 = 0, Q 1 = 0, Q 2 = 1, Q0 = 0, Q 1 = 0, Q 2 = 0,
Q3 = 0 1, Q3 = 0 Q3 = 1 Q3 = 1
Q0 = 1, Q 1 = 1, Q 2 = 1, Q0 = 1, Q 1 = 1, Q 2 = Q0 = 1, Q 1 = 0, Q 2 = 0, Q0 = 0, Q 1 = 0, Q 2 = 0,
Q3 = 1 0, Q3 = 0 Q3 = 0 Q3 = 0
Use the Q output of the Use the Q output of Tie all of the Q outputs Use the Q output of
first FF. the last FF. together. each FF.
presetting one flip-flop clearing one flip-flop presetting all the flip-
clearing all the flip-flops
and clearing all others and presetting all others flops
10 flip-flops 12 flip-flops 6 flip-flops 2 flip-flops
0 1111 111 None of these
2 4 5 8
to turn the register on and to control the number to determine which to determine the FFs
off of clocks output Q s are used that will be used
The feedback is
There is no difference. A ring is faster. The Johnson is faster.
reversed.
serial-in, parallel-out parallel-in, serial-out parallel-in, parallel-out serial-in, serial-out
synchronous and true

synchronous counters aynchronous counters true binary counters
binary counters
Serial in/ parallel out Serial in/ parallel in Parallel in/ serial out Parallel in/ parallel out
Moore model Mealy model In both cases Neither A nor B
Synchronous circuit Asynchronous circuit In both cases Neither a nor b
Moore model Mealy model In both cases Neither A nor B
Race condition Toggle condition Race around condition Lockout condition
Unwanted state Unavailable state Unused state Used state

Without bushing With bushing both neither a nor b
S-RFF J-K FF M SJ-K FF T FF
S-RFF J-K FF M SJ-K FF Decade Counter
1 M SJ-K FF 2 M SJ-K FF 3 M SJ-K FF 4 M SJ-K FF
S-RFF J-K FF D FF T FF
15 ns. 30 ns 45 ns 60 ns
4 5 6 8
Flip Flop & Only combinational

Only Flip-Flops Only gates
Combinational Circuit circuit
1,0,1 1,1,1 0,1,1 1,1,0
0 1 2 3
1 0 No Change High Impedance
1 0 No Change Botha A & B
JK SR D T
Mux Counter Register Flip-Flop
To set the initial
To increase speed To reduce power For synchronization
condition
000 to 111 0000 to 1111 111 to 000 1111 to 0000
0& X 1& X X& 1 X& 0
0 1 X None
Marks Correct Option
1 A
1 B
1 D
2 B
1 A
1 C
2 B
1 B
1 D
2 B
1 A
1 C
1 C
1 A
1 D
1 D
1 B
1 D
1 C
1 C
1 B
1 A
1 B
1 C
1 D
2 C
2 A
1 D
1 B
1 B
2 C
1 C
1 B
1 C
2 A
1 A
1 B
1 B
1 A
1 B
1 D
1 C
1 B
1 C
1 D
1 D
1 C
1 A
1 B
1 C
2 B
1 C
1 B
1 A
1 C
1 C
1 D
1 D
2 C
2 B
College Code: 4043
Colleg
e
Name:
Sinhga
d
Acade
my of
Engine
ering,P
une

Class: SEComputer:
Subject:Digital Electronics and Logic Design
Unit
Sr.No No. Question Option A Option B
A table that shows result of logical operations
1 1 conducted is called_____. logic table truth table
How many NAND gates are contained in a
2 1 7400 NAND IC? 1 2
When grouping cells within a K-map, the cells

3 1 must be combined in groups of ________. 2s only 1,2,4,8
can be found in can be used to
The NAND or NOR gates are referred to as almost all digital build all the other
4 1 "universal" gates because either circuits types of gates
In circuits the output at any
instant of time is dependent only on the inputs
5 1 present at that instant of time combinational sequential
Which among the following is not the output of
6 1 comparator? A>=B A=B
The result of BCD adder is corrected by
7 1 adding . 5 7
A binary code that progresses such that only nine's
one bit changes between two successive complement alpha-numeric
8 1 codes is_____. code code
How many select lines would be required for
9 1 16: 1 multiplexer? 3 4
coded
information non-coded
into non coded information into
10 1 A decoder means form coded form
________is a correction combination for an data=1101101 data=00010101,
11 1 odd parity data transmission system 1, parity=1 parity=1
The Excess-3 code word is obtained by
12 1 adding (2)10 (5)10
Which among the following is 8:1 multiplexer
13 1 IC? 74153 74158
Each individual term in canonical SOP form is
14 1 called as______. minterm maxterm
For SOP form are entered
corresponding to the input variables which
15 1 produce high output for don’t care conditions. 0's x
Which among the following is not a weighted
16 1 code? binary 8421
17 1 In BCD are valid BCD. 0000 to 1001 0000 to 1010
code is known as cyclic
18 1 code. Excess-3 Gray
is a 4-bit magnitude comparator
19 1 IC. 7481 7455
The octal to binary encoder has ________
20 1 input lines and output lines. 8,2 8,3
The addition of three bit operation is
performed by using
a ______ adder.
21 1 half full
If multiplexer has m input data and n controls
inputs and y Outputs then ____.
n m
22 1 2 =m 2 =n
A BCD number cannot be greater
23 1 than_____. 7 8
one data input
and a number
of selection
inputs, and they
have several one input and one
24 1 A demultiplexer has ________. outputs output
Which of the following is not a weighted value binary-coded
25 1 positional numbering system: hexadecimal decimal
Two half adders
cascaded
26 1 A full adder consist of_____. Two nand gates together
Which of the following combinations cannot Corners in the Corners in the
27 1 be combined into K-map groups? same row same column
Which is not present in Quine Mc Cluskey
28 1 technique? PI EPI
SOP can be POS can be
converted to converted to
29 1 Which is not true among the following? POS SOP
30 1 0110 represents which minterm? ABCD ABCD
31 1 Find the equivalent of ∑m(2,4,7). ∑M(0,1,3,5,6) ∏M(0,1,3,5,6)
4 bit binary 4 bit binary
32 1 IC74LS83 is __________. adder subtractor
33 1 In Half Subtractor (A,B) the Difference = ? A EXOR B A
34 1 In Look Ahead Carry , Carry Generate =? AiBi Ai EXOR Bi
Half Adder adds

Full Adder can two single bit
be designed numbers without
using Half considering
35 1 Which among the following is not true? Adder Carry.
Look Ahead Carry eliminates the problem due interstage carry
36 1 to _____ . delay borrow delay
The Pi in Look Ahead Carry is called Carry

37 1 as_____. Produced Carry Propogate
A Combinational Circuit in BCD Adder is
38 1 used to check if Sum is ____ or Carry= ____. less than 9 ,0 less than 9 ,1
In Half Subtractor Circuit , for the inputs 0 , 1
39 1 the Difference= ____ and Borrow=____. 0,0 1,1
Difference,
40 1 IC 7483 is having ___ and ___ as its outputs. Borrow Sum, Carry
41 1 Which are the Parity Inputs of IC 74180? A to H EVEN

What is the Expression for the output A>B in
42 1 1 bit Binary Comparator? AB AB'
An Edge-triggered flip-flop can change states The trigger is The D input is
51 2 only when HIGH HIGH
The advantage of J-K flip-flop over an S-R It has fewer It has only one
52 2 FF is that gates output
53 2 How is a J-K flip-flop made to toggle? J=0, K=0 J=1, K=0
On a J-K flip-flop when is the flip-flop in a
54 2 hold condition? J=0, K=0 J=1, K=0
For an S-R flip-flop to be set or reset the installed with in parallel with a
55 2 respective input must be---. steering diodes limiting resistor
The decimal equivalent of the largest number
that can be stored in a 4-bit binary counter
56 2 is____. 8 15
Asynchronous counters are often
57 2 called_____counters. toggle ripple
How many JK flip-flops are required to
58 2 construct a decade counter? 10 8
The terminal count of a typical modulus-10
59 2 binary counter is______. 1111 1010
An asynchronous 4-bit binary down counter
changes from count 2 to count 3. How many
60 2 transitional states are required? 3 1
A 4-bit up/down binary counter is in the
DOWN mode and in the 1100 state. To what
state does the counter go on the next clock
61 2 pulse? 1101 1011
Asynchronous Asynchronous
events do not events are
occur at the independent of
62 2 Which of the following statement is true? same time each other
Which of the following groups of logic devices Five flip-flop
would be the minimum required for a MOD- three AND Seven flip-flop
63 2 64 synchronous counter? gates five AND gates
Up count is Up count is active
active –HIGH –LOW the down
The designation (up/~DOWN) means that the down count count is active-
64 2 the--- is active-LOW HIGH
The flip-flops The flip-flops

Why can a synchronous counter operate at a changes one changes at the
65 2 higher frequency than a ripple counter? after the other same time
Which IC is divided by 2 and divided by 5
66 2 counters? 74191 74193
67 2 _______consists of JK flip-flops 7474 7473
The output of a sequential circuit depends on present inputs
68 2 ____ only past outputs only
What type of register would have a complete
binary number shifted in one bit at a time and
have all the stored bits shifted out one at a Parallel-In - Parallel -In -
69 2 time? Parallel-Out Serial-Out
What is the preset condition for a ring shift All flip flops set All flip flops
70 2 counter? to 1 cleared to 0
Serial-In - Parallel -In -
71 2 Which is not characteristic of a shift register? Parallel In Serial-Out
In a 4-bit Johnson counter sequence there are
72 2 a total of how many states, or bit patterns? 1 2
73 2 ______consists of MS-JK flip-flops 7474 7473
Up- down
74 2 A ring counter is same as_____. counter Parallel-counter
75 2 In general a sequential logic consists of ---- only flip flops only gates
The state table gives relation between -----,-- input, present
76 2 -- and output state next state, input
In state assignment the assignment number is
77 2 represented by using----- Gray code Binary code
To design a sequence detector using Mealy
machine of sequence 100,--- number of states
78 2 are required 4 3
A J-K flip-flop has two control inputs. What is Q toggles to the
79 2 Q ,if J= 0 and K=1 ? Q=1 other state
In synchronous counter all flip flops are clocked not clocked
80 2 _______________ simultaneously simultaneously
combinational
81 2 A flip flop is a _____________ . circuit. memory element.
In which register there is no interconnection
between successive flip-flops and no serial
82 2 shifting is required ? SISO PISO
condition
83 2 If S=1 and R=1 then ____. Q=1 prohibited
A J-K flip-flop has two control inputs. What is Q toggles to the
84 2 Q , if J= 1 and K=0 ? Q=1 other state
85 2 Which shifting method is faster ? serial parallel
Johnson's counter is also called as ___ ring
86 2 counter. twisted rounded
87 2 Johnson's counter is ___ counter. asynchronous synchronous

88 2 IC7495 is _____. counter flip flop
A shift register which can shift the data in both
89 2 the directions is called as a _____ shift register unidirectional bidirectional
A shift register which can shift the data only in
90 2 one direction is called as a _____ shift register unidirectional bidirectional
A shift register which can shift the data in both
the directions as well as load it parallely called
91 2 as a _____ shift register unidirectional bidirectional
J K flip flop can be converted to D flip flop
92 2 using____ gate in between J and K. and not
Programmable Programmable
93 4 PLD stands for _____. Large Device Logic Device
The AND matrix in PLA is used to implement
94 4 ___ terms in SOP form. Sum Product
95 4 ____ are inputs to AND matrix in PLA. Input Buffers Product Terms
96 4 In PLA , OR matrix is having ___ as input. Input Buffers Product Terms
In PLA , Invert/Non Invert matrix is having
97 4 ___ as input. Input Buffers Product Terms
98 4 PLA stands for ______. Logic Array Large Array
The OR matrix in PLA is used to implement
99 4 ___ terms in SOP form. Sum Product
PLD can not be PLD can be

programmed by programmed by
100 4 Which among the following is true? the user the user
Field
Programmable Field Portable
101 4 FPGA stands for________. Gate Array Gate Array
Simple
Simple Portable Programmable
102 4 SPLD stands for _______. Logic Device Logic Device
Complex Complex
Portable Logic Programmable
103 4 CPLD stands for _________. Device Logic Device
104 4 PAL stands for _________. Array Logic Array Large
105 4 Identify odd man out of following? CPLD FPGA
Which among the following is not type of
106 4 PLD? RAM ROM
107 4 PLD? PLA PAL
108 4 In PAL ___ is fixed. AND matrix OR matrix
109 4 In PAL ___ is programmable. AND matrix OR matrix

110 4 In PAL , OR matrix is having ___ as input. Input Buffers Product Terms
111 4 ____ are inputs to AND matrix in PAL. Input Buffers Product Terms
112 3 Control sequence state is indicated by state box decision box
An ASM chart is composed of basic
113 3 elements 1 2
In ASM, if a system is not performing any
114 3 function then it is in _____. clear state initial state
115 3 ASM chart is similar to _____. map data
An ASM block has entrance and
116 3 number of exit paths 2,6 1,6
An oval shaped box in ASM is known as
117 3 box______ Conditional state
Difference in conventional flowchart and ASM
118 3 chart lies in clock pulse timing relationship
119 3 Change of state in ASM chart is performed in processor metadata
Rounded corners of conditional box
120 3 differentiate it from decision box conditional box
Second level of design with mux in ASM has
121 3 register holding ______. present state input
Design with multiplexers controller method , is
122 3 consisting of _____. 1 level 2 levels
123 3 ASM chart takes entire block as 1 unit 2 unit
negative edge negative level
124 3 In ASM design flip-flops are considered to be triggered triggered
Hardware
High definition Description
125 3 HDL stands for language Language
Which VHDL data type can only have value
126 3 of '1' or '0'? signal bit
Library
127 3 Which is not the fundamental unit of VHDL? declarations ENTITY
In VHDL,how many modes are available for
128 3 ports? 3 4
The block of code which defines the
relationship between input, output and internal
signals or variables in a VHDL design is
129 3 the_____ . architecture entity
Synthesis and
Synthesis and documentation
130 3 VHDL can be used for simulation only only
Which statement can be used to check for Concurrent Sequential
131 3 error conditions? Statement Statement
In VHDL,which statement is used to jump out
132 3 of loop statement currently in execution? GOTO EXIT
SIGNAL X:INTEGER RANGE -127 TO X is an 8-bit X is an 8-bit

133 3 127;In this statement X means? Signed number unsigned number
STD_LOGIC_1164 is a in VHDL
134 3 IEEElibrary. module package
Architecture Entity represents
Which one of the following statements is true represents the the
135 3 about VHDL? interface implementation
Which symbol is used for signal assignment
136 3 statements? = ==
variable
Which one is not the type of sequential assignment
137 3 statement? statements abort statements
How many modeling styles are there in
138 3 VHDL? 4 3
Architecture
may contain
declarations of
types,signals,co Single entity can
Which one is not true about architecture nstants,subprog have several
139 3 declaration? rams architectures
140 3 Which are the possible modes of a port? only IN,OUT IN,OUT,INOUT
Which among the following is not the type of
141 3 modeling style in VHDL? Structural Behavioral
Which among the following is not the type of STD_LOGIC_
142 3 signal used in VHDL? VECTOR STD_LOGIC
BIT and BIT_VECTOR are defined in VHDL
143 3 standard____. IEEE 1164 IEEE 1614
___ modeling style in VHDL is any
combination of behavior, data flow and
144 3 structural modeling. Combined Mixed
______ modeling has a set of interconnected
145 3 components. Structural Behavioral
______ modeling has a set of concurrent
146 3 assignment statements. Structural Behavioral
It is used for only

Which among the following is not true about It has 4 combinational
147 3 VHDL? modeling styles circuits
______ modeling style consist of sequential
148 3 program statements. Structural Behavioral
Identify odd man out of following in VHDL
149 3 statements? If Switch
150 3 sequential statements? If Switch
Identify odd man out of following in VHDL
151 3 statements? If Loop
Option C Option D Marks Correct Option
gate table system table 1B
4 8 1C
4s only 3s only 1B
were the first
are used in all gates to be
circuits integrated 2B
adder multiplexer 1A
A<B A>B 1A
9 6 1D
gray code Excess-3 code 2C
2 8 1B
conversion from conversion from

high to low low to high 2A
data=10101111, data=11011011
parity=0 , parity=0 2A
(3)10 (6)10 1C
74157 74151 1D
binary variable 1A
1's 11 1C
2421 Excess-3 code 1D

0000 to 1000 0000 to 1100 1A
BCD ASCII 1B
7404 7485 1D
8,4 8,1 2B
look ahead n bit 1B
n 2
m =2 m =n 2A
9 10 1C
several inputs
and several several inputs
outputs and one output 1A
binary octal 1B
Two half adders
and one And Two half adders
gate and one Or gate 1D
Overlapping
Diagonal corners combinations 1C
Minterms I 1D
SOP and POS
SOP and POS are always
are not related to logically
each other equivalent 2C
ABCD ABCD 1C
∑m(0,1,3,5,6) ∏m(0,1,3,5,6) 1B
8 4 bit binary 8 bit binary
adder subtractor 1A
B AB 1A
Ai Bi 1A
Full Adder can
not be used as Full Adder adds
basic building two single bit
block for 4 bit numbers and
BCD Adder IC also considers
such as 7483 carry. 2C
subtraction delay inputs 1A

Carry
Propogation
Delay Carry Problem 1B
greater than 9 ,0 greater than 9 ,1 2D
1,0 0,1 2B
Difference,
Sum, Borrow Carry 2B
EVEN and
ODD ODD 1A
AB+AB' A'B 2B
The trigger is The trigger input
LOW changes level 1D
It does not 1
It has no invalid require a clock
states input C
J=0, K=1 J=1, K=1 1 D
J=0, K=1 J=1, K=1 1A
low high 1D
16 32 1B
binary race 1B
5 4 1D
1000 1001 1D
2 15 2D
1111 1100 1B
Synchronous Only
events do not asynchronous
need a clock to events need a
control them control clock 2A
Four flip-flop ten Six flip-flop four

AND gates AND gates 2D
Up and down Up and down

counts are both counts are both
active-LOW active -HIGH 1A
A synchronous
counter cannot
operate at higher A ripple counter
frequencies is faster 2B
7490 7483 1C
7476 7478 2B
both present and present outputs
past inputs only 1C
Serial -In - Serial -In -

Parallel-Out Serial-Out 1C
A single 0, the A single 1, the
rest 1 rest 0 1D
Serial -In - Serial -In -
Parallel-Out Serial-Out 1A
4 8 1D
7476 7478 2C
Ripple carry
Shift register counter 1C
only flip flops and
combinational combinational
logic circuits logic circuits 1D
present state,
next state input, next state 1C
ASCII code BCD code 1B
2 1 2B
Q remains
Q=0 unchanged 1C
initially clocked finally clocked 1A

arithmetic memory or
element arithmetic 1A
SIPO PIPO 1D
Q remains
Q=0 unchanged 1B
Q remains
Q=0 unchanged 1A
sequential random 1B
circular ms 1A
Ripple carry
register counter 1B
Shift register generator 1C
directional universal 1B
directional universal 1A
directional universal 2D
or nand 1B
Portable Logic Portable Large
Device Device 1B
Not Ex-OR 1B
Sum Terms Not Terms 1A
Sum Terms Not Terms 1B
Sum Terms Not Terms 1C

Portable Logic Portable Large
Array Array 1A
Not Ex-OR 1A
PLD cannot be
programmed as
PLD is fixed per user
function requirement 2B
Fine
Programmable Fine Portable
Gate Array Gate Array 1A
Simple
Programmable Simple Portable
Large Device Large Device 1B
Complex Complex
Programmable Portable Large
Large Device Device 1B
Portable Array Portable Array
Logic Large 1A
PLA PLG 1D
SPLD CPLD 1A
PAG FPGA 1C
Inver/Non Invert
buffer Output buffer 1B
Inver/Non Invert
buffer Output buffer 1A
Sum Terms Not Terms 1B
Sum Terms Not Terms 1A
data box conditional box 1A
3 4 1C
set state reset state 2B

flowchart structure chart 1C
1,8 1,any 2D
data decision 1A
conditions decision 1B
control logic condition logic 1C
data box state box 1D

output next state 1A
3 levels 4 levels 1C
3unit 6 unit 1A
positive edge positive level
triggered triggered 2C
Hardware Hardware
Definition database
Language Language 1B
integer std_logic 1D
ARCHITECTU
RE FORMAT 1D
5 6 1C
package library 1A
Simulation,
Synthesis and
documentation Programming 2A
Assertion Decision
Statement Statement 1C
NEXT END 1B
X is an 4-bit
X is an 4-bit unsigned
Signed number number 1A
function procedure 1B
Architecture is
Entity represents written inside
the interface the entity 2D
<= := 1C
signal assignment
statements next statements 1B
5 2 1A
Concurrent
statements in the
architecture
body define the
Architecture can relationship
be used without between inputs
an entity and outputs 2C
IN,CLK OUT,CLK 1B
Dataflow Combined 1D
BIT_LOGIC_V
BIT_VECTOR ECTOR 1D
IEEE 1416 IEEE 1146 2A
Total In all 2B
Dataflow Combined 1A
Dataflow Combined 1C
It is used for
combinational
and sequential It contains
circuits Foreign attribute 2B
Dataflow Combined 1B
Case Process 1B
Case Loop 1B
Case Function 1D

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1. Any signed negative binary number is recognised by its ________

4. The representation of octal number (532.2)8 in decimal is ________

5. The decimal equivalent of the binary number (1011.011)2 is ________

6. An important drawback of binary system is ________

7. The decimal equivalent of the octal number (645)8 is ______

8. The largest two digit hexadecimal number is ________

9. Representation of hexadecimal number (6DE)H in decimal:

10. The quantity of double word is ________

Sanfoundry Global Education & Learning Series – Digital Circuits.

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2. Java Programming Examples on Data-Structures

Digital Circuits Questions and Answers – Number

1. The given hexadecimal number (1E.53)16 is equivalent to ____________

2. The octal number (651.124)8 is equivalent to ______

3. The octal equivalent of the decimal number (417)10 is _____

4. Convert the hexadecimal number (1E2)16 to decimal:

collecting the remainders in reverse order.

6. Convert (214)8 into decimal:

7. Convert (0.345)10 into an octal number:

8. Convert the binary number (01011.1011)2 into decimal:

9. Octal to binary conversion: (24)8 =?

10. Convert binary to octal: (110110001010)2 =?

Sanfoundry Global Education & Learning Series – Digital Circuits.

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10. Digital Image Processing Questions and Answers

Digital Circuits Questions and Answers –

1. What is the addition of the binary numbers 11011011010 and 010100101?

2. Perform binary addition: 101101 + 011011 = ?

Therefore, the addition of 101101 + 011011 = 1001000.

3. Perform binary subtraction: 101111 – 010101 = ?

Therefore, The subtraction of 101111 – 010101 = 011010.

4. Binary subtraction of 100101 – 011110 is

Therefore, The subtraction of 100101 – 011110 = 000111.

5. Perform multiplication of the binary numbers: 01001 × 01011 = ?

Therefore, 01001 × 01011 = 001100011.

Therefore, 100101 x 0110 = 011011110.

7. On multiplication of (10.10) and (01.01), we get

Therefore, 10.10 x 01.01 = 011.0010.

Therefore, the remainder of 111101 ÷ 1001 = 0111.

Therefore, the quotient of 011010000 ÷ 1001 = 101001.

10. Binary subtraction of 101101 – 001011 = ?

Therefore, the subtraction of 101101 – 001011 = 100010.

Sanfoundry Global Education & Learning Series – Digital Circuits.

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Digital Circuits Questions and Answers – 1’s, 2’s,

1. 1’s complement of 1011101 is ____________

Thus, 1’s complement of 1011101 = 0100010.

2. 2’s complement of 11001011 is ____________

3. On subtracting (01010)2 from (11110)2 using 1’s complement, we get ____________

4. On subtracting (010110)2 from (1011001)2 using 2’s complement, we get ____________

5. On subtracting (001100)2 from (101001)2 using 2’s complement, we get ____________

1’s complement of subtrahend - 1 1 0 0 1 1

6. On addition of 28 and 18 using 2’s complement, we get ____________

7. On addition of +38 and -20 using 2’s complement, we get ____________

8. On addition of -46 and +28 using 2’s complement, we get ____________

9. On addition of -33 and -40 using 2’s complement, we get ____________

Sanfoundry Global Education & Learning Series – Digital Circuits.