8/25/2014 Hints for Successful Simulation Pattern Debug

Hints for Successful Simulation Pattern Debug

Doc Id: 010298 Product: TetraMAX Last Modified: 05/15/2007

Overview

You have already used TetraMAX to create ATPG patterns and now you are at the simulation verification
step.
You have written out these patterns in a serial Verilog format to simulate with a Verilog simulator and
now have simulation miscompares. This application note will point you where to look for help, and provide
you with some more debug hints.

What Kind of Errors Are You Getting?

Shift error?

If you are seeing an error during scan pattern 0 ( basic_chain_test ) then it must be a shift
violation that needs to be debugged. See:

Can I Run Multiple Chain Tests in a Row and then Save Them in the Same File?
Product: TetraMAX Type: Q&A Doc ID: 900982

This SolvNet article explains what the serial testbench is doing, shows you how to write out multiple
patterns for chain_test debug to make debug easier, and gives you some additional hints on simulating
with VCS.

Capture error due to clock capture pulse?

For serial testbench simulation, you will get an error like this:

// 0.00 ns : Begin test_setup

// 200.00 ns : Begin patterns, first pattern = 0
// 200.00 ns : ...begin scan load for pattern 0
// *** ERROR during scan pattern 1 (detected during load of pattern 2)
1 0chain 16 (exp=1, got=0) // pin SPEAKER, scan cell 16, T= 6510.00 ns
// 12000.00 ns : ...begin scan load for pattern 5
// 14400.00 ns : ...begin scan load for pattern 5, load 2
// 16500.00 ns : Simulation of 6 patterns completed with 1 errors

$finish at simulation time 16500.00 ns

In this case, the failure is caught during the unload of the values captured in the scan cells from pattern 1
capture clock pulse. It's caught during the load of pattern 2, because the load/unload
operation is overapped when the testbench is written out.

The time listed T=16510.00 ns is the time of the unload of the failing scan cell. Since this is the
serial testbench, it's the time the value of this cell is seen at the scan_out port. This means that you
must look at the last capture pulse that happened in pattern 1 to see what was captured into this cell.

You can get the testbench to print this info out for you by adding a simple display statement. To do this,
edit the capture_clockname event to add a display statement to print the time of the capture clock. For
example:
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8/25/2014 Hints for Successful Simulation Pattern Debug
event capture_CLOCK;
always @ capture_CLOCK begin
->forcePI_default_WFT;
#110; ->measurePO_default_WFT;
#135 PI[5] = 1; // CLOCK
$display("// %t : capture_clock being pulsed at this time ",$time); //add this
#10 PI[5] = 0; // CLOCK
end

This way you will get the simulation output to look as follows:

// 0.00 ns : Begin test_setup

// 200.00 ns : Begin patterns, first pattern = 0
// 200.00 ns : ...begin scan load for pattern 0
// 4745.00 ns : capture_clock being pulsed at this time

// *** ERROR during scan pattern 1 (detected during load of pattern 2)

1 0chain 16 (exp=1, got=0) // pin SPEAKER, scan cell 16, T= 6510.00 ns
// 7145.00 ns : capture_clock being pulsed at this time
// 9545.00 ns : capture_clock being pulsed at this time
// 12000.00 ns : ...begin scan load for pattern 5
// 14345.00 ns : capture_clock being pulsed at this time
// 14400.00 ns : ...begin scan load for pattern 5, load 2
// 16500.00 ns : Simulation of 6 patterns completed with 1 errors

$finish at simulation time 16500.00 ns

At this point, you know that the last capture before the unload of this cell happened at time 4745.00 ns.
This is where you need to look at in the waveforms. We expected to capture a 1, but simulation got a 0.

Now you also need to find out which cell is cell 16 of 0chain. You can find this out by doing a report scan
cell command in TetraMAX:

report scan cell -all > scan.rep

This will show the full name of the scan cell that you need to zero in on:

0chain 16 MASTER IN 732 U1/U1/U1/MINS_reg

In the interactive simulation tool that you use, display the needed pins of this scan cell at the time of the
last capture. As shown below, it shows that the D pin of this cell was at a 0, hence the scan cell captures
a 0 at the capture_clock pulse as shown by the Q

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8/25/2014 Hints for Successful Simulation Pattern Debug

Then you can also take a look at the values in the TetraMAX GUI.

You need to get TetraMAX to the same setup as you did when the patterns where create,d by running
build
and drc with the exact same switches and STIL file. Use the GSV to display the failing scan cell by using
"Show-> Scan cell " command

Then you can either do:

&TEST> set pat external saved_pat.bin //if you saved the patterns in binary format

-Or-

&TEST> set pat external serial_pat.v //pointing to the Verilog_testbench

&TEST> analyze simulation data -fast_sequential 1

This will simulate pattern 1 and display debug_sim_data as the pin data. Looking at the failing scan cell,
you should be
able to see what is expected to be captured on this cell.

In the schematic above, it shows:

D is #100
CP is #010
Q is #111

# stands for a chain load/unload operation

Three frames stand for value on pin pre_clock, clock_on and post_clock.
So, the D is a 1 pre_clock. This means that we expect to capture a 1 at this flop as shown by the value in
the third frame on Q.

Now you would trace the D pin and see why in simulation you got a 0 on it instead of a 1 at the pre_clock
time. This means
you will need to expand on the logic that drives pin D in the GSV and also display the waveforms in the
Verilog simulation.
In the case above, you would trace the NOR gate U1/U1/U1/U4. For it to be a 1 at the pre_clock time, all

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8/25/2014 Hints for Successful Simulation Pattern Debug
the three inputs must
be a 0. So, you would trace these inputs in the interactive Verilog simulation until the problem is identified.

Some other hints that could help you debug this. You can turn on verbose messaging for your simulation to
get more info
printed out; for example,

&vcs -R serial_pat.v net_list.v -v LIB/class.v +define+tmax_msg=4

You can also modify the pattern reporting interval via changing the default setting from 5 to another
smaller number,

&define+tmax_rpt=2

To create a extended VCD file, you can also define +define+tmax_vcde at the command line.
This will create a file named sim_vcde.out that could be used for debugging.

Another hint is to always write out the pattern report for your patterns from TetraMAX; for example,

&TEST> report pattern ?all > pattern.

Then, you can look at the failing pattern to see what was loaded into the chain, forced on the primary
inputs, measured at the primary outputs, which clock was pulsed and what was finally unloaded.

Pattern 1 (basic_scan)
Time 0: load 0chain = 0010011000 0111000010
Time 0: load 1chain = 1100000100 1011000001
Time 1: force_all_pis = 1101001101 11
Time 2: measure_all_pos = 0000000000 0000011011 0111110010 0Z
Time 3: pulse clocks CLOCK (5)
Time 4: unload 0chain = 0110111000 0111111111
Time 4: unload 1chain = 0101100101 0100110101

For more debug hints please see the TetraMAX online help topic Troubleshooting Simulation Failures. It's a
complete write up of how to go about debugging this issue.

For the parallel testbench see:

Parallel Testbench Simulation Failures
I am running a Verilog simulation of my parallel Verilog testbench created by TetraMAX write patterns
parallel_pat.v -format verilog_single -parallel and I'm getting the following ERRO
Product: TetraMAX Type: Q&A Doc ID: 900958

Why does my parallel load testbench fail?

I have a design for which I generated ATPG patterns using TetraMAX. I have written out my patterns in
verilog serial load format and run a VCS simulation which passed without errors. Now I generate ...
Product: TetraMAX Type: Q&A Doc ID: 901000

How to fix these capture violations if the netlist can't be changed:

Commands add cell const Versus add capture mask, Clarification
Can you clarify the difference between the TetraMAX commands "add capture mask gate_id" vs "add cell
const OX"?
Product: TetraMAX Type: Q&A Doc ID: 901030

Mask Patterns Without Rerunning ATPG

I would like to mask some flops using add cell constraints OX instance. Can this be done without rerunning
ATPG?
Product: TetraMAX Type: Q&A Doc ID: 901006

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